Continuous plasma and heat treatment

Abstract

To provide a method and a non-transitory computer-readable medium for manufacturing a memory device that improves the quality of a selectively deposited silicon-containing dielectric layer.SOLUTION: A method includes providing a film stack into a processing chamber, selectively depositing a silicon-containing dielectric layer in recessed areas of the film stack, exposing the selectively deposited silicon-containing dielectric layer to a high density plasma annealed at a temperature higher than 800°C, and annealing the silicon-containing dielectric layer at a temperature higher than 800°C to form a silicon-containing dielectric film having a wet etch rate of less than 4Å / min.SELECTED DRAWING: Figure 1

Description

【Technical Field】 【0001】 【0001】Embodiments of the present disclosure relate to the field of electronic devices and methods and apparatuses for manufacturing electronic devices. More specifically, embodiments of the present disclosure provide a method of forming a 3D-NAND device having a high-quality silicon-containing dielectric layer. 【Background Art】 【0002】 【0002】Semiconductor technology has advanced rapidly, and as technology progresses, device dimensions have been reduced in order to increase processing and storage speed per unit area. In NAND devices, a string current needs to be large enough to obtain a current sufficient to distinguish an ON cell from an OFF cell. The string current depends on the carrier mobility enhanced by increasing the grain size of the silicon channel. 【0003】 【0003】In the current processes employed in 3D-NAND manufacturing, high-temperature atomic layer deposition (ALD) or chemical vapor deposition (CVD) silicon nitride (SiN) and subsequent additional patterning steps are used. By selective deposition of SiN, the patterning step can be omitted. However, selective deposition requires a relatively low deposition temperature, which results in a low-quality film. 【0004】 【0004】Therefore, there is a need in the art for 3D-NAND devices having high-quality SiN films. Furthermore, there is a need in the art for methods and apparatuses for forming 3D-NAND devices. 【Summary of the Invention】 【0005】

[0005] One or more embodiments of the present disclosure relate to a processing method. In one embodiment, the processing method comprises selectively depositing a silicon-containing dielectric layer in recessed regions of a film stack, wherein the film stack comprises alternating layers of a first material layer and a second material layer, and having memory holes extending through the film stack; selectively depositing a silicon-containing dielectric layer; exposing the silicon-containing dielectric layer to a high-density plasma at a temperature of 500°C or less and a pressure of less than 1 Torr; and annealing the silicon-containing dielectric layer at a temperature exceeding 800°C to provide a silicon-containing dielectric film having a wet etching rate of less than 4 Å / min. 【0006】

[0006] Further embodiments of the present disclosure relate to processing tools. In one embodiment, a non-transient computer-readable medium includes instructions, when executed by a controller of a processing chamber, to cause the processing chamber to perform the following operations: selectively deposit a silicon-containing dielectric layer in recessed areas of a film stack, wherein the film stack comprises alternating layers of a first material layer and a second material layer, and having memory holes extending through the film stack; selectively deposit a silicon-containing dielectric layer in recessed areas of the film stack; expose the silicon-containing dielectric layer to a high-density plasma at a temperature of 500°C or less and a pressure of less than 1 Torr; and anneal the silicon-containing dielectric layer at a temperature of 800°C or more to provide a silicon-containing dielectric film having a wet etching rate of less than 4 Å / min. 【0007】

[0007] To enable a more detailed understanding of the above-mentioned features of the Disclosure, a more detailed description of the Disclosure, which has been briefly summarized above, can be given by reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the Disclosure and should therefore not be considered to limit its scope. Embodiments described herein are shown in the figures of the accompanying drawings as examples, not as limitations, and similar reference numerals indicate similar elements. [Brief explanation of the drawing] 【0008】 [Figure 1]

[0008] A flow diagram of one embodiment of the method according to the embodiments described herein is shown. [Figure 2A] 【0009】 A cross-sectional view of the device according to one or more embodiments is shown. [Figure 2B] 【0010】 This figure shows a cross-sectional view region 103 of the substrate in Figure 2A according to one or more embodiments. [Figure 3] 【0011】 A cross-sectional view of the device according to one or more embodiments is shown. [Figure 4] 【0012】 A cross-sectional view of the device according to one or more embodiments is shown. [Figure 5] 【0013】 A cross-sectional view of the device according to one or more embodiments is shown. [Figure 6] 【0014】 One or more embodiments of a cluster tool are shown. [Modes for carrying out the invention]

[0009] 【0015】 Before describing some exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the configuration or process step details described below. Other embodiments of this disclosure are possible and can be implemented or performed in various ways.

[0010] 【0016】 One or more embodiments provide a processing method, including plasma-based doping (PLAD) and annealing in an integrated processing tool, that enables the selective deposition of a silicon-containing dielectric film, such as silicon nitride, at low temperatures on a recessed polysilicon sidewall through high aspect ratio memory holes of a 3D NAND cell film stack.

[0011] 【0017】The selective deposition of silicon-containing dielectric films, such as silicon nitride, is a low-temperature process, resulting in a decrease in film quality. While not intended to be theoretically bound, if selectively deposited, low-quality silicon-containing dielectric films cannot be converted into high-quality silicon-containing films, then selectively deposited silicon-containing films, especially silicon nitride, cannot be used to form 3D NAND cell structures.

[0012] 【0018】 Figure 1 shows a flowchart of an exemplary method 10 for forming a memory device. Those skilled in the art will recognize that method 10 may include any or all of the illustrated processes. The order of each step may also be partially modified. Method 10 may begin with any of the enumerated processes without departing from the present disclosure. Referring to Figure 1, in operation 12, a film stack is provided. As used herein, the term “provided” means that the substrate is made available for processing (e.g., placed in a processing chamber). In operation 14, a silicon-containing dielectric layer is selectively deposited in the recessed areas of the film stack. In operation 16, the silicon-containing dielectric layer is exposed to a high-density plasma, and in operation 18, the silicon-containing dielectric layer is annealed at a temperature above 800°C to provide a silicon-containing dielectric film having a wet etching rate of less than 4 Å / min.

[0013] 【0019】 Figures 2 to 5 show some of the memory devices 100 that follow the process flow shown for method 10 in Figure 1. Figure 2 shows an electronic device 100 according to one or more embodiments of the present disclosure. In some embodiments, the electronic device 100 shown in Figure 2 is formed in layers on a bare substrate 105 as shown. The electronic device in Figure 2 consists of a substrate 105, a semiconductor layer 110, an optional sacrificial layer 120, a memory stack 130, and an optional oxide layer 140.

[0014] 【0020】The substrate 105 may be any suitable material known to those skilled in the art. As used in this specification and the accompanying claims, the term “substrate” refers to the surface or a portion of a surface on which the process acts. Furthermore, unless otherwise clearly indicated in the context, a reference to a substrate may refer only to a portion of a substrate. Moreover, a reference to deposition on a substrate may mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0015] 【0021】 As used herein, “substrate” refers to any substrate or material surface formed on a substrate on which a film treatment is performed during the manufacturing process. For example, substrate surfaces on which treatment can be performed include, depending on the application, materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, as well as any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates can be subjected to pretreatment processes for polishing, etching, reduction, oxidation, hydroxylation, annealing, and / or baking of the substrate surface. In addition to film treatment directly on the surface of the substrate itself, any of the film treatment steps disclosed in this disclosure may be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term “substrate surface” is intended to include such underlying layers as indicated in the context. Therefore, for example, when a film / layer or partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0016] 【0022】In one or more embodiments, the semiconductor layer 110 is located on the substrate 105. In some embodiments, the semiconductor layer 110 is also called a common source wire. The semiconductor layer 110 can be formed by any suitable technique known to those skilled in the art and can be made from any suitable material, including but not limited to polysilicon (polySi). In some embodiments, the semiconductor layer 110 is a common source wire made of a conductive material or a semiconductor material.

[0017] 【0023】 In one or more embodiments, an optional sacrificial layer 120 is formed on the semiconductor layer 110 and can be made of any suitable material. In some embodiments, the sacrificial layer 120 is removed and replaced in a later process. In some embodiments, the sacrificial layer 120 is not removed and remains in the memory device 100. In this case, the term “sacrificial” has an extended meaning that includes a permanent layer and may also be called a conductive layer. In one or more embodiments, the optional sacrificial layer 120 includes a material that can be selectively removed from the adjacent semiconductor layer 110 and the second material layer 132.

[0018] 【0024】In one or more embodiments, the memory stack 130 is formed on an optional sacrificial layer 120. The memory stack 130 in the illustrated embodiment includes a plurality of alternating second material layers 132 and a first material layer 134. In one or more embodiments, the first material layer 134 includes a nitride layer, and the second material layer 132 includes an oxide layer. In some embodiments, the memory stack 130 includes non-substitution gates such as alternating oxide and polysilicon, or oxide and metal, or oxide and sacrificial layer. The first material layer 134 includes a material that is etching selective to the second material layer 132 so that the first material layer 134 can be removed without substantially affecting the second material layer 132. In one or more embodiments, the first material layer 134 includes one or more of polysilicon, silicon nitride (SiN), silicon carbide (SiC), silicon oxycarbide (SiOC), germanium (Ge), and titanium nitride (TiN). In one or more embodiments, the first material layer 134 contains silicon nitride. In one or more embodiments, the second material layer 132 contains silicon oxide.

[0019] 【0025】 Each alternating layer can be formed to an appropriate thickness of any choice. In some embodiments, the thickness of each second layer 132 is approximately equal. In one or more embodiments, each second layer 132 has the thickness of the first second layer. In some embodiments, the thickness of each first layer 134 is approximately equal. When used in this respect, approximately equal thicknesses are within + / - 5% of each other. In some embodiments, a silicon layer (not shown) is formed between the second material layer 132 and the first material layer 134. The thickness of the silicon layer may be relatively thin compared to the thickness of the second material layer 132 or the first material layer 134.

[0020] 【0026】In one or more embodiments, the memory hole channel 150 is opened through the memory stack 130. In some embodiments, opening the memory hole channel 150 includes etching into the semiconductor layer 110 through the oxide layer 140, the memory stack 130, and the sacrificial layer 120. Referring to FIG. 2B, which is an enlarged view of region 103, the memory hole channel 150 extends through the memory stack 130 and has sidewalls that expose the surface 138 of the second material layer 132 and the surface 139 of the first material layer 134. 【0021】 【0027】 In one or more embodiments, the memory hole channel 150 has a high aspect ratio. As used herein, the term "high aspect ratio" refers to a feature having a height:width ratio of about 10, 20, or 50 or more. 【0022】 【0028】 In one or more embodiments, the optional sacrificial layer 120 has a surface 122 that is exposed as a sidewall of the memory hole channel 150. The memory hole channel 150 extends a distance within the semiconductor layer 110 such that the sidewall surface 112 and the bottom 114 of the memory hole channel 150 are formed within the semiconductor layer 110. The bottom 114 of the memory hole channel 150 can be formed anywhere within the thickness of the semiconductor layer 110. In some embodiments, the memory hole channel 150 extends within the semiconductor layer 110 with a thickness in the range of about 10% to about 90% of the thickness of the semiconductor layer 110, or in the range of about 20% to about 80% of the thickness of the semiconductor layer 110, about 30% to about 70% of the thickness of the semiconductor layer 110, or about 40% to about 60% of the thickness of the semiconductor layer 110. In some embodiments, the memory hole channel 150 extends within the semiconductor layer 110 a distance of 10%, 20%, 30%, 40%, 50%, 60%, 70% or 80% or more of the thickness of the semiconductor layer 110. 【0023】 【0029】Figure 3 shows the formation of a recess in the first material layer 134 relative to the second material layer 132 through the memory hole channel 150. In one or more embodiments, a recessed region 142 is formed. The first material layer 134 can be formed by any suitable process known to those skilled in the art. In other embodiments, the memory hole channel 150 can be formed structurally, for example, by depositing a polysilicon channel material into the memory holes of a SiN / SiO / SiN stack, after which the SiN is removed and the SiO is trimmed, leaving an SiO structure with a recess opening into the polysilicon channel. In this case, 134 is not only formed with a recess but is also completely removed, exposing the filled channel material.

[0024] 【0030】 Figure 4 shows operation 14 in which the silicon-containing dielectric layer 152 is selectively deposited within the recessed region 142. In one or more embodiments, the silicon-containing dielectric layer 152 can be deposited by any suitable means known to those skilled in the art. In one or more embodiments, the silicon-containing dielectric layer 152 is deposited at temperatures below 500°C, for example, by atomic layer deposition (ALD) or chemical vapor deposition (CVD). In other embodiments, the silicon-containing dielectric layer 152 is deposited at temperatures below 500°C, including below 490°C, below 450°C, below 400°C, below 350°C, and below 300°C.

[0025] 【0031】 The silicon-containing dielectric layer 152 may include any suitable dielectric material known to those skilled in the art. As used herein, the term “dielectric material” refers to a layer of material that is an electrical insulator capable of being polarized in an electric field. In one or more embodiments, the silicon-containing dielectric layer 152 is silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boride (SiB), silicon boron nitride (SiBN), and the like. In certain embodiments, the silicon-containing dielectric layer 152 includes silicon nitride (SiN).

[0026] 【0032】In one or more embodiments, the deposition of the silicon-containing dielectric layer 152 is selective to the first material layer 134 on the second material layer 132 such that the silicon-containing dielectric layer 152 is deposited within the recessed region 142.

[0027] 【0033】 In one or more embodiments, the silicon-containing dielectric layer 152 has a thickness in the range of greater than 0 Å to 25 Å.

[0028] 【0034】 While not intended to be constrained by theory, it is thought that relatively low deposition temperatures (i.e., below 490°C) degrade the quality of the silicon-containing dielectric layer 152. Therefore, a low-quality silicon-containing dielectric layer 152 will have a poor wet etching rate (WER) of over 300 Å.

[0029] 【0035】 Figure 5 shows operations 16 and 18 in which the silicon-containing dielectric layer 152 is exposed to a high-density plasma and then annealed to provide a high-quality silicon-containing dielectric film 154. In some embodiments, the silicon-containing dielectric layer 152 can be exposed to plasma at temperatures below 500°C, including 500°C, 475°C, 450°C, 425°C, 400°C, 350°C, 300°C, 250°C, 200°C, 150°C, 100°C, and 50°C. In some embodiments, the silicon-containing dielectric layer 152 can be exposed to plasma at temperatures in the range of 400°C to 500°C, including the range of 400 to 450°C, or the range of 420 to 490°C, or the range of 400 to 450°C, 420 to 490°C, or the range of 420 to 475°C, or the range of 420 to 490°C. In one or more embodiments, the silicon-containing dielectric layer 152 can be exposed to plasma at temperatures including 400°C, 405°C, 410°C, 415°C, 420°C, 425°C, 430°C, 435°C, 440°C, 445°C, 450°C, 455°C, 460°C, 465°C, 470°C, 475°C, 480°C, 485°C, 490°C, 495°C, and 500°C.

[0030] 【0036】In one or more embodiments, the aspect ratio of the memory hole channels 150 is very high, and plasma doping (PLAD) is branched out because a conformal injection process is optionally used to inject impurities from the top to the bottom of the sidewalls of the silicon-containing dielectric layer 152 through the very high AR memory holes. This is something that only PLAD can do. While not intended to be bound by theory, the plasma treatment effect is thought to be due to inert ion bombardment of the silicon-containing dielectric layer 152.

[0031] 【0037】 In one or more embodiments, the plasma contains a noble gas. In some embodiments, the plasma is selected from one or more of helium (He), hydrogen (H2), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe).

[0032] 【0038】 In some embodiments, the silicon-containing dielectric layer 152 can be exposed to plasma at a pressure of less than 1 Torr, and pressures in the range of greater than 0 mTorr to less than 1 Torr, greater than 0 mTorr to 100 mTorr, and greater than 0 mTorr to 500 mTorr.

[0033] 【0039】 In one or more embodiments, the plasma treatment includes a plasma doping process in which a silicon-containing dielectric layer 152 is exposed to a high-density plasma with a negative high-voltage DC bias over water. In some embodiments, the high-voltage pulse is in the range of -0.2kV to -10kV for a period of 20μs to 150μs at 0.5kHz to 10kHz.

[0034] 【0040】In one or more embodiments, in operation 18, the selectively deposited silicon-containing dielectric layer 152 is annealed using rapid heat treatment (RTP). In one or more embodiments, the silicon-containing dielectric layer 152 is annealed at a temperature above 800°C to provide a silicon-containing dielectric film 154. In some embodiments, the silicon-containing dielectric layer 152 is annealed at a temperature above 1000°C to provide a silicon-containing dielectric film 154. In one or more embodiments, after plasma treatment and annealing, the silicon-containing dielectric film 154 is a high-quality film and has a wet etching rate of less than 4 Å / min, including wet etching rates of less than 3 Å / min, less than 2 Å / min, and less than 1 Å / min.

[0035] 【0041】 In one or more embodiments, the silicon-containing dielectric film 154 has a thickness in the range of greater than 0 Å to 25 Å.

[0036] 【0042】 The method in one or more embodiments is an integration method. In one or more embodiments, the method can be carried out in one or more processing chambers without breaking the vacuum.

[0037] 【0043】 Further embodiments of the present disclosure relate to a processing tool 900 for forming the memory device and method described, as shown in Figure 6.

[0038] 【0044】 The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are positioned within the central transfer stations 921, 931 and are configured to move robot blades and wafers to each of the multiple sides.

[0039] 【0045】The cluster tool 900 includes a number of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also called process stations, connected to a central transfer station. The various processing chambers provide separate processing areas isolated from adjacent processing stations. The processing chambers may be, but are not limited to, any suitable chambers including pre-clean chambers, buffer chambers, transfer spaces, wafer orientation / degassing chambers, cryogenic cooling chambers, deposition chambers, annealing chambers, etching chambers, selective oxidation chambers, oxide layer thinning chambers, or word line deposition chambers. The specific arrangement of process chambers and components may vary depending on the cluster tool and should not be considered as limiting the scope of this disclosure.

[0040] 【0046】 In some embodiments, the cluster tool 900 includes a selective deposition chamber, a plasma processing chamber, and an annealing chamber. In some embodiments, the plasma processing and annealing chambers are Varian VIISTa® PLAD® and Vantage® Vulcan® RTP manufactured by Applied Materials of Santa Clara, California.

[0041] 【0047】 In the embodiment shown in Figure 6, the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front 951 of the factory interface 950. The loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, but those skilled in the art will understand that this is merely representative of one possible configuration.

[0042] 【0048】The size and shape of the loading chamber 954 and the unloading chamber 956 may vary, for example, depending on the substrate being processed by the cluster tool 900. In the shown embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette containing multiple wafers arranged in the cassette.

[0043] 【0049】 Robot 952 is located within the factory interface 950 and can move between the loading chamber 954 and the unloading chamber 956. Robot 952 can transfer wafers from a cassette in the loading chamber 954 to the load lock chamber 960 via the factory interface 950. Robot 952 can also transfer wafers from the load lock chamber 962 to a cassette in the unloading chamber 965 via the factory interface 950. As will be understood by those skilled in the art, the factory interface 950 may have multiple robots 952. For example, the factory interface 950 may have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960, and a second robot that transfers wafers between the load lock 962 and the unloading chamber 956.

[0044] 【0050】The cluster tool 900 shown has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 via load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 having at least one robot 925 located therein. The robot 925 is also called a robotic wafer transport mechanism. The first transfer chamber 921 is centrally located relative to the load lock chambers 960, 962, process chambers 902, 904, 916, 918, and buffer chambers 922, 924. In some embodiments, the robot 925 is a multi-arm robot capable of independently moving multiple wafers at once. In some embodiments, the first transfer chamber 921 comprises two or more robotic wafer transport mechanisms. The robot 925 within the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Each wafer is transported on a wafer transport blade located at the distal end of the first robotic mechanism.

[0045] 【0051】 After processing the wafer in the first section 920, the wafer can be moved to the second section 930 through a pass-through chamber. For example, chambers 922, 924 may be unidirectional or bidirectional pass-through chambers. Pass-through chambers 922, 924 can be used, for example, to cool the wafer to a low temperature before processing in the second section 930, or to allow cooling or post-processing of the wafer before returning it to the first section 920.

[0046] 【0052】The system controller 990 communicates with the first robot 925, the second robot 935, the first set of processing chambers 902, 904, 916, 918, and the second set of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 may be a computer including a central processing unit, memory, appropriate circuitry, and storage.

[0047] 【0053】 The process may generally be stored as a software routine in the memory of the system controller 990 and, when executed by the processor, cause the process chamber to execute the process of the present disclosure. The software routine may also be stored and / or executed by a second processor (not shown) located separately from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be executed in hardware. Thus, the process may be implemented in software and executed using a computer system, in hardware such as application-specific integrated circuits or other types of hardware implementations, or as a combination of software and hardware. When the software routine is executed by the processor, it transforms a general-purpose computer into a dedicated computer (controller) that controls the chamber operation so that the process can be executed.

[0048] 【0054】 In some embodiments, the system controller 990 has a configuration to control the selective deposition chamber to selectively deposit a silicon-containing dielectric layer in the recessed regions of the film stack at a temperature of less than 490°C. In some embodiments, the controller 990 has a configuration to operate the plasma processing chamber to expose the silicon-containing dielectric layer to a high-density plasma at a temperature in the range of 400°C to 500°C and a pressure of less than 1 Torr. In other embodiments, the controller 990 has a configuration to control the annealing chamber to anneal the silicon-containing dielectric layer at a temperature of more than 800°C to provide a silicon-containing dielectric film having a wet etching rate of less than 4 Å / min.

[0049] 【0055】 In one or more embodiments, the processing tool includes a central transport station including a robot configured to move wafers, a plurality of processing stations, each processing station connected to the central transport station and providing a processing area separated from the processing areas of adjacent processing stations, the plurality of process stations including a selective deposition chamber, a plasma processing chamber, and an annealing chamber, and a controller connected to the central transport station and the plurality of process stations, the controller being configured to activate the robot to move wafers between processing stations and to control the processing performed at each processing station.

[0050] 【0056】 In the context describing the materials and methods discussed herein (particularly in the context of the following claims), the terms “a,” “an,” and “the,” and similar references, should be interpreted as covering both singular and plural forms, unless otherwise stated herein or unless clearly contradicted by the context. The enumeration of value ranges herein is merely intended to serve as a shorthand notation for referring individually to each individual value within the range, unless otherwise stated herein, and each individual value is incorporated into the specification as if it were individually stated herein. All methods described herein may be performed in any suitable order, unless otherwise stated herein or unless clearly contradicted by the context. The use of any examples or illustrative language provided herein (e.g., “etc.”) is merely intended to better illustrate the materials and methods and does not impose any limitation on their scope unless otherwise specified in the claims. No wording in the specification should be interpreted as indicating any element not claimed to be essential to the implementation of the disclosed materials and methods.

[0051] 【0057】Throughout this specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiment” means that any particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this disclosure. Therefore, any occurrence of phrases such as “in one or more embodiments,” “a particular embodiment,” “in one embodiment,” or “in an embodiment” in various places throughout this specification does not necessarily refer to the same embodiment of this disclosure. Furthermore, any particular feature, structure, material, or property may be combined in any suitable manner in one or more embodiments.

[0052] 【0058】 While the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Accordingly, the disclosure is intended to include modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

[Claim 1] The method involves selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack, wherein the film stack comprises alternating layers of a first material layer and a second material layer, and has memory holes extending through the film stack, and selectively depositing the silicon-containing dielectric layer. Exposing the silicon-containing dielectric layer to a high-density plasma at a temperature of 500°C or less, The silicon-containing dielectric layer is annealed at a temperature exceeding 800°C to provide a silicon-containing dielectric film. A method of processing, including. [Claim 2] The method according to claim 1, wherein the second material layer includes an oxide layer. [Claim 3] The method according to claim 1, wherein the recessed region is formed by providing a recess in the first material layer with respect to the second material layer through the memory hole. [Claim 4] The method according to claim 1, wherein the first material layer comprises one or more of polysilicon, silicon nitride, silicon carbide, silicon oxycarbide, germanium, and titanium nitride. [Claim 5] The method according to claim 1, wherein the silicon-containing dielectric layer comprises one or more of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride, silicon oxycarbonitride, silicon boride (SiB), and silicon boron nitride (SiBN). [Claim 6] The method according to claim 5, wherein the silicon-containing dielectric layer contains silicon nitride. [Claim 7] The method according to claim 1, wherein the selective deposition of the silicon-containing dielectric layer is carried out at a temperature of less than 500°C. [Claim 8] The method according to claim 1, wherein the silicon-containing dielectric film has a wet etching rate of less than 4 Å / min. [Claim 9] The aforementioned high-density plasma contains helium (He) and hydrogen (H ２ The method according to claim 1, wherein one or more of the following are selected: ), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe). [Claim 10] The method according to claim 1, wherein the silicon-containing dielectric film has a thickness in the range of more than 0 Å to 25 Å. [Claim 11] The method according to claim 1, wherein the method is carried out in a processing chamber without breaking the vacuum. [Claim 12] When executed by the controller of the processing chamber, the processing chamber is subjected to: A method for selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack, wherein the film stack comprises alternating layers of a first material layer and a second material layer, and has memory holes extending through the film stack, and the silicon-containing dielectric layer is selectively deposited in this manner. The silicon-containing dielectric layer is exposed to a high-density plasma at a temperature of 500°C or less, and The silicon-containing dielectric layer is annealed at a temperature exceeding 800°C to provide a silicon-containing dielectric film. A non-temporary, computer-readable medium containing instructions that perform the following action. [Claim 13] The non-temporary computer-readable medium according to claim 12, wherein the first material layer includes an oxide layer. [Claim 14] The non-temporary computer-readable medium according to claim 12, wherein the recessed region is formed by providing a recess in the second material layer with respect to the first material layer through the memory hole. [Claim 15] The non-temporary computer-readable medium according to claim 12, wherein the second material layer comprises one or more of polysilicon, silicon nitride, silicon carbide, silicon oxycarbide, germanium, and titanium nitride. [Claim 16] The non-temporary computer-readable medium according to claim 12, wherein the silicon-containing dielectric layer comprises one or more of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride, silicon oxycarbonitride, silicon boride (SiB), and silicon boron nitride (SiBN). [Claim 17] The non-temporary computer-readable medium according to claim 16, wherein the silicon-containing dielectric layer comprises silicon nitride. [Claim 18] The non-temporary computer-readable medium according to claim 12, wherein the selective deposition of the silicon-containing dielectric layer includes deposition at a temperature of less than 500°C. [Claim 19] The non-temporary computer-readable medium according to claim 12, wherein the silicon-containing dielectric film has a wet etching rate of less than 4 Å / min. [Claim 20] The aforementioned high-density plasma contains helium (He) and hydrogen (H ２ A non-temporary computer-readable medium according to claim 12, selected from one or more of ), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe).

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