Semiconductor substrate, semiconductor device and electronic device

Abstract

A semiconductor substrate equipped with a heterogeneous substrate (1), a mask layer (6) which has an opening (KS) and a mask section (5), a seed section (3S) which overlaps the opening, and a semiconductor layer (8) which contains a GaN-based semiconductor and is arrayed on the seed section and the mask section, wherein the top surface of the effective section (YS) of the semiconductor layer includes one or more low-defect regions (AL) of a size measuring 10μm in a first direction along the widthwise direction of the opening and 10μm in a second direction perpendicular to the first direction, and line defects are not measured by the CL method in the low-defect regions (AL).

Description

Semiconductor substrates, semiconductor devices, electronic devices

[0001] The present invention relates to a semiconductor substrate, a semiconductor device, and an electronic device.

[0002] Semiconductor devices using gallium nitride (GaN) generally have higher power conversion efficiency than semiconductor devices made of silicon (Si). As a result, semiconductor devices using GaN have lower power loss than semiconductor devices made of Si, and are therefore expected to have an energy-saving effect. Research has been conducted on techniques for forming GaN-based semiconductor elements in order to manufacture semiconductor devices using GaN. For example, Patent Document 1 discloses a technique for forming a GaN-based semiconductor layer on a GaN-based substrate or a heterogeneous substrate (e.g., a sapphire substrate) using an epitaxial lateral overgrowth (ELO) method.

[0003] JP 2013-251304 A

[0004] The semiconductor substrate according to the present disclosure comprises a main substrate having a lattice constant different from that of a GaN-based semiconductor, a mask layer located above the main substrate and having an opening and a mask portion, a seed portion overlapping the opening in a planar view, and a semiconductor layer including a GaN-based semiconductor arranged on the seed portion and the mask portion, wherein the semiconductor layer includes an effective portion located between the opening and the center of the mask portion in a planar view, and an upper surface of the effective portion includes at least one low-defect region having a size of 10 μm in a first direction along the width direction of the opening and 10 μm in a second direction perpendicular to the first direction, and linear defects are not measured in the low-defect region by the CL method.

[0005] 1A and 1B are plan views and cross-sectional views showing the configuration of a semiconductor substrate according to an embodiment; FIG. 1C is a cross-sectional view showing another configuration of a semiconductor substrate according to an embodiment; FIG. 1D is a cross-sectional view showing another configuration of a semiconductor substrate according to an embodiment; FIG. 1E is a cross-sectional view showing another configuration of a semiconductor substrate according to an embodiment; FIG. 1F is a cross-sectional view showing another configuration of a semiconductor substrate according to an embodiment; FIG. 1G is a cross-sectional view showing another configuration of a semiconductor substrate according to an embodiment; FIG. 1H is a cross-sectional view showing another example of a device isolation process according to an embodiment; FIG. 1I is a plan view showing a device isolation process according to an embodiment; FIG. 1J is a cross-sectional view showing another example of a device isolation process; FIG. 1J is a cross-sectional view showing another example of a device separation process; FIG. 1J is a cross-sectional view showing another example of a device separation process; FIG. 1I is a schematic view showing the configuration of an electronic device according to an embodiment; FIG. 1I is a schematic view showing another configuration of an electronic device according to an embodiment; FIG. 1J is a cross-sectional view showing an example of lateral growth of a semiconductor layer; FIG. 1J is a plan view and a schematic view showing evaluation of the semiconductor substrate according to an embodiment (configuration in which the ELO semiconductor layer has edge surfaces on the mask); FIG. 1J is a plan view and a schematic view showing evaluation of the semiconductor substrate according to an embodiment (configuration in which the ELO semiconductor layer has edge surfaces on the mask); FIG. 1J is a plan view and a schematic view showing evaluation of the semiconductor substrate according to an embodiment (configuration in which the ELO semiconductor layer has edge surfaces on the mask); 1A and 1B are plan views and schematic diagrams showing evaluation of the present semiconductor substrate (configuration in which the ELO semiconductor layer has an edge surface on the mask). 1B are plan views and schematic diagrams showing evaluation of an integrated semiconductor substrate in which the ELO semiconductor layer has no edge surface on the mask. 1C are plan views and schematic diagrams showing evaluation of an integrated semiconductor substrate in which the ELO semiconductor layer has no edge surface on the mask. 1D are plan views and schematic diagrams showing evaluation of an integrated semiconductor substrate in which the ELO semiconductor layer has no edge surface on the mask. 1E are plan views and schematic diagrams showing evaluation of an integrated semiconductor substrate in which the ELO semiconductor layer has no edge surface on the mask. 1F are plan views and schematic diagrams showing evaluation of an integrated semiconductor substrate in which the ELO semiconductor layer has no edge surface on the mask. 1G are CL images of the ELO semiconductor layer 8 of a semiconductor substrate 10 (main substrate is a silicon substrate). 1G are CL images of the ELO semiconductor layer 8 of a semiconductor substrate 10 (main substrate is a sapphire substrate). 1G are CL images of the back surface (separated surface) of the ELO semiconductor layer of a semiconductor substrate 10. 1G are CL images of the surface of a GaN layer of a reference example. 1G are CL images of the surface of a GaN layer of a reference example. 10A and 10B are CL images of the surface of a GaN layer of a reference example, and CL images of the back surface (peeled surface) of a GaN layer formed by ELO of a reference example.FIG. 1 is a CL image of the rear surface (peeled surface) of a GaN layer formed by ELO in a reference example. FIG. 2 is a cross-sectional view showing the configuration of a semiconductor substrate in Example 1. FIG. 3 is a cross-sectional view showing an example of semiconductor layer peeling in Example 1. FIG. 4 is a cross-sectional view showing the configuration of a semiconductor substrate in Example 2. FIG. 5 is a cross-sectional view showing the configuration of a semiconductor substrate in Example 3. FIG. 6 is a cross-sectional view showing the configuration of a semiconductor substrate in Example 4. FIG. 7 is a cross-sectional view showing an application example of Example 4. FIG. 8 is a cross-sectional view showing the configuration of Example 5. FIG. 9 is a cross-sectional view showing the configuration of Example 6. FIG. 10 is a cross-sectional view showing another configuration of Example 6. FIG. 11 is a block diagram showing an example of the configuration of a semiconductor substrate manufacturing apparatus.

[0006] (Semiconductor Substrate) Fig. 1 is a plan view and a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in Fig. 1, the semiconductor substrate 10 (semiconductor wafer) according to this embodiment includes a main substrate 1, an underlayer 4 formed on the main substrate 1 and including a seed portion 3S, a mask layer 6 formed on the underlayer 4 and having an opening KS and a mask portion 5 overlapping the seed portion 3S in a plan view, and a semiconductor layer 8 including a nitride semiconductor (e.g., a GaN-based semiconductor) disposed on the seed portion 3S and the mask portion 5. The underlayer 4 may be the underlayer 4, the mask layer 6 may be the mask 6 (mask pattern), and the semiconductor layer 8 may be the semiconductor portion 8.

[0007] The opening KS of the mask layer 4 may have a tapered shape (a shape in which the width narrows toward the underlayer 4 side). In this case, the width of the opening KS and the width of the mask portion 5 can be expressed with respect to the upper surface of the mask layer. However, this is not limitative.

[0008] Nitride semiconductors can be expressed as, for example, AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N). Typical examples include GaN, AlGaN, AlGaInN, and InGaN. The semiconductor layer 8 may be doped (e.g., n-type containing donors) or non-doped. A semiconductor substrate refers to a substrate containing a nitride semiconductor (e.g., a GaN-based semiconductor), and the material of the main substrate 1 may be a semiconductor or a non-semiconductor. The main substrate 1 and the underlayer 4 may be collectively referred to as a base substrate, and the main substrate 1, the underlayer 4, and the mask layer 6 may be collectively referred to as a template substrate 7.

[0009] The semiconductor layer 8 is formed by an epitaxial lateral overgrowth (ELO) method, starting from the seed portion 3S exposed from the opening KS. For this reason, the semiconductor layer 8 may be referred to as an ELO semiconductor layer 8. The thickness direction of the semiconductor layer 8 is the Z direction (the <0001> direction of the GaN-based crystal). The opening KS has an elongated shape, and its width direction is the X direction (the <11-20> direction of the GaN-based crystal).

[0010] 2 is a cross-sectional view showing another configuration of the semiconductor substrate according to the present embodiment. As shown in Fig. 2, the semiconductor substrate 10 may have a configuration in which a main substrate 1, a base layer 4, a mask layer 6, a semiconductor layer 8, and a functional layer 9 are provided in this order.

[0011] In the semiconductor substrate 10, multiple layers are stacked on a main substrate, and the stacking direction can be referred to as the "upward direction." Also, viewing the semiconductor substrate 10 from a line of sight parallel to the normal direction of the semiconductor substrate 10 can be referred to as a "planar view."

[0012] (Main Substrate) A heterogeneous substrate having a lattice constant different from that of a GaN-based semiconductor can be used as the main substrate 1. Examples of heterogeneous substrates include silicon (Si) substrates, sapphire (Al ２ O ３) substrate, silicon carbide (SiC) substrate, ScAlMgO ４ Examples of the surface orientation of the main substrate 1 include the (111) surface of a silicon substrate, the (0001) surface of a sapphire substrate, and the 6H-SiC (0001) surface of a SiC substrate. These are merely examples, and any substrate and surface orientation that allows the semiconductor layer 8 to be grown by the ELO method may be used. The main substrate may also be a free-standing substrate (for example, a wafer cut out from a bulk crystal).

[0013] (Underlayer) As the underlayer 4, a buffer layer 2 (e.g., an AlN layer) and a seed layer 3 (e.g., a GaN-based semiconductor) can be provided in this order from the main substrate side. The buffer layer 2 is a melting suppression layer that can reduce mutual melting due to direct contact between the main substrate 1 and the seed layer 3. It also has the effect of enhancing the crystallinity of the seed layer 3. The AlN layer is formed to a thickness of approximately 10 nm to 5 μm using, for example, an MOCVD method. For example, if a main substrate 1 that does not melt with the seed layer 3, which is a GaN-based semiconductor, is used, it is possible to configure the device without providing the buffer layer 2. If a silicon substrate or the like is used for the main substrate 1, the AlN layer will melt with the GaN-based semiconductor seed layer, so providing a buffer layer 2 such as an AlN layer reduces melting.

[0014] The seed layer 3 may be, for example, an AlGaN layer. The seed layer 3 includes a seed portion 3S that overlaps with the opening KS of the mask layer 6. The seed layer 3 may be a graded layer in which the Al composition approaches GaN in a graded manner. The graded layer may be, for example, a first layer, an AlGaN layer, a second layer, an AlGaN layer, a ... ０．７ Ga ０．３ N layer and the second layer, Al ０．３ Ga ０．７The second layer (Al:Ga:N = 0.3:0.7:1) has a Ga composition ratio (0.7 / 2 = 0.35) greater than the first layer (Al:Ga:N = 0.7:0.3:1) (0.3 / 2 = 0.15). The graded layer can be easily formed using MOCVD and may be composed of three or more layers. Using a graded layer as the seed layer 3 can alleviate stress from the main substrate 1, which is a heterogeneous substrate. The seed layer 3 may include a GaN layer. In this case, the seed layer 3 may be a single GaN layer, or the top layer of the graded layer (seed layer 3) may be a GaN layer. The underlayer 4 may be composed of only one of the buffer layer 2 and the seed layer 3. Alternatively, a freestanding SiC substrate (e.g., a single crystal wafer cut from a bulk crystal) can be used as the main substrate 1, and a template substrate can be formed by forming a mask layer 6 on the SiC substrate without forming a base layer.

[0015] (Mask Layer) Mask portions 5 and openings KS are formed in the mask layer 6. The openings KS function as growth initiation openings that expose the seed layer 3 and initiate growth of the semiconductor layer 8, and the mask portions 5 may function as selective growth masks that cause the semiconductor layer 8 to grow laterally. The openings KS are portions of the mask layer 6 (mask pattern 6) where the mask portions 5 are not formed (non-formation portions), and do not have to be surrounded by the mask portions 5.

[0016] The mask layer 6 can be made of an inorganic insulating film such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiON) film, or a titanium nitride (TiNx) film. For example, a silicon oxide film having a thickness of approximately 50 nm to 4 μm (e.g., approximately 100 nm to 2 μm) is formed on the entire surface of the underlayer 4 using a sputtering method, and a resist is applied to the entire surface of the silicon oxide film. The resist is then patterned using photolithography to form a resist with stripe-shaped openings. A portion of the silicon oxide film is then removed using a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form the openings KS, and the resist is then removed using organic cleaning to form the mask layer 6 having the openings KS and the mask portion 5. It is also possible to form a mask portion on the entire substrate using photolithography, then apply and pattern a resist, remove the resist in the region that will become the openings KS, and then form the openings KS using a dry etching method.

[0017] The openings KS have an elongated shape, and a plurality of openings KS are periodically arranged with a first period in the a-axis direction (first direction X) of the ELO semiconductor layer 8 .

[0018] The width of the opening KS is set to approximately 0.1 μm to 20 μm. The smaller the width of the opening KS, the fewer the number of threading dislocations propagating from the opening KS to the ELO semiconductor layer 8. This also makes it easier to peel off the ELO semiconductor layer 8 in a later process. Furthermore, the area of ​​the effective portion with fewer surface defects can be increased.

[0019] The mask layer 6 may be a laminated film containing the above-mentioned materials, for example, a laminated film containing a silicon oxide film and a silicon nitride film.

[0020] (Deposition of ELO Semiconductor Layer) A GaN-based semiconductor layer is formed as the semiconductor layer 8 (ELO semiconductor layer 8) by the ELO method. The ELO semiconductor layer 8 may be made of GaN, and the seed portion 3S may also contain GaN. For example, a template substrate 7 including the main substrate 1, the underlayer 4, and the mask layer 6 is introduced into an MOCVD apparatus, and a GaN layer is deposited on the template substrate 7. Examples of ELO deposition conditions include a substrate temperature of 1120°C, a growth pressure of 50 kPa, TMG (trimethylgallium): 22 sccm, and NH ３ : 15 slm, V / III=6000 (ratio of the supply amount of Group V raw material to the supply amount of Group III raw material).

[0021] In forming the semiconductor layer 8, it is preferable to reduce the mutual reaction between the semiconductor layer 8 and the mask portion 5 and maintain a state in which the semiconductor layer 8 and the mask portion 5 are in contact with each other by van der Waals forces. That is, the semiconductor layer 8 and the mask portion 5 are in contact with each other mainly by van der Waals forces.

[0022] Adjacent ELO semiconductor layers 8 grown from adjacent openings KS may meet, or may not meet, forming a gap near the center of mask portion 5. If they meet, the entire surface of the substrate can be flat. If they do not meet, the gap can more effectively relieve stress (compressive stress or tensile stress) that occurs when using a main substrate 1 whose main component is a material other than a nitride semiconductor, and the occurrence of defects and cracks can be effectively suppressed.

[0023] (Shape of ELO Semiconductor Layer) The semiconductor layer 8 has an effective portion YS (a portion that will form an element portion in a later process) located between the opening KS and the center 5C of the mask portion in a plan view. The portion of the semiconductor layer 8 located on the seed portion 3S (a portion with many threading dislocations) becomes a non-effective portion NS. That is, the semiconductor layer 8 includes an effective portion YS with relatively few threading dislocations and a non-effective portion NS with relatively many threading dislocations. The non-effective portion NS is a dislocation inheriting portion with more threading dislocations than the effective portion YS (dislocation non-inheriting portion), but may be used as part of a device. For example, if the functional layer 9 includes an active layer, the portion of the active layer where electrons and holes combine (a light-emitting portion) can be arranged to overlap the effective portion YS in a plan view. An N-type electrode (cathode) or the like may be arranged to overlap the non-effective portion NS in a plan view.

[0024] Threading dislocations are dislocations (defects) that extend from the lower surface or the interior of the semiconductor layer 8 to the surface or surface layer thereof along the thickness direction (<0001> direction, Z direction) of the ELO semiconductor layer 8. Threading dislocations can be observed by performing CL (cathode luminescence) measurement on the surface (parallel to the c-plane) of the semiconductor layer 8.

[0025] 1 has an edge surface (side surface) 8E near the center of the mask portion 5, and does not meet with the semiconductor layer 8 grown from the adjacent seed portion 3S. When the c-plane ELO semiconductor layer 8 is formed in an island shape, the side surface of the ELO semiconductor layer 8 is typically formed by a <1-10α> plane (α is any integer), a <11-2β> plane (β is any integer), or a plane crystallographically equivalent to these. In other words, the edge surface 8E of the semiconductor layer 8 may have an inclined surface (facet).

[0026] In this way, the semiconductor layers 8 grown laterally in opposite directions from two adjacent seed portions 3S do not come into contact (meet) with each other on the mask portion 5, and a gap (gap) GP is formed, thereby reducing the internal stress of the semiconductor layer 8. This reduces cracks and defects that occur in the semiconductor layer 8. This effect is particularly effective in this embodiment in which the main substrate 1 is a heterogeneous substrate. The width of the gap GP is preferably 4 μm or less, and more preferably 3 μm or less.

[0027] The semiconductor layer 8 may be an n-type GaN-based semiconductor (for example, silicon as the donor). When the functional layer 9 including, for example, a p-type semiconductor layer is formed above the semiconductor layer 8 (see FIG. 2), if the semiconductor layer 8 contains silicon or oxygen as an n-type dopant, the p-type dopant (magnesium, etc.) can be compensated for, and this phenomenon can be significantly reduced by limiting the width of the gap GP within the above range.

[0028] 3 is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. When forming the functional layer 9, edge growth 9G (corners) may occur as shown in FIG. 3. For example, this occurs when the functional layer 9 includes an AlGaN layer. The edge growth may reach a width of 10 μm or more and a height of approximately 200 to 300 nm, which can hinder subsequent processes. However, by limiting the width of the gap GP to the above range, the edge growth 9G can be significantly reduced (for example, to 100 nm or less).

[0029] 4 and 5 are plan and cross-sectional views illustrating another configuration of a semiconductor substrate according to this embodiment. The semiconductor layer 8 in FIG. 4 has a structure in which semiconductor layers grown laterally in opposite directions from two adjacent seed portions 3S meet and integrate near the center 5C of the mask portion. In this structure, by appropriately setting the deposition conditions for the ELO semiconductor layer 8 and the width of the mask portion 5, a hollow portion 8C may be formed near the meeting point, i.e., the center 5C of the mask portion, as shown in FIG. 5. The hollow portion 8C has a shape that is wider on the mask portion 5 side (e.g., a cone or teardrop shape in cross section). In this case, the semiconductor layer 8 has a portion (non-effective portion NS) that overlaps with the hollow portion 8C in plan view. That is, the semiconductor layer 8 has a useful portion YS and a non-effective portion NS adjacent to the useful portion YS.

[0030] Silicon oxide, silicon nitride, and silicon oxynitride films used as materials for mask layer 6 have smaller thermal expansion coefficients than GaN-based semiconductors. Therefore, when ELO semiconductor layer 8, which has been formed at approximately 1000°C, is cooled to room temperature, cracks may occur in ELO semiconductor layer 8 due to the difference in thermal expansion coefficients. Hollow portion 8C has the effect of significantly reducing the internal stress of semiconductor layer 8, thereby effectively reducing the occurrence of such cracks. Furthermore, the surface of semiconductor layer 8 may have a depression 8D above hollow portion 8C. This depression 8D also has the effect of alleviating the internal stress of semiconductor layer 8.

[0031] (Functional Layer) The semiconductor substrate 10 of FIG. 2 includes a functional layer 9 on a semiconductor layer 8. The functional layer 9 includes, for example, at least one of a GaN-based n-type semiconductor layer, a GaN-based non-doped semiconductor layer, a GaN-based p-type semiconductor layer, a conductive layer, and an insulating layer. The GaN-based semiconductor layer of the functional layer 9 may be formed by any film formation method. The functional layer 9 may be a compound semiconductor layer (compound semiconductor portion). The compound semiconductor layer may be a nitride semiconductor layer (nitride semiconductor portion). In this case, the nitride semiconductor layer may include a p-type layer and an active layer (e.g., a light-emitting layer), or the nitride semiconductor layer may include an n-type layer, an active layer, and a p-type layer.

[0032] The functional layer 9 may be, but is not limited to, a semiconductor device (for example, an LED or a laser) formed together with the semiconductor layer 8. For example, only a GaN-based n-type semiconductor layer may be provided.

[0033] (Element isolation on semiconductor substrate) Fig. 6 is a cross-sectional view showing the element isolation process according to this embodiment. Fig. 7 is a plan view showing the element isolation process according to this embodiment. As shown in Fig. 6, a region AK that overlaps with the opening KS in a plan view in the semiconductor substrate 10 is removed by vapor-phase etching down to the base layer 4.

[0034] Here, portions of the base layer 4, mask layer 6, semiconductor layer 8, and functional layer 9 are removed, and the base layer 4 and mask portion 5 are exposed in a trench TR (element isolation trench) formed after removal. The opening width of the trench TR is desirably larger than the width of the opening KS of the mask layer. The element isolation process can separate element portions DS in the semiconductor substrate 10. At this stage, the element portions DS are van der Waals bonded to the mask portion 5 of the template substrate and are part of the semiconductor substrate 10.

[0035] 7, the trench TR can be formed in a lattice shape (lattice pattern) in plan view. In this case, a configuration may be adopted in which one element portion DS is included in a region surrounded by adjacent lateral trenches (extending in the X direction) and adjacent vertical trenches (extending in the Y direction).

[0036] The vapor-phase etching is performed by a general photolithography method. After the etching is completed, the photoresist that served as the mask for the vapor-phase etching must be removed. However, if organic cleaning using weak ultrasonic waves is performed, there is little risk that the element portion DS will peel off from the mask portion 5.

[0037] 8 is a cross-sectional view showing another example of the element isolation process. As shown in Fig. 8, the region of the semiconductor substrate 10 that overlaps with the opening KS in a plan view and the region that overlaps with the gap portion GP may be removed using vapor-phase etching down to the base layer 4. In this way, meandering of the semiconductor layer 8 in the second direction (the longitudinal direction of the opening KS, the Y direction) is eliminated, and element portions DS with uniform shapes can be obtained.

[0038] 9 is a cross-sectional view showing another example of an element isolation process. As shown in Fig. 9, the region of semiconductor substrate 10 that overlaps with opening KS in a plan view and the region that overlaps with the central portion (non-effective portion NS) of mask portion 5 can be removed down to underlayer 4 using vapor-phase etching.

[0039] (Element Peeling from Template Substrate) FIG. 10 is a cross-sectional view showing the element peeling process. Because the semiconductor layer 8 and the mask portion 5 are bonded by van der Waals forces (weak forces), as shown in FIG. 10 , the element portion DS can be easily peeled from the template substrate to form a semiconductor device 20 by pulling up the functional layer 9 using the attractive force (adhesion, suction, electrostatic force, etc.) of the stamp device ST or the like. Being able to directly peel the element portion DS from the mask portion 5 using a viscoelastic elastomer stamp, electrostatic adhesive stamp, or the like offers significant advantages in terms of cost, throughput, and the like. However, adhesion between the mask portion 5 and the semiconductor layer 8 makes peeling difficult, so reducing such adhesion is highly significant (described below). After contacting the viscoelastic elastomer stamp, electrostatic adhesive stamp, or the like with the semiconductor layer 8, ultrasonic vibration, for example, may be applied. This vibration, or the like, makes it even easier to peel the semiconductor layer 8 from the mask portion 5.

[0040] FIG. 11 is a cross-sectional view showing another example of the element peeling process. As shown in FIG. 11 , the mask portion 5 may be wet-etched to leave the element portion DS of the semiconductor layer 8 connected only to the seed layer 3, and then the element portion DS may be mechanically peeled off from the template substrate 7 using tape TP or the like. In this case, etching above the opening KS is not required, allowing for the formation of a large semiconductor device 20. This peeling method has the advantage of eliminating the element separation process when the semiconductor layer 8 is a separate type (when the mask portion has an edge surface). When the semiconductor layer 8 is an integrated type (when the mask portion does not have an edge surface), it is only necessary to form a recess (down to the base layer) for the inflow of etchant, which has the advantage of facilitating element peeling.

[0041] 10 and 11 , the element portion DS peeled off from the template substrate 7 functions as a semiconductor device 20. Specific examples of the semiconductor device 20 include a light-emitting diode (LED), a semiconductor laser, a Schottky diode, a photodiode, and a transistor (including a power transistor and a high electron mobility transistor).

[0042] (Electronic Device) Fig. 12 is a schematic diagram showing the configuration of an electronic device according to this embodiment. Electronic device 30 in Fig. 12 includes a semiconductor device 20 including a semiconductor layer 8 and a functional layer 9, a drive substrate 23 on which the semiconductor device 20 is mounted, and a control circuit 25 that controls the drive substrate 23. Fig. 13 is a schematic diagram showing another configuration of the electronic device according to this embodiment. Electronic device 30 in Fig. 13 includes a semiconductor substrate 10 including a semiconductor layer 8 and a functional layer 9, a drive substrate 23 on which the semiconductor substrate 10 is mounted, and a control circuit 25 that controls the drive substrate 23. In this case, main substrate 1 may be a light-transmitting substrate (e.g., a sapphire substrate).

[0043] Examples of electronic devices include display devices, laser emitting devices (including Fabry-Perot type and surface emitting type), measuring devices, lighting devices, communication devices, information processing devices, and power control devices.

[0044] (Gaps on the Backside of ELO Semiconductor Layer) Hereinafter, the backside of the ELO semiconductor layer 8 in the semiconductor substrate 10 (the boundary surface with the mask portion 5) will be described.

[0045] When a heterogeneous substrate is used and the mask portion 5 is wide, voids may occur on the back surface of the ELO semiconductor layer 8. These voids can become the cause of surface defects in the ELO semiconductor layer 8 (for example, the origin of defects when stress is applied to the semiconductor layer 8), leading to deterioration of the characteristics and reduced reliability of devices formed on the ELO semiconductor layer 8. In this embodiment, the lateral deposition rate is increased and the interaction between the ELO semiconductor layer 8 and the mask portion 5 is reduced, thereby improving the surface morphology of the mask portion 5 and, as a result, successfully reducing the voids on the back surface of the ELO semiconductor layer 8 and adhesion to the mask portion 5.

[0046] Specifically, the lateral film growth rate is increased to quickly cover the mask portion 5 with a laterally grown film (ELO semiconductor layer 8) in order to reduce deterioration of the mask portion 5. If the lateral film growth rate is low during MOCVD, the mask portion 5 will be exposed to hydrogen and nitrogen at high temperatures for a long period of time, which may accelerate evaporation and decomposition of the mask portion 5, leading to deterioration of the surface morphology, the generation of pinholes, the generation of pits, etc.

[0047] The technique for increasing the lateral film formation rate is as follows: First, a vertically grown layer growing in the c-axis direction is formed on the seed portion exposed through the opening KS of the mask layer 6, and then a horizontally grown layer growing in the a-axis direction is formed. In this case, by setting the thickness of the vertically grown layer to 10 μm or less, preferably 5 μm or less, and more preferably 3 μm or less, the thickness of the horizontally grown layer can be kept low and the lateral film formation rate can be increased.

[0048] FIG. 14 is a cross-sectional view showing an example of lateral growth of a semiconductor layer. As shown in FIG. 14 , it is desirable to form an initial growth layer SL on the seed portion 3S overlapping the opening KS, and then laterally grow the semiconductor layer 8 from the initial growth layer SL. The initial growth layer SL serves as the starting point for the lateral growth of the semiconductor layer 8. In the deposition of the semiconductor layer 8, it is preferable to stop the deposition of the initial growth layer SL immediately before the edge of the initial growth layer SL rises above the upper surface of the mask portion 5 (when it is in contact with the upper end of the side surface of the mask portion 5) or immediately after it rises above the upper surface of the mask portion 5 (i.e., to switch the ELO deposition conditions from c-axis direction deposition conditions to a-axis direction deposition conditions at this timing). This reduces material consumption in the thickness direction growth of the semiconductor layer 8, effectively enabling the lateral growth of the semiconductor layer 8 at a high speed. The initial growth layer SL can be formed to a thickness of 50 nm to 5.0 μm (for example, 80 nm to 2 μm). The thickness of the initial growth layer SL may be 500 nm or less.

[0049] 14 , by growing the semiconductor layer 8 laterally after forming the initial growth layer SL, it is possible to increase the number of non-threading dislocations inside the effective portion YS (reduce the threading dislocation density on the surface of the effective portion YS). It is also possible to control the distribution of impurity concentrations (e.g., silicon, oxygen) inside the effective portion YS. By appropriately controlling the conditions during the formation of the semiconductor layer 8, it is possible to control the growth of the semiconductor layer 8 in the Z direction (c-axis direction) or the X direction (a-axis direction).

[0050] For the effective portion YS of the semiconductor layer 8 shown in FIG. 14 , the ratio (W1 / d1) of the size W1 in the X direction (first direction) to the thickness d1 can be, for example, 2.0 or greater. Using the method shown in FIG. 14 , W1 / d1 can be set to 1.5 or greater, 2.0 or greater, 4.0 or greater, 5.0 or greater, 7.0 or greater, or 10.0 or greater. It has been found that setting W1 / d1 to 1.5 or greater facilitates the division process shown in FIG. 7 . Furthermore, the internal stress of the semiconductor layer 8 is reduced, reducing substrate warpage. The aspect ratio (ratio of the size in the X direction to the thickness = WL / d1) of the semiconductor layer 8 can be set to 3.5 or greater, 5.0 or greater, 6.0 or greater, 8.0 or greater, 10 or greater, 15 or greater, 20 or greater, 30 or greater, or 50 or greater. 14 , the ratio (WL / WK) of the size WL of the semiconductor layer 8 in the X direction to the width WK of the opening KS can be set to 3.5 or more, 5.0 or more, 6.0 or more, 8.0 or more, 10 or more, 15 or more, 20 or more, 30 or more, or 50 or more, thereby increasing the ratio of the effective area. The semiconductor layer 8 shown in FIG. 14 can be made of a nitride semiconductor crystal (for example, a GaN crystal, an AlGaN crystal, an InGaN crystal, or an InAlGaN crystal).

[0051] Non-threading dislocations are dislocations observed by CL in a cross section along a plane parallel to the c-axis (a plane parallel to the thickness direction), and are mainly basal plane (c-plane) dislocations. The plane parallel to the c-axis may be a plane parallel to the (1-100) plane (a plane whose normal is in the Y direction) or a plane parallel to the (11-20) plane (a plane whose normal is in the X direction).

[0052] The non-threading dislocation density of the effective portion YS of the semiconductor layer 8 is higher than the threading dislocation density of the effective portion YS. In other words, the effective portion YS of the semiconductor layer 8 can be expressed as a GaN-based crystal (GaN-based layer) in which the non-threading dislocation density is higher than the threading dislocation density. In this case, the non-threading dislocation density can be 10 times or more, for example, 20 times or more, the threading dislocation density. The threading dislocation density is, for example, 5×10 ６ [pcs / cm ２] or less. The width (length in the X direction) of the effective portion (GaN-based crystal body) can be, for example, 10 μm or more. The effective portion (GaN-based crystal body) can be formed into a longitudinal shape in which the size in the Y direction (m-axis direction) is larger than the size in the X direction (a-axis direction). The effective portion (GaN-based crystal body) may have a non-threading dislocation density in a cross section taken along a plane parallel to the (11-20) plane that is larger than the non-threading dislocation density in a cross section taken along a plane parallel to the (1-100) plane. Furthermore, since the effective portion (GaN-based crystal body) is formed by lateral (X-direction) growth, the effective portion (GaN-based crystal body) can be configured such that the concentration of impurities (atoms contained in the mask layer 6, such as silicon and oxygen) is lower at one end portion at the end of growth in the X direction than at the other end portion at the beginning of growth.

[0053] The quality of the mask portion 5 (thickness uniformity, film quality, etc.) is affected by the surface flatness, crystallinity, and material of the base layer on which the mask portion 5 is formed. If there are defects in the base layer, the reaction between the mask portion 5 and the base layer will proceed from the defects, degrading the quality of the mask portion 5. As a result, the reaction between the mask portion 5 and the ELO semiconductor layer 8 formed thereon is accelerated, and voids may occur on the back surface of the ELO semiconductor (the interface with the mask portion 5). In the ELO method, film formation proceeds from both sides of the mask portion 5 toward the center, so voids are likely to occur in areas near the center (areas where it takes a long time to form the film).

[0054] Regarding the deposition temperature for the ELO semiconductor layer 8, a temperature of 1150°C or less is preferable to a high temperature exceeding 1200°C. It is also possible to form the ELO semiconductor layer 8 at a low temperature below 1000°C, which is preferable from the viewpoint of reducing mutual reactions. It has been found that in such low-temperature deposition, when trimethylgallium (TMG) is used as the gallium source, the source material is not sufficiently decomposed, and gallium atoms and carbon atoms are simultaneously incorporated into the ELO semiconductor layer 8 in greater amounts than usual. This is thought to be because, with the ELO method, deposition in the a-axis direction is fast and deposition in the c-axis direction is slow, resulting in greater incorporation during deposition of the c-plane.

[0055] It is known that carbon incorporated into the ELO semiconductor film reduces reaction with the mask portion 5, reduces mutual reaction with the mask portion 5, and does not cause adhesion to the mask portion 5. Therefore, in low-temperature film formation of the ELO semiconductor layer 8, by reducing the amount of ammonia supplied and forming the film at a low V / III ratio (<1000), the ELO semiconductor layer 8 can incorporate carbon elements in the raw materials or chamber atmosphere, thereby reducing reaction with the mask portion 5. In this case, the semiconductor layer 8 has a configuration containing carbon.

[0056] Furthermore, triethylgallium (TEG) is preferably used as the gallium source gas for low-temperature film formation below 1000° C. TEG decomposes organic materials more efficiently at low temperatures than TMG, and therefore can increase the lateral film formation rate.

[0057] An InGaN layer may be formed as the ELO semiconductor layer 8. Lateral deposition of the InGaN layer is performed at a low temperature, for example, below 1000°C. This is because at high temperatures, the vapor pressure of indium increases and it is not effectively incorporated into the film. A low deposition temperature has the effect of reducing the mutual reaction between the mask portion 5 and the InGaN layer. Another effect is that the InGaN layer has a lower reactivity with the mask portion 5 than the GaN layer. Incorporation of indium into the InGaN layer at an In composition level of 1% or more is desirable because it further reduces the reactivity with the mask portion 5. Triethylgallium (TEG) is preferably used as the gallium source gas.

[0058] Since the interaction between the mask portion 5 and the ELO semiconductor layer 8 is caused by a combination of various factors, the above-mentioned measures may be combined.

[0059] By suppressing the generation of voids on the back surface of the ELO semiconductor layer 8, linear defects on the surface (surface layer) of the ELO semiconductor layer 8 can be reduced. The m-plane of the ELO semiconductor layer 8 is vulnerable to stress and prone to defects. These linear defects are thought to be caused by crystal slippage along the m-plane. In a specific cross section parallel to the c-plane, dislocations extending in the m-axis direction (presumably mixed dislocations consisting of edge dislocations and screw dislocations) may be observed as linear defects. However, it is sufficient if the linear defects disappear (are not observed) in a cross section (parallel to the c-plane) cut at a surface layer more superficial than this specific cross section.

[0060] (Adhesion on the rear surface of the ELO semiconductor layer) When a heterogeneous substrate is used and the mask portion 5 is made wide, adhesion may occur between the rear surface of the ELO semiconductor layer 8 and the mask portion 5. If such adhesion exists, it becomes difficult to relieve stress caused by the difference in thermal expansion coefficient between the ELO semiconductor layer 8 and the heterogeneous substrate, which causes surface defects. Furthermore, it deteriorates the peeling yield when the ELO semiconductor layer 8 is peeled off from the template substrate 7.

[0061] In this embodiment, adhesion between the ELO semiconductor layer 8 and the mask portion 5 is reduced by reducing the mutual reaction between them. Specifically, the material and thickness of the mask portion 5 are optimized, and the film density of the mask portion 5 is increased. If the film density of the mask portion 5 is low, the film will evaporate quickly and the etching rate will be high when film formation is performed in a high-temperature, hydrogen atmosphere in an MOCVD apparatus. When the laterally growing ELO semiconductor layer 8 covers such a mask portion 5, the mask portion 5 and the ELO semiconductor layer 8 will adhere to each other. This is thought to be because a reaction layer is generated in which the mask portion 5 and the ELO semiconductor layer 8 are mixed, causing the ELO semiconductor layer 8 to adhere to the mask portion 5.

[0062] When the ELO semiconductor layer 8 and the mask portion 5 are bonded to each other, an intermediate layer (a layer in which the mask portion 5 and the semiconductor layer 8 react or intermix) is formed on the back surface of the ELO semiconductor layer 8. This intermediate layer (adhesion layer) is not removed even when the mask portion 5 is removed using an etchant such as hydrofluoric acid, and remains on the back surface of the ELO semiconductor layer 8. Therefore, when the intermediate layer is formed, the surface morphology of the back surface of the ELO semiconductor layer 8 after peeling from the template substrate 7 deteriorates. Those with little adhesion have an arithmetic mean surface roughness Ra of 10 nm or less, preferably about 1 nm, as measured by an AFM (Atomic Force Microscope). Those with a large adhesion effect have an Ra of about 13 nm. The state of adhesion can be determined by measuring the surface roughness of the back surface of the ELO semiconductor layer 8 with an AFM using the peeling method described below (see Example 1).

[0063] (Preferable Structure of Mask Layer) The mask layer may be formed of the above-mentioned silicon oxide film (SiO ｘ ), examples of the film include a single layer film made of one of a titanium nitride film (TiN, etc.), a silicon nitride film (SiN, etc.), a silicon oxynitride film (SiON), and a high-melting-point metal film, or a multi-layer film made of two or more of them.

[0064] The mask portion 5 may be a silicon nitride film or a silicon oxynitride film. While a small amount of silicon oxide film may decompose and evaporate during the formation of the ELO semiconductor layer 8 and become incorporated into the ELO semiconductor layer 8, silicon nitride film and silicon oxynitride film have the advantage of being less susceptible to decomposition and evaporation at high temperatures. Even when a silicon oxide film, which is common in the ELO method, is used as the mask layer, the mutual reaction between the mask portion 5 and the ELO semiconductor layer 8 can be effectively reduced by optimizing the film formation conditions for the mask layer and the ELO semiconductor layer 8.

[0065] Therefore, the mask layer may be a single layer film of silicon nitride film or silicon oxynitride film, or a multi-layer film in which a silicon oxide film and a silicon nitride film are formed in this order on an underlayer, or a multi-layer film in which a silicon nitride film and a silicon oxide film are formed in this order on an underlayer, or a multi-layer film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in this order on an underlayer.

[0066] Pinholes and other abnormalities in the mask portion 5 may be eliminated by performing organic cleaning after film formation, and then re-introducing the mask into the film formation apparatus to form the same film. A good quality mask layer may be formed using a general silicon oxide film by the above-described re-film formation method.

[0067] (Evaluation of the Present Semiconductor Substrate) Evaluation of the semiconductor substrate 10 will be described below. FIGS. 15 to 18 are plan views and schematic diagrams showing evaluation of the present semiconductor substrate (configuration in which the ELO semiconductor layer has an edge surface on the mask). The back surface of the semiconductor layer 8 (interface 8R with the mask portion) can be evaluated in the state of the interface in contact with the mask portion 5, or the semiconductor layer 8 can be peeled off from the mask portion 5 and the peeled surface evaluated. In this case, the semiconductor layer 8 can be peeled off by removing the mask portion 5 by wet etching or the like (note that if the semiconductor layer 8 is an integrated type, prior digging down to the base layer 4 may also be performed).

[0068] Measurement of the surface of the ELO semiconductor layer 8 of the semiconductor substrate 10 by cathodoluminescence (CL) revealed that the upper surface 8F of the effective portion YS included at least one low-defect region AL measuring 10 μm in a first direction X (a-axis direction) along the width direction of the opening KS and 10 μm in a second direction Y (m-axis direction) perpendicular to the first direction, and no linear defects (linear defects oblique to the first direction X, which are thought to be due to m-plane slip) were measured in the low-defect region AL (see FIG. 15 , evaluation criterion 1). More specifically, the upper surface of the effective portion YS included multiple low-defect regions AL aligned in the first direction X and multiple low-defect regions AL aligned in the second direction Y (see FIG. 15 , evaluation criterion 2). The size of the effective portion YS in the first direction was larger than the width of the opening KS (see FIG. 15 , evaluation criterion 3).

[0069] The effective portion YS had, at the interface 8R with the mask portion 5, a first region A1 having a size of 10 μm in the first direction X and 10 μm in the second direction Y, and a second region A2 having the same size, located closer to the center of the mask portion 5 than the first region A1, and a distance PT from the center 5C of the mask portion 5 being 30% or less of the width of the mask portion 5. The effective portion YS was peeled off from the mask portion 5, and the first region A1 and the second region A2 were observed with an AFM. The number of recesses with a major axis of 0.1 μm or more in the first region A1 was found to be equal to or less than the number of recesses with a major axis of 0.1 μm or more in the second region A2 (see FIG. 16 , evaluation criterion 4). The major axes of the recesses present in the first region A1 were 1 μm or less (hereinafter, evaluation criterion 5).

[0070] Furthermore, cross-sectional observation of the first region A1 and the second region A2 of the effective portion YS before peeling from the mask portion 5 was performed using an AFM, and the results showed that the number of voids with a major axis of 0.1 μm or more in the first region A1 was less than the number of voids with a major axis of 0.1 μm or more in the second region A2 (see Figure 16, evaluation criterion 6).

[0071] The effective portion YS had, at the interface 8R with the mask portion 5, a third region A3 measuring 10 μm in the first direction X and 10 μm in the second direction Y, and a fourth region A4 of the same size but located closer to the center of the mask portion 5 than the third region A3. When the effective portion YS was peeled off from the mask portion 5 and the first region A3 and the second region A4 were observed with an AFM, the adhesion area of ​​the third region A3 was smaller than the adhesion area of ​​the fourth region A4 (see FIG. 17 , evaluation criterion 7). Furthermore, the third region A3 was a non-adhesion region in which substantial adhesion with the mask portion 5 was not observed (hereinafter, evaluation criterion 8). The fourth region A4 was located such that the distance PT from the center 5C of the mask portion was 30% or less of the width of the mask portion 5.

[0072] The effective portion YS includes a first portion P1 and a second portion P2 that is farther from the opening KS than the first portion P1 and has a distance KT of 10 μm or more from the opening KS. The surface roughness (Ra) of the peeled surface F1 obtained when the first portion P1 is peeled from the mask portion 5 is defined as the first surface roughness, and the surface roughness (Ra) of the peeled surface F2 obtained when the second portion P2 is peeled from the mask portion 5 is defined as the second surface roughness. The first surface roughness was equal to or less than the second surface roughness (see FIG. 18 , evaluation criterion 9). Here, the arithmetic mean roughness (Ra) of each peeled surface was measured by AFM, and a portion of the roughness curve was extracted as a reference length. The unevenness of that section could be expressed as an average value. Furthermore, the ratio of the second surface roughness to the first surface roughness was between 1.0 and 10 (evaluation criterion 10). Furthermore, when the effective portion YS was peeled from the mask portion 5, the peeled surface (including F1 and F2) included a flat region having a size of 10 μm in the first direction and 10 μm in the second direction, and no recesses with a major axis of 0.1 μm or more (evaluation criterion 11). The second surface roughness was less than 10 nm (evaluation criterion 12). In plan view, the first portion P1 was adjacent to the opening KS, and the distance PT between the second portion P2 and the center 5C of the mask portion was 30% or less of the width of the mask portion 5 (evaluation criterion 13). The first recess occupancy was defined as the area ratio of the peeled surface that was occupied by recesses with a major axis of 0.1 μm or more included in the peeled surface F1 of the first portion P1, and the second recess occupancy was defined as the area ratio of the peeled surface that was occupied by recesses with a major axis of 0.1 μm or more included in the peeled surface F2 of the second portion, and the first recess occupancy was less than the second recess occupancy (evaluation criterion 14). Here, the recesses (void regions) are measured by AFM within a 5 μm×5 μm area of ​​each peeled surface, and the major axis, occupancy rate, etc. can be obtained.

[0073] Furthermore, the impurity concentration at the peeled surface F1 of the first portion P1 was greater than the impurity concentration at the peeled surface F2 of the second portion P2 (evaluation criterion 15).

[0074] Furthermore, the threading dislocation density on the upper surface 8R of the effective portion YS is 5×10 ６ [pcs / cm ２ ] or less (evaluation standard 16).

[0075] As described above, in order to reduce surface defects in the semiconductor layer 8, it is important to reduce adhesion with the mask portion 5 to relieve stress and to reduce the occurrence of voids that cause surface defects (m-plane slip).

[0076] The crystallinity of the ELO semiconductor layer 8 that grows laterally on the mask 5 from the opening KS of the mask 5 is extremely high. In the semiconductor substrate 10, by reducing the mutual reaction between the mask portion 5 and the semiconductor layer 8, voids and adhesions that occur on the back surface of the semiconductor layer 8 are reduced, and stress from the main substrate 1 can be effectively alleviated. This means that defects that occur in the effective portion YS are confined within the semiconductor layer 8 without penetrating to the surface.

[0077] 19 to 22 are plan views and schematic diagrams showing the evaluation of a semiconductor substrate with a different configuration (an integrated type in which the ELO semiconductor layer does not have an edge surface on the mask). In this case as well, it was found that the evaluation criteria 1 to 16 were satisfied.

[0078] 23 is a CL (cathodoluminescence) image of the ELO semiconductor layer 8 of the semiconductor substrate 10 (main substrate is a silicon substrate). Neither dark spots nor dark lines are observed in the effective portion YS. Only in the non-effective portion NS, threading dislocations due to the difference in lattice constant between the silicon substrate and GaN are observed. １９ / cm ２ There is some degree of it.

[0079] 24 is a cathodoluminescence (CL) image of the ELO semiconductor layer 8 of the semiconductor substrate 10 (the main substrate is a sapphire substrate). Because the ELO semiconductor layer 8 was mechanically peeled off from the template substrate, the non-effective portion NS was slightly damaged and the peeled surface was not flat, so the CL image was slightly distorted. However, in the effective portion YS, no dark spots or dark lines, which are threading dislocations, were observed, or a low dislocation density was achieved.

[0080] 25 is a CL image of the rear surface (peeled surface) of the ELO semiconductor layer of the semiconductor substrate 10. It can be seen that no voids or adhesions are observed in the effective portion YS.

[0081] (Reference Example of ELO Film Formation) FIG. 26 is a CL image of the surface of a GaN layer of a reference example. In this reference example, sapphire is used as the main substrate, and a GaN layer is formed by the ELO method. Dark spots (10 １８ ~10 １９ / cm ２ Both dark spots and dark lines are present. Also, dark spots and dark lines are observed on the masked area, although the density is lower than on the opening. Figure 27 is a CL image of the GaN layer surface of a reference example. In this reference example, silicon is used as the main substrate, and the GaN layer is formed by the ELO method. There are 10 １９ / cm ２ Dark spots of about 100 nm were observed, and dark lines were also observed on the masked area.

[0082] 28 is a CL image of the backside of the GaN layer of the reference example. In this reference example, silicon is used as the main substrate, and the GaN layer is formed by the ELO method. Many voids are observed at the edge of the mask portion.

[0083] Figure 29 is an optical microscope image of the back surface (peeled surface) of the GaN layer formed by ELO in the reference example. The adhesion NL (reaction layer) between the mask portion and the GaN layer is clearly visible. If such a GaN layer is mechanically peeled off from the mask portion (for example, using a diamond pen), the GaN layer and the mask portion will peel off together from the template substrate, as shown by the peeled region NA in Figure 30.

[0084] The reference example shows that the use of the ELO method alone does not eliminate voids and adhesions or significantly reduce surface defects on the mask area. Dark lines (linear defects) have a wide-ranging impact when they occur, so reducing them is of great significance.

[0085] 31 is a cross-sectional view showing the structure of a semiconductor substrate of Example 1. A silicon substrate having a (111) plane was used as the main substrate 1. The buffer layer 2 of the underlayer 4 was an AlN layer (for example, 30 nm). The seed layer 3 of the underlayer 4 was a first layer of Al ０．６ Ga ０．４The graded layer is formed by stacking an N layer (e.g., 300 nm) and a second GaN layer (e.g., 1 to 2 μm) in this order. That is, the Ga composition ratio (1 / 2=0.5) in the second layer (Ga:N=1:1) is greater than the Ga composition ratio (0.6 / 2=0.3) in the first layer (Al:Ga:N=0.6:0.4:1).

[0086] The mask layer 6 is a silicon oxide film (SiO ２ A stacked structure was used in which a silicon oxide film and a silicon nitride film (SiN) were formed in this order. The thickness of the silicon oxide film was, for example, 0.3 μm, and the thickness of the silicon nitride film was, for example, 70 nm. The silicon oxide film and the silicon nitride film were each formed by plasma chemical vapor deposition (CVD).

[0087] The semiconductor layer 8 was a GaN layer, and ELO film formation was performed using an MOCVD apparatus. First, the ELO semiconductor layer 8 was selectively grown on the surface of the seed layer 3 (the second GaN layer) exposed in the opening KS, and then it grew laterally on the mask portion 5. At this time, the growth was stopped before the semiconductor layers growing laterally on both sides of the mask portion 5 met. The width of the gap GP at this time was 2 μm.

[0088] The width WM of the mask portion 5 was 50 μm, the width of the opening KS was 5 μm, the lateral width WL of the ELO semiconductor layer 8 was 53 μm, and the width (size in the X direction) of the effective portion YS was 24 μm. The thickness of the ELO semiconductor layer 8 was 5 μm, and the aspect ratio of the ELO semiconductor layer 8 was 53 μm / 5 μm=10.6, which was a very high aspect ratio.

[0089] When the semiconductor substrate 10 obtained in Example 1 was evaluated, it was found to satisfy the above-mentioned evaluation criteria 1 to 16.

[0090] Peeling of the semiconductor layer 8 when evaluating the backside of the semiconductor layer 8 can be performed as follows: For example, when the mask layer 6 is formed of a silicon oxide film, nitride film, or oxynitride film, the semiconductor substrate 10 that has undergone the element isolation process (see FIGS. 8 and 9 ) is immersed in a hydrofluoric acid etchant for about 10 to 60 minutes, whereby the mask layer 6 dissolves in the etchant and the semiconductor layer 8 can be peeled off from the template substrate 7.

[0091] As another peeling method, as shown in FIG. 32 , the semiconductor substrate 10 can be immersed in a hydrofluoric acid etchant to dissolve the mask layer 6. Then, adhesive tape (e.g., adhesive dicing tape used when dicing semiconductor wafers) can be attached to the surface of the semiconductor layer 8. A Peltier element can then be used to cool the semiconductor substrate 10 with the adhesive tape attached to a low temperature. During this process, the adhesive tape, which generally has a larger thermal expansion coefficient than the semiconductor, contracts significantly, applying stress to the semiconductor layer 8. Because the semiconductor layer 8 is bonded to the template substrate 7 only within the opening KS and the mask portion 5 has been removed, stress from the adhesive tape can be effectively applied to the bond with the template substrate 7, mechanically cleaving or destroying the bond. This eliminates the need to remove the bond by dry etching.

[0092] Example 2 Figure 33 is a cross-sectional view showing the configuration of a semiconductor substrate of Example 2. In Example 2, an integrated type in which the ELO semiconductor layer 8 does not have an edge surface on the mask portion 5 is adopted. The width of the mask portion 5 is 50 μm, and the width of the opening KS is 5 μm. From the viewpoint of alleviating film stress, the height of the hollow portion 8C is preferably 1 μm or more. The width of the bottom surface of the hollow portion 8C is also preferably 1 μm or more, more preferably 2 μm or more.

[0093] When the semiconductor substrate 10 obtained in Example 2 was evaluated, it was found to satisfy the above-mentioned evaluation criteria 1 to 16.

[0094] (Example 3) Figure 34 is a cross-sectional view showing the configuration of a semiconductor substrate of Example 3. In Example 3, the width of the opening KS is 700 nm, which is less than 1 μm, and the width of the mask portion 5 is 100 μm. In Example 3, the width of the effective portion YS can be made wide, making it suitable for high-power laser semiconductor elements (ridge width of about 40 μm), etc. Figure 34 shows a structure in which the semiconductor layer 8 has an edge surface on the mask portion 5, but it may also be an integrated type that does not have an edge on the mask portion 5.

[0095] When the semiconductor substrate 10 obtained in Example 3 was evaluated, it was found to satisfy the above-mentioned evaluation criteria 1 to 16.

[0096] Example 4 FIG. 35 is a cross-sectional view showing the configuration of Example 4. In Example 4, a functional layer 9 constituting an LED is formed on a semiconductor layer 8. The semiconductor layer 8 is, for example, n-type doped with silicon or the like. The functional layer 9 includes, from bottom to top, an active layer 34, an electron blocking layer 35, and a GaN-based p-type semiconductor layer 36. The active layer 34 is an MQW (multi-quantum well) and includes an InGaN layer and a GaN layer. The electron blocking layer 35 is, for example, an AlGaN layer. The GaN-based p-type semiconductor layer 36 is, for example, a GaN layer. An anode 38 is formed so as to be in contact with the GaN-based p-type semiconductor layer 36, and a cathode 39 is formed so as to be in contact with the semiconductor layer 8.

[0097] Voids on the back surface of the semiconductor layer cause surface defects (linear defects) and degrade the characteristics of the semiconductor device. Furthermore, if the semiconductor device is a light-emitting element, voids on the back surface of the semiconductor layer reduce the in-plane uniformity of the emitted light. In Example 6, these problems can be resolved by forming a device section (light-emitting element section) DS on the ELO semiconductor layer 8 and peeling it off to obtain the semiconductor device 20, which is a light-emitting element. Specifically, no defects were observed in the light-emitting region of the semiconductor device 20.

[0098] 36 is a cross-sectional view showing an application example of Example 4. According to Example 4, a red micro LED 20R, a green micro LED 20G, and a blue micro LED 20B can be obtained, and by mounting these on a drive substrate (TFT substrate) 23, a micro LED display 30D (electronic device) can be configured. As an example, the red micro LED 20R, the green micro LED 20G, and the blue micro LED 20B are mounted on a plurality of pixel circuits 27 of the drive substrate 23 via a conductive resin 24 (e.g., an anisotropic conductive resin) or the like, and then a control circuit 25, a driver circuit 29, and the like are mounted on the drive substrate 23. A part of the driver circuit 29 may be included in the drive substrate 23.

[0099] Example 5 Figure 37 is a cross-sectional view showing the configuration of Example 5. In Example 5, a functional layer 9 constituting a semiconductor laser is formed on a semiconductor layer 8. The functional layer 9 includes, from bottom to top, an n-type optical cladding layer 41, an n-type optical guide layer 42, an active layer 43, an electron blocking layer 44, a p-type optical guide layer 45, a p-type optical cladding layer 46, and a GaN-based p-type semiconductor layer 47. Each of the guide layers 42 and 45 can be an InGaN layer. Each of the cladding layers 41 and 46 can be a GaN layer or an AlGaN layer. An anode 48 is formed so as to be in contact with the GaN-based p-type semiconductor layer 47.

[0100] 37, after the element portion DS is peeled off, the cathode 49 is formed on the back surface of the semiconductor layer 8. Therefore, the quality of the back surface of the semiconductor layer 8 affects the device characteristics.

[0101] Example 6 Figure 38 is a cross-sectional view showing the configuration of Example 6. Figure 39 is a cross-sectional view showing another configuration of Example 6. In Example 6, a sapphire substrate with a textured surface is used as the main substrate 1. The underlayer 4 includes a buffer layer 2 and a seed layer 3. The semiconductor layer 8 may have an edge surface on the mask 5 (Figure 38) or may be an integrated type without an edge surface on the mask (Figure 39). In Example 6, a GaN layer having a (20-21) plane can be deposited as the underlayer 4 on the main substrate 1. In this case, the ELO semiconductor layer 8 has the (20-21) plane, which is the primary crystal plane of the underlayer 4, resulting in a semipolar ELO semiconductor layer 8. Providing a functional layer for a laser or LED on the semipolar plane has the advantages of reducing the piezoelectric field and increasing the probability of electron-hole recombination in the active layer. Using a sapphire substrate with a textured surface also allows a GaN layer having a (11-22) plane to be deposited as the underlayer 4 on the main substrate 1.

[0102] (Manufacturing Apparatus) The method for manufacturing the semiconductor substrate 10 includes at least a step of forming a semiconductor layer 8 on a template substrate 7 using an ELO method. The method may also include a step of forming an underlayer 4 and a mask layer 6 on a main substrate 1.

[0103] The semiconductor substrate 10 can be fabricated using, for example, the semiconductor substrate manufacturing apparatus shown in FIG. 40 . The semiconductor substrate manufacturing apparatus 70 includes at least a semiconductor layer forming unit 71 that performs a process of forming a semiconductor layer 8 on a template substrate 7 using the ELO method, and a control unit 72 that controls the semiconductor layer forming unit 71. The semiconductor layer forming unit 71 may include an MOCVD apparatus, and the control unit 72 may include a processor and memory. The control unit 72 may be configured to control the semiconductor layer forming unit 71 by executing a program stored in, for example, an internal memory, a communication device, or an accessible network. This program and a recording medium on which this program is stored are also included in this embodiment. The semiconductor substrate manufacturing apparatus 70 may include a template substrate forming unit that performs a process of forming an underlayer 4 and a mask layer 6 on a main substrate 1, a functional layer forming unit that performs a process of forming a functional layer 9 on the semiconductor layer 8, etc. Furthermore, it may also be configured as a semiconductor device manufacturing apparatus that performs a device peeling process. The semiconductor device manufacturing apparatus may also perform a device isolation process. The semiconductor device manufacturing apparatus may include the semiconductor substrate manufacturing apparatus 70.

[0104] (Notes) The invention according to the present disclosure has been described above based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-described embodiments. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art could easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure.

[0105] REFERENCE SIGNS LIST 1 Main substrate 2 Buffer layer 3 Seed layer 3S Seed portion 4 Underlayer 5 Mask portion 6 Mask layer 8 Semiconductor layer 9 Functional layer 10 Semiconductor substrate 20 Semiconductor device 30 Electronic device 70 Semiconductor substrate manufacturing apparatus KS Opening YS Effective portion

Claims

1. a main substrate having a lattice constant different from that of a GaN-based semiconductor; and a template substrate having a seed portion and a non-seed portion located above the main substrate; a semiconductor layer including a GaN-based semiconductor, the semiconductor layer including a first crystal portion located above the seed portion and a second crystal portion located above the non-seed portion; the second crystal portion has a first portion located on the first crystal portion side and a second portion spaced 10 μm or more from the first portion, A semiconductor substrate, wherein when the semiconductor layer is peeled off from the template substrate, a surface roughness of the first portion is defined as a first surface roughness and a surface roughness of the second portion is defined as a second surface roughness, and the first surface roughness is less than or equal to the second surface roughness.

2. 2. The semiconductor substrate according to claim 1, wherein a ratio of the second surface roughness to the first surface roughness is 1.0 to 10.

3. The template substrate has a mask pattern including a mask portion that is the non-seed portion and an opening through which the seed portion is exposed, The semiconductor substrate according to claim 1 , wherein the second crystal portion is located between the opening and a center of the mask portion in a plan view.

4. 4. The semiconductor substrate according to claim 3, wherein a peeled surface of the second crystal portion when peeled off from the mask portion includes a flat region having a size of 10 μm in a first direction along the width direction of the opening and 10 μm in a second direction perpendicular to the first direction, and no recesses having a major axis of 0.1 μm or more.

5. 5. The semiconductor substrate according to claim 1, wherein the second surface roughness is less than 10 nm.

6. The semiconductor substrate according to claim 3 , wherein, in a plan view, the first portion is adjacent to the opening, and a distance between the second portion and a center of the mask portion is 30% or less of a width of the mask portion.

7. a first recess occupancy rate, which is a ratio of an area of ​​the first portion of the peeled surface to recesses having a major axis of 0.1 μm or more; a second recess occupancy rate is defined as an area ratio of the second portion of the peeled surface that is occupied by recesses having a major axis of 0.1 μm or more, 7. The semiconductor substrate according to claim 1, wherein the first recess occupancy is equal to or smaller than the second recess occupancy.

8. 8. The semiconductor substrate according to claim 1, wherein an impurity concentration in the separation surface of the first portion is higher than an impurity concentration in the separation surface of the second portion.

9. The semiconductor substrate according to claim 3 , wherein the mask portion is made of silicon oxide.

10. The threading dislocation density in the upper surface of the second crystal portion is 5×10 ６ [pcs / cm ２ 10. The semiconductor substrate according to claim 1, wherein the thickness of the semiconductor substrate is less than or equal to 100 nm.

11. 4. The semiconductor substrate according to claim 3, wherein the width direction of the opening is a <11-20> direction of the semiconductor layer.

12. a seed layer including a group III atom other than Ga, Ga, and nitrogen atoms, above the main substrate; the seed layer includes a first layer on the main substrate side and a second layer above the first layer, 12. The semiconductor wafer according to claim 1, wherein the Ga composition ratio in the second layer is greater than the Ga composition ratio in the first layer.

13. 4. The semiconductor substrate according to claim 3, wherein the width of the mask portion is 20 μm to 200 μm.

14. The semiconductor substrate according to any one of claims 1 to 13, further comprising a functional layer provided on the semiconductor layer.

15. A semiconductor device comprising the semiconductor layer and the functional layer according to claim 14.

16. 16. An electronic device comprising the semiconductor device of claim 15.