Crystalline oxide thin film, laminate, and thin-film transistor

Abstract

Provided is a crystalline oxide thin film containing In as a main component. The crystalline oxide thin film has a low-resistance region A and a high-resistance region B which exhibit different spreading resistance values as measured by a scanning spreading resistance microscope (SSRM) in a plane direction of the crystalline oxide thin film, and the spreading resistance value in the high-resistance region B is at least 8 times the spreading resistance value in the low-resistance region A.

Description

Crystalline oxide thin film, laminate and thin film transistor

[0001] The present invention relates to a crystalline oxide thin film, a laminate, and a thin film transistor.

[0002] Thin film transistors (TFTs) that use a crystalline oxide thin film in the channel layer are known to have high mobility characteristics (see, for example, Patent Documents 1 to 7). In recent years, there has been a trend toward miniaturization of TFTs, and the characteristics of small TFTs have become important. Here, a small TFT is a TFT with a channel length L of 50 μm or less. Furthermore, to drive high-definition displays, TFTs with high mobility and reduced parasitic capacitance are required.

[0003] Japanese Patent No. 5373212 Japanese Patent Publication No. 2018-107316 Japanese Patent No. 6097458 Japanese Patent No. 6334598 Japanese Patent No. 6289693 International Publication No. 2018 / 043323 International Publication No. 2020 / 196716

[0004] A self-aligned TFT structure can be considered to obtain TFTs with reduced parasitic capacitance by using an oxide thin film for the channel layer. Furthermore, to obtain TFTs with high mobility, it is necessary to use a crystalline oxide material for the channel layer rather than an amorphous material. However, when the crystalline oxide thin films described in Patent Documents 1 to 7 are applied to a self-aligned TFT structure, there is no difference in resistivity between the region where the gate electrode is stacked (region B) and the other region (region A). This results in an insufficient energy barrier, which causes a drain-induced barrier lowering (DIBL) phenomenon, in which Vth tends to shift negatively when a high drain voltage Vd is applied to drive the TFT, resulting in unstable TFT characteristics. Furthermore, the average spacing (D) of the crystal grain boundaries in region A is not controlled, resulting in poor stability of the TFT's mobility and threshold voltage (Vth) relative to the device shape. When such TFTs are incorporated into a circuit and used to drive a display, issues such as uneven brightness and image retention may occur.

[0005] An object of the present invention is to provide a crystalline oxide thin film and a laminate that can form a region with a sufficiently large difference in resistivity, and a crystalline oxide thin film and a laminate that have a controlled average spacing between crystal grain boundaries.

[0006] According to the present invention, the following crystalline oxide thin films and the like are provided. 1. A crystalline oxide thin film containing In as a main component, which has a low-resistivity region A and a high-resistivity region B in a plane direction of the crystalline oxide thin film, the low-resistivity region A and the high-resistivity region B having different spreading resistance values ​​measured by scanning spreading resistance microscopy (SSRM), and the spreading resistance value of the high-resistivity region B is at least eight times the spreading resistance value of the low-resistivity region A. 2. The crystalline oxide thin film according to 1, wherein the spreading resistance value of the high-resistivity region B is at least ten times the spreading resistance value of the low-resistivity region A. 3. The crystalline oxide thin film according to 1, wherein the spreading resistance value of the high-resistivity region B is at least 15 times the spreading resistance value of the low-resistivity region A. 4. The crystalline oxide thin film according to any one of 1 to 3, which has a film thickness of 80 nm or less. 5. 5. The crystalline oxide thin film according to any one of 1 to 4, wherein the dC / dV value at the boundary between the low resistance region A and the high resistance region B is larger than the dC / dV value in the high resistance region B, as measured by a scanning capacitance microscope (SCM). 6. The crystalline oxide thin film according to any one of 1 to 5, wherein the average grain boundary angle θ between the lower surface of the crystalline oxide thin film and the grain boundaries in the thin film is 70° or more and 110° or less, and the average distance D between the grain boundaries is 0.01 μm or more and 2.0 μm or less. 7. The crystalline oxide thin film according to any one of 1 to 6, wherein the crystalline oxide thin film contains crystal grains that have a bixbyite structure in electron beam diffraction of the crystalline oxide thin film. 8. The crystalline oxide thin film according to any one of 1 to 7, wherein the crystalline oxide thin film further contains one or more elements selected from the group consisting of H, B, C, N, O, F, Mg, Al, Si, O, S, Cl, Ar, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln, Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb, and Bi. 9. A laminate comprising the crystalline oxide thin film according to any one of 1 to 8. 10. An average grain boundary angle θ formed between a surface where the crystalline oxide thin film and a lower layer contact each other and a crystal grain boundary in the crystalline oxide thin film. ｓｕｂis 70° or more and 110° or less. 11. The laminate according to 9 or 10, wherein the lower layer is a substrate of a thin film transistor or a constituent layer of a thin film transistor. 12. A thin film transistor comprising the crystalline oxide thin film according to any one of 1 to 8 or the laminate according to any one of 9 to 11. 13. A thin film transistor comprising: a channel layer; a source electrode and a drain electrode connected to both ends of the channel layer, respectively; and a gate electrode laminated on the channel layer via a gate insulating film, the channel layer being the crystalline oxide thin film, the gate insulating film being formed in the high resistance region B, and the source electrode and the drain electrode being formed in the low resistance region A, and distances L from ends of the source electrode and the drain electrode to points of intersection of a perpendicular line drawn from an end of the gate electrode in the thickness direction with the crystalline oxide thin film. ｏｆｆ is 4 μm or more and 20 μm or less, and the average spacing D between the crystal grain boundaries of the crystalline oxide thin film and the distance L ｏｆｆ 13. The thin film transistor according to 12, wherein 2≦L satisfies the following formula (1): ｏｆｆ / D≦100 (1) 14. The thin film transistor according to 12 or 13, wherein the contact region length Ls of the source electrode and the drain electrode with the channel layer is 4 μm or more and 20 μm or less, and the average distance D between the crystal grain boundaries of the crystalline oxide thin film and the contact region length Ls satisfy the following formula (2): 1≦Ls / D≦100 (2) 15. The thin film transistor according to any one of 12 to 14, wherein the horizontal gap ΔL between the low resistance region A and the gate electrode is less than 1 μm. 16. A crystalline oxide thin film containing In as a main component, having a film thickness of 80 nm or less, and having a high carrier concentration region A and a low carrier concentration region B with different carrier concentrations in the in-plane direction of the crystalline oxide thin film, １９ cm －３ That's it, 10 ２２ cm －３17. The crystalline oxide thin film according to 16, wherein the carrier concentration of the high carrier concentration region A is 8 times or more the carrier concentration of the low carrier concentration region B. 18. The crystalline oxide thin film according to 16, wherein the carrier concentration of the high carrier concentration region A is 15 times or more the carrier concentration of the low carrier concentration region B. 19. The crystalline oxide thin film according to 16, wherein the carrier concentration of the low carrier concentration region B is 10 times or more the carrier concentration of the high carrier concentration region A. １５ cm －３ That's it, 10 １９ cm －３ 20. The crystalline oxide thin film according to any one of 16 to 19, wherein the average grain boundary angle θ between the lower surface of the crystalline oxide thin film and the grain boundaries in the thin film is 70° or more and 110° or less, and the average spacing D between the grain boundaries is 0.01 μm or more and 2.0 μm or less. 21. The crystalline oxide thin film according to any one of 16 to 20, comprising crystal grains that have a bixbyite structure in electron beam diffraction of the crystalline oxide thin film. 22. The crystalline oxide thin film according to any one of 16 to 21, wherein the crystalline oxide thin film further contains one or more elements selected from the group consisting of H, B, C, N, O, F, Mg, Al, Si, O, S, Cl, Ar, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln, Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb, and Bi. 23. A laminate comprising the crystalline oxide thin film according to any one of 16 to 22. 24. An average grain boundary angle θ formed between a surface where the crystalline oxide thin film and a lower layer contact each other and a crystal grain boundary in the crystalline oxide thin film. ｓｕｂis 70° or more and 110° or less. 25. The laminate according to 23 or 24, wherein the lower layer is a substrate of a thin film transistor or a constituent layer of a thin film transistor. 26. A thin film transistor comprising the crystalline oxide thin film according to any one of 16 to 22 or the laminate according to 23 to 25. 27. A thin film transistor comprising: a channel layer; a source electrode and a drain electrode connected to both ends of the channel layer, respectively; and a gate electrode laminated on the channel layer via a gate insulating film, the channel layer being the crystalline oxide thin film, the gate insulating film being formed in the low carrier concentration region B, and the source electrode and the drain electrode being formed in the high carrier concentration region A, and distances L from ends of the source electrode and the drain electrode to points of intersection of a perpendicular line drawn from an end of the gate electrode in the thickness direction with the crystalline oxide thin film. ｏｆｆ is 4 μm or more and 20 μm or less, and the average spacing D between the crystal grain boundaries of the crystalline oxide thin film and the distance L ｏｆｆ 27. The thin film transistor according to 26, wherein 2≦L satisfies the following formula (1): ｏｆｆ / D≦100 (1) 28. The thin film transistor according to 26 or 27, wherein the contact region length Ls of the source electrode and the drain electrode with the channel layer is 4 μm or more and 20 μm or less, and the average distance D between the crystal grain boundaries of the crystalline oxide thin film and the contact region length Ls satisfy the following formula (2): 1≦Ls / D≦100 (2) 29. The thin film transistor according to any one of 26 to 28, wherein the horizontal gap ΔL between the high carrier concentration region A and the gate electrode is less than 1 μm. 30. A crystalline oxide thin film containing In as a main component, having a film thickness of 80 nm or less, an average distance D between the crystal grain boundaries of the crystalline oxide thin film being 2 μm or less, and a carrier concentration of 10 １９ cm －３ That's it, 10 ２２ cm －３ A crystalline oxide thin film, which is: 31. A thin film transistor comprising the crystalline oxide thin film according to 30. 32. An electronic circuit comprising the thin film transistor according to any one of 12 to 15, 26 to 29, and 31. 33. An electric device, an electronic device, a vehicle, or a power plant comprising the electronic circuit according to 32.

[0007] According to the present invention, it is possible to provide a crystalline oxide thin film and a laminate capable of forming a region with a sufficiently large difference in resistivity. Furthermore, it is possible to provide a crystalline oxide thin film and a laminate in which the average spacing of the crystal grain boundaries is controlled. This makes it possible to provide a self-aligned TFT that does not cause the DIBL phenomenon, maintains high mobility, and has high stability of mobility and Vth relative to the device shape.

[0008] 3A is a cross-sectional schematic diagram of a laminate according to an example of the present embodiment; FIG. 3B is a cross-sectional schematic diagram of a laminate according to another example of the present embodiment; FIG. 3C is a cross-sectional schematic diagram of a TFT according to an example of the present embodiment; FIG. 3D is an enlarged view of the vicinity of the source electrode in FIG. 3A; FIG. 3E is a cross-sectional schematic diagram of a TFT according to another example of the present embodiment; FIG. 3F is a cross-sectional schematic diagram of a TFT according to another example of the present embodiment; FIG. 3G is a cross-sectional schematic diagram of a TFT according to another example of the present embodiment; FIG. 3H is a cross-sectional schematic diagram of a TFT according to another example of the present embodiment; FIG. 3I is a cross-sectional schematic diagram of a pixel section when a liquid crystal element is applied; FIG. 3J is a top view of a display device according to the present embodiment; FIG. 3I is a cross-sectional schematic diagram of a TFT prepared in an example; FIG. 3J shows CL spectra measured in Example 217 and Comparative Example 20.

[0009] The ordinal numbers "first," "second," and "third" used in this specification are used to avoid confusion between components, and components that are not specified numerically are not limited in number.

[0010] In this specification and the like, the terms "film" or "thin film" and "layer" can be used interchangeably in some cases.

[0011] In the sintered body and oxide thin film of this specification and the like, the terms "compound" and "crystalline phase" can be interchangeable in some cases.

[0012] In this specification, the “oxide sintered body” may be simply referred to as the “sintered body.” In this specification, the “sputtering target” may be simply referred to as the “target.”

[0013] In this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes, wiring, switching elements (such as transistors), resistive elements, inductors, capacitors, and other elements with various functions.

[0014] In this specification, the functions of the source and drain of a transistor may be interchanged when transistors of different polarities are used or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms source and drain may be used interchangeably.

[0015] In this specification, "x to y" represents a numerical range of "not less than x and not more than y." The upper and lower limits of the numerical ranges can be combined in any combination. In addition, a combination of two or more of the individual embodiments of the present invention described below is also an embodiment of the present invention.

[0016] 1. Crystalline Oxide Thin Film (1) First Embodiment of Crystalline Oxide Thin Film The crystalline oxide thin film according to this embodiment is a crystalline oxide thin film containing In as a main component, and has a low-resistivity region A and a high-resistivity region B in the in-plane direction of the crystalline oxide thin film, which have different spreading resistance values ​​as measured by scanning spreading resistance microscopy (SSRM), and the spreading resistance value of the high-resistivity region B is at least eight times that of the low-resistivity region A.

[0017] The crystalline oxide thin film according to this embodiment is mainly composed of In element. Being the main component means that the composition ratio (atomic %: at %) of In relative to all metal elements in the crystalline oxide thin film is 50 at % or more. The composition ratio of In is preferably 70 at % or more, more preferably 80 at % or more, and even more preferably 85 at % or more. When 50 at % or more of the total number of atoms of the metal elements constituting the crystalline oxide thin film are In element, the crystalline oxide thin film according to this embodiment can exhibit sufficiently high mobility when used in a TFT.

[0018] In addition to In, the crystalline oxide thin film may contain one or more elements selected from the group consisting of H, B, C, N, O, F, Mg, Al, Si, O, S, Cl, Ar, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln, Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb, and Bi.

[0019] In this embodiment, the crystalline oxide thin film may consist essentially of elements selected from In, Mg, Al, Si, Zn, Ga, Mo, Sn, Ln elements (lanthanoid elements), and O. Here, "substantially" means that the crystalline oxide thin film according to this embodiment may contain other components as long as the effects of the present invention resulting from the combination of In, Mg, Al, Si, Zn, Ga, Mo, Sn, Ln, and O are achieved.

[0020] In this embodiment, a more preferred first form of the crystalline oxide thin film is one in which the metal elements are composed of In and Ga, and the atomic ratio satisfies the following formula (11): [Ga] / ([In]+[Ga])<22 at% (11). Note that the metal elements may contain inevitable impurities, and may further contain F or H in addition to O. By setting the composition within the above range, the In ratio becomes large, and Ga can be substituted for the In site even during annealing at a low temperature such as 300°C, allowing crystallization into a bixbyite structure. Furthermore, by adding Ga, which has a strong bond with oxygen, oxygen deficiency after annealing can be suppressed, and a stable film as a semiconductor can be formed.

[0021] In this embodiment, a more preferred second form of the crystalline oxide thin film comprises a metal element, In, and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, where X is a metal element other than In, and satisfies the following atomic ratio: [X] / ([In] + [X])<15 at% (12). The metal element may contain unavoidable impurities, and may further contain F or H in addition to O. By setting the composition within the above range, the In ratio is increased, enabling crystallization into a bixbyite structure in which X substitutes for the In site, even with annealing at a low temperature such as 300°C. Furthermore, adding an element X, which has a strong bond with oxygen, suppresses oxygen deficiency after annealing, resulting in the formation of a stable film as a semiconductor.

[0022] In the present embodiment, a more preferred third form of the crystalline oxide thin film is composed of metal elements In, Ga, and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, and when a metal element other than In or Ga is designated as an additional element X, the atomic ratios satisfy the following formulas (13) and (14): [Ga] / ([In]+[Ga]+[X])<22.5 at% (13) [X] / ([In]+[Ga]+[X])<8.0 at% (14) The metal elements may contain inevitable impurities, and may further contain F or H in addition to O. By setting the composition in the above range, the In ratio becomes large, and crystallization into a bixbyite structure in which Ga substitutes for the In site can be achieved even by annealing at a low temperature such as 300° C. Furthermore, by adding an additional element X that has a strong bond with oxygen, oxygen deficiency after annealing can be further suppressed, and a stable film as a semiconductor can be formed.

[0023] In the present embodiment, a fourth more preferable form of the crystalline oxide thin film is composed of metal elements In, Sn, and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, and when a metal element other than In and Sn is defined as element X, the atomic ratios satisfy the following formulas (15) and (16): [Sn] / ([In]+[Sn]+[X])<20 at% (15) [X] / ([In]+[Sn]+[X])<8.0 at% (16) The metal elements may contain inevitable impurities, and may further contain F or H in addition to O. By setting the composition in this range, the In ratio becomes large, and even when annealed at a low temperature such as 300°C, crystallization can be achieved into a bixbyite structure in which Sn substitutes for the In site. Sn has a large ionic radius and a large overlap of its orbital with In, so high mobility can be maintained. Furthermore, by adding an additional element X that has a strong bond with oxygen, oxygen deficiency after annealing can be further suppressed, and a stable film can be formed as a semiconductor.

[0024] In the present embodiment, a more preferable fifth form of the crystalline oxide thin film is composed of metal elements In, Zn, and one or more elements X selected from B, Al, Sc, Mg, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, and when a metal element other than In and Zn is element X, the atomic ratios satisfy the following formulas (17) and (18): [Zn] / ([In]+[Zn]+[X])<12 at% (17) [X] / ([In]+[Zn]+[X])<8.0 at% (18) The metal elements may contain inevitable impurities, and may further contain F or H in addition to O. By setting the composition within the above range, the In ratio becomes large, and even when annealed at a low temperature such as 300°C, the film can be crystallized into a bixbyite structure in which Zn substitutes for the In site. By adding Zn, the film can be made amorphous immediately after deposition, and can be processed without leaving any residue when semiconductor patterning is performed with acid during TFT fabrication. Furthermore, by adding an additional element X that has a strong bond with oxygen, oxygen deficiency after annealing can be suppressed, and a stable film can be formed as a semiconductor.

[0025] The content (atomic ratio) of each metal element in the crystalline oxide thin film can be determined by measuring the amount of each element by ICP (Inductive Coupled Plasma) measurement or XRF (X-ray Fluorescence) measurement. For ICP measurement, an inductively coupled plasma optical emission spectrometer (ICP-OES, manufactured by Agilent) can be used. For XRF measurement, a thin film X-ray fluorescence spectrometer (AZX400, manufactured by Rigaku Corporation) can be used.

[0026] Furthermore, the content (atomic ratio) of each metal element in a crystalline oxide thin film can be analyzed with an error accuracy of 2 atomic percent or less by TEM-EDS measurement using an electron microscope, ICP measurement using an inductively coupled plasma optical emission spectrometer, and SIMS analysis using a sector-type dynamic secondary ion mass spectrometer. First, the metal elements in the crystalline oxide thin film are identified by cross-sectional TEM-EDS, and the composition ratio is identified within an error range of approximately 10 atomic percent by semi-quantitative analysis. Next, standard oxide thin films are prepared from the semi-quantitative analysis results, each consisting of 10 different composition ratios with known atomic ratios of metal elements within a 20 atomic percent range. For the standard oxide thin films, the values ​​measured using an inductively coupled plasma optical emission spectrometer or a thin-film X-ray fluorescence analyzer are used as absolute values ​​of the composition ratio. Furthermore, source and drain electrodes formed of the same material and with the same channel length as the TFT element are fabricated on the top surface of the standard oxide thin film, and using this as the standard material, the oxide semiconductor layer is analyzed using a sector-type dynamic secondary ion mass spectrometer SIMS (IMS 7f-Auto, manufactured by AMETEK Corporation) to obtain the mass spectral intensity of each element, and a calibration curve of known element concentrations and mass spectral intensities is prepared. Next, the oxide thin film portion of the actual TFT element removed from the panel is analyzed using the sector-type dynamic secondary ion mass spectrometer to obtain the spectral intensities. Using the above-mentioned calibration curve, the atomic ratio is calculated from the spectral intensities obtained by SIMS analysis using the sector-type dynamic secondary ion mass spectrometer. The calculated atomic ratio can be confirmed to an accuracy of within 2 atomic % of the atomic ratio of the oxide thin film measured separately using a thin film fluorescent X-ray analyzer or an inductively coupled plasma optical emission analyzer.

[0027] The crystalline oxide thin film according to this embodiment has a low resistance region A and a high resistance region B, which have different spreading resistance values ​​measured by a scanning spreading resistance microscope (SSRM), in the surface direction of the crystalline oxide thin film. Ａ The spreading resistance R of the high resistance region B Ｂ The ratio (R Ｂ / R Ａ ) is 8 times or more. Ｂ / R Ａ is preferably 10 times or more, and more preferably 15 times or more. Ｂ / R ＡThe larger R is, the more sufficient the energy barrier formed between the low resistance region A and the high resistance region B is, so that when the crystalline oxide thin film is used in the channel layer of a TFT, the DIBL phenomenon can be suppressed and the TFT characteristics become stable. Ｂ / R Ａ There is no particular upper limit to the R ratio, but it is, for example, 100,000 times or less, and may be 10,000 times or less. Ｂ / R Ａ If the resistance R is too large, the energy barrier between the low resistance region A and the high resistance region B becomes too large, which acts as an electron injection barrier when a voltage Vd is applied between the source electrode and the drain electrode, resulting in a decrease in the mobility of the TFT. Note that the "high" and "low" in "resistance" refer to the relative high and low spreading resistance values ​​between region A and region B. The spreading resistance R of the low resistance region A is Ａ is 1 Ω or more, 1 x 10 ６ Ω or less is preferred.

[0028] The low-resistance region A can be formed by reducing the resistance of a target portion of the crystalline oxide thin film by, for example, heat treatment (annealing) in the presence of indium-tin oxide (ITO), indium zinc oxide (IZO), aluminum, etc., plasma treatment, or ion implantation. The region that is not subjected to the resistance-reducing treatment becomes the high-resistance region B.

[0029] In one embodiment, the thickness of the crystalline oxide thin film is preferably 80 nm or less. A thickness of 80 nm or less facilitates the effect of the resistance reduction treatment, and the crystals of the crystalline oxide thin film tend to form columnar single-layer crystals. The thickness of the crystalline oxide thin film is preferably 60 nm or less, more preferably 50 nm or less, and particularly preferably 40 nm or less. Meanwhile, the thickness of the crystalline oxide thin film is, for example, 3 nm or more, and may be 5 nm or more, or 10 nm or more. By making the thickness of the crystalline oxide thin film 3 nm or more, high-quality crystals can be grown without being affected by the underlayer during annealing crystallization. In this specification, the thickness is measured based on a cross-sectional TEM observation image (sometimes referred to as a "cross-sectional TEM image").

[0030] In one embodiment, the dC / dV value measured by scanning capacitance microscopy (SCM) is such that the dC / dV value at the boundary between the low-resistance region A and the high-resistance region B is greater than the dC / dV value in the high-resistance region B. This results in a continuous change in carrier concentration at the boundary between the low-resistance region A and the high-resistance region B, and therefore no electrical potential barrier exists between the source and drain when the TFT is driven (here, Vg > 0, and electrons are accumulated at the interface between the gate insulating film and the channel layer), resulting in high mobility characteristics. The SCM measurement conditions will be described in detail in the Examples.

[0031] In one embodiment, the average grain boundary angle θ between the bottom surface of the crystalline oxide thin film and the grain boundaries in the thin film is preferably 70° or more and 110° or less. This prevents the grain boundaries from being too tilted relative to the electrode surface, even in small TFTs with a short contact region with the electrode, allowing the grain boundaries to be densely packed in the longitudinal direction of the contact region. As a result, TFTs having the crystalline oxide thin film according to this embodiment exhibit better mobility.

[0032] The average grain boundary angle θ between the thin film surface and the grain boundaries in the thin film is measured based on a cross-sectional TEM observation image (sometimes referred to as a "cross-sectional TEM image"). That is, it is calculated by analyzing the angle between the grain boundaries and the thin film surface observed in a cross-sectional TEM under magnification using a transmission electron microscope.

[0033] In one embodiment, the average spacing D between grain boundaries in the crystalline oxide thin film is preferably 0.01 μm or more and 2.0 μm or less. This allows a small TFT having the crystalline oxide thin film of this embodiment to exhibit high mobility and achieve uniform mobility and threshold voltage (Vth) characteristics relative to the device shape. As a result, when the TFT is incorporated into a circuit and used to drive a display, a high-resolution display can be achieved without uneven brightness or image retention. The average spacing D between grain boundaries in the thin film is measured based on cross-sectional TEM observation images. The measurement conditions are described in detail in the Examples.

[0034] In one embodiment, the crystalline oxide thin film contains crystal grains that have a bixbyite structure as determined by electron diffraction. Because the bixbyite structure crystal grains have a cubic crystal structure with good symmetry, degradation of TFT characteristics (mobility) can be suppressed even when the crystal grain boundaries are crossed.

[0035] (2) Second embodiment of crystalline oxide thin film The crystalline oxide thin film of this embodiment is a crystalline oxide thin film containing In as a main component and having a film thickness of 80 nm or less. The crystalline oxide thin film has a high carrier concentration region A and a low carrier concentration region B with different carrier concentrations in the in-plane direction of the crystalline oxide thin film, and the carrier concentration in the high carrier concentration region A is 10 １９ cm －３ That's it, 10 ２２ cm －３ or less, and the carrier concentration of the high carrier concentration region A is 8 times or more than the carrier concentration of the low carrier concentration region B. It is preferably 10 times or more, more preferably 15 times or more, and even more preferably 100 times or more. By increasing the difference in carrier concentration, an energy barrier between the low resistance region and the high resistance region is formed, and when applied to a TFT channel and driven, the DIBL phenomenon is less likely to occur, and stable TFT characteristics are obtained.

[0036] In this embodiment, instead of the low resistance region A and high resistance region B of the crystalline oxide thin film of the first embodiment, the crystalline oxide thin film is defined by a high carrier concentration region A and a low carrier concentration region B. The high carrier concentration region A corresponds to the low resistance region A, and the low carrier concentration region B corresponds to the high resistance region B.

[0037] In this embodiment, the film thickness of the crystalline oxide thin film is 80 nm or less. A film thickness of 80 nm or less makes it easier for the effect of the resistance-reducing treatment to be realized, and the crystals of the crystalline oxide thin film tend to become columnar single-layer crystals. As in the first embodiment, the film thickness of the crystalline oxide thin film is preferably 60 nm or less, more preferably 50 nm or less, and particularly preferably 40 nm or less. On the other hand, the film thickness of the crystalline oxide thin film is, for example, 3 nm or more, and may be 5 nm or more, or 10 nm or more.

[0038] The carrier concentration in the high carrier concentration region A is 10 １９ cm －３ That's it, 10 ２２ cm －３ is less than or equal to 10 １９ cm －３ That's it, 10 ２1 cm －３ The following is preferable: As a result, the conductivity of the low resistance region is sufficiently high, and when used in a crystalline oxide thin film under the source and drain electrodes of a self-aligned TFT, and in a crystalline oxide thin film located from the end of the source and drain electrodes to the intersection of a perpendicular line drawn from the end of the gate electrode in the thickness direction with the crystalline oxide thin film, the thin film does not become a resistance component when the TFT is driven, and a high-mobility TFT can be realized.

[0039] In one embodiment, the carrier concentration of the low carrier concentration region B is 10 １５ cm －３ That's it, 10 １９ cm －３ As a result, when the low carrier concentration region B is used in the crystalline oxide thin film region under the gate electrode and gate insulating film of a self-aligned TFT, Vth approaches 0 V in the Id-Vg curve when Vd = 0.1 V is applied and the TFT is driven, and good performance of normally-off characteristics is exhibited. The carrier concentration can be determined by Hall effect measurement as will be explained in the examples.

[0040] The constituent elements, manufacturing method, preferred ranges, etc. of the crystalline oxide thin film according to this embodiment are the same as those of the first embodiment. Furthermore, the laminate, TFT, electronic circuit, electrical device, electronic device, vehicle, and power engine described below are explained for the crystalline oxide thin film of the first embodiment, but can also be applied to the second embodiment. Specifically, by replacing the low-resistance region A with the high-carrier-concentration region A and the high-resistance region B with the low-carrier-concentration region B, an application example of the second embodiment is obtained.

[0041] (3) Third embodiment of crystalline oxide thin film The crystalline oxide thin film of this embodiment is a crystalline oxide thin film containing In as a main component, having a film thickness of 80 nm or less, an average distance D between crystal grain boundaries of the crystalline oxide thin film being 2 μm or less, and a carrier concentration of 10 １９ cm －３That's it, 10 ２２ cm －３ The crystalline oxide thin film of this embodiment has the high carrier concentration region A of the crystalline oxide thin film of the second embodiment. The constituent elements, manufacturing method, suitable ranges, etc. of the crystalline oxide thin film of this embodiment are the same as those of the first and second embodiments.

[0042] 2. Laminate The laminate according to this embodiment includes the crystalline oxide thin film according to the embodiment described above and a lower layer supporting the crystalline oxide thin film. Fig. 1 is a cross-sectional schematic diagram of an example of the laminate according to this embodiment. The laminate 10 includes a crystalline oxide thin film 11 and a lower layer 12 supporting the crystalline oxide thin film 11. The crystalline oxide thin film 11 includes one high-resistance region B (11B) in the planar direction and two low-resistance regions A (11A) sandwiching the high-resistance region B (11B).

[0043] The crystalline oxide thin film and laminate according to this embodiment are not limited in configuration as long as the crystalline oxide thin film has a high-resistance region B and a low-resistance region A. Fig. 2 is a cross-sectional schematic diagram of a laminate according to another embodiment. The laminate 20 has a crystalline oxide thin film 11 and a lower layer 12 that supports the crystalline oxide thin film 11. In the laminate 20, the crystalline oxide thin film 11 has high-resistance regions B (11B) and low-resistance regions A (11A) formed alternately in the surface direction.

[0044] In the laminates 10 and 20, the lower layer 12 is a single layer, but is not limited to this and may be a laminate of two or more layers. Examples of the lower layer 12 include a substrate, a buffer layer, an insulating layer, an electrode, a write shield layer, etc. Each of these may be composed of two or more layers.

[0045] In the laminate according to this embodiment, the average grain boundary angle θ between the surface of the lower layer and the grain boundary in the crystalline oxide thin film ｓｕｂ The average grain boundary angle θ between the surface of the lower layer and the grain boundaries in the crystalline oxide thin film is preferably 70° or more and 110° or less. ｓｕｂBy satisfying the above range, it is possible to make the crystal grain boundaries densely present on the surface of the lower layer with which the crystalline oxide thin film is in contact. As a result, when the crystalline oxide thin film is in contact with an electrode (e.g., a source electrode) as the lower layer, the crystal grain boundaries are densely present on the electrode surface. As a result, even when the contact area with the electrode is narrow (e.g., in a small TFT), electron injection into the crystalline oxide thin film can be ensured, and a decrease in mobility can be suppressed.

[0046] (Method for manufacturing crystalline oxide thin film and laminate) The crystalline oxide thin film of this embodiment and a laminate including the crystalline oxide thin film can be manufactured by depositing a thin film containing an oxide of In as a main component on, for example, a substrate, a buffer layer, an insulating layer, or a lower layer constituting a TFT, and then performing the above-described resistance reduction treatment on the desired portion. The deposition method is not particularly limited, and examples thereof include DC sputtering, AC sputtering, RF sputtering, ICP sputtering, reactive sputtering, ion plating, ALD, PLD, MO-CVD, ICP-CVD, a sol-gel method, a coating method, and mist CVD. When depositing a film by sputtering, the film may be deposited using a planar sputtering cathode apparatus or a rotary sputtering cathode apparatus.

[0047] As an example of a film formation method, a film can be formed by DC sputtering using a sputtering target containing an oxide sintered body mainly composed of In oxide, and then the desired portion is subjected to the above-mentioned resistance reduction treatment. The atomic composition ratio of the crystalline oxide thin film obtained by the sputtering method reflects the atomic composition ratio of the oxide sintered body in the sputtering target. Therefore, it is preferable to form the film using a sputtering target containing an oxide sintered body having an atomic composition ratio similar to that of the desired oxide thin film.

[0048] Furthermore, after forming the thin film, a heat treatment may be carried out before the resistance reduction treatment. The heat treatment process is not particularly limited, but a hot air oven, an IR oven, a lamp annealing device, a laser annealing device, a thermal plasma device, etc. may be used. After further annealing, N may be added before the resistance reduction treatment. ２Plasma oxidation treatment using O or O ２ The plasma oxidation treatment may be performed by using a plasma oxidizing device such as PE-CVD, although the device is not particularly limited.

[0049] The target used in the sputtering method preferably contains 500 ppm or less of impurity metals, more preferably 100 ppm or less. The content of impurity metals in the target can be measured by ICP or SIMS, as with crystalline oxide thin films. "Impurities" contained in the target refer to trace elements that are mixed in with raw materials or during the manufacturing process and are not intentionally added, and do not substantially affect the performance of the target or semiconductor. "Impurity metals" refer to metal elements among the elements considered as "impurities."

[0050] In this embodiment, the sputtering target may consist essentially of In and an element selected from Mg, Al, Si, Zn, Ga, Mo, Sn, Ln elements (lanthanoid elements), and O. Here, "substantially" means that the sputtering target may contain other components in addition to the above-mentioned In, as long as the effects of the present invention resulting from the combination of Mg, Al, Si, Zn, Ga, Mo, Sn, Ln, and O are achieved.

[0051] As with the above-described crystalline oxide thin film of the present invention, in this embodiment, a more preferred first form of the sputtering target is an oxide containing metal elements In and Ga, and the atomic ratio satisfies the following formula (11): [Ga] / ([In]+[Ga])<22 at% (11).

[0052] A more preferred second embodiment of the sputtering target is an oxide composed of a metal element In and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, where X represents a metal element other than In, and the atomic ratio satisfies the following formula (12): [X] / ([In]+[X])<15 at% (12).

[0053] A more preferred third embodiment of the sputtering target is an oxide composed of metal elements In, Ga, and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, wherein when a metal element other than In or Ga is an additional element X, the atomic ratios satisfy the following formulas (13) and (14): [Ga] / ([In]+[Ga]+[X])<22.5 at% (13) [X] / ([In]+[Ga]+[X])<8.0 at% (14).

[0054] A more preferred fourth embodiment of the sputtering target is an oxide comprising metal elements In, Sn, and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, wherein when a metal element other than In and Sn is defined as element X, the atomic ratios satisfy the following formulas (15) and (16): [Sn] / ([In]+[Sn]+[X])<20 at% (15) [X] / ([In]+[Sn]+[X])<8.0 at% (16).

[0055] A more preferred fifth embodiment of the sputtering target is an oxide comprising metal elements In, Zn, and one or more elements X selected from B, Al, Sc, Mg, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, wherein, when a metal element other than In and Zn is element X, the atomic ratios satisfy the following formulas (17) and (18): [Zn] / ([In]+[Zn]+[X])<12 at% (17) [X] / ([In]+[Zn]+[X])<8.0 at% (18).

[0056] The oxide thin film obtained by sputtering using a sputtering target containing indium oxide as the main component is an amorphous oxide thin film. This oxide thin film is patterned into islands by photolithography, and then heated and crystallized before forming a protective film, resulting in a crystalline oxide thin film with surface crystals having a single crystal orientation. Each step is explained below.

[0057] (Oxide thin film formation process) In the oxide thin film formation process, the sputtering target described above is used, and an oxide thin film is formed by sputtering using one or more gases selected from the group consisting of argon and oxygen, which are substantially free of impurity gases, as a sputtering gas. In this process, it is preferable to mount the sputtering target in an RF magnetron sputtering device or a DC magnetron sputtering device and perform sputtering.

[0058] The phrase "the sputtering gas is substantially free of impurity gases" means that impurity gases other than the sputtering gas are not actively introduced, except for adsorbed water brought in with the introduction of gas, and gases that cannot be eliminated (unavoidable impurity gases) such as gases leaking from the chamber or adsorbed gases. If possible, impurities are preferably excluded from the gas (sputtering gas) introduced during sputtering film formation.

[0059] The proportion of impurity gas in the sputtering gas is preferably 0.1% by volume or less, and more preferably 0.05% by volume or less. If the proportion of impurity gas is 0.1% by volume or less, crystallization of the oxide thin film proceeds without any problems. The purity of high-purity argon and high-purity oxygen, which are examples of sputtering gases, is preferably 99% by volume or more, more preferably 99.9% by volume or more, and even more preferably 99.99% by volume or more.

[0060] The gas (sputtering gas) introduced during sputtering deposition is not particularly limited, and examples include argon, nitrogen, oxygen, water, hydrogen, and a mixed gas containing two or more of these gases. For example, when argon and oxygen are used, the oxygen partial pressure in the mixed gas is preferably greater than 0 vol% and less than 50 vol%, more preferably greater than 0 vol% and less than 20 vol%. When the oxygen partial pressure is greater than 0 vol% and less than 50 vol%, the oxide thin film easily crystallizes and becomes a semiconductor upon heating. By changing the oxygen partial pressure, the degree of oxidation of the oxide thin film, i.e., the degree of crystallization, can be adjusted. The oxygen partial pressure can be appropriately selected as needed. For example, when argon and water are used, the water pressure in the mixed gas is preferably greater than 0.03 vol% and less than 10 vol%, more preferably greater than 0.03 vol% and less than 5 vol%. When the water pressure is greater than 0.03 vol% and less than 5 vol%, the oxide thin film easily crystallizes and becomes a semiconductor upon heating. Alternatively, a mixed gas of hydrogen and oxygen may be used instead of water.

[0061] The crystalline oxide thin film according to this embodiment preferably contains In as a main component. By heating this oxide thin film in a heat treatment process described below, columnar crystals can be grown in the lower layer. By applying the oxide thin film formed as described above to a small TFT, the electron carrier injection property is excellent during operation, resulting in high mobility, and uniform characteristics of mobility and threshold voltage (Vth) depending on the device shape can be obtained.

[0062] (Step of forming TFT constituent layers) When forming TFT constituent layers such as an insulating layer on a crystalline oxide thin film, it is preferable to form the constituent layers on the oxide thin film after subjecting the obtained oxide thin film to heat treatment. By performing annealing before forming the TFT constituent layers, oxygen and hydrogen are diffused during annealing, resulting in columnar, high-quality crystals, and a small TFT with few interfacial electron trap levels and high mobility can be obtained after forming the constituent layers.

[0063] (Heat Treatment Step) After the oxide thin film is formed, a heat treatment is performed. This heat treatment is sometimes called annealing. The heat treatment temperature is preferably 250°C or higher and 500°C or lower, more preferably 280°C or higher and 470°C or lower, and even more preferably 300°C or higher and 450°C or lower. If the heat treatment temperature after the oxide thin film formation is 250°C or higher, the oxide thin film is likely to crystallize. If the heat treatment temperature after the oxide thin film formation is 500°C or lower, abnormal crystal growth and enlargement of the crystal grains can be prevented, and the crystal grain size can be controlled to be small.

[0064] The heating time in the heat treatment step is preferably 0.1 to 5 hours, more preferably 0.3 to 3 hours, and even more preferably 0.5 to 2 hours. If the heating time in the heat treatment step is 0.1 hours or more, the oxide thin film is likely to crystallize without failure to crystallize. If the heating time in the heat treatment step is 5 hours or less, it is economically efficient. "Heating time" refers to the time during which a predetermined maximum temperature is maintained (retention time) during heat treatment.

[0065] The temperature rise rate in the heat treatment step is preferably 2°C / min or more and 40°C / min or less, and more preferably 3°C / min or more and 20°C / min or less. If the temperature rise rate in the heat treatment step is 2°C / min or more, the production efficiency of the oxide thin film is improved compared to when it is less than 1°C / min. If the temperature rise rate in the heat treatment step is 40°C / min or less, the metal elements are uniformly diffused during crystallization, and crystals can be formed in which metal is not segregated at grain boundaries. Furthermore, the temperature rise rate in the heat treatment step is different from a value calculated from the set temperature and set time of the furnace, but is a value obtained by dividing the actual temperature of the oxide thin film by time. The actual temperature of the oxide thin film can be determined, for example, by measuring an area within 1 cm of the oxide thin film in the furnace with a thermocouple.

[0066] The heat treatment step is preferably carried out in an air atmosphere with a humidity of 10% or more at 25° C. By carrying out the heat treatment step in an air atmosphere with a humidity of 10% or more, hydrogen and oxygen can be diffused into the film during annealing, thereby promoting crystallization.

[0067] The heat treatment step is preferably carried out after patterning the oxide thin film. By carrying out the heat treatment step after patterning, crystallization can be promoted while removing excess oxygen present in the film during film formation and organic substances that adhere during patterning. As a result, a film with few crystal defects and no organic substances or excess oxygen within the crystal grains can be formed, and an oxide thin film with few electron traps and good conductivity can be formed.

[0068] Crystal defects in the film after heat treatment can be evaluated by defect analysis such as cathodoluminescence (CL). When there are many defects due to oxygen, strong light emission at 680 nm is detected. In order to obtain an oxide thin film with few electron traps and good conductivity, it is necessary to adjust the film formation method and annealing conditions so that the film quality is such that CL emission is not detected as much as possible.

[0069] The heat treatment step may be performed multiple times. For example, the above-mentioned heat treatment step (first heat treatment step) may be performed after patterning the oxide thin film, and then, after fabricating the TFT element, a heat treatment step (second heat treatment step) may be performed as a final step. The second heat treatment step is preferably performed at a higher annealing temperature than the first heat treatment step.

[0070] (Resistance Reduction Treatment Step) A low resistance region A and a high resistance region B are formed in the crystalline oxide thin film obtained in the heat treatment step. The low resistance region A can be formed by, but is not limited to, reducing the resistance of a target portion of the crystalline oxide thin film by a dry process such as heat treatment (annealing) in the presence of indium tin oxide (ITO), aluminum, etc., plasma treatment, or ion implantation. The region not subjected to the resistance reduction treatment becomes the high resistance region B.

[0071] When forming the low-resistance region A by annealing in the presence of ITO, an ITO layer is formed by sputtering or the like on the crystalline oxide thin film of the region to be made low-resistance, and then annealed at a temperature of 250° C. to 500° C. (preferably 280° C. to 470° C., more preferably 300° C. to 450° C.) for 0.1 to 5 hours. After annealing, the ITO layer may be removed by etching, or may be left in place.

[0072] When forming the low-resistance region A by annealing in the presence of aluminum, an aluminum layer is formed by sputtering or the like on the crystalline oxide thin film of the region to be made low-resistance, and then annealed at a temperature of 250° C. to 500° C. (preferably 280° C. to 470° C., more preferably 300° C. to 450° C.) for 0.1 to 5 hours. After annealing, aluminum may remain or aluminum oxide may be formed. In either case, the aluminum or aluminum oxide layer may be removed by etching or may be left.

[0073] When forming the low resistance region A by plasma treatment, the crystalline oxide thin film obtained by the heat treatment step is treated. The gas used for the plasma treatment is not particularly limited, but H ２ , He, Ar, N ２ , F-based gases, etc. Generally, elements with small ionic radii are preferred for use in plasma treatment. Plasma treatment using these elements generates oxygen vacancies in the crystalline oxide thin film, increasing the carrier concentration and lowering the resistance.

[0074] When forming the low resistance region A by ion implantation, there are two ways: ion implantation directly into the crystalline oxide thin film obtained by the heat treatment process, and ion implantation through a gate insulating film or an interlayer insulating film formed on the oxide thin film. The ions used for implantation are not particularly limited, but H ＋ , He ＋ , B ＋ , N ＋ , F ＋ , PHx ＋ , Ar ＋ The element may be any element that generates oxygen vacancies by ion implantation or an element that releases electrons and acts as a donor when left in the film. The element may or may not remain in the film.

[0075] In one embodiment, the resistance reduction process is preferably performed after the formation of the gate insulating film and / or gate electrode. Specifically, the gate insulating film and / or gate electrode can be used instead of a mask (self-alignment) to form the low resistance region A and the high resistance region B. For example, when the above-mentioned ITO layer is used, the region of the crystalline oxide thin film where the ITO layer is directly stacked becomes the low resistance region A, and the region below the gate insulating film and / or gate electrode becomes the high resistance region B.

[0076] 3. Thin Film Transistor (TFT) The TFT according to this embodiment includes the above-described crystalline oxide thin film or laminate of the present invention. Preferably, the crystalline oxide thin film of the present invention is used as the channel layer of the TFT. More preferably, both ends of the channel layer, i.e., near the regions where the source electrode and drain electrode are connected, are low-resistance regions A of the crystalline oxide thin film, and the region in contact with the underside of the gate insulating film is high-resistance region B.

[0077] In one embodiment, the TFT has a channel layer, a source electrode and a drain electrode connected to both ends of the channel layer, respectively, and a gate electrode laminated on the channel layer via a gate insulating film, the channel layer being a crystalline oxide thin film, and having a structure in which a gate insulating film is formed in a high resistance region B and the source electrode and the drain electrode are formed in a low resistance region A. The distance L from the end of the source electrode and the end of the drain electrode to the intersection of a perpendicular line drawn from the end of the gate electrode in the thickness direction and the crystalline oxide thin film is ｏｆｆ However, the thickness is 4 μm or more and 20 μm or less.

[0078] In addition, the average distance D between the crystal grain boundaries of the crystalline oxide thin film and the distance L ｏｆｆ satisfies the following formula (1): 2≦L ｏｆｆ / D≦100 (1)

[0079] In one embodiment, the TFT has a contact region length Ls between the source and drain electrodes and the channel layer of 4 μm or more and 20 μm or less. Furthermore, the average distance D between the crystal grain boundaries of the crystalline oxide thin film and the contact region length Ls satisfy the following formula (2): 1≦Ls / D≦100 (2). This allows the TFT to exhibit excellent mobility even when the contact regions between the source and drain electrodes and the channel layer are small.

[0080] TFTs fabricated using conventional technology use a crystalline oxide thin film to achieve high mobility, but the source and drain electrodes are formed on the oxide thin film using a metal mask, resulting in a contact area length of about 100 μm between the source electrode and the oxide thin film. Therefore, even if the crystal grain size in the oxide thin film is 1 μm or more, there are about 100 crystal grain boundaries in the contact area with the source electrode, and a sufficient number of crystal grain boundaries, which are conductive regions, are in contact with the source electrode, so this has not been a major problem in terms of mobility.

[0081] In addition, in conventional technology, parasitic capacitance occurs in the overlapping regions between the gate electrode and the source and drain electrodes. However, this was not a major problem because high resolution, high-speed operation, and large area displays were not required. However, in recent years, high resolution, high-speed operation, and large area displays have been required for OLED and other displays. In the trend toward higher resolution, TFT size has been reduced to increase the aperture ratio of pixel circuits. Therefore, it is necessary to control the characteristics of small TFTs patterned by photolithography, rather than the conventional method of film formation using a metal mask. Furthermore, in the trend toward higher resolution, higher speed, and larger area displays, it is necessary to reduce parasitic capacitance in the backplane drive circuit to eliminate RC delay, which is a delay in the time from input to drive due to the influence of parasitic resistance and parasitic capacitance. It is also necessary to minimize the variation in parasitic capacitance to eliminate uneven brightness of each OLED pixel.

[0082] To solve these problems simultaneously, a self-aligned TFT structure is effective. In this structure, the gate electrode is used as a mask to selectively reduce the resistance of the semiconductor, and these regions are used as the source and drain regions. When an oxide thin film is applied to a self-aligned and compact TFT structure (self-aligned compact TFT structure), the contact area between the source electrode and the crystalline oxide thin film is shortened. Furthermore, the distance between the edge of the source electrode and the edge of the drain electrode and the perpendicular line drawn from the edge of the gate electrode in the thickness direction and the crystalline oxide thin film is shortened.

[0083] In order to apply a high-mobility crystalline oxide thin film to a self-aligned small TFT structure, achieve sufficient mobility, and stably control the threshold voltage (Vth), it is necessary to have a sufficient number of crystal grain boundaries in the region from the end of the source electrode and the end of the drain electrode to the intersection of the crystalline oxide thin film and a perpendicular line drawn from the end of the gate electrode in the thickness direction. ｏｆｆ , the contact region length Ls, and the formulas (1) and (2) are satisfied, the mobility is excellent and the Vth can be stably controlled.

[0084] In one embodiment, the horizontal gap ΔL between the low resistance region A and the gate electrode is less than 1 μm. The crystalline oxide thin film of the present invention is suitable for self-aligned TFTs, so the gap ΔL can be made extremely small.

[0085] The TFT according to this embodiment can be configured using, for example, a conventionally known configuration. The TFT according to this embodiment can be manufactured by employing the above-described method for manufacturing a crystalline oxide thin film and a laminate. That is, the manufacturing method includes a step of forming an oxide thin film by sputtering using a sputtering target and one or more gases selected from the group consisting of argon, nitrogen, hydrogen, water, and oxygen, which are substantially free of impurity gases, as a sputtering gas (sometimes referred to as a film formation step), and a step of subjecting the oxide thin film to a heat treatment (sometimes referred to as a heat treatment step). The conditions for the film formation step and the heat treatment step are as described above. The source electrode, the drain electrode, the gate electrode, and the gate insulating film can be formed using known materials and methods.

[0086] The crystalline oxide thin film according to one embodiment has high mobility in the direction parallel to the film surface. By using such a crystalline oxide thin film in the oxide semiconductor layer (channel layer) or conductive region of a small self-aligned TFT, high mobility and stable control of Vth are possible. Here, the mobility when Vd = 0.1 V is determined as linear mobility, and the mobility when Vd = 20 V is defined as saturated mobility. Specifically, the mobility can be calculated by creating a transfer characteristic Id-Vg graph when each Vd is applied, calculating the transconductance (Gm) for each Vg, and then using the equation for the linear or saturated region to determine the mobility. The current Id is the current between the source electrode and the drain electrode, the voltage Vd is the voltage applied between the source electrode and the drain electrode (drain voltage), and the voltage Vg is the voltage applied between the source electrode and the gate electrode (gate voltage). The mobility is 20 cm ２ / (V·s) or more, and the higher the value, the more preferable.

[0087] Furthermore, the crystalline oxide thin film according to one embodiment can be used to form a Schottky barrier diode, MES-FET, or the like by arranging an ohmic electrode of metal, ITO, IZO, or the like on one surface of the high-resistance region B and arranging a Schottky electrode of metal, oxide, or the like with a work function of 4.8 eV or more on the other surface.

[0088] The shape of the thin film transistor according to this embodiment is not particularly limited as long as it is a self-aligned type, but a top gate type transistor, a back channel etch type transistor, an etch stopper type transistor, or the like is preferred.

[0089] Hereinafter, embodiments will be described with reference to the drawings, etc. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0090] In the drawings, sizes, layer thicknesses, regions, etc. may be exaggerated for clarity. Therefore, the present invention is not limited to the illustrated sizes, layer thicknesses, regions, etc. Note that the drawings are schematic illustrations of ideal examples, and the present invention is not limited to the shapes, values, etc. shown in the drawings.

[0091] 3A is a schematic cross-sectional view of an example of a TFT according to this embodiment. The TFT 50 is a top-gate TFT and includes a substrate 21, a buffer layer 22, a channel layer (crystalline oxide thin film) 11, an ITO layer 23, a gate insulating film 24, a gate electrode 25, an interlayer insulating film 26, a source electrode 27, a drain electrode 28, and a protective film 29.

[0092] The TFT 50 has a structure in which a substrate 21, a buffer layer 22, and a channel layer (crystalline oxide thin film) 11 are stacked in this order. A high-resistance region 11B is located in the center of the channel layer 11, and a gate insulating film 24 and a gate electrode 25 are stacked in this order on the high-resistance region 11B. The gate insulating film 24 is an insulating film that blocks electrical conduction between the gate electrode 25 and the crystalline oxide thin film 11. Low-resistance regions 11A-1 and 11A-2 of the channel layer 11 are located on both sides of the high-resistance region 11B. An ITO layer 23 and an interlayer insulating film 26 cover the low-resistance regions 11A-1 and 11A-2 and the gate electrode 25. The ITO layer 23 is used to form the low-resistance region of the channel layer 11. A source electrode 27 and a drain electrode 28 are connected to the low-resistance regions 11A-1 and 11A-2, respectively, via contact holes provided in the ITO layer 23 and the interlayer insulating film 26. The source electrode 27 and the drain electrode 28 are conductive terminals for passing a source current and a drain current to the channel layer 11. A protective film 29 is provided so as to cover the TFT constituent layers, such as the interlayer insulating film 26, the source electrode 27, and the drain electrode 28.

[0093] 3B is an enlarged view of the vicinity of the source electrode in FIG. 3A. In the TFT 50, the distance L from the edge of the source electrode and the edge of the drain electrode to the intersection of the perpendicular line drawn from the edge of the gate electrode in the thickness direction and the crystalline oxide thin film is ｏｆｆ2 illustrates the contact region length Ls between the source electrode (drain electrode) and the channel layer, and the horizontal gap ΔL between the low resistance region A and the gate electrode.

[0094] 4 is a schematic cross-sectional view of another example of a TFT according to this embodiment. The TFT 51 has the same configuration as the TFT 50, except that a write shield layer 31 is provided between the substrate 21 and the buffer layer 22. The write shield layer 31 is formed to prevent the TFT from malfunctioning due to light.

[0095] 5 is a schematic cross-sectional view of another example of a TFT according to this embodiment. The TFT 52 has the same configuration as the TFT 50, except that the ITO layer 23 is not formed. In this example, the low-resistance regions 11A-1 and 11A-2 are formed by, for example, ion implantation or a dry process such as plasma treatment.

[0096] 6 is a schematic cross-sectional view of another example of a TFT according to this embodiment. The TFT 60 has the same configuration as the TFT 50, except that the ITO layer 23 is not formed and the interlayer insulating film 26 has a two-layer structure (interlayer insulating films 26-1 and 26-2). In this example, the region of the interlayer insulating film 26-1 below the gate electrode 25 corresponds to the gate insulating film 24. In this example, the low-resistance regions 11A-1 and 11A-2 are formed by, for example, ion implantation.

[0097] 7 is a schematic cross-sectional view of another example of a TFT according to the present embodiment. The TFT 70 is a bottom-gate TFT and includes a substrate 21, a gate electrode 25, a gate insulating film 24, a channel layer (crystalline oxide thin film) 11, an interlayer insulating film 26, a source electrode 27, a drain electrode 28, and a protective film 29.

[0098] In the TFT 70, a gate electrode 25 is formed on a substrate 21, and a gate insulating film 24 is laminated on the substrate 21 and the gate electrode 25. A channel layer (crystalline oxide thin film) 11 is laminated on the gate insulating film 24, and the region corresponding to the gate electrode 25 is a high-resistance region 11B, with low-resistance regions 11A-1 and 11A-2 of the channel layer 11 on both sides of the high-resistance region 11B. An interlayer insulating film 26 covers the channel layer (crystalline oxide thin film) 11. A source electrode 27 and a drain electrode 28 are connected to the low-resistance regions 11A-1 and 11A-2, respectively, through contact holes provided in the interlayer insulating film 26. A protective film 29 is provided to cover the TFT constituent layers, such as the interlayer insulating film 26, the source electrode 27, and the drain electrode 28.

[0099] The TFT of this embodiment can be improved with a known configuration.

[0100] The material for forming the substrate is not particularly limited, and any commonly used material can be selected. For example, a glass substrate, a ceramic substrate, a quartz substrate, or a sapphire substrate can be used. Alternatively, a single-crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, or an SIO (Silicon In Insulator) substrate can also be used. These substrates on which semiconductor elements are provided may also be used as the substrate.

[0101] A flexible substrate may also be used as the substrate. As a method for providing a TFT on a flexible substrate, in addition to a method for directly fabricating a TFT on a flexible substrate, there is also a method for fabricating a TFT on a non-flexible substrate, and then peeling the TFT and placing it on a flexible substrate. In this case, it is preferable to provide a peeling layer between the non-flexible substrate and the TFT.

[0102] There is no particular limitation on the material for forming the buffer layer 22, and any commonly used material can be selected, or a laminated film can be used. For example, SiO ２ , SiNx, silicon oxynitride, Al ２ O ３ , Ta ２ O ５ , TiO ２ , MgO, ZrO２ , Ga ２ O ３ , GeO ２ , Nd ２ O ３ , La ２ O ３ , CeO ２ , K. ２ O, Li ２ O, Na ２ O, Rb ２ O, Sc ２ O ３ , Y ２ O ３ , HfO ２ , CaHfO ３ , PbTiO ３ ,BaTa ２ O ６ , SrTiO ３ , Sm ２ O ３ , AlN can be used. The oxidation number of each material may vary. The buffer layer 22 can be designed appropriately according to the type of substrate.

[0103] The write shield layer 31 may be connected to either the source electrode 27 or the gate electrode 25. There are no particular restrictions on the material from which the write shield layer can be formed, and any commonly used material can be selected. Specific examples include metal electrodes made of Al, Ag, Cu, Cr, Ni, Co, Mo, Au, Ti, Zr, Ru, Y, Nb, Ta, W, etc., and metal electrodes made of alloys containing two or more of these metals. A laminated electrode with two or more layers can also be used.

[0104] A second buffer layer may be provided between the write shield layer 31 and the substrate 21. There are no particular restrictions on the material for forming the second buffer layer, and any commonly used material may be selected, or a laminated film may be used. For example, SiO ２ , SiNx, silicon oxynitride, Al ２ O ３ , Ta ２ O ５ , TiO ２ , MgO, ZrO ２ , Ga ２ O ３ , GeO２ , Nd ２ O ３ , La ２ O ３ , CeO ２ , K. ２ O, Li ２ O, Na ２ O, Rb ２ O, Sc ２ O ３ , Y ２ O ３ , HfO ２ , CaHfO ３ , PbTiO ３ ,BaTa ２ O ６ , SrTiO ３ , Sm ２ O ３ , AlN can be used. The oxidation number of each material may be varied.

[0105] There is no particular limitation on the material for forming the gate insulating film, and any commonly used material can be selected, and a laminated film can also be used. For example, SiO ２ , SiNx, silicon oxynitride, Al ２ O ３ , Ta ２ O ５ , TiO ２ , MgO, ZrO ２ , Ga ２ O ３ , GeO ２ , Nd ２ O ３ , La ２ O ３ , CeO ２ , K. ２ O, Li ２ O, Na ２ O, Rb ２ O, Sc ２ O ３ , Y ２ O ３ , HfO ２ , CaHfO ３ , PbTiO ３ ,BaTa ２ O ６ , SrTiO ３ , Sm ２ O ３, AlN can be used. The oxidation number of each material may vary.

[0106] In this embodiment, when the TFT is a small TFT, the crystalline oxide thin film serving as a channel layer for the source electrode and the drain electrode has a channel length (L length) of 1 μm or more and 50 μm or less. The channel width is not particularly limited, but is, for example, 1 μm or more and 1000 μm or less.

[0107] There is no particular limitation on the materials for forming the drain electrode, source electrode, and gate electrode, and any commonly used material can be selected. Specifically, ITO, IZO, ZnO, SnO ２ Examples of the electrode include transparent electrodes such as those made of Al, Ag, Cu, Cr, Ni, Co, Mo, Au, Ti, Zr, Ru, Y, Nb, Ta, and W, and metal electrodes made of alloys containing two or more of these metals. Also, a laminated electrode having two or more layers can be used.

[0108] There is no particular limitation on the material for forming each interlayer insulating film, and any commonly used material can be selected, and a laminated film can also be used. For example, SiO ２ , SiN ｘ , silicon oxynitride, Al ２ O ３ , Ta ２ O ５ , TiO ２ , MgO, ZrO ２ , Ga ２ O ３ , GeO ２ , Nd ２ O ３ , La ２ O ３ , CeO ２ , K. ２ O, Li ２ O, Na ２ O, Rb ２ O, Sc ２ O ３ , Y ２ O ３ , HfO ２ , CaHfO ３ , PbTiO ３ ,BaTa ２ O ６, SrTiO ３ , Sm ２ O ３ , AlN, etc. The oxidation number of each material may be varied.

[0109] Regardless of the TFT structure, it is preferable to provide an interlayer insulating film on the drain electrode, source electrode, and conductive region. Furthermore, in the case of a bottom gate type, it is preferable to provide a protective film on the channel layer. By providing a protective film, the durability of the TFT tends to be improved even when driven for a long time.

[0110] There is no particular limitation on the method for producing the insulating films of the buffer layer, gate insulating film, interlayer insulating film, and protective film. Examples of the production method include PE-CVD, ALD, PLD, MO-CVD, RF sputtering, ICP sputtering, reactive sputtering, ICP-CVD, ion plating, the sol-gel method, the coating method, and mist CVD. The gas species used in PE-CVD include silane (SiH ４ Besides, tetraethoxysilane (TEOS) can also be used.

[0111] For example, when forming the gate insulating film by PE-CVD, the process may require high temperatures. Furthermore, since the protective film or insulating film often contains impurity gases immediately after deposition, it is preferable to perform a heat treatment (annealing treatment). By removing the impurity gases through heat treatment, the protective film or insulating film becomes stable, facilitating the formation of highly durable TFTs. Furthermore, by performing annealing after the formation of the gate insulating film, hydrogen contained in the gate insulating film diffuses into the oxide thin film, terminating crystal defects present on the surface of the oxide thin film with hydroxyl groups, resulting in the formation of an oxide thin film with few electron traps and good conductivity.

[0112] By using the crystalline oxide thin film of the present invention, the film is less susceptible to the effects of temperature in the PE-CVD process and subsequent heat treatment, and therefore the stability of TFT characteristics can be improved even when a protective film or insulating film is formed.

[0113] The threshold voltage (Vth) is preferably −3.0 V or more and 3.0 V or less, more preferably −2.0 V or more and 2.0 V or less, and even more preferably −1.0 V or more and 1.0 V or less. When the threshold voltage (Vth) is −3.0 V or more and 3.0 V or less, a Vth correction circuit can be installed in the TFT to correct Vth to 0 V. When the TFT obtained in this way is installed in a panel, it is possible to drive a display without uneven brightness or burn-in.

[0114] The threshold voltage (Vth) is Id = 10 －９ It can be defined as Vg at A. The on-off ratio is 10 ６ That's it, 10 １２ The following is preferred: ７ That's it, 10 １１ More preferably, 10 or less ８ That's it, 10 １０ More preferably, the on-off ratio is 10 or less. ６ If the on-off ratio is 10 or more, the liquid crystal display can be driven. １２ When the on-off ratio is 10 or less, an organic EL element with high contrast can be driven. １２ If the off-state current is 10 －１２ A or less, and when used in the transfer transistor or reset transistor of a CMOS image sensor, it is possible to extend the image retention time and improve the sensitivity.

[0115] The on-off ratio is determined by determining the ratio [on current value / off current value], where the value of Id when Vg = -10 V is the off current value and the value of Id when Vg = 20 V is the on current value. －１０ A or less is preferable, and 10 －１１ A or less is more preferable, and 10 －１２ A or less is more preferable. －１０ When the resistance is A or less, it is possible to drive an organic EL device with high contrast. Furthermore, when used in the transfer transistor or reset transistor of a CMOS image sensor, it is possible to extend the image retention time and improve the sensitivity.

[0116] The TFT according to this embodiment can be suitably used in display elements such as solar cells, liquid crystal elements, organic electroluminescence elements, and inorganic electroluminescence elements, power semiconductor elements, touch panels, and other electronic devices.

[0117] The thin film transistor according to this embodiment can be applied to various integrated circuits such as field-effect transistors, logic circuits, memory circuits, and differential amplifier circuits, and these can be applied to electronic devices, etc. Furthermore, the thin film transistor according to this embodiment can also be applied to static induction transistors and Schottky barrier transistors in addition to field-effect transistors. The thin film transistor according to this embodiment can be suitably used in display devices such as portable or in-vehicle display devices and solid-state imaging devices. Furthermore, the thin film transistor according to this embodiment can also be suitably used as a transistor for flat panel detectors for X-ray image sensors in medical applications. The crystalline oxide thin film according to this embodiment can also be applied to Schottky diodes, resistance change memory, and resistor elements. Below, the use of the thin film transistor according to this embodiment in a display device will be described.

[0118] Fig. 8A is an example of a circuit diagram of a pixel portion when a liquid crystal element is applied. When this is used in a mini LED display, Fig. 8A can be used not only as a liquid crystal control circuit but also as a circuit for controlling an LED chip. Fig. 8B is an example of a circuit diagram of a pixel portion when an organic EL element is applied.

[0119] The pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrodes. Each pixel electrode is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. This allows the signals applied to each pixel electrode of a multi-domain designed pixel to be controlled independently.

[0120] It is sufficient that at least one of the transistors in the circuit diagram uses the TFT according to this embodiment. This makes it possible to provide a highly reliable display device. The circuit diagram is not limited to the configuration shown in FIGS. 8A and 8B. For example, switches, resistive elements, capacitive elements, transistors, sensors, or logic circuits may be added. Furthermore, a display device using the TFT according to this embodiment may be equipped with both a Si-based transistor and the TFT according to this embodiment.

[0121] 8C is a top view of the display device according to this embodiment. The thin film transistor according to this embodiment can be used as a transistor disposed in a pixel portion. Since the thin film transistor according to this embodiment can be easily made into an n-channel type, part of a driver circuit that can be configured with an n-channel transistor is formed on the same substrate as the transistor in the pixel portion. By using the thin film transistor shown in this embodiment in the pixel portion or the driver circuit, a highly reliable display device can be provided.

[0122] 8C shows an example of a top view of an active matrix display device. A pixel portion 301, a first scanning line driver circuit 302, a second scanning line driver circuit 303, and a signal line driver circuit 304 are formed on a substrate 300 of the display device. A plurality of signal lines are arranged in the pixel portion 301, extending from the signal line driver circuit 304, and a plurality of scanning lines are arranged in the pixel portion 301, extending from the first scanning line driver circuit 302 and the second scanning line driver circuit 303. Pixels each having a display element are provided in a matrix at an intersection between the scanning lines and the signal lines. The substrate 300 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) via a connection portion such as an FPC (Flexible Printed Circuit).

[0123] 8C , the first scanning line driver circuit 302, the second scanning line driver circuit 303, and the signal line driver circuit 304 are formed on the same substrate 300 as the pixel portion 301. This reduces the number of components, such as driver circuits, that are provided externally, thereby reducing costs. Furthermore, if the driver circuits are provided externally to the substrate 300, it becomes necessary to extend the wiring, which increases the number of connections between the wiring. If the driver circuits are provided on the same substrate 300, the number of connections between the wiring can be reduced, thereby improving reliability and yield.

[0124] The present invention will be specifically described below based on examples, but the present invention is not limited to these examples.

[0125] [Fabrication of a Self-Aligned Top-Gate Structure Small TFT] Example 1 A thin film transistor (TFT) 53 shown in FIG. 9 was fabricated by the following process. The TFT 53 has the same structure as the TFT 50 shown in FIG. 3A except that it does not have a protective layer 29. (1) Formation of a buffer layer 22: SiO ２ A SiOx layer (buffer layer 22) having a thickness of 300 nm was formed by sputtering on a 4-inch diameter non-alkali glass substrate 21 (EAGLE XG manufactured by Corning Incorporated) using a sputtering target of 1000 nm. The sputtering conditions were as follows: substrate temperature: 25°C; ultimate pressure: 8.5×10 －５ Pa Atmospheric gas: Ar Sputtering pressure (total pressure): 0.4 Pa Input voltage: RF300W Distance between S (substrate) and T (target): 70 mm

[0126] (2) Formation of oxide thin film Next, a channel layer was formed by sputtering using an oxide sputtering target obtained from a raw material mixture having the composition ratio shown in Table 1. The metal composition ratio (unit: at%) in the oxide sputtering target is shown in Table 1. The film formation conditions in sputtering and the thickness of the channel layer are shown in Table 1. The sputtering conditions other than those shown in Table 1 were as follows: Substrate temperature: 25°C Ultimate pressure: 1.0 x 10 －４ Pa Atmospheric gas: Ar and H ２O mixed gas Sputtering pressure (total pressure): 0.5 Pa Input voltage: DC 300 W Distance between S (substrate) and T (target): 70 mm

[0127] (3) Formation of Channel Layer 11 Next, the oxide thin film was patterned into an island shape by photolithography to form the channel layer 11. First, a photoresist film was formed on the oxide thin film. AZ1500 (manufactured by AZ Electronic Materials Co., Ltd.) was used as the photoresist. ｏｆｆ The substrate was exposed to light through a photomask on which a pattern of 20 μm in length and 20 μm in width (×2+Ls×2+2 (both ends)×2) μm was formed. After exposure, the substrate was developed with tetramethylammonium hydroxide (TMAH). After development, the oxide thin film was etched with oxalic acid (ITO-06N, manufactured by Kanto Chemical Co., Ltd.). After etching, the photoresist was peeled off to obtain a substrate 21 with a patterned oxide thin film (channel layer 11). The dimensions of the obtained channel layer 11 were 10 μm in width and 20 μm in length. ｏｆｆ × 2 + Ls × 2 + 2 (both ends) × 2) μm × 20 μm in length.

[0128] (4) Annealing Next, the substrate 21 on which the channel layer 11 was formed was placed in a furnace, and the temperature was raised to 350°C at a rate of 10°C / min in the atmosphere, and then held for 1 hour. After the inside of the furnace was held at 350°C for 1 hour, it was allowed to cool naturally, and after the temperature inside the furnace returned to room temperature, the substrate 21 was taken out of the furnace.

[0129] (5) Formation of gate insulating film 24. Next, SiO ２ The sputtering conditions were as follows: substrate temperature: 25° C., ultimate pressure: 8.5×10 －５ Pa Atmospheric gas: Ar + O ２ Mixture of gases (O ２ Flow rate 30%) Sputtering pressure (total pressure): 0.4 Pa Input voltage: RF100W Distance between S (substrate) and T (target): 70 mm

[0130] (6) Annealing of Gate Insulating Film 24 Next, the substrate 21 was placed in a furnace, and the temperature was raised to 400°C at a rate of 10°C / min in the atmosphere, and then held for 1 hour. The inside of the furnace was held at 400°C for 1 hour, and then naturally cooled. After the temperature inside the furnace returned to room temperature, the substrate 21 was removed from the furnace.

[0131] (7) Formation of gate insulating film 24 Next, SiO ２ A SiOx layer (gate insulating film 24) having a thickness of 100 nm was formed by sputtering using a sputtering target of 100 nm. The sputtering conditions were as follows: substrate temperature: 25° C., ultimate pressure: 8.5×10 －５ Pa Atmospheric gas: Ar + O ２ Mixture of gases (O ２ Flow rate: 30%) Sputtering pressure (total pressure): 0.4 Pa Input voltage: RF 100 W Distance between S (substrate) and T (target): 70 mm As a result, the total thickness of the gate insulating film 24 became 110 nm.

[0132] (8) Formation of Gate Electrode 25 Next, a Mo film having a thickness of 150 nm was formed using a Mo sputtering target. The sputtering conditions were as follows: substrate temperature: 25° C. ultimate pressure: 8.5×10 －５ Pa Atmospheric gas: Ar Sputtering pressure (total pressure): 0.4 Pa Input voltage: DC 100 W Distance between S (substrate) and T (target): 70 mm

[0133] (9) Patterning of the Gate Electrode 25 and the Gate Insulator 24 Next, the Mo film and the gate insulator 24 were patterned into islands by photolithography. First, a photoresist film was formed on the channel layer. AZ1500 (manufactured by AZ Electronic Materials) was used as the photoresist. Exposure was performed through a photomask with a pattern of 10 μm horizontal x 28 μm vertical. After exposure, development was performed with tetramethylammonium hydroxide (TMAH). After development, the Mo film was etched with PAN (a mixed acid of phosphoric acid, nitric acid, and acetic acid) to form the gate electrode 25. Next, the gate insulator 24 was etched with buffered hydrofluoric acid (BHF) and patterned into islands. Next, the photoresist was stripped, and the region where the channel layer 11 was exposed was etched to a thickness of 10 nm using oxalic acid (ITO-06N, manufactured by Kanto Chemical Co., Ltd.) and then washed. The dimensions of the obtained gate electrode layer 25 and gate insulating film 24 were 10 μm wide×28 μm long.

[0134] (9) Resistance Reduction Treatment Low resistance regions A (11A-1, 11A-2) were formed in the channel layer 11 by self-alignment using the gate electrode 25. An ITO layer 23 having a thickness of 2 nm was formed using an ITO sputtering target. The sputtering conditions were as follows: Substrate temperature: 25°C Ultimate pressure: 8.5×10 －５ Pa Atmospheric gas: Ar + O ２ Mixture of gases (O ２ Flow rate 2%) Sputtering pressure (total pressure): 0.4 Pa Input voltage: DC 100 W Distance between S (substrate) and T (target): 70 mm

[0135] Next, the substrate 21 was placed in a furnace, and the temperature was raised to 350°C at a rate of 10°C / min in the atmosphere, and then held for 1 hour for annealing. The inside of the furnace was held at 350°C for 1 hour, and then allowed to cool naturally. After the temperature inside the furnace returned to room temperature, the substrate 21 was removed from the furnace.

[0136] (10) Formation of Interlayer Insulating Film 26 Next, SiO ２The sputtering was performed using a sputtering target of 100 nm to form a SiOx layer (interlayer insulating film 26) having a thickness of 150 nm. The sputtering conditions were as follows: substrate temperature: 25° C., ultimate pressure: 8.5×10 －５ Pa Atmospheric gas: Ar + O ２ Mixture of gases (O ２ Flow rate 30%) Sputtering pressure (total pressure): 0.4 Pa Input voltage: RF100W Distance between S (substrate) and T (target): 70 mm

[0137] (11) Formation of Contact Holes in Interlayer Insulating Film 26 The substrate on which the interlayer insulating film 26 was formed was exposed to light through a photomask using photoresist AZ1500 (manufactured by AZ Electronic Materials), and then developed with tetramethylammonium hydroxide (TMAH). After development, contact holes with a width Ls (the contact region length between the source electrode 27 and the drain electrode 28 and the channel layer 11, FIG. 3(B)) shown in Table 1 and a length of 18 μm were formed using buffered hydrofluoric acid (BHF).

[0138] (12) Formation of Source Electrode 27 and Drain Electrode 28 Using image reversal resist AZ5214 and a photomask, the source electrode 27 and the drain electrode 28 were patterned by a lift-off process. The image reversal resist AZ5214 was exposed through a photomask formed so as to be patterned into the final device shape shown in Table 1, and after a reversal bake process, the entire surface was exposed and developed with TMAH. A Mo layer with a thickness of 150 nm was formed on the substrate with the patterned resist under the following sputtering conditions: Substrate temperature: 25°C Ultimate pressure: 8.5 x 10 －５ Pa Atmospheric gas: Ar Sputtering pressure (total pressure): 0.4 Pa Input voltage: DC 100 W Distance between S (substrate) and T (target): 70 mm Thereafter, the substrate on which the Mo layer was formed was lifted off in acetone to pattern the source electrode 27 and the drain electrode 28.

[0139] (13) Final annealing Finally, N ２The resulting thin film was annealed at 300° C. for 1 hour in a 100% atmosphere to obtain a small self-aligned top-gate TFT. Tables 1 and 2 show a summary of the TFT fabrication conditions.

[0140] Comparative Example 1 A TFT was fabricated in the same manner as in Example 1, except that the resistance-lowering treatment (9) in Example 1 was not carried out.

[0141] Comparative Example 2 A TFT was fabricated in the same manner as in Example 1, except that in (9) the resistance reducing treatment of Example 1, an ITO layer 23 was formed and annealing was not performed.

[0142]

[0143]

[0144] Example 2 TFTs were fabricated in the same manner as in Example 1, except that in (2) Formation of an oxide thin film in Example 1, an oxide sputtering target obtained from a raw material mixture having the composition ratio shown in Table 1 was used. In the following examples and comparative examples, the formation of a gate insulating film in step (7) of Example 1 was not performed, and a gate insulating film having a thickness of 100 nm was formed in step (5).

[0145] Example 3 In the step (2) of forming an oxide thin film in Example 1, an oxide sputtering target obtained from a raw material mixture having the composition ratio shown in Table 3 was used, and the atmospheric gas during film formation was Ar+O ２ The TFT was fabricated in the same manner as in Example 1, except that the mixed gas used was changed to the above and the conditions for forming each component layer were changed as shown in Tables 3 and 4. Tables 3 and 4 show a summary of the TFT fabrication conditions.

[0146] Comparative Examples 3 to 5 TFTs were fabricated in the same manner as in Example 3, except that the thickness of the oxide thin film in Example 3 was changed as shown in Table 3 and the (9) resistance reduction treatment was changed as shown in Table 4.

[0147]

[0148]

[0149] Example 4 and Comparative Examples 6 to 9 TFTs were fabricated in the same manner as in Example 1, except that in (2) Formation of the oxide thin film in Example 1, an oxide sputtering target obtained from a raw material mixture having the composition ratio shown in Table 5 was used, and the conditions for forming each constituent layer were changed as shown in Tables 5 and 6. Tables 5 and 6 show a summary of the TFT fabrication conditions.

[0150]

[0151]

[0152] The TFTs obtained in the examples and comparative examples were evaluated as follows. The results are shown in Tables 7 to 9. In the tables, "E+XX" means "×10 ＸＸ (A) Evaluation of the Channel Layer (Crystalline Oxide Thin Film) of the TFT (1) State of the Channel Layer after Fabrication of the TFT The crystalline state of the cross section of the channel layer in the TFT was evaluated by pretreating the channel layer using a focused ion beam (FIB) and observing the cross section of the channel layer using a transmission electron microscope (TEM). This confirmed the following: (a) the average grain boundary angle θ relative to the thin film surface, (b) the average grain boundary angle θ relative to the lower layer, and ｓｕｂ , (c) the average spacing D of the grain boundaries, and (d) the crystalline state were evaluated.

[0153] Specifically, an ion beam was first applied perpendicularly to the surface of the channel layer using an FIB (Hitachi High-Technologies Corporation, "FB2100") device, and a 16 μm x 4 μm test piece was sampled. Then, two samples were extracted from the sampled test piece in a 3 μm region in the channel length direction (horizontal direction in the drawing) from the edge of the region where the source electrode or drain electrode and the channel layer overlap toward the non-overlapping region. Ar ion milling was performed on the two extracted samples in the channel width direction (depth direction in the drawing), perpendicular to the channel length direction and film thickness direction, until the thickness of the thin piece was approximately 100 nm, thereby thinning the thickness of the two extracted samples. If crystal grains could not be confirmed due to ion sputter damage during FIB processing, etching was repeatedly performed using Ar ion milling (Gatan Corporation, "Model 691") with an ion gun voltage of 4 keV until crystal grains could be confirmed. The cross-sectional TEM image was observed using a transmission electron microscope (JEM-2800 type manufactured by JEOL Ltd.) at an acceleration voltage of 200 kV and a magnification of 100,000 times (an area of ​​approximately 4 μm square).

[0154] (a) Average grain boundary angle θ relative to the thin film surface The average grain boundary angle θ relative to the thin film surface when observing the cross section of the channel layer (crystalline oxide thin film) can be calculated by analyzing the angle between the crystal grain boundary observed by cross-sectional TEM and the thin film surface. In an image (channel length direction × thickness direction = 4 μm square) observed at 100,000 times observation magnification, Ls, L ｏｆｆThree randomly selected fields were observed, each covering the crystalline oxide film in the L and L areas. Furthermore, when the grain boundaries were too large to be observed, multiple fields were selected within a 4-μm square area in the channel length direction and thickness direction, with no overlapping observation points in the channel length direction, allowing the entire channel layer in the TFT to be observed. Cross-sectional TEM images were then taken. Image analysis was performed on the cross-sectional TEM images of each field using "SPIP, Version 4.3.2.0" manufactured by Image Metrology, Inc. to calculate the angle between the thin film surface and the grain boundaries. Details are as follows. In the cross-sectional TEM images, lines with color codes H0, S0, and V10 were drawn on the grain boundaries in the observed image of the crystalline oxide thin film. Furthermore, image analysis software was used to quantify the contrast, and a height of (maximum density - minimum density) x 1 / 4 was set as the threshold. Regions showing contrast below the threshold were defined as grain boundaries, and the angle between each thin film surface and the grain boundaries was calculated. The sum of the angles between the obtained thin film surface and the grain boundary was divided by the number of grains, and the average value of the angles obtained for each of the obtained fields was taken as the average grain boundary angle θ with respect to the thin film surface.

[0155] (b) Average grain boundary angle θ relative to the lower layer ｓｕｂ The grain boundaries were extracted using the same cross-sectional TEM image and analysis method as above, and the angles they formed with the lower layer were calculated. The sum of the angles between the grain boundaries and the surface of each lower layer was divided by the number of particles, and the average value of the angles calculated for each of the obtained fields was calculated as the average grain boundary angle θ with respect to the surface of the lower layer. ｓｕｂ It was decided.

[0156] (c) Average spacing D of crystal grain boundaries The average spacing D when observing the cross section of an oxide thin film can be calculated by analyzing the spacing of crystal grains observed by cross-sectional TEM. At an observation magnification of 100,000 times (channel length direction × thickness direction = 4 μm square), Ls, L ｏｆｆThree randomly selected fields were observed, each including the crystalline oxide film in the L area. Furthermore, when the crystal grains were too large to observe the grain boundaries, multiple fields were selected within a 4-μm square area in the channel length direction and thickness direction, with no overlapping observation points in the channel length direction, allowing the entire channel layer in the thin-film transistor to be observed, and cross-sectional TEM images were taken. The cross-sectional TEM images of each field were analyzed using "SPIP, Version 4.3.2.0" manufactured by Image Metrology, Inc., to calculate the average spacing D of the crystal grain boundaries. Details are as follows: Lines with color codes H0, S0, and V10 were drawn on the crystal grain boundaries in the cross-sectional TEM images. Furthermore, image analysis software was used to quantify the contrast, and a height of (maximum density - minimum density) x 1 / 4 was set as the threshold. Regions showing contrast below the threshold were defined as crystal grain boundaries, and the spacing between each crystal grain boundary and the nearest particle was calculated to determine the spacing of the crystal grain boundaries. The total value of the spacing between the grain boundaries obtained was divided by the number of locations where the spacing was measured to obtain the average spacing between the grain boundaries, and the average value of the average spacing between the grain boundaries obtained in each of all visual fields was calculated as D.

[0157] (d) Crystalline State The crystalline state was determined by observing the electron beam diffraction pattern of the sample obtained by observing the cross-sectional TEM image. Specifically, using an electron microscope (JEOL "JEM-2800" model), the oxide thin film area observed in the cross-sectional TEM image was irradiated with an electron beam at an irradiation area of ​​approximately 100 nmφ and an acceleration voltage of 200 kV using a selected area aperture, and the diffraction pattern was measured with the camera length set to 2 m. An oxide thin film that did not show a clear diffraction spot in three arbitrary fields of view selected so that the observation points did not overlap in the channel length direction of the cross-sectional TEM image sample was judged to be "amorphous." On the other hand, an oxide thin film in which symmetrical diffraction spots were observed in the diffraction pattern was judged to be "crystalline." Furthermore, an oxide thin film in which similar diffraction patterns were observed in three arbitrary fields of view selected so that the observation points did not overlap in the film thickness direction was judged to be "columnar crystal."

[0158] (2) Method for measuring spreading resistance of cross section of oxide thin film by SSRM The spreading resistance of the low resistance region A and the high resistance region B of the channel layer can be determined by measuring with a scanning resistance microscope (SSRM). The equipment and measurement conditions are as follows: Equipment: NanoScope IVa AFM Dimension 3100 stage AFM system + SSRM option, manufactured by Digital Instruments division of Bruker AXS (formerly Veeco) SSRM scanning mode: simultaneous measurement of contact mode and spreading resistance SSRM probe (Tip): p-type semiconductor diamond-coated silicon cantilever Sample processing: After preparing a cross section by mechanical polishing, each layer was short-circuited to allow application of a bias voltage. Furthermore, a DC bias voltage of -3.0 V was applied to the sample and measurements were carried out. Measurement environment: Room temperature, in air

[0159] (a) Spreading resistance R Ａ and R Ｂ A cross section of the channel layer, 1 μm in the thickness direction and 4 μm in the channel length direction, was extracted so as to include the gate electrode layer, the gate insulating film layer, the low resistance region A, and the high resistance region B, and an observation cross section was obtained by underwater mechanical polishing. Subsequently, the spreading resistance of the cross section was measured using SSRM. The line profile of the spreading resistance value was measured while moving the cantilever 7.8 nm at a time parallel to the channel length direction relative to the channel region, and the minimum value of the spreading resistance in the low resistance region A was designated as the "spreading resistance value R of the low resistance region A." Ａ ", the maximum value of the spreading resistance in the high resistance region B is defined as "the spreading resistance value R Ｂ "

[0160] (b) Spreading resistance Rs(L), Rs(L ｏｆｆ ), and Rs(Ls) for the channel layer of the TFT, L ｏｆｆ The area L was extracted so as to include the area L and the area L contacting the underside of the gate insulating film, and an observation cross section was obtained by underwater mechanical polishing. Subsequently, the spreading resistance of the cross section was measured by SSRM. The line profile of the spreading resistance value was measured while moving the cantilever in increments of 7.8 nm parallel to the channel length direction for the area L.ｏｆｆ The minimum value of the spreading resistance in the region is defined as "Rs(L ｏｆｆ The maximum value of the spreading resistance at L was defined as "Rs(L)". ｏｆｆ The area L and the area Ls in contact with the source electrode or drain electrode were extracted, and an observation cross section was obtained by underwater mechanical polishing. The line profile of the spreading resistance was measured while moving the cantilever in 7.8 nm increments for the area L. ｏｆｆ The minimum value of the spreading resistance in the region is defined as "Rs(L ｏｆｆ ) 2", and the minimum value of the spreading resistance at Ls was taken as "Rs(Ls)". ｏｆｆ ) is Rs(L ｏｆｆ ) 1 and Rs (L ｏｆｆ )2 was taken as the average value.

[0161] (c) Measurement of the horizontal gap ΔL between the low resistance region A and the gate electrode For the cross section obtained by underwater mechanical polishing, an AFM mode cross section height image was measured using the same device as that used for SSRM measurement. The line profile of the height image was measured while moving the cantilever in increments of 7.8 nm in the horizontal direction relative to the gate electrode surface so as to include the gate electrode layer and the adjacent interlayer insulating film layer, and the location where the height changed abruptly was determined to be the horizontal end of the gate electrode. Next, the spreading resistance R evaluated by the SSRM was measured. Ａ The channel length direction profile of the gate electrode was compared with the horizontal profile of the gate electrode surface, and the difference between the ends of each was defined as ΔL. Note that a positive ΔL means that there is a gap between the low-resistance region A and the gate electrode in the horizontal direction, a ΔL of 0 means that there is no gap, and a negative ΔL means that the end of the gate electrode and the low-resistance region A overlap in the horizontal direction.

[0162] (3) Scanning Capacitance Microscope (SCM) Measurement The capacitance voltage change (dC / dV) of the low resistance region A and high resistance region B of the channel layer can be determined by scanning capacitance microscope (SCM) measurement. The equipment used and measurement conditions are as follows: Observation equipment: NanoScope IVa AFM Dimension 3100 stage AFM system + SCM option, manufactured by Digital Instruments division of Bruker AXS (formerly Veeco) SCM scanning mode: Simultaneous measurement of dC / dV signals in contact mode and XY mode SCM probe (Tip): PtIr-coated silicon cantilever Sample processing: After preparing a cross section by mechanical polishing, each layer was short-circuited to allow application of a bias voltage. Furthermore, measurements were carried out by applying a modulation voltage of 4.0 V and a DC bias voltage of 0 V to the sample. Measurement environment: Room temperature, in the atmosphere

[0163] (a) Relationship between dC / dV(A-B) and dC / dV(B) A cross section of the channel layer, 1.25 μm in the thickness direction and 10 μm in the plane direction, was extracted to include the low-resistivity region A and the high-resistivity region B, and the cross section was observed by underwater mechanical polishing. The cross section was then subjected to SCM to obtain a signal representing the capacitance voltage change (dC / dV). The dC / dV line profile was measured while moving the cantilever 19.6 nm increments relative to the channel region, and the relationship between the minimum value of dC / dV(B) in the high-resistivity region B and the dC / dV(A-B) at the boundary between the low-resistivity region A and the high-resistivity region B was evaluated.

[0164] (4) Identification of Crystal Structure by Electron Beam Diffraction Whether the crystal structure of the oxide thin film is a bixbyite structure was evaluated by observing the electron beam diffraction pattern of the sample obtained by observing the cross-sectional TEM image. Specifically, using an electron microscope (JEOL Ltd. "JEM-2800 type"), the oxide thin film area observed in the cross-sectional TEM image was irradiated with an electron beam using a selected area aperture at an irradiation area of ​​approximately 100 nmφ and an acceleration voltage of 200 kV, and the camera length was set to 2 m to measure the diffraction pattern. Furthermore, to identify the crystal structure, electron beam diffraction simulation software ReciPro (free software ver. 4.641 (2019 / 03 / 04)) was used to measure the In ２ O ３ A simulation of the electron diffraction pattern of the bixbyite structure was carried out. In the simulation, the crystal structure data of the bixbyite structure was 14388 from the Inorganic Crystal Structure Database (ICSD: Chemical Information Association), with a space group of Ia-3, a lattice constant of a = 10.17700 Å, and atomic coordinates of In site (0.250, 0.250, 0.250), In site (0.466, 0.000, 0.250), and O site (0.391, 0.156, 0.380). Furthermore, with a camera length of 2 m, simulations were performed with 11 types of reciprocal lattice vectors (100), (111), (110), (211), (311), (221), (331), (210), (310), (321), and (230) as the incident electron beam directions. The electron diffraction pattern of the oxide thin film was compared with the diffraction spot results for the obtained simulation pattern, and if it matched any of the 11 types of simulation patterns, it was determined that the oxide thin film contained crystal grains with a bixbyite structure.

[0165] (B) Evaluation of TFT Performance The obtained TFTs were measured at room temperature in a light-shielded environment (inside a shielded box) using a semiconductor parameter analyzer (Agilent Technologies, "B1500"). A drain voltage (Vd) of 0.1 V or 20 V was applied. For each Vd applied, the gate voltage (Vg) was varied from -5 V to 20 V in 0.2 V steps to measure the current value Id, thereby obtaining the Id-Vg characteristics. Various parameters calculated from the Id-Vg characteristics are shown in Tables 7, 8, and 9. The calculation method for each parameter is as follows:

[0166] (a) Maximum value of linear mobility (μlin Max) The maximum value of linear mobility when Vd = 0.1 V was determined by creating a graph of Id-Vg characteristics, calculating the transconductance (Gm) for each Vg, and deriving the linear mobility (μlin) using the equation for the linear region. Specifically, Gm was calculated by ∂(Id) / ∂(Vg). μlin was then calculated using equation (b) for the linear region. μlin = (Gm L) / (W Ci Vd) ... (b) In equation (b), Ci is the capacitance of the gate insulating film, and is calculated based on the thickness of the gate insulating film in the final shape shown in Tables 2, 4, and 6, and the SiO ２ The relative dielectric constant of 3.9 and the dielectric constant of vacuum is 8.85 x 10 －１４ Ci [F / cm] calculated based on [F / cm] ２ In formula (b), L is the channel length (L length), and W is the channel width (W length).

[0167] From each Vg-μlin graph, the maximum value of μlin at Vg = 0 to 20 V was calculated, and this was taken as the maximum value of linear mobility "μlin Max." ｏｆｆ The values ​​shown are for a TFT having a thickness of 4 μm and a length of 2 μm.

[0168] (b) Linear mobility variation of TFT (Δμlin) ｏｆｆ and TFT36 elements with different Ls (condition: L ｏｆｆThe maximum linear mobility was calculated for each of the 36 elements (6 conditions of Ls [μm] × 6 conditions of Ls [μm]) by the method shown in (a) above. The range of variation in the maximum linear mobility of the 36 elements was defined as the "linear mobility variation of the 36 elements (Δμlin)."

[0169] (c) Maximum value of saturated mobility (μsat Max) The maximum value of saturated mobility when Vd = 20 V was determined by creating a graph of Id-Vg characteristics, calculating the transconductance (Gm) for each Vg, and deriving the saturated mobility (μsat) using the formula for the saturated region. Specifically, Gm was calculated using the following formula (c1). Furthermore, μsat was calculated by the following formula (c) in the saturation region: μsat = (2 Gm L) / (W Ci) ... (c) In formula (c), L is the channel length (L length) and W is the channel width (W length). Furthermore, from each Vg-μsat graph, the maximum value of μsat at Vg = 0 to 20 V was calculated and designated as "μsat Max." Tables 7 to 9 show the values ​​of L ｏｆｆ The values ​​shown are for a TFT having a thickness of 4 μm and a length of 2 μm.

[0170] (d) Linear mobility variation Δμsat of TFT ｏｆｆ The maximum saturated mobility was calculated for each of the 36 types of TFTs with different Ls and Ls by the method (c) above. The range of variation in the maximum linear mobility of the 36 elements was defined as the "saturation mobility variation (Δμsat) of the 36 elements."

[0171] (e) S value and Vth The S value and threshold voltage (Vth) were evaluated from the graph of each Id-Vg characteristic. －１１ ~10 －１０ In the [A] region, the value obtained by the following formula (d) was calculated as the S value. －８ The value of Vg at [A] was calculated as the threshold voltage (Vth). ｏｆｆ The values ​​shown are for a TFT having a thickness of 4 μm and a length of 2 μm.

[0172] (f) Vth variation ΔVth ｏｆｆFor each of the 36 types of TFTs with different Ls and Vth, the Vth was calculated using the method (e) above. The range of variation in the maximum linear mobility of the 36 elements was defined as the "linear mobility variation (ΔVth) of the 36 elements."

[0173]

[0174]

[0175]

[0176] [Formation of Crystalline Oxide Thin Film] In Examples 5 to 8, laminates were fabricated and evaluated in which only a crystalline oxide thin film was formed on a substrate under the same conditions as for the channel layers of the TFTs fabricated in Examples 1 to 4. Example 5 (1) Formation of Oxide Thin Film A 10-nm-thick oxide thin film was formed on a 4-inch diameter alkali-free glass substrate (EAGLE XG manufactured by Corning Incorporated) by sputtering using a sputtering target obtained from a raw material mixture having the composition ratio shown in Table 10. The metal composition ratio (unit: at%) of the sputtering target and the sputtering conditions are shown in Table 10. The sputtering conditions not listed in Table 10 are as follows: Substrate temperature: 25°C Ultimate pressure: 1.0 x 10 －４ Pa Atmospheric gas: Ar and H ２ O mixed gas Sputtering pressure (total pressure): 0.5 Pa Input voltage: DC 300 W Distance between S (substrate) and T (target): 70 mm

[0177] (2) Annealing of oxide thin film The substrate on which the oxide thin film was formed was placed in a furnace, and the temperature was raised to 350°C at a rate of 10°C / min in the atmosphere, and then held for 1 hour. The inside of the furnace was held at 350°C for 1 hour, and then allowed to cool naturally. After the temperature inside the furnace returned to room temperature, the substrate was removed from the furnace.

[0178] (3) Treatment for reducing resistivity (high carrier concentration) (3-1) Formation of ITO film Using an ITO sputtering target, an ITO layer with a thickness of 2 nm was formed. The sputtering conditions were as follows: Substrate temperature: 25°C Ultimate pressure: 8.5 × 10 －５ Pa Atmospheric gas: Ar + O ２ Mixture of gases (O ２Flow rate 2%) Sputtering pressure (total pressure): 0.4 Pa Input voltage: DC 100 W Distance between S (substrate) and T (target): 70 mm

[0179] (3-2) Patterning of ITO Layer The ITO layer was patterned into 1 cm square islands by photolithography. First, a photoresist film was formed on the ITO layer. AZ1500 (manufactured by AZ Electronic Materials) was used as the photoresist. The photoresist film was exposed to light through a photomask with numerous 1 cm square patterns. After exposure, the film was developed with tetramethylammonium hydroxide (TMAH). After development, the ITO layer was etched with oxalic acid (ITO-06N, manufactured by Kanto Chemical). After etching, the photoresist was peeled off to obtain a substrate with a 1 cm square ITO layer formed at equal intervals on an oxide thin film.

[0180] (3-3) Annealing The substrate with the patterned ITO layer was placed in a furnace, and the temperature was raised to 350°C at a rate of 10°C / min in the atmosphere, and then held for 1 hour. The interior of the furnace was held at 350°C for 1 hour, and then allowed to cool naturally. After the temperature inside the furnace returned to room temperature, the substrate was removed from the furnace. Here, the oxide thin film in the region that was annealed without being covered with an ITO layer becomes the high-resistance region B. On the other hand, the oxide thin film in the region that was annealed while being covered with an ITO layer becomes the low-resistance region A.

[0181] (3-4) Removal of ITO Layer The ITO layer on the annealed substrate was removed by etching with oxalic acid (ITO-06N, manufactured by Kanto Chemical Co., Ltd.). As a result, a crystalline oxide thin film having alternating 1 cm square high-resistance regions B and 1 cm square low-resistance regions A was obtained on the substrate.

[0182] Comparative Example 10 A crystalline oxide thin film was formed in the same manner as in Example 5, except that the resistance-lowering treatment (3) in Example 5 was not carried out.

[0183] Comparative Example 11 A crystalline oxide thin film was formed in the same manner as in Example 5, except that an ITO layer was formed and annealing was not performed in the (3) resistance reducing treatment of Example 5.

[0184] Example 6 A crystalline oxide thin film was formed in the same manner as in Example 5, except that in (1) Formation of an oxide thin film in Example 5, an oxide sputtering target obtained from a raw material mixture having the composition ratio shown in Table 10 was used.

[0185] Example 7 A crystalline oxide thin film was formed in the same manner as in Example 5 (1) Formation of an oxide thin film, except that an oxide sputtering target obtained from a raw material mixture having the charged composition ratio shown in Table 11 was used and the formation conditions for each constituent layer were changed as shown in Table 11.

[0186] Comparative Examples 12 to 14 Crystalline oxide thin films were formed in the same manner as in Example 5, except that (3) the resistance-lowering treatment or the thickness of the oxide thin film was changed as shown in Table 11.

[0187] Example 8, Comparative Examples 15 to 18 In (1) Formation of oxide thin film in Example 5, an oxide sputtering target obtained from a raw material mixture having the charged composition ratio shown in Table 12 was used, and the formation conditions for each constituent layer were changed as shown in Table 12. Except for this, a crystalline oxide thin film was formed in the same manner as in Example 5.

[0188] The crystalline oxide thin films obtained in the examples and comparative examples were evaluated in the same manner as the channel layer in Example 1. In addition, the carrier concentration of the crystalline oxide thin films was measured. The results are shown in Tables 10 to 12. (1) Carrier Concentration The low-resistance region A and the high-resistance region B of the crystalline oxide thin film were each cut into a 1 cm square, and electrodes were attached to the four corners using In solder to form elements for Hall effect measurement, and the carrier concentration was measured. The carrier concentration was determined by measuring the AC Hall effect at room temperature using a ResiTest 8400 model (manufactured by Toyo Corporation). The measurement conditions were as follows. For measurement accuracy, the value of the electron carrier concentration was adopted when the F value was 0.9 or more and the absolute value of the Hall voltage phase was 170° to 180°. Current value: 1×10 －１２ ~1 x 10 －３ A Magnetic field strength: 0.36T

[0189] (2) Measurement of SSRM and SCM A cross section was obtained by cutting out a region of the crystalline oxide thin film including the low resistance region A and the high resistance region B into a 1 cm square. The cross section was evaluated in the same manner as the channel layer of the TFT.

[0190] (3) Cross-sectional TEM and electron diffraction measurements A cross section was obtained by cutting out an arbitrary region of the crystalline oxide thin film into a 1 cm square. The target position on the cross section was evaluated in the same manner as the channel layer of the TFT.

[0191]

[0192]

[0193]

[0194] [Fabrication of small self-aligned top-gate TFTs] Examples 9 to 11 and Comparative Example 19 TFTs were fabricated in the same manner as in Example 1, except that in (2) Formation of the oxide thin film in Example 1, an oxide sputtering target obtained from a raw material mixture having the composition ratio shown in Table 13 was used, and the formation conditions for each component layer were changed as shown in Tables 13 and 14. Tables 13 and 14 show a summary of the TFT fabrication conditions. Table 15 shows the evaluation results of the TFTs.

[0195]

[0196]

[0197]

[0198] Examples 12 to 20 TFTs were fabricated in the same manner as in Example 1, except that in the formation of the oxide thin film in (2) of Example 1, an oxide sputtering target obtained from a raw material mixture having the composition ratios shown in Tables 16 and 17 was used, and a channel layer was formed under the sputtering conditions shown in Tables 16 to 19. Tables 16 to 19 show a summary of the TFT fabrication conditions. Tables 20 and 21 show the evaluation results of the TFTs.

[0199]

[0200]

[0201]

[0202]

[0203]

[0204]

[0205] Examples 21 to 34B TFTs were fabricated in the same manner as in Example 1, except that in the formation of the oxide thin film in (2) of Example 1, oxide sputtering targets obtained from raw material mixtures having the compositional ratios shown in Tables 22 to 24 were used, and the formation conditions for each constituent layer were changed as shown in Tables 22 to 27. Tables 22 to 27 show a summary of the TFT fabrication conditions. Tables 28 to 30 show the evaluation results of the TFTs.

[0206]

[0207]

[0208]

[0209]

[0210]

[0211]

[0212]

[0213]

[0214]

[0215] Examples 35 to 216 TFTs were fabricated in the same manner as in Example 1, except that in (2) Formation of the oxide thin film in Example 1, oxide sputtering targets obtained from raw material mixtures having the composition ratios shown in Tables 31 to 55 were used and the sputtering conditions for the oxide thin film were changed as shown in Tables 31 to 55. Tables 31 to 55 show the evaluation results of the obtained channel layers and the TFT performance.

[0216]

[0217]

[0218]

[0219]

[0220]

[0221]

[0222]

[0223]

[0224]

[0225]

[0226]

[0227]

[0228]

[0229]

[0230]

[0231]

[0232]

[0233]

[0234]

[0235]

[0236]

[0237]

[0238]

[0239]

[0240]

[0241] Example 217, Comparative Example 20 (1) Formation of Oxide Thin Film On a 4-inch diameter alkali-free glass substrate (EAGLE XG manufactured by Corning Incorporated), a 50 nm thick oxide thin film was formed by sputtering using a sputtering target obtained from a raw material mixture having the composition ratio shown in Table 56. The metal composition ratio (unit: at %) of the sputtering target and the sputtering conditions are shown in Table 56. X listed in Table 56 represents a metal element other than In and Ga. The sputtering conditions not listed in Table 56 are as follows: Substrate temperature: 25°C Ultimate pressure: 1.0 x 10 －４ Pa Atmospheric gas: O ２ Sputtering pressure (total pressure): 0.5 Pa Input voltage: DC 400 W Distance between S (substrate) and T (target): 70 mm

[0242] (2) Annealing of oxide thin film The substrate on which the oxide thin film was formed was placed in a furnace, and the temperature was raised to 350°C at a rate of 10°C / min in the atmosphere, and then held for 1 hour. The inside of the furnace was held at 350°C for 1 hour, and then allowed to cool naturally. After the temperature inside the furnace returned to room temperature, the substrate was removed from the furnace.

[0243] (3) Electron Beam Diffraction Measurement A cross section was obtained by cutting out an arbitrary region of the oxide thin film into a 1 cm square. The target position of the cross section was evaluated in the same manner as the channel layer of the TFT. As a result, Example 217 had a bixbyite structure, and Comparative Example 41 was amorphous.

[0244] (4) CL (Cathodoluminescence Spectroscopy) Measurement CL measurements were performed using the following measurement device and under the following conditions. [Measurement Device] Device: Cathodoluminescence Spectrometer Spectrometer: Manufactured by Horiba, Ltd. SEM: Schottky Emission SEM JSM-7100F / TTLS manufactured by JEOL Ltd. Spectrometer: iHR-320 Diffraction Grating (100 gr / mm, blaze wavelength 450 nm) Detector: CCD: Jobin Yvon [Measurement Conditions] Temperature: Room temperature Slit: 500 μm Acceleration voltage: 1 kV Irradiation current: 0.7 nA (1 kV) WD: 10.3 mm Spectral integration time: 60 to 180 s The intensity of the obtained spectrum was converted into the number of counts per second. The CL spectrum results of the oxide thin films obtained in Example 217 and Comparative Example 20 are shown in FIG.

[0245] Furthermore, the ratio I(640 nm) / I(380 nm) of the 640 nm emission intensity I(640 nm) derived from crystal defects such as oxygen defects to the 380 nm emission intensity I(380 nm) due to interband transition luminescence was calculated and compared for each spectrum to compare the defect amounts in the oxide thin films. The results are shown in Table 52. Example 217, which was crystallized into a bixbyite structure, had lower luminescence and fewer defects than Comparative Example 20, which was amorphous.

[0246]

[0247] The crystalline oxide thin film of the present invention can be suitably used as a component of a thin film transistor, for example, as a channel layer, and can also be used in electronic circuits used in electrical equipment, electronic devices, vehicles, and power plants.

[0248] Although several embodiments and / or examples of the present invention have been described in detail above, those skilled in the art will readily be able to make numerous modifications to these exemplary embodiments and / or examples without substantially departing from the novel teachings and advantages of the present invention. Accordingly, these numerous modifications are within the scope of the present invention. The contents of all documents cited in this specification and of the applications from which this application claims priority under the Paris Convention are incorporated by reference in their entirety.

Claims

1. A crystalline oxide thin film having In as a main component, in the plane direction of the crystalline oxide thin film, having a low-resistance region A and a high-resistance region B with different spreading resistance values measured by a scanning spreading resistance microscope (SSRM), wherein the spreading resistance value of the high-resistance region B is 8 times or more the spreading resistance value of the low-resistance region A, a crystalline oxide thin film in which, in the dC / dV value measured by a scanning capacitance microscope (SCM), the dC / dV value at the boundary between the low-resistance region A and the high-resistance region B is larger than the dC / dV value of the high-resistance region B.

2. The crystalline oxide thin film according to Claim 1, wherein the spreading resistance value of the high-resistance region B is 10 times or more the spreading resistance value of the low-resistance region A.

3. The crystalline oxide thin film according to Claim 1, wherein the spreading resistance value of the high-resistance region B is 15 times or more the spreading resistance value of the low-resistance region A.

4. The crystalline oxide thin film according to Claim 1, having a film thickness of 80 nm or less.

5. wherein an average grain boundary angle θ formed between the lower surface of the thin film and the grain boundaries in the thin film of the crystalline oxide thin film is 70° or more and 110° or less, and an average interval D between the grain boundaries is 0.01 μm or more and 2.0 μm or less, the crystalline oxide thin film according to Claim 1.

6. The crystalline oxide thin film according to Claim 1, including crystal grains having a Bixbyite structure in the electron diffraction of the crystalline oxide thin film.

7. The crystalline oxide thin film according to Claim 1, further including one or more elements selected from the group consisting of H, B, C, N, O, F, Mg, Al, Si, O, S, Cl, Ar, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln, Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb, and Bi.

8. A laminate including the crystalline oxide thin film according to Claim 1.

9. The average grain boundary angle θ formed between the surface where the crystalline oxide film and the lower layer are in contact and the grain boundaries in the crystalline oxide film ｓｕｂ is 70° or more and 110° or less, and the laminate according to claim 8.

10. The laminate according to Claim 8, wherein the lower layer is a substrate of a thin film transistor or a constituent layer of a thin film transistor.

11. A thin film transistor including the crystalline oxide thin film according to Claim 1.

12. a channel layer and a source electrode and a drain electrode respectively connected to both ends of the channel layer, and a gate electrode laminated on the channel layer via a gate insulating film. The channel layer is the crystalline oxide thin film, the gate insulating film is formed in the high-resistance region B, and the source electrode and the drain electrode are formed in the low-resistance region A. The distance L from the ends of the source electrode and the drain electrode to the intersection point between the perpendicular line drawn in the thickness direction from the end of the gate electrode and the crystalline oxide thin film ｏｆｆ is 4 μm or more and 20 μm or less, The average distance D between the grain boundaries of the crystalline oxide film and the distance L ｏｆｆ The thin film transistor according to claim 11, wherein the following formula (1) is satisfied. 2 ≤ L ｏｆｆ / D ≤ 100...(1)

13. The contact region length Ls between the source electrode and the drain electrode and the channel layer is 4 μm or more and 20 μm or less. The thin film transistor according to claim 11, wherein the average interval D between the crystal grain boundaries of the crystalline oxide thin film and the contact region length Ls satisfy the following formula (2). 1 ≦ Ls / D ≦ 100... (2)

14. The thin film transistor according to claim 11, wherein the horizontal gap ΔL between the low-resistance region A and the gate electrode is less than 1 μm.

15. A crystalline oxide thin film containing In as a main component, having a film thickness of 80 nm or less, having a high carrier concentration region A and a low carrier concentration region B with different carrier concentrations in the plane direction of the crystalline oxide thin film, The carrier concentration in the high carrier concentration region A is 10 １９ cm －３ or more and 10 ２２ cm －３ or less, and A crystalline oxide thin film in which the carrier concentration in the high carrier concentration region A is 8 times or more the carrier concentration in the low carrier concentration region B.

16. The crystalline oxide thin film according to claim 15, wherein the carrier concentration in the high carrier concentration region A is 10 times or more the carrier concentration in the low carrier concentration region B.

17. The crystalline oxide thin film according to claim 15, wherein the carrier concentration in the high carrier concentration region A is 15 times or more the carrier concentration in the low carrier concentration region B.

18. The carrier concentration in the low carrier concentration region B is 10 １５ cm －３ or more and less than 10 １９ cm －３ The crystalline oxide thin film according to claim 15

19. The average grain boundary angle θ formed by the lower surface of the thin film and the crystal grain boundaries in the crystalline oxide thin film is 70° or more and 110° or less, The crystalline oxide thin film according to claim 15, wherein the average interval D between the crystal grain boundaries is 0.01 μm or more and 2.0 μm or less.

20. The crystalline oxide thin film according to claim 15, which contains crystal grains having a Bixbyite structure in the electron diffraction of the crystalline oxide thin film.

21. The crystalline oxide thin film according to claim 15, wherein the crystalline oxide thin film further contains one or more elements selected from the group consisting of H, B, C, N, O, F, Mg, Al, Si, O, S, Cl, Ar, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln, Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb, and Bi.

22. A laminate including the crystalline oxide thin film according to claim 15.

23. The average grain boundary angle θ formed between the surface where the crystalline oxide thin film and the lower layer are in contact and the grain boundaries in the crystalline oxide thin film ｓｕｂ is 70° or more and 110° or less, and the laminate according to claim 22.

24. The laminate according to claim 22, wherein the lower layer is a substrate of a thin film transistor or a constituent layer of a thin film transistor.

25. A thin film transistor including the crystalline oxide film according to claim 15.

26. A channel layer and A source electrode and a drain electrode respectively connected to both ends of the channel layer, and A gate electrode laminated on the channel layer via a gate insulating film, and having The channel layer is the crystalline oxide film, the gate insulating film is formed in the low carrier concentration region B, and the source electrode and the drain electrode are formed in the high carrier concentration region A. The distance L from the ends of the source electrode and the ends of the drain electrode to the intersection of the perpendicular line drawn in the thickness direction from the ends of the gate electrode and the crystalline oxide thin film ｏｆｆ is 4 μm or more and 20 μm or less, The average distance D between the grain boundaries of the crystalline oxide film and the distance L ｏｆｆ The thin film transistor according to claim 25, wherein the following formula (1) is satisfied. 2 ≤ L ｏｆｆ / D ≤ 100...(1)

27. The contact region length Ls between the source electrode and the drain electrode and the channel layer is 4 μm or more and 20 μm or less, The thin film transistor according to claim 25, wherein the average interval D between the grain boundaries of the crystalline oxide film and the contact region length Ls satisfy the following formula (2). 1 ≦ Ls / D ≦ 100... (2)

28. The thin film transistor according to claim 25, wherein the horizontal gap ΔL between the high carrier concentration region A and the gate electrode is less than 1 μm.

29. A crystalline oxide film containing In as a main component, The film thickness is 80 nm or less, The average interval D between the grain boundaries of the crystalline oxide film is 2 μm or less. A carrier concentration of 10 １９ cm －３ or more and 10 ２２ cm －３ or less, a crystalline oxide thin film.

30. A thin film transistor including the crystalline oxide film according to claim 29.

31. An electronic circuit including the thin film transistor according to any one of claims 11 to 14, 25 to 28, and 30.

32. An electric device, an electronic device, a vehicle, or a power unit including the electronic circuit according to claim 31.