Spintronics device, magnetic memory, electronic apparatus, and manufacturing method for spintronics device

Abstract

This spintronics device generates a spin flow and comprises: a metal layer; a semiconductor layer for which the carrier mobility or the electrical conductivity is lower than the metal layer; and a gradient layer that is positioned in the boundary between the metal layer and the semiconductor layer and that has a carrier mobility gradient or an electrical conductivity gradient.

Description

Spintronic device, magnetic memory, electronic device, and method for manufacturing spintronic device

[0001] This disclosure relates to a spintronic device, a magnetic memory, an electronic device, and a method for manufacturing a spintronic device. This application claims priority to Japanese Application No. 2021-201018 filed on December 10, 2021, and incorporates by reference all of the contents of said Japanese application.

[0002] Patent Document 1 discloses technology related to a spintronics device. This spintronics device includes a first conductive layer and a second conductive layer having a carrier mobility or electrical conductivity lower than that of the first conductive layer. The boundary region between the first and second conductive layers has a gradient in carrier mobility or electrical conductivity, and a spin current is generated by the rotation of an electron velocity field caused by this gradient. Patent Document 1 describes, as an example, that the first conductive layer mainly contains copper and the second conductive layer mainly contains copper oxide.

[0003] Non-Patent Documents 1 and 2 disclose research on the diffusion motion of spins resulting from the magnetization motion of magnetic materials. Non-Patent Documents 3 and 4 disclose research on the relativistic effect of up-spin and down-spin scattering in opposite directions in noble metals such as platinum (Pt).

[0004] International Publication No. 2020 / 050329

[0005] Mizukami et al., “The study on ferromagnetic resonance linewidth for NM / 80NiFe / NM (NM=Cu,Ta,Pd and Pt) films”, Japanese Journal of Applied Physics, 40(2A), p.580, (2001)Urban et al., “Gilbert Damping in Single and Multilayer Ultrathin Films: Role of Interfaces in Nonlocal Spin Dynamics”, Physical Review Letters, Volume 87, 217204, (2001)Kato et al., “Observation of the spin Hall effect in semiconductors”, Science, Volume 306, pp.1910-1913 (2004)Kimura et al., “Room-temperature reversible spin Hall effect”, Physical Review Letters, Volume 98, 156601 (2007)Chen et al., “Spin-torque and spin-Hall nano-oscillators”, Proceedings, IEEE, Volume 104, pp.1919-1945 (2016)An et al., “Spin-torque generator engineered by natural oxidation of Cu” Nature Communications, 7, 13069 (2016)

[0006] Spin current is a flow of spin angular momentum without accompanying electric charge, and can be widely used to control various spintronic devices. Because it does not involve electric charge, it does not generate Joule heat, which can significantly reduce the energy consumption of electronic devices. Furthermore, spin current can exert torque on magnetization more efficiently than an Oersted magnetic field. Spin current has the potential to dramatically improve the performance of electronic devices such as transistors, random access memories, and logic operation elements, which are currently facing the fundamental limits of performance enhancement due to miniaturization.

[0007] Conventional spin current generation theories are based on the spin-orbit interaction (SOI) that exists in materials. SOI is a material-specific phenomenon and is known to be strong in rare metals with high atomic numbers, such as platinum, tantalum, tungsten, and bismuth. This severely limits the materials that can be used, which inhibits further improvements in spin current intensity.

[0008] Furthermore, Patent Document 1 describes that metals such as copper (Cu), aluminum (Al), iron (Fe), and platinum (Pt), conductive nitrides such as titanium nitride (TiN), conductive polymers such as polyacetylene, and semiconductors such as silicon (Si) can be used as materials for the first conductive layer, and gives examples of materials for the second conductive layer that are oxides of the material for the first conductive layer. However, oxides generally have low electrical conductivity, and in devices such as magnetic memories that have this spintronics device, a large amount of current is released as Joule heat, causing various problems such as increased power consumption and heat generation.

[0009] An object of the present disclosure is to provide a spintronics device, a magnetic memory, an electronic device, and a method for fabricating a spintronics device that has high electrical conductivity and can generate a large spin current without excessively limiting the materials used.

[0010] A spintronic device according to one embodiment is a spintronic device that generates spin current and includes a metal layer, a semiconductor layer having a carrier mobility or electrical conductivity lower than that of the metal layer, and a gradient layer located at the interface between the metal layer and the semiconductor layer and having a gradient in carrier mobility or electrical conductivity.

[0011] When a voltage is applied to a region with a gradient in carrier mobility or electrical conductivity, electrons collide with scatterers as they move forward, but the electron velocity or current density moving through regions with high carrier mobility or electrical conductivity is greater than the electron velocity or current density moving through regions with low carrier mobility or electrical conductivity. That is, in regions with a gradient in carrier mobility or electrical conductivity, unlike in ordinary materials with uniform carrier mobility or electrical conductivity, a non-uniform distribution of electron velocity or current density occurs. Focusing on a small region within the region, the electron velocity field or current field (vector field) can be considered to rotate in that region due to differences in electron velocity or current density. The magnitude of rotation of this velocity field or current field can also be understood as vorticity. This rotation of the velocity field or current field results in the existence of "angular momentum" in the flow of multiple electrons in the region. This angular momentum is converted into unidirectional spin (up spin or down spin), disrupting the equilibrium between up spin and down spin, resulting in a bias in the relative distribution of up spin and down spin. As a result, a spin current is generated in a direction that eliminates the distribution bias.

[0012] According to the inventor's findings, the above effects can generate a large spin current, comparable to or greater than that of an SOI-based device. Furthermore, the above effects are realized simply by forming a gradient in carrier mobility or electrical conductivity, without requiring rare materials such as precious metals (e.g., Pt) that generate SOI. That is, by combining a metal layer, such as Al, which is abundant in the Earth's crust, with a semiconductor layer, such as Si, which is abundant in the Earth's crust, a gradient layer with a carrier mobility or electrical conductivity gradient can be easily formed. Furthermore, metal and semiconductor layers have higher electrical conductivity than oxides, which can reduce Joule heat emission in devices such as magnetic memories that incorporate this spintronic device. Thus, the above spintronic device can generate a large spin current while increasing electrical conductivity without excessively limiting the materials used.

[0013] In the spintronic device, the metal layer may contain aluminum (Al). Alternatively, the metal layer may be an Al layer. Al is the third most abundant element in the Earth's crust after oxygen (O) and silicon (Si), and is the most abundant element among metallic elements. Furthermore, Al has a relatively high electrical conductivity among metallic elements. Therefore, a sustainable spintronic device capable of reducing power consumption can be provided.

[0014] In the spintronic device, the semiconductor layer may contain Si. Alternatively, the semiconductor layer may be a Si layer. Si is the second most abundant element in the Earth's crust after oxygen (O) and is the most abundant element in semiconductors. Therefore, a sustainable spintronic device can be provided.

[0015] In the spintronic device, the metal layer may be an Al layer, the semiconductor layer may be a Si layer, and the thickness of the gradient layer may be 2.4 nm or less. Experiments by the inventors have shown that when the gradient layer has such a thickness, it is possible to generate a spin current that is larger than the spin current generated by SOI.

[0016] The above spintronic devices may generate spin current by the rotation of the electron velocity field or current field caused by the gradient. Furthermore, they may generate spin current by the angular momentum caused by the rotation of the electron velocity field or current field. These can generate spin current as described above.

[0017] A magnetic memory according to one embodiment includes any one of the spintronics devices described above, which allows the magnetization direction to be controlled while reducing power consumption without excessively limiting the materials used.

[0018] Another embodiment of a magnetic memory includes a first ferromagnetic layer, a non-magnetic layer disposed on the first ferromagnetic layer, a second ferromagnetic layer disposed on the non-magnetic layer, a metal layer disposed on the second ferromagnetic layer, a semiconductor layer disposed on the metal layer and having a carrier mobility or electrical conductivity lower than that of the metal layer, and a gradient layer located at the interface between the metal layer and the semiconductor layer and having a gradient in carrier mobility or electrical conductivity. Information is stored by controlling the magnetization direction of the second ferromagnetic layer using a spin current generated in the gradient layer. This magnetic memory has the configuration of the spintronics device described above. Therefore, the magnetization direction can be controlled while reducing power consumption without excessively limiting the materials used.

[0019] An electronic device according to one embodiment includes one or more of the magnetic memories described above. The electronic device has the spintronics device configuration described above. Therefore, the electronic device can control the magnetization direction while reducing power consumption without excessively limiting the materials used.

[0020] A method for fabricating a spintronic device according to one embodiment is a method for fabricating any of the spintronic devices described above, and includes the steps of forming a first layer by sputtering the same material as the metal layer on the semiconductor layer, forming a second layer by sputtering the same material as the semiconductor layer on the first layer, and forming a metal layer on the second layer.

[0021] In this fabrication method, a gradient layer is formed by intermixing atoms of the first and second layers during sputtering. The thickness of the gradient layer depends on the total thickness of the first and second layers. Therefore, a gradient layer of any thickness can be easily formed. Alternatively, a gradient layer can be formed by simultaneously depositing the semiconductor layer material and the metal layer material and gradually changing the deposition ratio. However, in this case, targets made of the semiconductor layer material and the metal layer material must be simultaneously placed in the sputtering apparatus, which increases the size of the sputtering apparatus. In the above fabrication method, the semiconductor layer material and the metal layer material are alternately deposited, so it is sufficient to alternately place targets made of the semiconductor layer material and the metal layer material in the sputtering apparatus. Therefore, the number of targets simultaneously placed in the sputtering apparatus can be reduced, allowing for a more compact sputtering apparatus.

[0022] According to the present disclosure, it is possible to provide a spintronics device, a magnetic memory, an electronic device, and a method for manufacturing a spintronics device that can generate a large spin current while reducing power consumption without excessively limiting the materials used.

[0023] FIG. 1 is a perspective view showing the configuration of a spintronic device according to a first embodiment of the present disclosure. Parts (a) to (e) of FIG. 2 are schematic diagrams illustrating a method for fabricating a spintronic device in which the materials constituting the semiconductor layer and the metal layer are in a non-solid-solution state. Parts (a) to (d) of FIG. 3 are schematic diagrams illustrating a method for fabricating a spintronic device in which the materials constituting the semiconductor layer and the metal layer are in a solid-solution state. FIG. 4 is a graph showing the change in electrical conductivity of device 1 in the stacking direction. Parts (a) and (b) of FIG. 5 are schematic diagrams showing the speed or current density of electrons moving inside a spintronic device when a voltage is applied in a direction intersecting the stacking direction. FIG. 6 is a schematic diagram showing the mechanism for generating spin current by Rayleigh waves as a reference example. FIG. 7 is a diagram showing the structure of a sample used in the experiment. Parts (a) and (b) of FIG. 8 are HAADF-STEM images showing the layer structure of the fabricated sample. Part (c) of Figure 8 is a graph showing the distribution of Si and Al atomic concentrations obtained by energy dispersive X-ray analysis of the area enclosed by the dashed line in part (b) of Figure 8. Parts (a) and (b) of Figure 9 are HAADF-STEM images showing the layer structure of the prepared sample. Part (c) of Figure 9 is a graph showing the distribution of Si and Al atomic concentrations obtained by energy dispersive X-ray analysis of the area enclosed by the dashed line in part (b) of Figure 9. Parts (a) and (b) of Figure 10 are HAADF-STEM images showing the layer structure of the prepared sample. Part (c) of Figure 10 is a graph showing the distribution of Si and Al atomic concentrations obtained by energy dispersive X-ray analysis of the area enclosed by the dashed line in part (b) of Figure 10. Parts (a) and (b) of Figure 11 are nanobeam electron diffraction (NBED) patterns for a 10 nm thick semiconductor layer (Si layer) and a metal layer (Al layer), respectively. Fig. 12 is a diagram for explaining the principle of ST-FMR measurement. Fig. 13 is a diagram showing the circuit used for ST-FMR measurement. Part (a) of Fig. 14 is a graph showing the ST-FMR spectrum of a sample in which the total thickness of the first and second layers is 0.5 nm. Part (b) of Fig. 14 shows the symmetric and antisymmetric Lorentzian function components included in the graph shown in part (a) of Fig. 14.FIG. 15 is a graph showing the relationship between the obtained spin torque efficiency and the total thickness of the first and second layers. Part (a) of FIG. 16 is a graph showing the relationship between symmetric Lorentzian function components and the applied angle of an external magnetic field. Part (b) of FIG. 16 is a graph showing the relationship between antisymmetric Lorentzian function components and the applied angle of an external magnetic field. FIG. 17 is a graph showing the relationship between the spin torque efficiency and both the damping-like torque efficiency and the field-like torque efficiency. FIG. 18 is a graph showing the relationship between the spin current-to-electric current conversion efficiency and the damping-like torque efficiency. FIG. 19 is a graph showing the relationship between the total thickness of the first and second layers and the electrical conductivity of the sample. FIG. 20 is a graph showing the relationship between the electrical conductivity and the product of the damping-like torque efficiency and the electrical conductivity for each sample. FIG. 21 is a perspective view showing the configuration of a magnetic memory according to a second embodiment of the present disclosure. Parts (a) and (b) of FIG. 22 are cross-sectional views showing the configuration of a memory element. Figure 23 is a graph plotting various materials according to their spin Hall conductivity and electrical conductivity. Part (a) of Figure 24 is a schematic diagram showing the atomic structure of the semiconductor layer, the metal layer, and the gradient layer. Part (b) of Figure 24 is a graph showing the variation of electrical conductivity in the thickness direction.

[0024] Hereinafter, embodiments of a spintronics device, a magnetic memory, an electronic device, and a method for fabricating a spintronics device according to the present disclosure will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are designated by the same reference numerals, and duplicated explanations will be omitted.

[0025] First Embodiment FIG. 1 is a perspective view showing the configuration of a spintronic device 1 (hereinafter simply referred to as device 1) according to a first embodiment of the present disclosure. As shown in FIG. 1, the device 1 includes a semiconductor layer 2, a metal layer 3, and a gradient layer 4. The carrier mobility (hereinafter sometimes simply referred to as mobility) or electrical conductivity of the material constituting the semiconductor layer 2 is lower than the mobility or electrical conductivity of the material constituting the metal layer 3. The semiconductor layer 2 includes a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP), or a combination thereof. The semiconductor layer 2 may be composed of any of these semiconductors or a combination of these semiconductors. In one example, the semiconductor layer 2 includes Si or is a Si layer. The thickness of the semiconductor layer 2 is, for example, in the range of 0.1 nm to 1000 nm.

[0026] The metal layer 3 includes, for example, any one of metals such as copper (Cu), aluminum (Al), iron (Fe), platinum (Pt), gold (Au), and silver (Ag), or a combination (e.g., an alloy) of at least two of these metals. The metal layer 3 may be made of any one of these metals or a combination of at least two of these metals. In one example, the metal layer 3 includes Al or is an Al layer. The thickness of the metal layer 3 is, for example, in the range of 0.1 nm to 1000 nm. The metal layer 3 may be formed on the semiconductor layer 2 by, for example, sputtering or the like.

[0027] The gradient layer 4 is a layered region present at the boundary between the semiconductor layer 2 and the metal layer 3. When observed macroscopically, the semiconductor layer 2 and the metal layer 3 are in contact with each other, but when observed microscopically, a slight gradient layer 4 exists between the semiconductor layer 2 and the metal layer 3. The thickness of the gradient layer 4 is, for example, greater than 0 nm and less than 100 nm. When the gradient layer 4 is made of Si and Al, the thickness of the gradient layer 4 is, for example, greater than 0 nm and less than 2.4 nm. The thickness of the gradient layer 4 may be a value extremely close to zero, such as a few angstroms. In the gradient layer 4, the constituent material of the metal layer 3 and the constituent material of the semiconductor layer 2 are mixed. In the gradient layer 4, the proportion of the constituent material of the metal layer 3 increases as the gradient layer 4 approaches the interface with the metal layer 3, and the proportion of the constituent material of the semiconductor layer 2 increases as the gradient layer 4 approaches the interface with the semiconductor layer 2.

[0028] The materials constituting the semiconductor layer 2 and the metal layer 3 may be immiscible with each other. From this perspective, when the semiconductor layer 2 primarily contains Si, the metal layer 3 may primarily contain Al, Ag, or Au, or a combination of at least two of these metals. When the materials constituting the semiconductor layer 2 and the metal layer 3 are immiscible with each other, the atoms constituting the semiconductor layer 2 and the metal layer 3 are less likely to diffuse into each other. Therefore, changes over time in the thickness of the gradient layer 4 and the composition distribution in the thickness direction of the gradient layer 4 can be kept small. In particular, when manufacturing a device such as a magnetic memory including the device 1, heat treatment at temperatures ranging from several hundred degrees Celsius to several thousand degrees Celsius may be performed during the manufacturing process. Even in such cases, when the materials constituting the semiconductor layer 2 and the metal layer 3 are immiscible with each other, changes over time in the thickness of the gradient layer 4 and the composition distribution in the thickness direction of the gradient layer 4 can be kept small. Therefore, characteristics of the device 1, such as spin current generation efficiency, can be maintained for a long period of time.

[0029] Alternatively, the materials constituting the semiconductor layer 2 and the metal layer 3 may form a solid solution with each other. From this perspective, when the semiconductor layer 2 mainly contains Si, the metal layer 3 may mainly contain one of Cu, chromium (Cr), Fe, nickel (Ni), Pt, tantalum (Ta), titanium (Ti), and tungsten (W), or a combination of at least two of these metals. When the materials constituting the semiconductor layer 2 and the metal layer 3 respectively form a solid solution with each other, the atoms constituting the semiconductor layer 2 and the metal layer 3 are likely to diffuse into each other. Therefore, the gradient layer 4 can be easily formed by atomic diffusion between the semiconductor layer 2 and the metal layer 3, for example, by heat treatment or the like.

[0030] Parts (a) to (e) of FIG. 2 are schematic diagrams illustrating a method for fabricating a device 1 in which the materials constituting the semiconductor layer 2 and the metal layer 3 are insoluble with each other. First, as shown in part (a) of FIG. 2, a substrate 5 is prepared. Various substrates, such as a surface-oxidized Si substrate, can be used as the substrate 5. Next, the substrate 5 is placed in a sputtering apparatus, and a first target made of the same material as the semiconductor layer 2 is placed in the sputtering apparatus. Then, as shown in part (b) of FIG. 2, the material for the semiconductor layer 2 is deposited on the substrate 5 by sputtering to form the semiconductor layer 2. The deposited thickness of the semiconductor layer 2 is, for example, 10 nm or more. Alternatively, the deposited thickness of the semiconductor layer 2 may be greater than 0 nm and less than 10 nm. Next, instead of the first target, a second target made of the same material as the metal layer 3 is placed in the sputtering apparatus. As shown in part (c) of FIG. 2, the same material as the metal layer 3 is deposited on the semiconductor layer 2 by sputtering to form a first layer 4a. The deposition thickness of the first layer 4a is, for example, 0.25 nm or more and 1.0 nm or less. Alternatively, the deposition thickness of the first layer 4a may be greater than 0 nm and less than 0.25 nm. Subsequently, the first target is replaced with the second target in the sputtering apparatus, and as shown in part (d) of FIG. 2, the same material as the semiconductor layer 2 is deposited on the first layer 4a by sputtering to form a second layer 4b. The deposition thickness of the second layer 4b is, for example, 0.25 nm or more and 1.0 nm or less. Alternatively, the deposition thickness of the first layer 4a may be greater than 0 nm and less than 0.25 nm. In one example, the deposition thickness of the second layer 4b is equal to the deposition thickness of the first layer 4a. Subsequently, the second target is replaced with the first target in the sputtering apparatus, and as shown in part (e) of FIG. 2, the material of the metal layer 3 is deposited on the second layer 4b by sputtering to form the metal layer 3. The deposition thickness of the metal layer 3 is, for example, 10 nm or more. Alternatively, the deposition thickness of the metal layer 3 may be greater than 0 nm and less than 10 nm.

[0031] When the first layer 4a, the second layer 4b, and the metal layer 3 are deposited by sputtering, material particles impinge on the surface of the substrate 5 with great force. Due to the particles' large kinetic energy, they mix with atoms of the underlying layers (the semiconductor layer 2 for the first layer 4a, the first layer 4a for the second layer 4b, and the second layer 4b for the metal layer 3). Therefore, the first layer 4a and the second layer 4b do not form a neat layer, and a smooth gradient in the composition ratio between the semiconductor layer 2 and the metal layer 3 is formed between the semiconductor layer 2 and the metal layer 3. This increases the intermixed region between the semiconductor layer 2 and the metal layer 3, forming the gradient layer 4. In this case, since the materials constituting the semiconductor layer 2 and the metal layer 3 are in an immiscible system, diffusion does not occur on an atomic level, and clumps of agglomerated atoms of the material constituting the semiconductor layer 2 and the material constituting the metal layer 3 may form, respectively. Through the above steps, the device 1 is fabricated.

[0032] Parts (a) to (d) of FIG. 3 are schematic diagrams illustrating a method for fabricating a device 1 in which the materials constituting the semiconductor layer 2 and the metal layer 3 form a solid solution. First, as shown in part (a) of FIG. 3, a substrate 5 is prepared. Next, as shown in part (b) of FIG. 3, the substrate 5 is placed in a film formation apparatus, and the semiconductor layer 2 is formed on the substrate 5. The thickness of the semiconductor layer 2 is, for example, 10 nm or more. Alternatively, the deposited thickness of the semiconductor layer 2 may be greater than 0 nm and less than 10 nm. Then, as shown in part (c) of FIG. 3, a metal layer 3 is formed on the semiconductor layer 2. The thickness of the metal layer 3 is, for example, 10 nm or more. Alternatively, the deposited thickness of the metal layer 3 may be greater than 0 nm and less than 10 nm. These film formations can be performed by, for example, sputtering, chemical vapor deposition, or vacuum deposition. 3(d), the substrate 5 is placed in a heat treatment device 9, and heat treatment is performed to mutually diffuse atoms at the interface between the semiconductor layer 2 and the metal layer 3, thereby forming a gradient layer 4. Through the above steps, the device 1 is fabricated. Note that even when the materials constituting the semiconductor layer 2 and the metal layer 3 form a solid solution system, the methods shown in parts (a) to (e) of FIG. 2 may be used.

[0033] The substrate 5 used in each of the above-described manufacturing methods may be removed from the device 1 as needed.

[0034] 4 is a graph showing the change in electrical conductivity of device 1 in the stacking direction. ２ corresponds to the semiconductor layer 2, and the range D ３ corresponds to the metal layer 3, and the range D ４ corresponds to the gradient layer 4.

[0035] As shown in FIG. 4, the electrical conductivity σ of the material constituting the semiconductor layer 2 ２ is the electrical conductivity σ of the material constituting the metal layer 3 ３ Electrical conductivity σ ２ and σ ３ is, for example, greater than 0 and 100 MSm －１ The ratio of these electrical conductivities (σ ３ / σ ２ The lower limit of the ratio (σ ３ / σ ２ ) is, for example, 100,000, but may be larger from the viewpoint of spin current generation. The electrical conductivity of the gradient layer 4 has a gradient and changes continuously from the interface with the semiconductor layer 2 to the interface with the metal layer 3. The rate of change of the electrical conductivity in the gradient layer 4 may or may not be constant in the thickness direction. For example, the rate of change of the electrical conductivity in the region located between the semiconductor layer 2 and the metal layer 3 may be larger than the regions close to the semiconductor layer 2 and the metal layer 3. The change in electrical conductivity is caused by a change in the ratio of the materials constituting the gradient layer 4.

[0036] In the above description, the electrical conductivity may be replaced with the carrier mobility. That is, the carrier mobility μ of the material constituting the semiconductor layer 2 ２ is the carrier mobility μ of the material constituting the metal layer 3 ３ The ratio of these carrier mobilities (μ ３ / μ ２ The lower limit of the ratio (μ ３ / μ ２) is, for example, 100,000, but may be larger from the viewpoint of spin current generation. The carrier mobility of the gradient layer 4 has a gradient and changes continuously from the interface with the semiconductor layer 2 to the interface with the metal layer 3. The rate of change of the carrier mobility in the gradient layer 4 may or may not be constant in the thickness direction. For example, the rate of change of the carrier mobility in the region located between the semiconductor layer 2 and the metal layer 3 may be larger than the regions close to the semiconductor layer 2 and the metal layer 3. The change in carrier mobility is caused by a change in the ratio of the materials constituting the gradient layer 4.

[0037] Parts (a) and (b) of Fig. 5 are schematic diagrams showing the speed of electrons moving inside the device 1 or the magnitude of current density when a voltage is applied in a direction intersecting the stacking direction. Part (a) of Fig. 5 shows the entire device 1, and part (b) of Fig. 5 shows an enlarged view of the gradient layer 4 and its vicinity. Arrow A in the figure ２ indicates the movement of electrons in the semiconductor layer 2, and arrow A ３ indicates the movement of electrons in the metal layer 3, and arrow A ４ indicates the movement of electrons in the gradient layer 4. ２ ~A ４ The length of the arrow represents the electron movement speed or current density, and the longer the arrow, the greater the electron movement speed or current density. When voltage is applied to a material containing free electrons, each electron repeatedly accelerates and decelerates while colliding with scatterers in the material, moving in a zigzag pattern through the material in the direction of the applied voltage. When viewed on a large scale in terms of time and space, this can be seen as a group of electrons moving uniformly in one direction. Arrow A in parts (a) and (b) of Figure 5 ２ ~A ４ is a representation of the uniform movement of such electrons.

[0038] The current density in the metal layer 3 with high electrical conductivity is higher than the current density of electrons moving through the semiconductor layer 2 with low electrical conductivity. Also, the movement speed of electrons moving through the metal layer 3 with high carrier mobility is faster than the movement speed of electrons moving through the semiconductor layer 2 with low carrier mobility. Therefore, arrow A ３ is arrow A ２5B ). On the other hand, unlike the semiconductor layer 2 and the metal layer 3, which have uniform electrical conductivity or carrier mobility, the gradient layer 4 exhibits a non-uniform distribution of current density or electron migration velocity. In this embodiment, the gradient layer 4 has a gradient in electrical conductivity or carrier mobility, and the electrical conductivity or carrier mobility continuously changes, being high near the interface with the metal layer 3 and low near the interface with the semiconductor layer 2. Therefore, as shown in part (b) of FIG. 5B , the current density or electron migration velocity in the gradient layer 4 continuously changes, being high near the interface with the metal layer 3 and low near the interface with the semiconductor layer 2. The rate of change of the current density or electron migration velocity in the gradient layer 4 may or may not be constant in the thickness direction. For example, the rate of change of the current density or electron migration velocity in the region intermediate between the semiconductor layer 2 and the metal layer 3 may be higher than the region close to the semiconductor layer 2 and the region close to the metal layer 3. Such a change in current density or electron migration velocity is also due to a change in the ratio of the materials constituting the gradient layer 4.

[0039] The spin current generation function in device 1 will now be described. FIG. 6 is a schematic diagram illustrating the spin current generation mechanism using Rayleigh waves as a reference example. Rayleigh waves are a type of acoustic wave, a phenomenon in which elastic deformation of a solid propagates across a surface. When a pair of comb-shaped electrodes is arranged facing each other on the surface of a piezoelectric body and a high-frequency voltage is applied between these comb-shaped electrodes, Rayleigh waves are generated on the surface of the piezoelectric body. When a metal coating 102 is formed in the direction of the Rayleigh waves, the Rayleigh waves propagate along the surface 102a of the metal coating 102. At this time, in a cross section near the surface 102a of the metal coating 102, a lattice point Q in the metal coating 102 rotates elliptically. Note that two circles C1 and C2 in the figure represent the loci of two representative lattice points Q1 and Q2, respectively. This means that each lattice point Q in the metal coating 102 has angular momentum. The rotational frequency reaches several GHz. Due to the law of conservation of angular momentum, mechanical rotational motion is converted into electron spin, known as the Barnett effect, and this angular momentum is converted into electron spin (up spin or down spin) in one direction. Normally, in a paramagnetic material, the number of up spins and down spins, which are opposite in direction, are equal locally. However, when the number of electron spins on one side increases, this equilibrium state is disturbed, and a concentration of up spins and down spins occurs. In other words, a region is created where one spin is more abundant than the other. At this time, to maintain the equilibrium state between the up spins and down spins, the spins move in a direction that eliminates the concentration. This is spin current. However, since there is no movement of charge, no current flows.

[0040] The generation of spin current in this embodiment can also be explained by this mechanism. Focusing on a microscopic region of the gradient layer 4, it can be considered that the electron velocity field or current field (vector field) rotates due to differences in electron movement speed or current density (arrow Ar in part (b) of Figure 5). The magnitude of the rotation Ar of this velocity field or current field can also be understood as vorticity. The rotation Ar of this velocity field or current field results in the existence of angular momentum in the flow of multiple electrons in the gradient layer 4. This angular momentum is then converted into unidirectional electron spin (up spin or down spin). This disrupts the equilibrium state of the up spin and down spin, causing a bias in the relative distribution of the up spin and down spin. As a result, a spin current is generated in a direction that eliminates the distribution bias (i.e., a direction from the gradient layer 4 to the metal layer 3).

[0041] As shown in the examples below, the above effects enable the generation of spin currents of magnitudes equal to or greater than those based on spin-orbit interaction (SOI). Furthermore, while conventional SOI-based spin current generation requires special materials, such as noble metals (e.g., Pt) that generate SOI, the above effects are realized simply by forming a gradient in carrier mobility or electrical conductivity, and do not require special materials such as Pt. In other words, by combining a metal layer, such as Al, which is abundant in the Earth's crust, with a semiconductor layer, such as Si, which is abundant in the Earth's crust, a gradient layer 4 with a gradient in carrier mobility or electrical conductivity can be easily formed. Therefore, large spin currents can be generated without excessively limiting the materials used.

[0042] Furthermore, low electrical conductivity of spintronic devices can cause problems such as wiring delays and Joule losses in integrated circuits. Furthermore, the performance of semiconductor devices is often degraded by contamination with elements that cause SOI. Therefore, there is a need for spintronic devices that are highly conductive and do not rely on elements that cause SOI. In the device 1 of this embodiment, the metal layer 3 and the semiconductor layer 2 have higher electrical conductivity than oxides, which can reduce problems such as wiring delays and Joule losses in integrated circuits in devices such as magnetic memories that include this device 1.

[0043] As described above, the metal layer 3 may contain Al. Alternatively, the metal layer 3 may be an Al layer. Al is the third most abundant element in the Earth's crust after oxygen (O) and Si, and is the most abundant element among metallic elements. Furthermore, Al has a relatively high electrical conductivity among metallic elements. Therefore, it is possible to provide a sustainable spintronics device that can reduce power consumption.

[0044] As described above, the semiconductor layer 2 may contain Si. Alternatively, the semiconductor layer 2 may be a Si layer. Si is the second most abundant element in the Earth's crust after oxygen (O), and is the most abundant element in semiconductors. Therefore, a sustainable spintronics device can be provided.

[0045] When the metal layer 3 is an Al layer and the semiconductor layer 2 is a Si layer (i.e., when the gradient layer 4 is made of Si and Al), the thickness of the gradient layer 4 may be 2.4 nm or less. According to experiments by the inventors, when the gradient layer 4 has such a thickness, it is possible to generate a spin current that is larger than the spin current generated by SOI.

[0046] As described above, one example of a method for fabricating the device 1 according to this embodiment includes the steps of: forming a first layer 4a by sputtering the same material as the metal layer 3 on the semiconductor layer 2; forming a second layer 4b by sputtering the same material as the semiconductor layer 2 on the first layer 4a; and forming a metal layer 3 on the second layer 4b. In this fabrication method, the gradient layer 4 is formed by intermixing of atoms from the first layer 4a and the second layer 4b during sputtering. The thickness of the gradient layer 4 depends on the total thickness of the first layer 4a and the second layer 4b. Therefore, a gradient layer 4 of any desired thickness can be easily formed. Alternatively, the gradient layer 4 can be formed by simultaneously depositing the material of the semiconductor layer 2 and the material of the metal layer 3 and gradually changing the deposition ratio. However, in this case, targets made of the material of the semiconductor layer 2 and the material of the metal layer 3 must be simultaneously installed in the sputtering apparatus, which increases the size of the sputtering apparatus. In the manufacturing method of this embodiment, the material of the semiconductor layer 2 and the material of the metal layer 3 are alternately deposited, so it is sufficient to alternately place targets made of the material of the semiconductor layer 2 and targets made of the material of the metal layer 3 in the sputtering apparatus. Therefore, the number of targets simultaneously placed in the sputtering apparatus can be reduced, allowing the sputtering apparatus to be made smaller.

[0047] (Example) An experiment conducted by the present inventor to confirm the above theory will be described. As shown in FIG. 7, the present inventor formed a Si layer (semiconductor layer 2: thickness 10 nm) and an Al layer (first layer 4a: thickness (t ｉ / 2) nm), Si layer (second layer 4b: thickness (t ｉ / 2) nm), Al layer (metal layer 3: thickness 10 nm), Ni ０．９５ Cu ０．０５ Layer 6 (thickness 10 nm), and SiO ２ The first layer 4a and the second layer 4b were formed in this order. ｉ The total thickness t was varied from 0.0 nm to 2.0 nm in 0.5 nm increments, and five samples were prepared. ｉ Setting the thickness to 0.0 nm means that the first layer 4a and the second layer 4b are not formed.

[0048] Specifically, these layers were formed on a surface-oxidized Si substrate by magnetron sputtering at room temperature. The chamber base pressure before deposition of these layers was 2.0 × 10 －４ The argon (Ar) pressure was 0.21 Pa, and the argon (Ar) flow rate was 4.0 sccm. For the formation of the Al layer, a 99.9% pure Al target was used, and the power density was 1.4 W / m ２ The Si layer was deposited by radio frequency (RF) sputtering at 13.56 MHz with a deposition rate of 0.043 nm / s. A non-doped Si target was used for the deposition of the Si layer, and the power density was 3.5 W / m. ２ RF sputtering was performed at 13.56 MHz with a deposition rate of 0.062 nm / s. ０．９５ Cu ０．０５ In the production of the layer, 99.9% pure Ni ０．９５ Cu ０．０５ An alloy target was used, and the power density was 1.4 W / m ２ Direct current (DC) sputtering was performed at a deposition rate of 0.2 nm / s. ２ In the production of the layer, 99.99% pure SiO ２ A target was used, and the power density was 3.5 W / m ２ The multilayer film was then subjected to photolithography and lift-off processes to fabricate strip-shaped samples with a width of 10 μm and a length of 100 μm.

[0049] Parts (a) and (b) of Figures 8 to 10 are scanning transmission electron microscope (STEM) images taken by a high-angle annular dark field (HAADF) method, showing the layer structure of the fabricated sample. In Figures 8 to 10, part (a) shows the semiconductor layer 2 (Si layer), the metal layer 3 (Al layer), and the Ni ０．９５ Cu ０．０５ Layer 6, and SiO ２ 8 shows the cross-sectional structure of the layer 7. Part (b) shows an enlarged view of the boundary between the semiconductor layer 2 and the metal layer 3. Parts (a) and (b) of FIG. 8 show the total thickness tｉ is set to 2.0 nm (i.e., the thickness t ｉ / 2 and the thickness t of the second layer 4b ｉ 9 shows the results when the total thickness t ｉ is set to 1.0 nm (i.e., the thickness t ｉ / 2 and the thickness t of the second layer 4b ｉ 10 shows the results when the total thickness t ｉ is set to 0.0 nm (that is, the metal layer 3 is formed directly on the semiconductor layer 2 without forming the first layer 4a and the second layer 4b).

[0050] Part (c) of each of Figures 8 to 10 is a graph showing the distribution of Si and Al atomic concentrations obtained by energy dispersive X-ray spectroscopy (EDS) within the dashed frame in part (b) of each figure. In the graph in part (c), the horizontal axis represents the thickness direction position (nm) and the vertical axis represents the atomic concentration (atomic %). In part (c), line G1 represents the analysis results of the Al concentration, and line G2 represents a function fitted to line G1. Line G3 represents the analysis results of the Si concentration, and line G4 represents a function fitted to line G3. The functions of lines G2 and G4 are expressed by the following mathematical formula (1): However, C １ and C ２ The z axis represents the position in the thickness direction, and the z axis represents the composition at the upper and lower ends of the dashed frame in part (b). ｉｎｔ is the center position of the boundary portion in the thickness direction. L is the thickness of the composition gradient from Si to Al (i.e., the thickness of the gradient layer 4).

[0051] As shown in part (c) of each of Figures 8 and 9, it can be seen that by forming the first layer 4a and the second layer 4b, a gradient layer 4 having a gradual gradient in composition is suitably formed. As a result of the analysis, it was found that the total thickness t ｉWhen the thickness t of the gradient layer 4 was set to 2.0 nm, the thickness L of the gradient layer 4 was 2.4 nm. ｉ When the thickness L of the gradient layer 4 was set to 1.0 nm, the thickness L of the gradient layer 4 was 1.3 nm. Although a region with a gradual composition gradient is also formed in part (c) of Figure 10, the thickness L of the gradient layer 4 is 1.1 nm, which is close to the lower limit of spatial resolution. Therefore, it is presumed that the thickness L of the gradient layer 4 is actually smaller than 1.1 nm, resulting in a sharp interface between Si and Al. Parts (a) and (b) of Figure 11 are nanobeam electron diffraction (NBED) patterns for the semiconductor layer 2 (Si layer) and the metal layer 3 (Al layer), each having a thickness of 10 nm. It can be seen that the semiconductor layer 2 (Si layer) has an amorphous structure, and the metal layer 3 (Al layer) has a polycrystalline structure.

[0052] When a current is applied to a two-layer structure consisting of a non-magnetic layer and a ferromagnetic layer, part of the spin current generated in the non-magnetic layer moves toward the ferromagnetic layer, and a spin torque is applied to the magnetization of the ferromagnetic layer. This torque is a damping-like torque τ ＤＬ On the other hand, the field-like torque τ ＦＬ Another spin torque, known as the polarization σ, arises from the spin current reflected at the interface between the non-magnetic and ferromagnetic layers. ｓ These torques τ on the magnetization m are generated by the spin current with ＤＬ , τ ＦＬ The effect of is described by the following equation (2): However, ξ ＤＬ and ξ ＦＬ is the current density j ｃ are the damping-like torque and field-like torque efficiencies for ０ , and h are the elementary charge, vacuum permeability, and normalized Planck's constant, respectively. M ｓ is the saturation magnetization, and d ＦＭ is the thickness of the ferromagnetic layer.

[0053] In this example, spin torque ferromagnetic resonance (ST-FMR) measurements were performed to evaluate the strength of the spin torque generated by passing a current through the sample. Fig. 12 is a diagram for explaining the principle of ST-FMR measurements. An AC current I was passed in the longitudinal direction of a sample S having a nonmagnetic layer NM and a ferromagnetic layer FM. ｒｆ When an AC current I ｒｆ The alternating magnetic field h is perpendicular to ｒｆ At the same time, spin accumulation occurs in the boundary region between the non-magnetic layer NM and the ferromagnetic layer FM due to the spin-Hall effect (SHE). ｓ is injected into the ferromagnetic layer FM, and a spin torque ST acts on the magnetization m. Then, an external magnetic field B acts on the magnetization m of the ferromagnetic layer FM, and ferromagnetic resonance FMR, which is the precession of the magnetization m, is excited. This ST-FMR excitation generates an AC current I ｒｆ A DC voltage is generated in the same direction as the spin torque. By measuring the magnitude of this DC voltage, the strength of the spin torque can be determined.

[0054] FIG. 13 shows the circuit used for ST-FMR measurements. This circuit includes a substrate 10 on which a sample S is mounted, an AC current source 11, a bias tee circuit 12, and a voltmeter 13. Conductive films 10a to 10c with a thickness of 70 nm are formed on the surface of the substrate 10, forming a coplanar waveguide. The conductive films 10a to 10c are, for example, Au films. One end of each of the conductive films 10a to 10c is aligned in this order along one side of the substrate 10. The other end of each of the conductive films 10a and 10c is electrically shorted to one end of the sample S in the longitudinal direction (x direction). The other end of the conductive film 10b is electrically shorted to the other end of the sample S in the longitudinal direction. The conductive films 10a and 10c are connected to the reference potential line (ground potential line) of this circuit. The conductive film 10b is connected to a node 121 of the bias tee circuit 12. The bias tee circuit 12 includes a capacitor 122 having one end connected to the node 121 and the other end connected to the AC current source 11, and an inductor 123 having one end connected to the node 121 and the other end connected to the voltmeter 13. The AC current source 11 has one end connected to the capacitor 122 and the other end connected to a reference potential line (ground potential line), and outputs an AC current I ｒｆ The voltmeter 13 has one end connected to the inductor 123 and the other end connected to a reference potential line (ground potential line), and measures the voltage generated between the conductive films 10a, 10c and the conductive film 10b. Note that FIG. 13 shows an orthogonal coordinate system consisting of the x direction, which is the longitudinal direction of the strip-shaped sample S, and the y direction, which is the lateral direction, and an angle θ ｍ Furthermore, in FIG. 13, the AC current I ｒｆ An arrow indicating the

[0055] In this example, a microwave having a power of 20 dBm and a frequency of 20 GHz is output from an AC current source 11, and an AC current I ｒｆ The magnitude of the DC voltage was measured by the voltmeter 13 while sweeping the external magnetic field B between 0 T and 2.0 T. All measurements were carried out at room temperature.

[0056] Part (a) of Figure 14 is a graph showing, as an example, the ST-FMR spectrum of a sample with ti = 0.5 nm measured in this manner. In part (a) of Figure 14, the horizontal axis indicates the external magnetic field (mT), and the vertical axis indicates the magnitude of the DC voltage (µV). Part (b) of Figure 14 shows the symmetric (graph G51) and antisymmetric (graph G52) Lorentz function components included in the graph shown in part (a) of Figure 11. Here, in ST-FMR, ξ ＦＬ ξ when is negligible ＤＬ The spin torque efficiency ξ, which is commonly used as an estimate of ＦＭＲ satisfies the following formula (3). This spin torque efficiency ξ ＦＭＲ was evaluated based on the amplitude ratio Vs / Va between the symmetric Lorentzian function component Vs and the antisymmetric Lorentzian function component Va. As a result, for example, t ｉ = 0.5 nm sample, the spin torque efficiency ξ ＦＭＲ = 0.029, and t ｉ = 1.0 nm sample, the spin torque efficiency ξ ＦＭＲ = 0.024, and t ｉ = 2.0 nm sample, the spin torque efficiency ξ ＦＭＲ The obtained spin torque efficiency ξ ＦＭＲ and the total thickness t of the first layer 4a and the second layer 4b. ｉ 15 is a graph showing the relationship between the total thickness t ｉ (nm), and the vertical axis represents the spin torque efficiency ξ ＦＭＲ (More specifically, ξ ＦＭＲ (standard deviation calculated from the least squares deviation of the fitting parameters used in the calculation of ).

[0057] As shown in FIG. ｉ = Spin torque efficiency ξ of samples with 0.5 nm to 2.0 nm ＦＭＲ The figure shows the structure of an Al layer (10 nm) and Ni layer fabricated on a surface-oxidized Si substrate. ９５ Cu ５ The spin torque efficiency ξ of the reference sample with a bilayer structure of 10 nm ＦＭＲ A larger value was obtained compared to the dashed line G in the figure. ｉ= 0.5 nm to 2.0 nm, the smaller ti is, the larger the spin torque efficiency ξ ＦＭＲ was obtained. ｉ =0 nm, that is, the spin torque efficiency ξ in the sample in which the first layer 4a and the second layer 4b are not formed ＦＭＲ was smaller than that of the reference sample (dashed line G). This result means that in the sample without the first layer 4 a and the second layer 4 b (i.e., without the gradient layer 4), most of the spin current is generated in the metal layer 3 through the spin Hall effect, and the sharp Si / Al interface does not generate additional spin current. In other words, it can be said that in the other samples, the nanometer-thickness gradient from the Si layer to the Al layer is the most important factor for the generation of spin current in the sample.

[0058] 16(a) shows the relationship between the symmetric Lorentz function component Vs and the applied angle θ of the external magnetic field B. ｍ 16 is a graph showing the relationship between the antisymmetric Lorentz function component Va and the applied angle θ of the external magnetic field B. ｍ These graphs show that a spin current having the same spin polarization as the spin Hall effect in bulk SOI is generated.

[0059] The large difference in electrical conductivity between the non-magnetic and ferromagnetic layers increases the field-like torque efficiency ξ ＦＬ As shown in the above formula, the damping-like torque efficiency ξ ＤＬ and field-like torque efficiency ξ ＦＬ Both of these are the spin torque efficiency ξ ＦＭＲ and the thickness of the ferromagnetic layer d ＦＭ Furthermore, the damping-like torque efficiency ξ ＤＬ and field-like torque efficiency ξ ＦＬ The ratio of (ξ ＦＬ / ξ ＤＬ ) is the interface between the non-magnetic layer and the ferromagnetic layer, i.e., the metal layer 3 (Al layer) and Ni ０．９５ Cu ０．０５ It depends on the condition of the interface with layer 6. Therefore, the ratio (ξ ＦＬ / ξ ＤＬThe value of t is determined independently of the thickness L of the gradient layer 4 between the semiconductor layer 2 (Si layer) and the metal layer 3 (Al layer). ｉ Damping-like torque efficiency ξ in the sample with ρ = 1.0 nm ＤＬ and field-like torque efficiency ξ ＦＬ Based on each value of ＦＬ / ξ ＤＬ ) was 3.

[0060] FIG. 17 shows the spin torque efficiency ξ ＦＭＲ and damping-like torque efficiency ξ ＤＬ and field-like torque efficiency ξ ＦＬ In FIG. 17, the horizontal axis represents the damping-like torque efficiency ξ ＤＬ The vertical axis represents the field-like torque efficiency ξ ＦＬ Also, the spin torque efficiency ξ ＦＭＲ is shown in different shades of color, and the darker the color, the greater the spin torque efficiency ξ ＦＭＲ The smaller the value and the lighter the color, the greater the spin torque efficiency ξ ＦＭＲ Moreover, the dashed line D in FIG. ＦＬ / ξ ＤＬ = 3. Furthermore, in FIG. ｉ The plots corresponding to the samples with a spin torque efficiency ξ of 0.0 nm to 2.0 nm are ＦＭＲ The positions on the line D are shown according to the actual measured values ​​(see FIG. 15).

[0061] As is clear from FIG. 17, the damping-like torque efficiency ξ ＤＬ and field-like torque efficiency ξ ＦＬ The size of the total thickness t of the first layer 4a and the second layer 4b ｉ In other words, the damping-like torque efficiency ξ ＤＬ and field-like torque efficiency ξ ＦＬ The magnitude of t increases with decreasing thickness L of the gradient layer 4. For example, t ｉ = 1.0 nm sample damping-like torque efficiency ξ ＤＬ is the damping-like torque efficiency ξ of Pt ＤＬIt reaches three times the size of t ｉ = Damping-like torque efficiency ξ of the 0.5 nm sample ＤＬ will increase even more than that.

[0062] In this embodiment, the ratio (ξ ＦＬ / ξ ＤＬ ) is 3, which suggests that the reflected spin current is three times the transmitted spin current. ０．９５ Cu ０．０５ This is because the electrical conductivity of the layer 6 is one order of magnitude smaller than that of the metal layer 3 (Al layer) on the side into which the spin current is injected. ０．９５ Cu ０．０５ By using a ferromagnetic material with higher electrical conductivity than layer 6, the damping-like torque efficiency ξ ＤＬ can be further increased.

[0063] As mentioned above, t ｉ For samples with t = 0.5 nm to 2.0 nm, ｉ Compared with the sample with t = 0.0 nm, more spin current is generated, and ｉ Among the samples with t = 0.5 nm to 2.0 nm, ｉ The smaller the value, the more spin current was generated. This strongly suggests that the spin current is generated by the rotation of the current velocity field or current field (spin vorticity coupling; SVC) caused by the change in the carrier mobility or electrical conductivity in the thickness direction in the gradient layer 4. It is estimated that the magnitude of the spin current is maximized when the thickness of the gradient layer 4 is equal to the effective mean free path of the electrons.

[0064] The contribution of SVC to the generation of spin current can also be explained by the strong nonreciprocity between electric current and spin current. Here, the nonreciprocity between electric current and spin current means that the conversion efficiency from electric current to spin current is significantly different from the conversion efficiency from spin current to electric current. When the generation of spin current is an SOI-based phenomenon, the conversion efficiency from electric current to spin current and the conversion efficiency from spin current to electric current are nearly equal. On the other hand, when the generation of spin current is an SVC-based phenomenon, the conversion of spin current to electric current is not possible, and therefore the conversion efficiency from spin current to electric current is significantly smaller than the conversion efficiency from electric current to spin current.

[0065] Therefore, in order to evaluate the conversion efficiency from spin current to electric current for the above-mentioned sample, the inventors applied an AC magnetic field to the sample and measured the magnitude of the inverse spin Hall effect due to the generated spin current. ｊｓ→ｊｃ and damping-like torque efficiency ξ ＤＬ 1 is a graph showing the relationship between the damping-like torque efficiency ξ and the torque saturation efficiency ξ. ＤＬ The vertical axis represents the conversion efficiency θ ｊｓ→ｊｃ In the figure, t ｉ The plots corresponding to the samples with thicknesses of 0.0 nm, 0.5 nm, and 2.0 nm are shown. In addition, the plots also show Pt (thickness 10 nm) and Ni as reference examples. ０．９５ Cu ０．０５ The plots for a bilayer film consisting of a 10 nm thick film are also shown. The lines extending above and below each plot represent the θ ｊｓ→ｊｃ σ ...

[0066] As shown in FIG. ｉ For the sample with .theta.=0.0 nm and Pt, the plots are on the straight line E in the figure, and the conversion efficiency .theta. ｊｓ→ｊｃ is the damping-like torque efficiency ξ ＤＬ This means that t ｉ This suggests that spin current is generated by the SOI in the sample with t = 0.0 nm and in Pt. ｉ= Conversion efficiency θ of each sample from 0.5 nm to 2.0 nm ｊｓ→ｊｃ is near zero, and the conversion efficiency θ ｊｓ→ｊｃ is the damping-like torque efficiency ξ ＤＬ It can be seen that the value is extremely small regardless of t ｉ In the samples with t = 0.5 nm to 2.0 nm, the electric current and the spin current have a high non-reciprocity. ｉ This suggests that SVC contributes to the generation of spin current in samples with a spin diameter of 0.5 nm to 2.0 nm.

[0067] FIG. 19 shows the total thickness t ｉ and the electrical conductivity of the sample σ ｅ In this figure, the horizontal axis represents the total thickness t ｉ (nm), and the vertical axis represents electrical conductivity σ ｅ (MSm －１ As shown in the figure, the total thickness t ｉ is 0.0 nm (i.e., when the first layer 4a and the second layer 4b are not formed), the electrical conductivity σ ｅ is the highest, but the total thickness t ｉ In the samples with a total thickness t ｉ The smaller the value, the higher the electrical conductivity of the sample σ ｅ becomes higher, and the total thickness t ｉ Electrical conductivity σ when the thickness is 0.5 nm ｅ is the electrical conductivity σ when the first layer 4a and the second layer 4b are not formed ｅ As mentioned above, t ｉ For samples with t = 0.5 nm to 2.0 nm, ｉ The smaller is the damping-like torque efficiency ξ ＤＬ Therefore, this result is consistent with the damping-like torque efficiency ξ ＤＬ With the increase of electrical conductivity σ ｅ This shows that the spin current generation in this embodiment is due to the SVC rather than the SOI.

[0068] In addition, from the viewpoint of reducing the applied voltage required for magnetic switching by spin torque, the damping-like torque efficiency ξ ＤＬ and the electrical conductivity of the ferromagnetic material σ ｅ In addition, in order to reduce the resistance-capacitance delay that hinders high-speed operation of integrated circuits, it is desirable to have a large value for the product of the electrical conductivity σ ｅ Therefore, the performance index is set as ξ ＤＬ ・σ ｅ ２ Define

[0069] FIG. 20 shows the electrical conductivity σ for each sample. ｅ and damping-like torque efficiency ξ ＤＬ and electrical conductivity σ ｅ The product ξ ＤＬ ・σ ｅ In this figure, the horizontal axis represents the electrical conductivity σ ｅ (unit: MSm －１ ) in logarithm, and the vertical axis is the product ξ ＤＬ ・σ ｅ (unit: MSm －１ ) is shown in logarithm. ｉ The plots for each sample with a SiO2 content of 0.0 nm to 2.0 nm (black circles in the figure) and the plot for the Pt / NiCu bilayer film (white squares in the figure) are shown. ＤＬ ・σ ｅ ２ The contours for t are shown by dashed lines. ｉ In the sample with t = 1.0 nm, the figure of merit exceeds that of the Pt / NiCu bilayer film, ｉ For the sample with a thickness of 1.0 nm, the figure of merit is nearly 10 times that of a Pt / NiCu bilayer film. Thus, the device 1 having the Al / Si gradient layer 4 has the potential to significantly exceed that of Pt, a typical SOI material, in terms of the figure of merit that takes into account the applied voltage and electrical conductivity required for magnetic switching. In other words, a spintronics device that generates spin current based on SVC using the gradient layer 4 can operate at higher speeds and consume less power than one that generates spin current based on SOI. (Second Embodiment)

[0070] 21 is a perspective view showing the configuration of a magnetic memory 30 according to the second embodiment of the present disclosure. The magnetic memory 30 is a magnetic random access memory and includes the device 1 according to the first embodiment. Specifically, the magnetic memory 30 includes memory elements (memory cells) M arranged in a matrix in the row direction (s direction) and column direction (t direction). １，１ ~M Ｉ，Ｊ The figure shows a representative memory element M ｉ，ｊ , M ｉ，（ｊ＋１） , M （ｉ＋１），ｊ , M （ｉ＋１），（ｊ＋１） are shown (i=1, 2, . . . , I-1, j=1, 2, . . . , J-1).

[0071] Part (a) of FIG. 22 shows the memory element M ｉ，ｊ 1 is a cross-sectional view showing the configuration of a memory element M. ｉ，ｊ The present embodiment is a giant magnetoresistance (GMR) element or a tunnel magnetoresistance (TMR) element, and includes a first ferromagnetic layer (fixed layer) 31, a nonmagnetic layer 32 provided on the ferromagnetic layer 31, a second ferromagnetic layer (movable layer) 33 provided on the nonmagnetic layer 32, and a device 1 provided on the ferromagnetic layer 33. The device 1 has a configuration similar to that of the first embodiment. That is, the device 1 includes a metal layer 3 provided on the ferromagnetic layer 33, a semiconductor layer 2 provided on the metal layer 3, and a gradient layer 4 (not shown) formed between the metal layer 3 and the semiconductor layer 2. The configurations of the semiconductor layer 2 and the metal layer 3 are similar to those of the first embodiment, and the carrier mobility or electrical conductivity of the semiconductor layer 2 is lower than that of the metal layer 3. The gradient layer 4 located at the boundary between the metal layer 3 and the semiconductor layer 2 has a gradient of carrier mobility or electrical conductivity in the stacking direction. The rotation of the electron velocity field or current field caused by the gradient in carrier mobility or electrical conductivity generates a spin current in the device 1. A pair of electrodes 35 and 36 are disposed on the metal layer 3. The electrodes 35 and 36 are arranged side by side with a gap between them. An electrode 37 is disposed below the ferromagnetic layer 31.

[0072] Note that the other memory element M shown in FIG. ｉ，（ｊ＋１） , M （ｉ＋１），ｊ , M （ｉ＋１），（ｊ＋１）is also the memory element M shown in part (a) of FIG. ｉ，ｊ The element is a GMR element or a TMR element having a similar structure to that described above.

[0073] The memory element M shown in part (a) of FIG. ｉ，ｊ The relative magnetization M of the ferromagnetic layers 31 and 33 is １ , M ２ The ferromagnetic layers 31 and 33 are made of, for example, NiFe. The ferromagnetic layers 31 and 33 may be made of different materials or the same material. The magnetization M of the ferromagnetic layer 31 １ is fixed, and the magnetization M ２ The material of the non-magnetic layer 32 may be a non-magnetic metal such as Cu, or may be aluminum oxide (Al ２ O ３ Insulators such as silicon dioxide (SiO 2 ) and magnesium oxide (MgO) can also be used.

[0074] Referring again to FIG. 21, the j-th row has a word line WL ｊ are arranged in the (j+1)th row, and the word line WL ｊ＋１ In the i-th column, three bit lines BLA are arranged. ｉ , BLB ｉ , BLC ｉ are arranged, and three bit lines BLA are arranged in the (i+1)th column. ｉ＋１ , BLB ｉ＋１ , BLC ｉ＋１ In this way, at least one word line is provided for each row, and at least three bit lines are provided for each column. ｉ，ｊ , M ｉ，（ｊ＋１） , M （ｉ＋１），ｊ , M （ｉ＋１），（ｊ＋１） A pair of select transistors STA and STB is connected to the i-th column of memory elements M. One current terminal of the select transistor STA is connected to an electrode 35, and one current terminal of the select transistor STB is connected to an electrode 36. ｉ，ｊ , M ｉ，（ｊ＋１） The other current terminals of the select transistors STA and STB connected to the bit line BLA are ｉ , BLB ｉThe (i+1)th column memory element M （ｉ＋１），ｊ , M （ｉ＋１），（ｊ＋１） The other current terminals of the select transistors STA and STB connected to the bit line BLA are ｉ＋１ , BLB ｉ＋１ The jth row memory element M ｉ，ｊ , M （ｉ＋１），ｊ Select transistor STA connected to ， Each control terminal of the STB is connected to a word line WL ｊ The memory element M in the (j+1)th row is connected to ｉ，（ｊ＋１） , M （ｉ＋１），（ｊ＋１） Select transistor STA connected to ， Each control terminal of the STB is connected to a word line WL ｊ＋１ is connected to.

[0075] In addition, the memory element M ｉ，ｊ , M ｉ，（ｊ＋１） The electrode 37 is connected to the bit line BLC ｉ The (i+1)th column memory element M （ｉ＋１），ｊ , M （ｉ＋１），（ｊ＋１） The electrode 37 is connected to the bit line BLC ｉ＋１ The word line WL is connected to ｊ , W.L. ｊ＋１ , bit line BLA ｉ , B.L.A. ｉ＋１ , BLB ｉ , BLB ｉ＋１ , BLC ｉ , and BLC ｉ＋１ is connected to a control circuit (not shown).

[0076] Memory element M ｉ，ｊ , M ｉ，（ｊ＋１） , M （ｉ＋１），ｊ , M （ｉ＋１），（ｊ＋１） When writing to the selected memory element (here, memory element M ｉ，ｊ The word line WL corresponding to ｊ through the select transistor STA of the row ， STB is turned on, and the bit line BLA of the corresponding column ｉ , BLB ｉ By passing a current between the electrodes 35 and 36 through ｉ，ｊ Spin current J in device 1 ｓThis spin current J ｓ is the magnetization M of the ferromagnetic layer 33. ２ interacts with the magnetization M ２ As a result, the magnetization M of the ferromagnetic layer 33 ２ is inverted.

[0077] Memory element M ｉ，ｊ , M ｉ，（ｊ＋１） , M （ｉ＋１），ｊ , M （ｉ＋１），（ｊ＋１） The memory cell reads information by utilizing the GMR effect or the TMR effect. ｉ，ｊ The word line WL corresponding to ｊ through the select transistor STA of the row ， STB is turned on, and the bit line BLA of the corresponding column ｉ , BLB ｉ , BLC ｉ 22(a), when the magnetizations of the ferromagnetic layers 31 and 33 are parallel, the vertical current path passing through the ferromagnetic layer 31, the nonmagnetic layer 32, and the ferromagnetic layer 33 has a relatively low resistance, and the bit line BLA ｉ , BLB ｉ , BLC ｉ On the other hand, as shown in part (b) of FIG. 22, when the magnetization direction of the ferromagnetic layer 33 is reversed and the magnetizations of the ferromagnetic layers 31 and 33 are in an antiparallel state, the vertical current path passing through the ferromagnetic layer 31, the nonmagnetic layer 32, and the ferromagnetic layer 33 has a relatively high resistance, and the bit line BLA ｉ , BLB ｉ , BLC ｉ For example, "0" is read out via

[0078] According to the magnetic memory 30 of this embodiment, a spin current is generated by a device 1 capable of generating a spin current without relying on a specific material, and this spin current interacts with the magnetization of the ferromagnetic layer 33, thereby controlling the magnetization direction of the ferromagnetic layer 33.

[0079] The magnetic memory 30 of this embodiment can be applied to various electronic devices. That is, an electronic device may be equipped with one or more magnetic memories 30. Examples of electronic devices include a memory board equipped with multiple magnetic memories 30, an electronic component equipped with multiple magnetic memories 30 or memory boards, a home appliance equipped with a magnetic memory 30, a memory board, or an electronic component, a personal computer, a smartphone, an in-vehicle device, a measuring device, a control device, and other devices that require memory.

[0080] Furthermore, the magnetic memory 30 of this embodiment can provide the following new effects.

[0081] The efficiency of spin current generation due to the spin Hall effect resulting from spin-orbit interaction (SOI) is given by the spin Hall conductivity σ ＳＨ Just as the current density is obtained by multiplying the voltage V by the electrical conductivity σ (Ohm's law), the current density can be obtained by multiplying the voltage V by the spin Hall conductivity σ ＳＨ The voltage V required to generate the spin current required for bit rewriting in magnetic memory is multiplied by the spin Hall conductivity σ ＳＨ The larger the voltage, the smaller the energy consumption of the bit rewrite. Since the energy consumption of the bit rewrite is proportional to the square of the voltage V, the spin Hall conductivity σ ＳＨ The larger the value, the smaller the energy consumption of bit rewriting can be.

[0082] Here, Figure 23 shows the spin Hall conductivity σ ＳＨ 23 is a graph plotting various materials according to the spin Hall conductivity σ. ＳＨ is divided by h / (4πe) (h is Planck's constant, e is the elementary charge) (unit: Sm －１ ), and the horizontal axis represents electrical conductivity σ (unit: Sm －１ As shown in FIG. 23, in metals such as Cu and Ag, which generally have a large electrical conductivity σ, the spin Hall conductivity σ ＳＨ is small. Also, the spin Hall conductivity σ ＳＨThe electrical conductivity σ of topological insulators such as BiSb, which has a large electrical conductivity σ, is small. If a material with a small electrical conductivity σ is used as the spin current source of a magnetic memory, the wiring resistance of each bit of the magnetic memory increases, resulting in signal delay and attenuation, signal waveform distortion, increased power consumption, electromagnetic wave radiation, and the like, which hinders high-speed and energy-saving operation. In contrast, in this embodiment, by generating spin current based on a completely new principle, it is possible to generate spin current from a material such as AlSi, which has a large electrical conductivity σ but a material-specific spin Hall conductivity σ. ＳＨ A large spin current can be generated using a material with a small t ｉ Plots corresponding to the samples with SiAlO.0, SiAlO.5, SiAl1.0, SiAl1.5, and SiAl2.0 are shown in the figure.

[0083] Part (a) of Fig. 24 is a diagram showing a schematic view of the atomic structures of the semiconductor layer 2, the metal layer 3, and the gradient layer 4. In the figure, the area D ２ corresponds to the semiconductor layer 2, and the range D ３ corresponds to the metal layer 3, and the range D ４ corresponds to the gradient layer 4. The figure also shows a schematic representation of atoms 41 constituting the metal layer 3 and atoms 42 constituting the semiconductor layer 2. As shown in the figure, in the gradient layer 4, the atoms 41 constituting the metal layer 3 and the atoms 42 constituting the semiconductor layer 2 are mutually diffused, with the proportion of atoms 41 increasing closer to the metal layer 3 and the proportion of atoms 42 increasing closer to the semiconductor layer 2. Part (b) of Figure 24 is a graph showing the change in electrical conductivity σ in the thickness direction, with the horizontal axis representing electrical conductivity σ and the vertical axis representing the position in the thickness direction corresponding to part (a).

[0084] As shown in part (b) of FIG. 24, by providing a gradient in composition at the boundary between different materials, the electrical conductivity σ is σ Ｈ (maximum electrical conductivity) to σ Ｌ (minimum electrical conductivity, σ Ｈ >σ Ｌ ) is gradually changed to the maximum electrical conductivity σ Ｈ is the electrical conductivity of the metal layer 3, and the minimum electrical conductivity σ Ｌis the electrical conductivity of the semiconductor layer 2. At this time, the electrical conductivity at the center of the gradient layer 4 is the maximum electrical conductivity σ Ｈ and minimum electrical conductivity σ Ｌ The average value of (σ Ｈ +σ Ｌ ) / 2, so σ Ｈ is σ Ｌ If it is sufficiently larger than σ Ｈ On the other hand, the spin Hall conductivity σ of the spin current generated by the current vortex in the gradient layer 4 can be approximated as ＳＨ is given by the following formula (4) through theoretical calculation. Here, l is the mean free path (collision distance) of electrons flowing through the gradient layer 4. Also, Lh = L / 2 (L is the thickness of the gradient layer 4). As is clear from this formula, the spin Hall conductivity σ of the gradient layer 4 ＳＨ is σ Ｈ This means that the intrinsic spin Hall conductivity σ of the various materials shown in Fig. 23 is proportional to ＳＨ Furthermore, in the above equation (4), we show that a large spin current can be generated by using a material with a large electrical conductivity σ, regardless of the spin Hall conductivity σ. ＳＨ is inversely proportional to the square of Lh. That is, the spin Hall conductivity σ ＳＨ is inversely proportional to the square of the thickness L of the gradient layer 4. Therefore, by reducing the thickness L, it is possible to improve the efficiency of spin current generation without changing the material systems of the semiconductor layer 2 and the metal layer 3. As described above, the magnetic memory 30 of this embodiment, which generates spin current by the rotation of the electron velocity field or current field caused by the gradient of the gradient layer 4 having a carrier mobility or electrical conductivity gradient, can significantly reduce the wiring resistance in each bit compared to conventional magnetic memories, and can suppress signal delay and attenuation, signal waveform distortion, increased power consumption, electromagnetic wave radiation, etc.

[0085] The spintronics device, magnetic memory, and electronic device according to the present invention are not limited to the above-described embodiments, and various modifications are possible. For example, in the above-described embodiments, Al is exemplified as the material for the metal layer 3, and Si is exemplified as the material for the semiconductor layer 2. However, the metal layer 3 may be made of a metal other than Al, and the semiconductor layer 2 may be made of a semiconductor other than Si.

[0086] Furthermore, although preferred embodiments of the present invention have been described in detail, the present invention is not limited to these specific embodiments. In other words, the present invention has only described a portion of the many examples of the present invention, and it goes without saying that various modifications and variations are possible even if not directly described in the examples, as long as the objectives, problems, and effects of the present invention can be achieved. In particular, the combinations of multiple components or functions described in the examples can be changed (added or deleted).

[0087] Furthermore, although the problems and objectives of the present invention are generally described in the "Problems to be Solved by the Invention," they are not limited to this, and it goes without saying that the problems and objectives described in the examples are also valid for each invention. Furthermore, since the effects described in the examples are the reverse of the problems or objectives, their existence should be understood even if the problems or objectives are not directly described there.

[0088] Furthermore, although the examples describe inventions for achieving a problem or purpose, the degree of achievement does not necessarily have to be 100%; it varies depending on the combination of the invention's components. It goes without saying that an invention should not be rejected on the grounds that it does not achieve its purpose, even if it achieves only 10% of the purpose.

[0089] REFERENCE SIGNS LIST 1...spintronic device, 2...semiconductor layer, 3...metal layer, 4...gradient layer, 4a...first layer, 4b...second layer, 5...substrate, 6...Ni ０．９５ Cu ０．０５ layer, 7...SiO ２layer, 9...heat treatment apparatus, 10...substrate, 11...AC current source, 12...bias tee circuit, 13...voltmeter, 30...magnetic memory, 31...ferromagnetic layer, 32...non-magnetic layer, 33...ferromagnetic layer, 35, 36, 37...electrodes, 10a to 10c...conductive film, 102a...surface, 121...node, 122...capacitor, 123...inductor, B...external magnetic field, FM...ferromagnetic layer, J ｓ ...spin current, m...magnetization, FMR...ferromagnetic resonance, NM...non-magnetic layer, Q...lattice point, S...sample, STA, STB...selection transistor, θ ｍ ...angle of applied external magnetic field.

Claims

1. A spintronics device that generates spin current, comprising: a metal layer; a semiconductor layer having a carrier mobility or electrical conductivity lower than that of the metal layer; and a gradient layer located at the interface between the metal layer and the semiconductor layer, the gradient layer having a gradient in carrier mobility or electrical conductivity.

2. The spintronic device of claim 1, wherein the metal layer comprises Al.

3. The spintronic device of claim 1, wherein the metal layer is an Al layer.

4. A spintronic device according to any one of claims 1 to 3, wherein the semiconductor layer comprises Si.

5. A spintronic device according to any one of claims 1 to 3, wherein the semiconductor layer is a Si layer.

6. The spintronic device of claim 1, wherein the metal layer is an Al layer, the semiconductor layer is a Si layer, and the thickness of the graded layer is 2.4 nm or less.

7. A spintronics device according to any one of claims 1 to 6, which generates a spin current by the rotation of an electron velocity field or current field caused by the gradient.

8. The spintronics device according to claim 7, wherein the spin current is generated by angular momentum due to rotation of the electron velocity field or current field.

9. A magnetic memory comprising a spintronic device according to any one of claims 1 to 8.

10. A magnetic memory comprising: a first ferromagnetic layer; a non-magnetic layer provided on the first ferromagnetic layer; a second ferromagnetic layer provided on the non-magnetic layer; a metal layer provided on the second ferromagnetic layer; a semiconductor layer provided on the metal layer, the semiconductor layer having a lower carrier mobility or electrical conductivity than the metal layer; and a gradient layer located at the interface between the metal layer and the semiconductor layer, the gradient layer having a gradient in carrier mobility or electrical conductivity, wherein information is stored by controlling the orientation of magnetization of the second ferromagnetic layer using a spin current generated in the gradient layer.

11. An electronic device equipped with one or more magnetic memories according to claim 9 or 10.

12. A method for producing a spintronic device according to any one of claims 1 to 8, comprising the steps of: depositing the same material as the metal layer on the semiconductor layer by sputtering to form a first layer; depositing the same material as the semiconductor layer on the first layer by sputtering to form a second layer; and forming the metal layer on the second layer.

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