Storage device

Abstract

Provided is a novel memory device. Provided is a memory device in which N (N is an integer of 2 or more) layers of memory layers that each include a plurality of memory cells formed in a matrix are laminated. Along the lamination direction of the memory layers, a write bit line, a read bit line, and a selection line are provided. Along a direction orthogonal to the lamination direction of the memory layers, a write word line and a read word line are provided. The memory cells each have a first transistor, a second transistor, and a capacitive element. The source or drain of the first transistor is electrically connected to the write bit line via a first conductor having a region functioning as a source electrode or a drain electrode. At least one of the upper surface, lateral surface, and lower surface of the first conductor has a region being in contact with the write bit line.

Description

storage device

[0001] One aspect of the present invention relates to a storage device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] Therefore, examples of technical fields related to one embodiment of the present invention include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, testing methods thereof, and methods of using thereof.

[0004] In recent years, development of semiconductor devices such as LSIs, CPUs, and memories (storage devices) has progressed. These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. Furthermore, memories with various storage methods have been developed depending on the application, such as temporary storage during arithmetic processing and long-term storage of data. Typical memory storage methods include DRAM, SRAM, and flash memory.

[0005] Furthermore, as the amount of data handled increases, semiconductor devices with larger storage capacities are required. Patent Document 1 and Non-Patent Document 1 disclose memory cells formed by stacking transistors.

[0006] International Publication No. 2021 / 053473

[0007] M. Oota et. al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0008] An object of one embodiment of the present invention is to provide a storage device with a large storage capacity, a storage device with a small occupation area, a storage device with high reliability, a storage device with low power consumption, or a novel storage device.

[0009] The problems associated with one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. The problems associated with one embodiment of the present invention do not necessarily solve all of the problems listed above and other problems. One embodiment of the present invention solves at least one of the problems listed above and other problems.

[0010] One aspect of the present invention includes N memory layers (N is an integer of 2 or more), a plurality of first wirings extending in a first direction (e.g., Z direction) that is a stacking direction of the N memory layers, a plurality of second wirings extending in the first direction, a plurality of third wirings extending in the first direction, a plurality of fourth wirings extending in a second direction (e.g., X direction or Y direction) that is orthogonal to the first direction, and a plurality of fifth wirings extending in the second direction, each of the N memory layers having a plurality of memory cells arranged in a matrix, each of the plurality of memory cells having a first transistor, a second transistor, and a capacitor, and a gate of the first transistor is connected to the plurality of fourth wirings. a first conductor electrically connected to one of the wirings, one of the source or drain of the first transistor electrically connected to the first wiring via the first conductor, one electrode of the capacitance element electrically connected to the fifth wiring, one electrode of the capacitance element electrically connected to the other of the source or drain of the first transistor and the gate of the second transistor, one of the source or drain of the second transistor electrically connected to the second wiring, and the other of the source or drain of the second transistor electrically connected to the third wiring, and the first conductor has an area on at least one of its top surface, side surface, and bottom surface that is in contact with the first wiring.

[0011] The second transistor may have a source or a drain electrically connected to the second wiring via a second conductor. The second conductor preferably has a region on at least one of its upper surface, side surface, and lower surface that is in contact with the second wiring.

[0012] The other of the source and the drain of the second transistor may be electrically connected to the third wiring via a third conductor. It is preferable that the third conductor has a region on at least one of its top surface, side surface, and bottom surface that is in contact with the third wiring.

[0013] The first transistor is preferably a transistor having a back gate and is preferably a transistor including an oxide semiconductor.

[0014] According to one embodiment of the present invention, a storage device with a large storage capacity, a storage device with a small area, a storage device with high reliability, a storage device with low power consumption, or a novel storage device can be provided.

[0015] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Therefore, one embodiment of the present invention may not have the effects listed above. The other effects are described below and are not mentioned in this section. Those skilled in the art can derive the other effects from the description in the specification or drawings, etc., and can extract them as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects.

[0016] FIG. 1A is a perspective view illustrating an example of the configuration of a semiconductor device. FIG. 1B is a block diagram illustrating an example of the configuration of a semiconductor device. FIG. 2A is a perspective block diagram illustrating an enlarged view of a portion of a memory layer. FIG. 2B is a plan view of a portion of the memory layer viewed from the Z direction. FIG. 3A is a schematic cross-sectional view of a memory cell. FIG. 3B is an example of a circuit configuration of a memory cell. FIG. 4 is a diagram illustrating an example of a cross-sectional configuration of a memory layer. FIG. 5 is a diagram illustrating an example of a circuit configuration of a memory layer. FIG. 6 is a timing chart illustrating an example of the operation of a memory cell 10. FIGS. 7A and 7B are circuit diagrams illustrating an example of the operation of a memory cell 10. FIGS. 8A and 8B are circuit diagrams illustrating an example of the operation of a memory cell 10. FIGS. 9A to 9D are diagrams illustrating an example of the configuration of a semiconductor device. FIG. 10 is a diagram illustrating an example of the configuration of a semiconductor device. FIGS. 11A to 11C are diagrams illustrating an example of the configuration of a semiconductor device. FIGS. 12A and 12B are diagrams illustrating an example of the configuration of a semiconductor device. FIGS. 13A and 13B are diagrams illustrating an example of the configuration of a semiconductor device. FIGS. 14A to 14D are diagrams illustrating an example of the configuration of a semiconductor device. Fig. 15 is a diagram illustrating an example of the configuration of a semiconductor device. Figs. 16A and 16B are perspective views showing an example of an electronic component. Figs. 17A to 17J are diagrams illustrating an example of an electronic device. Figs. 18A to 18E are diagrams illustrating an example of an electronic device. Figs. 19A to 19C are diagrams illustrating an example of an electronic device.

[0017] The embodiments described in this specification will be described below with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Furthermore, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, top views, etc.

[0018] In addition, in the drawings and the like relating to this specification, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the size or aspect ratio is not necessarily limited. Note that the drawings are schematic illustrations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences, etc., may be included.

[0019] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0020] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0021] As an example of the case where X and Y are electrically connected, one or more elements (e.g., switches, transistors, capacitance elements, inductors, resistance elements, diodes, display devices, light-emitting devices, loads, etc.) that enable the electrical connection between X and Y can be connected between X and Y.

[0022] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or amount of current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0023] It should be noted that when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit sandwiched between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit sandwiched between them).

[0024] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0025] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "electrically connected" also includes such cases where one conductive film has the functions of multiple components.

[0026] Furthermore, in this specification, the term "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, parasitic capacitance, or the gate capacitance of a transistor. Therefore, in this specification, the term "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric between the electrodes, but also parasitic capacitance occurring between wiring and one of the source or drain of a transistor and the gate, and the like. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," "pair of regions," and the like. The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It may also be, for example, 1 pF or more and 10 μF or less.

[0027] Furthermore, in this specification and the like, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the amount of current that flows between the source and the drain. The two terminals that function as a source or a drain are the input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the conductivity type of the transistor (n-channel type, p-channel type) and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification and the like, the terms source and drain can be interchanged.

[0028] In this specification and the like, a gate refers to a gate electrode and a part or all of a gate wiring. The gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring, and includes, for example, a scan line in a display device.

[0029] The source refers to a source region, a source electrode, and part or all of a source wiring. The source region refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The source electrode refers to a conductive layer including a portion connected to the source region. The source wiring refers to a wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring. For example, when a signal line in a display device is electrically connected to a source electrode, the signal line is also included in the source wiring.

[0030] The drain refers to a part or all of the drain region, drain electrode, and drain wiring. The drain region refers to a region of the semiconductor layer whose resistivity is equal to or less than a certain value. The drain electrode refers to a conductive layer including a portion connected to the drain region. The drain wiring refers to a wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring. For example, when a signal line in a display device is electrically connected to the drain electrode, the signal line is also included in the drain wiring.

[0031] Furthermore, in this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) may be used. Note that, depending on the structure of a transistor, a back gate may be included in addition to the three terminals described above. In this case, in this specification and the like, one of the gate or back gate of the transistor may be referred to as the first gate, and the other of the gate or back gate of the transistor may be referred to as the second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, the respective gates may be referred to as the first gate, the second gate, the third gate, etc.

[0032] Furthermore, in this specification and the like, the term "node" can be rephrased as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration, device structure, etc. Furthermore, the term "node" can be rephrased as a terminal, wiring, etc.

[0033] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment, in the claims, etc. Furthermore, for example, a component referred to as "first" in one embodiment of this specification, etc. may be omitted in another embodiment, in the claims, etc.

[0034] Furthermore, in this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0035] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0036] Furthermore, in this specification and the like, the term "overlap" does not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0037] Furthermore, in this specification and the like, the terms "adjacent" and "close to" do not necessarily mean that components are in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0038] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Or, depending on the situation, terms such as "film" and "layer" may be replaced with other terms without using terms such as "film" and "layer." For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, the term "conductor" may be changed to the term "conductive layer" or "conductive film." Or, for example, the term "insulating layer" or "insulating film" may be changed to the term "insulator." Or, the term "insulator" may be changed to the term "insulating layer" or "insulating film."

[0039] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region."

[0040] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0041] In addition, in this specification, a "switch" has multiple terminals and has the function of switching (selecting) between conduction and non-conduction between the terminals. For example, when a switch has two terminals and both terminals are conductive, the switch is said to be in a "conductive state" or "on state." When both terminals are non-conductive, the switch is said to be in a "non-conductive state" or "off state." Note that switching between a conductive state or a non-conductive state, or maintaining one of a conductive state or a non-conductive state, is sometimes referred to as "controlling the conductive state."

[0042] In other words, a switch is a device that has the function of controlling whether or not a current flows. Alternatively, a switch is a device that has the function of selecting and switching the path through which a current flows. As an example, an electrical switch, a mechanical switch, etc. can be used. In other words, a switch is not limited to a specific type as long as it can control a current.

[0043] Examples of switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. Furthermore, the "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0044] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. Such a switch has an electrode that can be mechanically moved, and the movement of the electrode selects whether the switch is conductive or non-conductive.

[0045] Note that in this specification and the like, the "on state" (sometimes abbreviated as "on") of a transistor refers to a state in which the source and drain of the transistor can be considered to be electrically short-circuited (also referred to as a "conducting state"). Alternatively, unless otherwise specified, the "on state" refers to a state in which the voltage between the gate and source (also referred to as a "gate voltage" or "Vg") is equal to or higher than a threshold voltage (also referred to as "Vth") in an n-channel transistor, or a state in which Vg is equal to or lower than Vth in a p-channel transistor.

[0046] The "off state" (sometimes abbreviated as "off") of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically disconnected (also referred to as a "non-conduction state"). Alternatively, unless otherwise specified, the "off state" refers to a state in which Vg is lower than Vth for an n-channel transistor, and a state in which Vg is higher than Vth for a p-channel transistor.

[0047] In this specification, the term "on-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is on, and the term "off-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is off.

[0048] In this specification and the like, a high power supply potential VDD (hereinafter simply referred to as "potential VDD" or "VDD") refers to a power supply potential that is higher than a low power supply potential VSS (hereinafter simply referred to as "potential VSS" or "VSS"). The low power supply potential VSS refers to a power supply potential that is lower than the high power supply potential VDD.

[0049] Furthermore, when a potential H (hereinafter also simply referred to as "H") is supplied to the gate of an n-channel transistor, the transistor is turned on. Furthermore, when a potential L (hereinafter also simply referred to as "L") is supplied to the gate of an n-channel transistor, the transistor is turned off. Therefore, the potential H is a potential higher than the potential L. Unless otherwise specified, the potential H and VDD may be the same potential. Furthermore, the potential L is a potential lower than the potential H. Unless otherwise specified, the potential L and the potential VSS may be the same potential.

[0050] Furthermore, the ground potential can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0051] In this specification and the like, a gate refers to a gate electrode and a part or all of a gate wiring, and a gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0052] In this specification, the term "source" refers to a source region, a source electrode, and part or all of a source wiring. The term "source region" refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The term "source electrode" refers to a conductive layer including a portion connected to the source region. The term "source wiring" refers to wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0053] In this specification, the term "drain" refers to a drain region, a drain electrode, and part or all of a drain wiring. The term "drain region" refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The term "drain electrode" refers to a conductive layer including a portion connected to the drain region. The term "drain wiring" refers to wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0054] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0055] In this specification, when referring to counting values ​​and measurement values, terms such as "identical," "same," "equal," or "uniform" (including synonyms thereof) are used, they are considered to include an error of plus or minus 20%, unless otherwise specified.

[0056] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. More specifically, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0057] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as “A”, “b”, “_1”, "[n]”, or "[m, n]” may be added to the symbol.

[0058] Embodiment 1 A configuration example of a memory device 100 including a memory cell 10 (also referred to as a "memory element") will be described.

[0059] 1A is a schematic perspective view illustrating a configuration example of a memory device 100 according to one embodiment of the present invention. FIG. 1B is a block diagram illustrating a configuration example of the memory device 100 according to one embodiment of the present invention. The memory device 100 includes a drive circuit layer 50 and N memory layers 60 (N is an integer of 1 or more).

[0060] The N memory layers 60 are provided on the drive circuit layer 50. By providing the N memory layers 60 on the drive circuit layer 50, the area occupied by the memory device 100 can be reduced. In addition, the memory capacity per unit area can be increased.

[0061] In the present embodiment and the like, the first memory layer 60 is referred to as memory layer 60_1, the second memory layer 60 is referred to as memory layer 60_2, the third memory layer 60 is referred to as memory layer 60_3, and the fourth memory layer 60 is referred to as memory layer 60_4. Furthermore, the kth memory layer 60 (k is an integer of 1 to N) is referred to as memory layer 60_k, and the Nth memory layer 60 is referred to as memory layer 60_N. Note that in the present embodiment and the like, when describing matters relating to all N memory layers 60 or when indicating matters common to each of the N memory layers 60, the term "memory layer 60" may be used.

[0062] <Configuration Example of Drive Circuit Layer 50> The drive circuit layer 50 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0063] In the storage device 100, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0064] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 32.

[0065] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 100. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 100. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0066] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0067] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cells 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0068] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting a wiring WWL (write word line) or a wiring RWL (read word line) specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cell 10, reading data from the memory cell 10, and retaining the read data. The column driver 45 has the function of selecting a wiring WBL (write bit line) or a wiring RBL (read bit line) specified by the column decoder 44.

[0069] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the memory device 100. The data output from the output circuit 48 is a signal RDA.

[0070] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. In this example, the high power supply voltage of the memory device 100 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of PSW22 is controlled by signal PON1, and the on / off of PSW23 is controlled by signal PON2. In FIG. 1B, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0071] <Configuration Example of Memory Layer 60> A configuration example of N memory layers 60 will be described. Each of the N memory layers 60 has a memory array 15. Each memory array 15 has a plurality of memory cells 10. 1A and 1B show an example in which the memory array 15 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or greater).

[0072] The rows and columns extend in directions perpendicular to each other. In this embodiment, the X direction is referred to as the "rows" and the Y direction is referred to as the "columns," but the X direction may also be referred to as the "columns" and the Y direction may also be referred to as the "rows."

[0073] 1B, the memory cell 10 located in the first row and first column is indicated as memory cell 10[1,1], and the memory cell 10 located in the first row and nth column is indicated as memory cell 10[1,n]. The memory cell 10 located in the mth row and first column is indicated as memory cell 10[m,1], and the memory cell 10 located in the mth row and nth column is indicated as memory cell 10[m,n]. The memory cell 10 located in the i-th row and j-th column (i is an integer between 1 and m, and j is an integer between 1 and n) is indicated as memory cell 10[i,j].

[0074] FIG. 2A is a perspective block diagram showing an enlarged view of a portion of the memory layer 60_k. FIG. 2B is a plan view of the portion corresponding to FIG. 2A as viewed from the Z direction. Each layer of the memory layer 60 has n wirings WWL (write word lines) extending in the Y direction (column direction) and n wirings RWL (read word lines) extending in the Y direction (column direction). In FIGS. 2A and 2B, the wiring WWL provided in the jth column is indicated as wiring WWL[j], and the wiring RWL provided in the jth column is indicated as wiring RWL[j]. The wiring WWL[j] and the wiring RWL[j] are electrically connected to the memory cell 10 provided in the jth column. Furthermore, the wiring WWL provided in the j+1th column is indicated as wiring WWL[j+1], and the wiring RWL provided in the j+1th column is indicated as wiring RWL[j+1]. The wiring WWL provided in the j+2th column is indicated as wiring WWL[j+2], the wiring RWL provided in the j+2th column is indicated as wiring RWL[j+2], the wiring WWL provided in the j+3th column is indicated as wiring WWL[j+3], and the wiring RWL provided in the j+3th column is indicated as wiring RWL[j+3].

[0075] The memory layer 60 also has wiring WBL (write bit line), wiring RBL (read bit line), and wiring SL (selection line). The wiring WBL, wiring RBL, and wiring SL extend in the Z direction (vertical direction) and are arranged in a matrix of m rows and R columns. In Figures 2A and 2B, the wiring WBL, wiring RBL, and wiring SL arranged in the i-th row and s-th column (s is an integer greater than or equal to 1 and less than or equal to R) are indicated as wiring WBL[i,s], wiring RBL[i,s], and wiring SL[i,s], respectively.

[0076] In the memory layer 60_k, one wiring WBL is electrically connected to two memory cells 10. One wiring RBL is electrically connected to two memory cells 10. One wiring SL is electrically connected to two memory cells 10. By two adjacent memory cells 10 sharing one wiring WBL, one wiring RBL, and one wiring SL, the area occupied by the memory array 15 can be reduced. Furthermore, the integration degree of the memory cells 10 is improved, and the storage capacity of the storage device 100 can be increased.

[0077] 2A and 2B, the wiring WBL[i,s] and the wiring RBL[i,s] are electrically connected to the memory cell 10[i,j] and the memory cell 10[i,j+1]. The wiring WBL[i,s+1] and the wiring RBL[i,s+1] are electrically connected to the memory cell 10[i,j+2] and the memory cell 10[i,j+3]. The wiring WBL[i,s] and the wiring RBL[i,s] are electrically connected to the memory cell 10[i,2×s−1]_k and the memory cell 10[i,2×s]_k.

[0078] 2A and 2B, the wiring SL[i,s+1] is electrically connected to the memory cell 10[i,j+1] and the memory cell 10[i,j+2]. Note that the memory cell 10[i,j] is electrically connected to the wiring SL[i,s], and the memory cell 10[i,j+3] is electrically connected to the wiring SL[i,s+2].

[0079] The relationship between R and n, which indicates the column position, can be expressed by Equation 1 or Equation 2 when n is an odd number.

[0080] R = (n + 1) / 2 (Equation 1)

[0081] n=2×R−1 (Equation 2)

[0082] The relationship between R and n, which indicates the column position, can be expressed by Equation 3 or Equation 4 when n is an even number.

[0083] R = n / 2 (Equation 3)

[0084] n = 2 × R (Equation 4)

[0085] The column positions s and j can be expressed by Equation 5 or Equation 6 when j is an odd number.

[0086] s = (j + 1) / 2 (Equation 5)

[0087] j=2×s−1 (Equation 6)

[0088] The columns s and j can be expressed by Equation 7 or 8 when j is an even number.

[0089] s = j / 2 (Equation 7)

[0090] j = 2 × s (Equation 8)

[0091] 3A shows a schematic cross-sectional view of a memory cell 10[i,j] and a memory cell 10[i,j+1] of a memory layer 60_k. FIG. 3B shows an example of the circuit configuration of FIG. 3A. Note that FIG. 3A shows an enlarged view of a portion of the schematic cross-sectional view. Furthermore, the wiring RBL[i,s] is provided at a position different from that shown in FIG. 3A. Therefore, the wiring RBL[i,s] is not shown in the cross-sectional view shown in FIG. 3A.

[0092] The memory cell 10[i,j] includes a transistor M1, a transistor M2, and a capacitor C. A memory cell configured with two transistors and one capacitor is also called a 2Tr1C type memory cell. Therefore, the memory cell 10 shown in this embodiment is a 2Tr1C type memory cell.

[0093] In the memory cell 10[i,j], the gate of the transistor M1 is electrically connected to the wiring WWL[j], and one of the source and drain is electrically connected to the wiring WBL[i,s]. Note that FIG. 3A shows a configuration example in which a part of the wiring WWL[j] functions as the gate of the transistor M1. One electrode of the capacitor C is electrically connected to the wiring RWL[j], and the other electrode is electrically connected to the other of the source and drain of the transistor M1. Note that FIG. 3A and other figures show a configuration example in which a part of the wiring RWL[j] functions as one electrode of the capacitor C. Furthermore, the gate of the transistor M2 is electrically connected to the other electrode of the capacitor C, one of the source and drain is electrically connected to the wiring RBL[i,s], and the other of the source and drain is electrically connected to the wiring SL[i,s].

[0094] In the memory cell 10[i,j], the other electrode of the capacitance element C, the other of the source or drain of the transistor M1, and the gate of the transistor M2 are electrically connected and always at the same potential, and this region is called a "node ND."

[0095] In the memory cell 10[i,j+1], the gate of the transistor M1 is electrically connected to the wiring WWL[j+1], and one of the source and drain is electrically connected to the wiring WBL[i,s]. Note that FIG. 3A shows a configuration example in which a part of the wiring WWL[j+1] functions as the gate of the transistor M1. One electrode of the capacitor C is electrically connected to the wiring RWL[j+1], and the other electrode is electrically connected to the other of the source and drain of the transistor M1. Note that FIG. 3A and other figures show a configuration example in which a part of the wiring RWL[j+1] functions as one electrode of the capacitor C. Furthermore, the gate of the transistor M2 is electrically connected to the other electrode of the capacitor C, one of the source and drain is electrically connected to the wiring RBL[i,s], and the other of the source and drain is electrically connected to the wiring SL[i,s+1].

[0096] In the memory cell 10[i, j+1], the other electrode of the capacitance element C, the other of the source or drain of the transistor M1, and the gate of the transistor M2 are electrically connected and always at the same potential, and this region is called a node ND.

[0097] 3A and 3B, transistors having back gates may be used as the transistors M1 and M2. The gate and back gate are arranged to sandwich a semiconductor channel formation region between them. The gate and back gate are formed of conductors. The back gate can function in the same way as the gate. The threshold voltage of the transistor can be changed by changing the potential of the back gate. The potential of the back gate may be the same as the gate, or may be ground potential or any other potential.

[0098] In addition, since the gate and back gate are made of conductors, they also have the function of preventing an electric field generated outside the transistor from acting on the semiconductor in which the channel is formed (particularly, an electrostatic shielding function against static electricity). That is, it is possible to prevent the electrical characteristics of the transistor from fluctuating due to the influence of an external electric field such as static electricity. Furthermore, by providing a back gate, it is possible to reduce the amount of change in the threshold voltage of the transistor before and after the BT test.

[0099] For example, by using a transistor having a back gate as the transistor M1, the influence of an external electric field can be reduced and the transistor M1 can be stably maintained in an off state. Therefore, data written to the node ND can be stably held. By providing a back gate, the operation of the memory cell 10 can be stabilized, and the reliability of the storage device including the memory cell 10 can be improved.

[0100] The semiconductor layers in which the channels of the transistors M1 and M2 are formed can be made of a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like, either singly or in combination. Examples of semiconductor materials include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.

[0101] Note that the transistors M1 and M2 are preferably transistors using an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed (also referred to as "OS transistors"). The band gap of an oxide semiconductor is 2 eV or more, and therefore the off-state current is significantly small. Therefore, the power consumption of the memory cell 10 can be reduced. Therefore, the power consumption of the memory device 100 including the memory cell 10 can be reduced.

[0102] A memory cell including an OS transistor can be called an "OS memory." The memory device 100 including the memory cell can also be called an "OS memory."

[0103] Furthermore, the OS transistor operates stably even in a high-temperature environment, and its characteristics fluctuate little. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range of room temperature to 200° C. Furthermore, the on-state current hardly decreases even in a high-temperature environment. Therefore, the OS memory operates stably even in a high-temperature environment, and high reliability is achieved.

[0104] 3A, the conductor 242a (conductor 242a1, conductor 242a2) including a region that functions as one of the source electrode or drain electrode of the transistor M1 extends beyond the oxide 230 (oxide 230a, oxide 230b) that functions as a semiconductor layer. Therefore, the conductor 242 also functions as a wiring. In FIG. 3A, a portion of each of the upper surface, side surface, and lower surface of the conductor 242a is electrically connected to the wiring WBL[i, s] that extends in the Z direction.

[0105] By having the wiring WBL[i,s] directly contact at least one of the top surface, side surface, and bottom surface of the conductor 242a, there is no need to provide a separate connection electrode, thereby reducing the area occupied by the memory array 15. Furthermore, the integration density of the memory cells 10 is improved, allowing the storage capacity of the storage device 100 to be increased. Note that it is preferable that the wiring WBL[i,s] contact two or more of the top surface, side surface, and bottom surface of the conductor 242a. By having the wiring WBL[i,s] contact multiple surfaces of the conductor 242a, the contact resistance between the wiring WBL[i,s] and the conductor 242a can be reduced.

[0106] Furthermore, the conductor 242b (conductor 242b1, conductor 242b2) including a region functioning as the other of the source or drain of the transistor M1 extends beyond the oxide 230 (oxide 230a, oxide 230b) functioning as a semiconductor layer. In the cross-sectional configuration example shown in FIG. 3A, a conductor 366 is provided in contact with the lower surface of the conductor 242b. The conductor 242b and the gate of the transistor M2 are electrically connected via the conductor 366. The conductor 366 functions as a contact plug.

[0107] By providing the conductor 366 in the region overlapping with the conductor 242b and electrically connecting it to the conductor in the lower layer, the connection distance between them can be shortened. In addition, the number of wirings required to configure the memory cell 10 can be reduced. Therefore, the area occupied by the memory cell 10 can be reduced. Therefore, the memory capacity and memory density of the memory device can be increased.

[0108] Although not shown, one of the source and drain of the transistor M2 may be electrically connected to the wiring RBL[i,s] in a similar configuration to the one of the source and drain of the transistor M1. Specifically, the transistor M2 may be electrically connected to the wiring RBL[i,s] through a conductor including a region that functions as one of the source and drain electrodes of the transistor M2. Preferably, at least one of the top surface, side surface, and bottom surface of the conductor is in contact with the wiring RBL[i,s].

[0109] The other of the source and drain of the transistor M2 may be electrically connected to the wiring SL[i,s] in a similar configuration to the other of the source and drain of the transistor M1. Specifically, the other of the source and drain of the transistor M2 may be electrically connected to the wiring SL[i,s] through a conductor including a region that functions as the other of the source and drain electrodes of the transistor M2. Preferably, at least one of the top surface, side surface, and bottom surface of the conductor is in contact with the wiring SL[i,s].

[0110] The cross-sectional structure of the memory cell 10 will be described in detail in other embodiments.

[0111] 4 shows an example of a cross-sectional configuration of a memory layer 60 in which memory layers 60_1 to 60_5 are stacked. FIG. 5 shows an example of a circuit configuration of FIG. 4. In FIGS. 4 and 5, the memory cells 10[i,j] included in the memory layers 60_1 to 60_5 are denoted as memory cells 10[i,j]_1 to 10[i,j]_5. The wiring WWL[j] included in the memory layer 60_5 is denoted as wiring WWL[j]_5, and the wiring RWL[j] included in the memory layer 60_5 is denoted as wiring RWL[j]_5. The wiring WWL[j+1] included in the memory layer 60_5 is denoted as wiring WWL[j+1]_5, and the wiring RWL[j+1] included in the memory layer 60_5 is denoted as wiring RWL[j+1]_5.

[0112] 4 and 5 show an example of a configuration in which five memory layers 60 are stacked, but the number of stacked memory layers 60 is not limited to five. By increasing the number of stacked memory layers 60, the memory capacity of the memory device 100 can be increased without increasing the area occupied by the memory cells 10. Therefore, the area occupied per bit is reduced, and a small memory device with a large memory capacity can be realized.

[0113] <Operation Example of Memory Cell 10> Next, an example of a data write operation and an example of a data read operation of the memory cell 10 will be described. In this embodiment, normally-off n-channel transistors are used as the transistors M1 and M2. FIG. 6 is a timing chart for explaining an example of an operation of the memory cell 10. FIGS. 7A, 7B, 8A, and 8B are circuit diagrams for explaining an example of an operation of the memory cell 10.

[0114] In addition, in drawings and the like, to indicate the potential of a wiring or an electrode, "H" indicating a potential H or "L" indicating a potential L may be added next to the wiring or electrode. Furthermore, a wiring or electrode in which a potential change has occurred may be marked with "H" or "L" enclosed in a box. Furthermore, when a transistor is in an off state, an "x" symbol may be added over the transistor.

[0115] First, in the period T0, the potential of the wiring WWL is VSS, the potential of the wiring RWL, the wiring WBL, and the node ND is L, and the potential of the wiring RBL and the wiring SL is H (see FIG. 6). In this embodiment and the like, VSS is a potential equal to or lower than a potential 2L described later. GND is supplied to the back gates of the transistors M1 and M2.

[0116] [Data Write Operation] In a period T1, an H potential is supplied to the wiring RWL, the wiring WWL, and the wiring WBL (see FIGS. 6 and 7A). Then, the transistor M1 is turned on, and an H potential is written to the node ND as data indicating "1." More precisely, an amount of charge is supplied to the node ND such that the potential of the node ND becomes an H potential.

[0117] Furthermore, the gate, source, and drain of the transistor M2 are all at the same potential (H potential), so the transistor M2 is turned off.

[0118] [Retention Operation] In the period T2, VSS is supplied to the wiring WWL, and the potential L is supplied to the wiring RWL. As a result, the transistor M1 is turned off, and the node ND is brought into a floating state. Therefore, the data (charge) written to the node ND is retained (see FIGS. 6 and 7B).

[0119] At this time, since the node ND is in a floating state, the potential of the node ND also changes following the potential fluctuation of the wiring RWL. Note that the amount of potential fluctuation of the node ND is determined by the capacitance ratio between the capacitance element C and the gate capacitance of the transistor M2. For example, if the capacitance value of the capacitance element C is sufficiently larger than the gate capacitance of the transistor M2, the same potential change as the potential change of the wiring RWL also occurs in the node ND.

[0120] In this embodiment, the capacitance of the capacitor C is set to be sufficiently larger than the gate capacitance of the transistor M2. Therefore, when the potential of the wiring RWL changes from the potential H to the potential L, the potential of the node ND also changes from the potential H to the potential L.

[0121] Note that when the potential L is supplied to the node ND as data indicating "0" in the period T1, the potential of the node ND in the period T2 becomes a potential (also referred to as "potential 2L") that is lower than the potential L by the potential difference between the potential H and the potential L. To prevent the transistor M1 from being turned on when the node ND becomes the potential 2L, the VSS supplied to the gate of the transistor M1 needs to be a potential equal to or lower than the potential 2L.

[0122] As described above, an OS transistor has an extremely low off-state current. By using an OS transistor as the transistor M1, data written to the node ND can be held for a long period of time. Therefore, the node ND does not need to be refreshed, and the power consumption of the memory cell 10 can be reduced. Therefore, the power consumption of the memory device 100 can be reduced.

[0123] In addition, an OS transistor has a higher drain breakdown voltage than a transistor using silicon in a semiconductor layer in which a channel is formed (also referred to as a Si transistor). Therefore, by using the transistor M1 as an OS transistor, the range of potentials held in the node ND can be widened. Therefore, multilevel data or analog data can be held in the node ND.

[0124] [Read Operation] In the period T3, the wiring RBL is precharged (H(Pre)) to a potential H. That is, the wiring RBL is kept in a floating state at the potential H (see FIGS. 6 and 8A).

[0125] Next, in a period T4, a potential H is supplied to the wiring RWL, and a potential L is supplied to the wiring SL (see FIGS. 6 and 8B). When the wiring RWL changes from the potential L to the potential H, the potential of the node ND also changes from the potential L to the potential H. When the potential of the node ND becomes the potential H and the potential of the wiring SL becomes the potential L, the transistor M2 is turned on. When the transistor M2 is turned on, the wiring RBL and the wiring SL are brought into electrical conduction, and the potential of the wiring RBL changes from the H potential to the L potential.

[0126] On the other hand, when an L potential is written to the node ND as data indicating "0", the transistor M2 does not turn on even when an L potential is supplied to the wiring SL. Therefore, by detecting a change in the potential of the wiring RBL when an L potential is supplied to the wiring SL, the data written to the memory cell 10 can be read.

[0127] In the memory cell 10 using an OS transistor, charge is written to the node ND via the OS transistor, so the high voltage required in conventional flash memories is not necessary and high-speed write operations can be achieved. Furthermore, because charge is not injected into or extracted from the floating gate or the charge trapping layer, the memory cell 10 using an OS transistor can write and read data an essentially unlimited number of times. Unlike flash memories, the memory cell 10 using an OS transistor does not exhibit instability due to an increase in electron trap centers even during repeated rewrite operations. The memory cell 10 using an OS transistor exhibits less degradation and higher reliability than conventional flash memories.

[0128] The memory cell 10 using an OS transistor does not involve a structural change at the atomic level, unlike a magnetic memory or a resistance change memory, etc. Therefore, the memory cell 10 using an OS transistor has higher rewrite endurance than a magnetic memory or a resistance change memory.

[0129] In the memory device 100 according to one embodiment of the present invention, the memory cell 10 and the driver circuit layer 50 are electrically connected to each other via wirings WBL and RBL that extend in the Z direction. Therefore, the wirings WBL and RBL have short routing distances and low wiring resistance and parasitic capacitance. The memory device 100 according to one embodiment of the present invention has high data write and read speeds due to the low wiring resistance and parasitic capacitance of the wirings WBL and RBL.

[0130] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0131] Embodiment 2 In this embodiment, a structural example of a semiconductor device that can be used as the memory cell 10 according to one embodiment of the present invention will be described with reference to drawings. The semiconductor device described in this embodiment includes a transistor and a capacitor.

[0132] <Structural Example of Semiconductor Device> A structural example of a semiconductor device including a transistor and a capacitor will be described with reference to Fig. 9. Fig. 9A to Fig. 9D are top views and cross-sectional views of a semiconductor device including a transistor 200a, a transistor 200b, a capacitor 150a, and a capacitor 150b.

[0133] The transistor 200a or the transistor 200b can be used as the transistor M1 or the transistor M2 described in the above embodiment. The capacitor 150a or the capacitor 150b can be used as the capacitor C described in the above embodiment.

[0134] FIG. 9A is a plan view of the semiconductor device. FIGS. 9B to 9D are cross-sectional views of the semiconductor device. FIG. 9B is a cross-sectional view of a portion indicated by dashed dotted line A1-A2 in FIG. 9A , which is a cross-sectional view of the transistors 200a and 200b in the channel length direction and also a cross-sectional view of the capacitors 150a and 150b. FIG. 9C is a cross-sectional view of a portion indicated by dashed dotted line A3-A4 in FIG. 9A , which is a cross-sectional view of the transistor 200a in the channel width direction. FIG. 9D is a cross-sectional view of a portion indicated by dashed dotted line A5-A6 in FIG. 9A , which is a cross-sectional view of the transistor 200a and the capacitor 150a in the channel width direction. Note that some components are omitted from the plan view in FIG. 9A for clarity.

[0135] The X direction shown in FIG. 9A is parallel to the channel length direction of the transistor 200a and the channel length direction of the transistor 200b.

[0136] A semiconductor device of one embodiment of the present invention includes an insulator 214 over a substrate (not shown), transistors 200a, 200b, capacitors 150a, and 150b over the insulator 214, an insulator 280 over the insulator 275 provided in the transistors 200a and 200b, an insulator 282 over the capacitors 150a, 150b, and 280, an insulator 285 over the insulator 282, and a conductor 240 (conductors 240a and 240b). The insulator 214, the insulator 280, the insulator 282, and the insulator 285 function as interlayer films. As shown in FIG. 9B , the transistor 200a, the transistor 200b, the capacitor 150a, and the capacitor 150b are at least partially embedded in the insulator 280.

[0137] Here, the transistor 200a and the transistor 200b each include an oxide 230 that functions as a semiconductor layer, a conductor 260 that functions as a first gate (also referred to as a top gate) electrode, a conductor 205 that functions as a second gate (also referred to as a back gate) electrode, a conductor 242a that functions as one of a source electrode and a drain electrode, and a conductor 242b that functions as the other of the source electrode and the drain electrode. The transistors 200a and 200b also include an insulator 253 and an insulator 254 that function as a first gate insulator. The transistors 200a and 200b also include an insulator 222 and an insulator 224 that function as a second gate insulator. The gate insulator may also be referred to as a gate insulating layer or a gate insulating film.

[0138] Since transistors 200a and 200b have the same configuration, when describing matters common to transistors 200a and 200b, the symbols added to the reference numerals may be omitted and the transistors may be referred to as transistor 200.

[0139] The first gate electrode and the first gate insulating film are disposed in an opening 258 formed in the insulator 280 and the insulator 275. That is, the conductor 260, the insulator 254, and the insulator 253 are disposed in the opening 258.

[0140] Each of the capacitors 150a and 150b has a conductor 242b that functions as a lower electrode, an insulator 275, an insulator 153, and an insulator 154 that function as dielectrics, and a conductor 160 that functions as an upper electrode. That is, each of the capacitors 150a and 150b constitutes a metal-insulator-metal (MIM) capacitor.

[0141] Since the capacitance elements 150a and 150b have the same configuration, when describing matters common to the capacitance elements 150a and 150b below, the symbols added to the reference numerals may be omitted and the capacitance elements may be described as capacitance element 150.

[0142] The upper electrode and a portion of the dielectric of the capacitance element 150 are disposed within the opening 158 formed in the insulator 280. That is, the conductor 160, the insulator 154, and the insulator 153 are disposed within the opening 158.

[0143] The semiconductor device of one embodiment of the present invention also includes a conductor 240 (a conductor 240a and a conductor 240b). The conductor 240 has a region in contact with the conductor 242a and is electrically connected to the transistor 200 to function as a plug.

[0144] Furthermore, the semiconductor device of one embodiment of the present invention includes an insulator 210 and a conductor 209 between a substrate (not shown) and an insulator 214. The conductor 209 is disposed so as to be embedded in the insulator 210. The conductor 209 has a region in contact with the conductor 240.

[0145] Furthermore, the semiconductor device of one embodiment of the present invention may include an insulator 212 between the insulator 210 and the conductor 209 and the insulator 214 .

[0146] The semiconductor device including the transistor 200 and the capacitor 150 described in this embodiment can be used as a memory cell of a memory device. In this case, the conductor 240 may be electrically connected to a sense amplifier. As shown in FIG. 9A , the capacitor 150 is provided so that at least a part of it overlaps with the oxide 230 of the transistor 200. Therefore, the capacitor 150 can be provided without significantly increasing the occupied area in a plan view, which allows miniaturization or high integration of the semiconductor device according to this embodiment.

[0147] 9A 。 In addition, the semiconductor device described in this embodiment has a structure that is symmetrical with respect to the dashed line A7-A8 in FIG. 9A . One of the source electrode or drain electrode of transistor 200a and one of the source electrode or drain electrode of transistor 200b are also served by conductor 242a. In this way, by configuring the connections between two transistors, two capacitors, and plugs as described above, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0148] [Transistor 200] As shown in FIGS. 9A to 9D , the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductors 205a and 205b) disposed so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and a conductor 242a (conductors 242a1 and 242a2) on the oxide 230b. 242a2) and conductor 242b (conductor 242b1 and conductor 242b2), insulator 253 on oxide 230b, insulator 254 on insulator 253, conductor 260 (conductor 260a and conductor 260b) located on insulator 254 and overlapping with part of oxide 230b, and insulator 275 arranged on insulator 222, insulator 224, oxide 230a, oxide 230b, conductor 242a, and conductor 242b.

[0149] In this specification and the like, the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230. Furthermore, the conductor 242a and the conductor 242b may be collectively referred to as the conductor 242.

[0150] An opening 258 reaching the oxide 230b is provided in the insulator 280 and the insulator 275. That is, the opening 258 can be said to have a region overlapping with the oxide 230b. The insulator 275 can be said to have an opening overlapping with the opening of the insulator 280. The insulator 253, the insulator 254, and the conductor 260 are disposed in the opening 258. That is, the conductor 260 has a region overlapping with the oxide 230b with the insulators 253 and 254 interposed therebetween. The conductor 260, the insulator 253, and the insulator 254 are provided between the conductor 242a and the conductor 242b in the channel length direction of the transistor 200. The insulator 254 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260. As shown in FIG. 9C, the upper surface of the insulator 222 is exposed in the region of the opening 258 that does not overlap with the oxide 230.

[0151] The oxide 230 preferably includes an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on the oxide 230a. By having the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b.

[0152] Note that in the transistor 200, the oxide 230 has a two-layer structure of the oxide 230a and the oxide 230b, but the present invention is not limited to this. For example, the oxide 230b may have a single layer or a stacked structure of three or more layers, or each of the oxide 230a and the oxide 230b may have a stacked structure.

[0153] The conductor 260 functions as a first gate electrode, and the conductor 205 functions as a second gate electrode. The insulators 253 and 254 function as first gate insulators, and the insulators 222 and 224 function as second gate insulators. The conductor 242a functions as one of a source electrode and a drain electrode, and the conductor 242b functions as the other of the source electrode and the drain electrode. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0154] Here, FIG. 11A shows an enlarged view of the vicinity of the channel formation region in FIG. 9B . As shown in FIG. 11A , in a cross-sectional view of the transistor 200 in the channel length direction, the distance L2 between the conductor 242a and the conductor 242b is preferably smaller than the width of the opening 258. Here, the width of the opening 258 corresponds to the distance L1 between the interface between the insulator 280 and the insulator 253 on the conductor 242a side and the interface between the insulator 280 and the insulator 253 on the conductor 242b side, as shown in FIG. 11A . As will be described in detail later, in this embodiment, channel etching of the conductors 242a and 242b is performed after the formation of the opening 258. With this configuration, the distance L2 between the conductors 242a and 242b can be made relatively easily into a very fine structure (e.g., 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). Furthermore, since the conductor 260 has a region of distance L1 which is greater than distance L2, the conductivity of the conductor 260 located in the region of distance L1 is prevented from decreasing, allowing the conductor 260 to function as wiring.

[0155] 11A and 9C , opening 258 can also be considered to have a shape in which a portion of a structure including insulator 224, oxide 230, conductor 242, and insulator 275 protrudes into an opening having insulator 222 as a bottom surface and insulator 280 as a side surface. Furthermore, in the structure including insulator 224, oxide 230, conductor 242, and insulator 275, the region of oxide 230 sandwiched between conductor 242 a and conductor 242 b can be considered to be exposed.

[0156] 11A and 9C , insulator 253 is provided in contact with the bottom surface and inner wall of opening 258. Thus, insulator 253 is in contact with at least a portion of the top surface of insulator 222, the side surface of insulator 224, the side surface of oxide 230a, the top surface and side surface of oxide 230b, the side surfaces of conductors 242a and 242b, the side surface of insulator 275, the side surface of insulator 280, and the bottom surface of insulator 254. Furthermore, insulator 254 and conductor 260 are stacked on insulator 253. Therefore, insulator 253, insulator 254, and conductor 260 are provided to cover conductor 242 and insulator 275 that partially protrude into opening 258.

[0157] A channel formation region is formed in the region of the oxide 230b at a distance L2. Therefore, the channel formation region of the transistor 200 has a very fine structure. This increases the on-state current of the transistor 200, thereby improving the frequency characteristics.

[0158] The shape of the opening 258 is not limited to the shape shown in FIG. 11A . As shown in FIG. 11B , the opening 258 may have a shape in which the distance L1 and the distance L2 are equal. In this case, as shown in FIG. 11B , the side surfaces of the conductor 242a and the insulator 275 roughly coincide with the side surfaces of the insulator 280. Furthermore, the side surfaces of the conductor 242b and the insulator 275 roughly coincide with the side surfaces of the insulator 280. This configuration can simplify the manufacturing process of the semiconductor device and improve productivity. Furthermore, when providing multiple transistors 200, it is possible to reduce the area and increase the density.

[0159] 11B shows a configuration in which the sidewalls of opening 258 are approximately perpendicular to the upper surface of insulator 222, but the present invention is not limited to this. As shown in Fig. 11C, the sidewalls of opening 258 may be tapered. By tapering the sidewalls of opening 258, coverage of insulator 253 and the like can be improved in subsequent processes, and defects such as voids can be reduced.

[0160] In this specification, the term "tapered shape" refers to a shape in which at least a portion of the side surface of the structure is inclined relative to the substrate surface. For example, it is preferable that the angle between the inclined side surface of the structure and the substrate surface (bottom surface) (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side surface and the substrate surface (bottom surface) of the structure do not necessarily have to be completely flat, but may be substantially planar with a slight curvature or a slight unevenness.

[0161] 11A , the oxide 230b includes a region 230bc that functions as a channel formation region of the transistor 200, and regions 230ba and 230bb that are provided on either side of the region 230bc and function as source and drain regions. The region 230bc at least partially overlaps with the conductor 260. In other words, the region 230bc is provided in a region between the conductor 242a and the conductor 242b. The region 230ba is provided overlapping with the conductor 242a, and the region 230bb is provided overlapping with the conductor 242b.

[0162] The region 230bc, which functions as a channel formation region, has fewer oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb, and is therefore a high-resistance region with a low carrier concentration. Therefore, the region 230bc can be said to be i-type (intrinsic) or substantially i-type.

[0163] Furthermore, the regions 230ba and 230bb, which function as source and drain regions, have a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, which increases the carrier concentration and reduces the resistance. That is, the regions 230ba and 230bb are n-type regions with a higher carrier concentration and lower resistance than the region 230bc.

[0164] 11A, the opposing side surfaces of the conductor 242a and the conductor 242b are preferably approximately perpendicular to the top surface of the oxide 230b. This configuration prevents the side edge of the region 230ba, formed under the conductor 242a, on the region 230bc side from being excessively recessed from the side edge of the conductor 242a on the region 230bc side. Similarly, the side edge of the region 230bb, formed under the conductor 242b, on the region 230bc side from being excessively recessed from the side edge of the conductor 242b on the region 230bc side. This reduces the formation of so-called Loff regions between the regions 230ba and 230bc and between the regions 230bb and 230bc. Here, "the side edge of region 230ba on the region 230bc side is recessed" means that the side edge of region 230ba is located closer to conductor 240 than the side surface of conductor 242a on the region 230bc side. Also, "the side edge of region 230bb on the region 230bc side is recessed" means that the side edge of region 230bb is located closer to conductor 160 than the side surface of conductor 242b on the region 230bc side.

[0165] As a result, the frequency characteristics of the transistor 200 can be improved, and the operation speed of the semiconductor device according to one embodiment of the present invention can be increased. For example, when the semiconductor device according to one embodiment of the present invention is used as a memory cell of a memory device, the writing speed and reading speed can be improved.

[0166] The carrier concentration of the region 230bc functioning as a channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ The lower limit of the carrier concentration of the region 230bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10−９ cm −３ It can be said that:

[0167] Furthermore, a region may be formed between region 230bc and region 230ba, or between region 230bc and region 230bb, whose carrier concentration is equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. That is, this region functions as a junction region between region 230bc and region 230ba, or between region 230bc and region 230bb. The junction region may have a hydrogen concentration equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. The junction region may also have oxygen vacancies equal to or lower than those of region 230ba and region 230bb, and equal to or higher than those of region 230bc.

[0168] 11A shows an example in which the regions 230ba, 230bb, and 230bc are formed in the oxide 230b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 230b but also in the oxide 230a.

[0169] Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in a region closer to the channel formation region.

[0170] In the transistor 200, a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230a and the oxide 230b) including the channel formation region.

[0171] The band gap of the metal oxide functioning as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. Use of a metal oxide with a wide band gap can reduce the off-state current of a transistor.

[0172] The oxide 230 is preferably a metal oxide such as indium oxide, gallium oxide, or zinc oxide. The oxide 230 is preferably a metal oxide containing two or three elements selected from indium, element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. The element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin. A metal oxide containing indium, element M, and zinc may be referred to as an In-M-Zn oxide.

[0173] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably larger than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a into the oxide 230b.

[0174] In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. With this structure, the transistor 200 can have a large on-state current and high frequency characteristics.

[0175] Furthermore, since the oxide 230a and the oxide 230b contain a common element other than oxygen as a main component, the density of defect states at the interface between the oxide 230a and the oxide 230b can be reduced. This reduces the effect of interface scattering on carrier conduction, and the transistor 200 can achieve a large on-state current and high frequency characteristics.

[0176] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:M:Zn = 1:3:4 or a similar composition, or an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition. The oxide 230b may be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, or an atomic ratio of In:M:Zn = 4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M. When a single layer of the oxide 230b is provided as the oxide 230, the same metal oxide that can be used for the oxide 230a may also be used as the oxide 230b.

[0177] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0178] The oxide 230b preferably has crystallinity. In particular, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b.

[0179] CAAC-OS is a metal oxide having a highly crystalline and dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide is not polycrystallized after formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0180] Furthermore, since it is difficult to identify clear crystal boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to crystal boundaries is unlikely to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0181] Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide 230b, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Thus, even when heat treatment is performed, extraction of oxygen from the oxide 230b can be suppressed, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0182] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in a region where a channel is formed in an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in an oxide semiconductor, impurities, oxygen vacancies, and V ＯIt is preferable that H be reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0183] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 200 may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0184] Therefore, in the oxide semiconductor, the region 230bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 230ba and 230bb that function as source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is preferable to reduce H. It is also preferable to prevent an excessive amount of oxygen from being supplied to the regions 230ba and 230bb, and to reduce V Ｏ It is preferable to prevent the amount of H from being reduced excessively. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor is V Ｏ H can be formed, so V ＯTo reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0185] Therefore, in this embodiment, the semiconductor device is configured to reduce the hydrogen concentration in region 230bc, suppress oxidation of conductor 242a, conductor 242b, and conductor 260, and suppress the reduction in the hydrogen concentration in regions 230ba and 230bb.

[0186] In order to reduce the hydrogen concentration in the region 230bc, it is preferable that the insulator 253 has the function of capturing and fixing hydrogen. As shown in FIG. 9C, the insulator 253 has a region that contacts the region 230bc of the oxide 230b. With this configuration, the hydrogen concentration in the region 230bc of the oxide 230b can be reduced. Therefore, V in the region 230bc Ｏ H can be reduced to make the region 230bc i-type or substantially i-type.

[0187] Examples of insulators capable of capturing and fixing hydrogen include metal oxides with an amorphous structure. For example, it is preferable to use metal oxides such as magnesium oxide or oxides containing one or both of aluminum and hafnium. In such metal oxides with an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides with an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0188] The insulator 253 and the insulator 153 of the capacitor 150 are formed using the same insulating film. That is, the insulator 253 and the insulator 153 are made of the same material. The insulator 153 also functions as a dielectric of the capacitor 150. Therefore, it is preferable to use a high-dielectric-constant (high-k) material for the insulator 153. In this case, the insulator 253 includes a high-k material. Note that an example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material as the insulator 253 makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0189] For the above reasons, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulator 253, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use hafnium oxide having an amorphous structure. In this embodiment, hafnium oxide is used as the insulator 253. In this case, the insulator 253 is an insulator containing at least oxygen and hafnium. Furthermore, the hafnium oxide has an amorphous structure. In this case, the insulator 253 has an amorphous structure.

[0190] In order to suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to provide a barrier insulator against oxygen near each of the conductor 242a, the conductor 242b, and the conductor 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulator 253, the insulator 254, and the insulator 275.

[0191] In this specification and the like, a barrier insulator refers to an insulator having barrier properties. In this specification and the like, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0192] Examples of the oxygen barrier insulator include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulators 253, 254, and 275 may each be a single layer or a stack of the above-mentioned oxygen barrier insulators.

[0193] The insulator 253 preferably has a barrier property against oxygen. Note that the insulator 253 is required to be at least less permeable to oxygen than the insulator 280. The insulator 253 has a region in contact with the side surface of the conductor 242a and the side surface of the conductor 242b. The insulator 253 having a barrier property against oxygen can prevent the side surfaces of the conductor 242a and the conductor 242b from being oxidized and forming an oxide film on the side surface. This can prevent a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200.

[0194] Furthermore, the insulator 253 is provided in contact with the top surface and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surfaces of the insulator 224, and the top surface of the insulator 222. The insulator 253 has a barrier property against oxygen, which can prevent oxygen from being desorbed from the region 230bc of the oxide 230b when heat treatment or the like is performed. Therefore, the formation of oxygen vacancies in the oxide 230a and the oxide 230b can be reduced.

[0195] Conversely, even if the insulator 280 contains an excessive amount of oxygen, the oxygen can be prevented from being excessively supplied to the oxide 230a and the oxide 230b. Therefore, the regions 230ba and 230bb can be prevented from being excessively oxidized, which can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0196] An oxide containing one or both of aluminum and hafnium has barrier properties against oxygen and can therefore be suitably used as the insulator 253 .

[0197] The insulator 254 preferably has a barrier property against oxygen. The insulator 254 is provided between the region 230bc of the oxide 230 and the conductor 260, and between the insulator 280 and the conductor 260. This configuration can prevent oxygen contained in the region 230bc of the oxide 230 from diffusing into the conductor 260 and forming oxygen vacancies in the region 230bc of the oxide 230. Furthermore, it can prevent oxygen contained in the oxide 230 and oxygen contained in the insulator 280 from diffusing into the conductor 260 and oxidizing the conductor 260. Note that the insulator 254 only needs to be at least more resistant to oxygen permeation (or diffusion) than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 254. In this case, the insulator 254 is an insulator containing at least nitrogen and silicon.

[0198] The insulator 275 preferably has barrier properties against oxygen. The insulator 275 is provided between the insulator 280 and the conductors 242a and 242b. This configuration can prevent oxygen contained in the insulator 280 from diffusing into the conductors 242a and 242b. Therefore, it is possible to prevent the conductors 242a and 242b from being oxidized by the oxygen contained in the insulator 280, which would increase their resistivity and reduce their on-state current. Note that the insulator 275 only needs to be at least less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 275. In this case, the insulator 275 is an insulator containing at least nitrogen and silicon.

[0199] In order to prevent the hydrogen concentration in the regions 230ba and 230bb from decreasing, it is preferable to provide a hydrogen barrier insulator near each of the regions 230ba and 230bb. In the semiconductor device described in this embodiment, the hydrogen barrier insulator is, for example, the insulator 275.

[0200] Examples of the hydrogen barrier insulator include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 may be a single layer or a stack of the above hydrogen barrier insulators.

[0201] The insulator 275 preferably has a barrier property against hydrogen. The insulator 275 is arranged in contact with each of the side surfaces of the region 230ba of the oxide 230b and the region 230bb of the oxide 230b. The insulator 275 is also arranged between the insulator 253 and the side surfaces of the region 230ba of the oxide 230b and the region 230bb of the oxide 230b. The insulator 275 having a barrier property against hydrogen can prevent the insulator 253 from capturing and fixing hydrogen in the region 230ba and the region 230bb. Therefore, the region 230ba and the region 230bb can be made n-type.

[0202] By adopting the above-described configuration, the region 230bc functioning as a channel formation region can be made i-type or substantially i-type, and the regions 230ba and 230bb functioning as source and drain regions can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, by adopting the above-described configuration, the semiconductor device can maintain excellent electrical characteristics even when miniaturized or highly integrated. For example, even when the distance L2 shown in FIG. 11A is 20 nm or less, 15 nm or less, 10 nm or less, or 7 nm or less, or 2 nm or more, 3 nm or more, or 5 nm or more, excellent electrical characteristics can be obtained.

[0203] Furthermore, miniaturization of the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved. When the gate length is within any of the above ranges, the cutoff frequency of the transistor can be set to 50 GHz or higher, or 100 GHz or higher, for example, in a room temperature environment.

[0204] 9B, the insulator 253 is provided in contact with a part of the top surface and the side surface of the insulator 275 and the side surface of the insulator 280.

[0205] Furthermore, the insulator 253, together with the insulator 254 and the conductor 260, needs to be provided in an opening formed in the insulator 280 or the like. To miniaturize the transistor 200, it is preferable that the insulator 253 have a small thickness. The thickness of the insulator 253 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 5.0 nm or less, more preferably 1.0 nm or more and less than 5.0 nm, and even more preferably 1.0 nm or more and 3.0 nm or less. In this case, the insulator 253 only needs to have a region with the above thickness in at least a portion thereof.

[0206] To thin the insulator 253 as described above, it is preferable to form the film using atomic layer deposition (ALD). ALD methods include thermal ALD, in which a precursor and a reactant react using only thermal energy, and plasma enhanced ALD, in which a plasma-excited reactant is used. The PEALD method may be preferable because it uses plasma, allowing film formation at a lower temperature.

[0207] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling extremely thin films to be formed, films to be formed on structures with high aspect ratios, films with few defects such as pinholes, films with excellent coverage, and films to be formed at low temperatures, etc. Therefore, the insulator 253 can be formed with good coverage on the side surfaces of the openings formed in the insulator 280, etc., and on the side edges of the conductor 242, etc., with a thin film thickness as described above.

[0208] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0209] The insulator 254 functions as part of the gate insulator. The insulator 254 preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide 230b.

[0210] Furthermore, the insulator 254, together with the insulator 253 and the conductor 260, needs to be provided in an opening formed in the insulator 280 or the like. To miniaturize the transistor 200, it is preferable that the insulator 254 be thin. The thickness of the insulator 254 is 0.1 nm to 5.0 nm, preferably 0.5 nm to 3.0 nm, and more preferably 1.0 nm to 3.0 nm. In this case, the insulator 254 only needs to have a region with the above thickness in at least a portion thereof.

[0211] For example, the insulator 254 may be a silicon nitride film formed by a PEALD method.

[0212] Note that by using an insulator such as hafnium oxide that has a function of suppressing permeation of impurities such as hydrogen and oxygen as the insulator 253, the insulator 253 can also function as the insulator 254. In such a case, by not providing the insulator 254, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0213] The insulator 275 is provided to cover the insulator 224, the oxide 230a, the oxide 230b, and the conductor 242. Specifically, the insulator 275 has regions in contact with each of the side surfaces of the oxide 230b, the conductor 242a, and the conductor 242b.

[0214] In addition, in the opening 258, the insulator 275 overlaps with the conductor 242. With this structure, the physical distance between the conductor 242 and the conductor 260 can be increased, and the parasitic capacitance between the conductor 242 and the conductor 260 can be reduced. Therefore, a semiconductor device with favorable electrical characteristics can be provided.

[0215] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion (or permeation) of oxygen as the conductors 242a, 242b, and 260. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductors 242a, 242b, and 260. When a conductive material containing metal and nitrogen is used as the conductors 242a, 242b, and 260, the conductors 242a, 242b, and 260 are conductors that contain at least metal and nitrogen.

[0216] One or both of the conductor 242 and the conductor 260 may have a layered structure. For example, as shown in FIG. 9B , the conductor 242a and the conductor 242b may each have a two-layer layered structure. In this case, the layers in contact with the oxide 230b (the conductors 242a1 and 242b1) may be made of a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion (or permeation) of oxygen. Furthermore, for example, when the conductor 260 has a layered structure of the conductors 260a and 260b as shown in FIG. 9B , the conductor 260a may be made of a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen.

[0217] Furthermore, to prevent a decrease in the conductivity of the conductor 242, it is preferable to use a crystalline oxide such as CAAC-OS as the oxide 230b. It is preferable to use a metal oxide applicable to the oxide 230 described above as the oxide. In particular, it is preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. CAAC-OS is a crystalline oxide, and the c-axis of the crystal is approximately perpendicular to the surface of the oxide or the surface on which it is formed. This can prevent the conductor 242a or the conductor 242b from extracting oxygen from the oxide 230b (gettering). It can also prevent a decrease in the conductivity of the conductor 242a and the conductor 242b.

[0218] In this embodiment, the conductors 242a and 242b are covered with the insulator 275 on the oxide 230b, and the oxide 230bc is exposed. In this state, microwave treatment is performed in an atmosphere containing oxygen to remove oxygen vacancies in the region 230bc and V Ｏ The microwave treatment here refers to a treatment using high density plasma generated by using microwaves or high frequency waves such as RF.

[0219] By subjecting the sample in the above state to microwave processing in an oxygen-containing atmosphere, the generated oxygen plasma can be applied to the sample. At this time, microwaves or high-frequency waves such as RF are also irradiated onto the region 230bc. The action of the oxygen plasma, microwaves, or high-frequency waves such as RF increases the V Ｏ The H is split into oxygen vacancies and hydrogen, the hydrogen is removed from the region 230bc, and the oxygen vacancies are compensated for with oxygen. Ｏ H is reduced, and the carrier concentration in the region 230bc can be reduced.

[0220] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, high frequencies such as microwaves or RF are shielded by the conductors 242a and 242b. Therefore, high frequencies such as microwaves or RF do not affect the regions 230ba and 230bb. Furthermore, by providing the insulator 275 covering the conductor 242, oxidation of the conductor 242 by oxygen plasma can be prevented. Furthermore, by providing the insulator 275 and the conductor 242 on the regions 230ba and 230bb, even when microwave processing is performed in an atmosphere containing oxygen, V Ｏ Since a reduction in H and an excessive supply of oxygen do not occur, a decrease in the carrier concentration in the regions 230ba and 230bb can be prevented.

[0221] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that will become the insulator 253. By performing microwave treatment in an oxygen-containing atmosphere through the insulator 253 in this manner, oxygen can be efficiently injected into the region 230bc. Furthermore, by arranging the insulator 253 so that it is in contact with the side surface of the conductor 242 and the surface of the region 230bc, it is possible to prevent more oxygen than necessary from being injected into the region 230bc and to prevent oxidation of the side surface of the conductor 242.

[0222] The oxygen implanted into the region 230bc can take various forms, such as oxygen atoms, oxygen molecules, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also known as O radicals). The oxygen implanted into the region 230bc may take one or more of the above forms, and oxygen radicals are particularly preferred. Furthermore, the film quality of the insulator 253 can be improved, thereby improving the reliability of the transistor 200.

[0223] In this manner, oxygen vacancies and V Ｏ By removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb, which function as source and drain regions, can be prevented, maintaining the n-type state of the regions before the microwave treatment. This prevents fluctuations in the electrical characteristics of the transistor 200 and suppresses variations in the electrical characteristics of the transistor 200 across the substrate.

[0224] By adopting the above-described configuration, it is possible to provide a semiconductor device with little variation in transistor characteristics. It is also possible to provide a semiconductor device with good frequency characteristics. It is also possible to provide a semiconductor device with high operating speed. It is also possible to provide a semiconductor device with good reliability. It is also possible to provide a semiconductor device with good electrical characteristics. It is also possible to provide a semiconductor device that allows for miniaturization or high integration.

[0225] 9C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as a rounded shape).

[0226] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably 1 nm or greater and 15 nm or less, and more preferably 2 nm or greater and 10 nm or less. By using such a shape, the coverage of the oxide 230b by the insulator 253, the insulator 254, and the conductor 260 can be improved.

[0227] During the manufacturing process of the transistor 200, heat treatment is preferably performed while the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 600° C. or lower, more preferably 350° C. or higher and 550° C. or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230, thereby reducing oxygen vacancies. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher to replenish desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher, followed by another heat treatment in a nitrogen gas or inert gas atmosphere.

[0228] By performing oxygen addition treatment on the oxide 230, oxygen vacancies in the oxide 230 can be repaired by the supplied oxygen. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide 230 to convert the hydrogen into H ２As a result, the hydrogen remaining in the oxide 230 is recombined with the oxygen vacancies to form V. Ｏ The formation of H can be suppressed.

[0229] 9C and other figures, providing the insulator 253 in contact with the top surface and side surface of the oxide 230 can cause indium contained in the oxide 230 to be unevenly distributed at and near the interface between the oxide 230 and the insulator 253. This results in the surface area of ​​the oxide 230 having an atomic ratio close to that of indium oxide or In—Zn oxide. The increased atomic ratio of indium near the surface of the oxide 230, particularly the oxide 230b, can improve the field-effect mobility of the transistor 200.

[0230] In addition to the above structure, in this embodiment, the semiconductor device preferably has a structure that prevents hydrogen from entering the transistor 200. For example, an insulator that has a function of suppressing hydrogen diffusion is preferably provided to cover the transistor 200. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 212.

[0231] An insulator having a function of suppressing diffusion of hydrogen is preferably used as the insulator 212. This can suppress diffusion of hydrogen from below the insulator 212 to the transistor 200. Note that the insulator 212 may be any of the insulators that can be used for the insulator 275.

[0232] At least one of the insulators 212, 214, 282, and 285 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, at least one of the insulators 212, 214, 282, and 285 preferably suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0233] For the insulators 212, 214, 282, and 285, it is preferable to use an insulator that has the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has a higher hydrogen barrier property, for the insulator 212. Furthermore, it is preferable to use aluminum oxide or magnesium oxide, which has a high function of capturing and fixing hydrogen, for the insulators 214, 282, and 285. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, it can suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film disposed outside the insulator 285 to the transistor 200 side. Alternatively, it can suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side through the insulators 212 and 214. Alternatively, oxygen contained in the insulator 280 or the like can be prevented from diffusing upward from the transistor 200 via the insulator 282 or the like. In this manner, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 282, and 285, which have the function of preventing the diffusion of impurities such as water and hydrogen, and oxygen.

[0234] Here, it is preferable to use an oxide having an amorphous structure as the insulators 212, 214, 282, and 285. For example, AlO ｘ (x is any number greater than 0), or MgO ｙIt is preferable to use a metal oxide such as a metal oxide having an amorphous structure (where y is an arbitrary number greater than 0). In such a metal oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, hydrogen contained in the transistor 200 or hydrogen present around the transistor 200 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, a highly reliable transistor 200 and a semiconductor device can be manufactured.

[0235] Furthermore, the insulators 212, 214, 282, and 285 preferably have an amorphous structure, but may have a polycrystalline structure in part. Furthermore, the insulators 212, 214, 282, and 285 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0236] The insulators 212, 214, 282, and 285 may be formed by, for example, a sputtering method. Sputtering does not require the use of hydrogen-containing molecules in the film formation gas, and therefore can reduce the hydrogen concentrations in the insulators 212, 214, 282, and 285. Note that the film formation method is not limited to sputtering, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like may also be used as appropriate.

[0237] It may also be preferable to lower the resistivity of the insulator 212. For example, the resistivity of the insulator 212 may be set to approximately 1×10 １３ By setting the resistivity to Ωcm, the insulator 212 may be able to reduce charge-up of the conductor 205, the conductor 242, the conductor 260, or the conductor 240 in a process using plasma or the like in a semiconductor device manufacturing process. １０ Ωcm or more 1×10 １５ Ωcm or less.

[0238] The insulators 216, 280, and 285 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, the insulators 216, 280, and 285 may be made of silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0239] The conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. In addition, a part of the conductor 205 may be embedded in the insulator 214.

[0240] The conductor 205 includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the height of the upper surface of the conductor 205b is approximately the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216.

[0241] Here, the conductor 205a is composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0242] By using a conductive material for the conductor 205a that has the function of reducing hydrogen diffusion, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulators 216 and 224, etc. Furthermore, by using a conductive material for the conductor 205a that has the function of suppressing oxygen diffusion, it is possible to suppress oxidation of the conductor 205b and a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be formed as a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be made of titanium nitride.

[0243] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0244] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.

[0245] Furthermore, the electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. Furthermore, the film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of the impurities into the oxide 230.

[0246] As shown in FIG. 9A , the conductor 205 is preferably larger than the area of ​​the oxide 230 that does not overlap with the conductors 242a and 242b. In particular, as shown in FIG. 9C , the conductor 205 preferably extends to an area outside the channel width direction ends of the oxides 230a and 230b. That is, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator outside the side surfaces of the oxide 230 in the channel width direction. This structure allows the channel formation region of the oxide 230 to be electrically surrounded by the electric field of the conductor 260, which functions as a first gate electrode, and the electric field of the conductor 205, which functions as a second gate electrode.

[0247] In this specification, etc., a transistor structure in which a channel formation region is electrically surrounded by the electric field of at least a first gate electrode is called a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification, etc., is different from a Fin structure and a planar structure. On the other hand, the S-channel structure disclosed in this specification, etc., can also be regarded as a type of Fin structure. In this specification, etc., a Fin structure refers to a structure in which a gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By employing the Fin structure and the S-channel structure, resistance to the short channel effect can be increased, in other words, a transistor in which the short channel effect is less likely to occur can be obtained.

[0248] By forming the transistor 200 in the S-channel structure, the channel formation region can be electrically surrounded. Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By forming the transistor 200 in the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be the entire bulk of the oxide 230. Therefore, the current density flowing through the transistor can be improved, which is expected to improve the on-state current of the transistor or the field-effect mobility of the transistor.

[0249] 9B illustrates an example of a transistor with an S-channel structure, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistor structure that can be used in one embodiment of the present invention may be one or more selected from a planar structure, a Fin structure, and a GAA structure.

[0250] 9C , the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0251] Note that although the conductor 205 in the transistor 200 has a stacked structure of the conductor 205 a and the conductor 205 b, the present invention is not limited to this. For example, the conductor 205 may have a single layer structure or a stacked structure of three or more layers.

[0252] Insulators 222 and 224 function as gate insulators.

[0253] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0254] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. Alternatively, an oxide containing hafnium and zirconium, such as hafnium zirconium oxide, is preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with the oxygen contained in the insulator 224 and the oxide 230.

[0255] Alternatively, the insulator may be doped with, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on the insulator.

[0256] The insulator 222 may be a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. The insulator 222 may be made of lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), (Ba,Sr)TiO ３ In some cases, a material with a high dielectric constant such as (BST) can be used.

[0257] The insulator 224 in contact with the oxide 230 may be made of, for example, silicon oxide, silicon oxynitride, or the like as appropriate.

[0258] Note that the insulators 222 and 224 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure containing the same material, and may be a stacked structure containing different materials. The insulator 224 may be formed in an island shape overlapping the oxide 230a. In this case, the insulator 275 is configured to be in contact with the side surface of the insulator 224 and the top surface of the insulator 222. Note that in this specification, the term "island shape" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0259] The conductor 242a and the conductor 242b are provided in contact with the top surface of the oxide 230b. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0260] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen.

[0261] Note that hydrogen contained in the oxide 230b and the like may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b and the like is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b and the like may be absorbed by the conductor 242a or the conductor 242b.

[0262] Preferably, no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. The conductor 242 having no curved surface can increase the cross-sectional area of ​​the conductor 242 in the cross section in the channel width direction, as shown in Figure 9D. This can increase the conductivity of the conductor 242 and the on-state current of the transistor 200.

[0263] 9A , the conductor 242a has an opening in the region between the transistor 200a and the transistor 200b. The conductor 240 is arranged to overlap the opening. With this configuration, the conductor 242a and the conductor 240 have a region where they are in contact with each other. This allows the conductor 242a and the conductor 240 to be electrically connected to each other.

[0264] Furthermore, when heat treatment is performed while the conductor 242a (conductor 242b) and the oxide 230b are in contact with each other, the sheet resistance of the oxide 230b in the region overlapping with the conductor 242a (conductor 242b) may decrease. Also, the carrier concentration may increase. Therefore, the resistance of the oxide 230b in the region overlapping with the conductor 242a (conductor 242b) can be reduced in a self-aligned manner.

[0265] The conductors 242a and 242b are preferably formed using a conductive film having compressive stress. This allows strain (hereinafter sometimes referred to as tensile strain) that expands in the tensile direction to be formed in the regions 230ba and 230bb. The tensile strain causes V Ｏ By stably forming H, regions 230ba and 230bb can become stable n-type regions. The compressive stress of conductor 242a is a stress that attempts to relax the compressed shape of conductor 242a, and is a stress with a vector in the direction from the center to the end of conductor 242a. The same applies to the compressive stress of conductor 242b.

[0266] The magnitude of the compressive stress of the conductor 242a may be, for example, 500 MPa or more, preferably 1000 MPa or more, more preferably 1500 MPa or more, and even more preferably 2000 MPa or more. The magnitude of the stress of the conductor 242a may be determined by preparing a sample in which the conductive film used for the conductor 242a is formed on a substrate and measuring the stress of the sample. The same applies to the magnitude of the compressive stress of the conductor 242b. Examples of conductors having the above-mentioned magnitude of compressive stress include nitrides containing tantalum.

[0267] Strain is formed in each of the regions 230ba and 230bb due to the action of compressive stresses of the conductors 242a and 242b. The strain is a strain (tensile strain) that is expanded in the tensile direction due to the action of compressive stresses of the conductors 242a and 242b. When the regions 230ba and 230bb have a CAAC structure, the strain corresponds to elongation in a direction perpendicular to the c-axis of the CAAC structure. When the CAAC structure elongates in a direction perpendicular to the c-axis of the CAAC structure, oxygen vacancies are likely to be formed in the strain. In addition, hydrogen is likely to be taken up in the strain, so that V Ｏ Therefore, in this strain, oxygen vacancies and V Ｏ H is easily formed and these easily take a stable structure. As a result, the regions 230ba and 230bb become stable n-type regions with high carrier concentrations.

[0268] Although the above description has been made on the distortion formed in the oxide 230b, the present invention is not limited to this. Similar distortion may be formed in the oxide 230a.

[0269] 9A to 9D, the conductor 242 has a two-layer stacked structure. Specifically, the conductor 242a has a conductor 242a1 and a conductor 242a2 on the conductor 242a1. Similarly, the conductor 242b has a conductor 242b1 and a conductor 242b2 on the conductor 242b1. In this case, the conductor 242a1 and the conductor 242b1 are arranged on the side in contact with the oxide 230b.

[0270] In the following, the conductors 242a1 and 242b1 may be collectively referred to as the lower layer of the conductor 242. The conductors 242a2 and 242b2 may be collectively referred to as the upper layer of the conductor 242.

[0271] The lower layer of the conductor 242 (conductor 242a1 and conductor 242b1) is preferably made of a conductive material that is resistant to oxidation. This prevents the lower layer of the conductor 242 from oxidizing and reducing the conductivity of the conductor 242. The lower layer of the conductor 242 may also have the property of easily absorbing (extracting) hydrogen. This allows hydrogen from the oxide 230 to diffuse into the lower layer of the conductor 242, reducing the hydrogen concentration in the oxide 230. This allows the transistor 200 to have stable electrical characteristics. Furthermore, the lower layer of the conductor 242 preferably has a large compressive stress, as described above, and preferably has a compressive stress greater than that of the upper layer of the conductor 242. This allows the regions 230ba and 230bb, which are in contact with the lower layer of the conductor 242, to be stable n-type regions with high carrier concentrations, as described above.

[0272] Furthermore, it is preferable that the upper layer of the conductor 242 (conductor 242a2 and conductor 242b2) has higher conductivity than the lower layer of the conductor 242 (conductor 242a1 and conductor 242b1). For example, the film thickness of the upper layer of the conductor 242 may be greater than the film thickness of the lower layer of the conductor 242. Note that the upper layer of the conductor 242 may have at least a portion that is more conductive than the lower layer of the conductor 242. Alternatively, it is preferable that the upper layer of the conductor 242 is made of a conductive material with lower resistivity than the lower layer of the conductor 242. This makes it possible to manufacture a semiconductor device in which wiring delay is suppressed.

[0273] The upper layer of the conductor 242 may have a property of easily absorbing hydrogen. This allows hydrogen absorbed by the lower layer of the conductor 242 to diffuse into the upper layer of the conductor 242, further reducing the hydrogen concentration in the oxide 230. This allows the transistor 200 to have stable electrical characteristics.

[0274] When the conductor 242 has a two-layer laminated structure, the lower layer of the conductor 242 and the upper layer of the conductor 242 may be different in one or more of the constituent elements, chemical composition, and film formation conditions.

[0275] For example, tantalum nitride or titanium nitride can be used for the lower layer of conductor 242 (conductor 242a1 and conductor 242b1), and tungsten can be used for the upper layer of conductor 242 (conductor 242a2 and conductor 242b2). In this case, conductor 242a1 and conductor 242b1 are conductors containing tantalum or titanium and nitrogen. This configuration can prevent the lower layer of conductor 242 from oxidizing and reducing the conductivity of conductor 242. This configuration can also surround conductor 242a2 with insulator 275, which has oxygen barrier properties, and conductor 242a1, which has oxidation resistance, and surround conductor 242b2 with insulator 275, which has oxygen barrier properties, and conductor 242b1, which has oxidation resistance. Therefore, it is possible to manufacture a semiconductor device in which oxidation of the conductors 242a2 and 242b2 is suppressed and wiring delay is suppressed.

[0276] Alternatively, for example, a nitride containing tantalum (e.g., tantalum nitride) may be used as the lower layer of the conductor 242, and a nitride containing titanium (e.g., titanium nitride) may be used as the upper layer of the conductor 242. Titanium nitride can have higher conductivity than tantalum nitride, so the conductivity of the upper layer of the conductor 242 can be made higher than that of the lower layer of the conductor 242. Therefore, the contact resistance with the conductor 240 provided in contact with the upper surface of the conductor 242 can be reduced, and a semiconductor device with reduced wiring delay can be manufactured.

[0277] Although an example in which the lower layer of the conductor 242 and the upper layer of the conductor 242 are made of different conductive materials has been shown, the present invention is not limited to this.

[0278] The lower layer and the upper layer of the conductor 242 may be made of conductive materials that have the same constituent elements but different chemical compositions. In this case, the lower layer and the upper layer of the conductor 242 can be formed successively without being exposed to the atmospheric environment. By forming the layers without being exposed to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the surface of the lower layer of the conductor 242, and it is possible to keep the vicinity of the interface between the lower layer of the conductor 242 and the upper layer of the conductor 242 clean.

[0279] It is also preferable to use a tantalum-containing nitride having a high atomic ratio of nitrogen to tantalum for the lower layer of the conductor 242, and a tantalum-containing nitride having a low atomic ratio of nitrogen to tantalum for the upper layer of the conductor 242. For example, a tantalum-containing nitride having a nitrogen-to-tantalum atomic ratio of 1.0 to 2.0, preferably 1.1 to 1.8, and more preferably 1.2 to 1.5, is used for the lower layer of the conductor 242. Furthermore, for example, a tantalum-containing nitride having a nitrogen-to-tantalum atomic ratio of 0.3 to 1.5, preferably 0.5 to 1.3, and more preferably 0.6 to 1.0, is used for the upper layer of the conductor 242.

[0280] In a tantalum-containing nitride, increasing the atomic ratio of nitrogen to tantalum can suppress oxidation of the tantalum-containing nitride. Furthermore, the oxidation resistance of the tantalum-containing nitride can be improved. Furthermore, the diffusion of oxygen into the tantalum-containing nitride can be suppressed. Therefore, it is preferable to use a tantalum-containing nitride with a high atomic ratio of nitrogen to tantalum for the lower layer of the conductor 242. This can prevent the formation of an oxide layer between the lower layer of the conductor 242 and the oxide 230, or can reduce the thickness of the oxide layer.

[0281] Furthermore, in a nitride containing tantalum, the resistivity of the nitride can be reduced by lowering the atomic ratio of nitrogen to tantalum. Therefore, it is preferable to use a nitride containing tantalum with a low atomic ratio of nitrogen to tantalum as the upper layer of the conductor 242. This makes it possible to manufacture a semiconductor device with reduced wiring delay.

[0282] It should be noted that it may be difficult to clearly detect the boundary between the upper and lower layers of the conductor 242. When a nitride containing tantalum is used for the conductor 242, the tantalum and nitrogen concentrations detected in each layer are not limited to a stepwise change in each layer, but may also change continuously (also called a gradation) in the region between the upper and lower layers. In other words, the closer to the oxide 230 in the region of the conductor 242, the higher the atomic ratio of nitrogen to tantalum should be. Therefore, it is preferable that the atomic ratio of nitrogen to tantalum in the region located below the conductor 242 be higher than the atomic ratio of nitrogen to tantalum in the region located above the conductor 242.

[0283] Note that although the transistor 200 shows a structure in which the conductor 242 is stacked in two layers, the present invention is not limited to this. For example, the conductor 242 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0284] The conductor 260 is arranged so that its upper surface is approximately flush with the height of the top of the insulator 254 , the top of the insulator 253 , and the top surface of the insulator 280 .

[0285] The conductor 260 functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed over the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. Note that although the conductor 260 is shown in FIGS. 9B and 9C as having a two-layer structure of the conductor 260a and the conductor 260b, it may have a single-layer structure or a stacked structure of three or more layers.

[0286] The conductor 260a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0287] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen diffused from the insulator 280. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0288] The conductor 260 is formed to fill the opening 258 extending in the channel width direction, and the conductor 260 is also provided extending in the channel width direction. This allows the conductor 260 to function as wiring when multiple transistors 200 are provided. In this case, the insulators 253 and 254 are also provided extending along with the conductor 260.

[0289] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0290] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill the opening 258 formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in the region between the conductor 242 a and the conductor 242 b without alignment.

[0291] 9C , in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b, relative to the bottom surface of the insulator 222. When the conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 253 or the like, the electric field of the conductor 260 can be easily applied to the entire channel formation region of the oxide 230b. Therefore, the on-state current of the transistor 200 can be increased, and the frequency characteristics can be improved. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxides 230a and 230b do not overlap with the conductor 260, relative to the bottom surface of the insulator 222, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less.

[0292] The insulator 280 is provided on the insulator 275, and openings are formed in the regions where the insulator 253, the insulator 254, and the conductor 260 are provided. The top surface of the insulator 280 may be flattened.

[0293] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form a region containing oxygen that is released by heating.

[0294] The insulator 280 preferably has a reduced concentration of impurities such as water and hydrogen in the insulator 280. For example, the insulator 280 may be formed using an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate.

[0295] The insulator 282 is arranged to contact at least a portion of the upper surface of each of the conductor 260, the insulator 253, the insulator 254, and the insulator 280.

[0296] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280 and preferably has a function of capturing impurities such as hydrogen. The insulator 282 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 282 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. In this case, the insulator 282 contains at least oxygen and aluminum. By providing the insulator 282 that has a function of capturing impurities such as hydrogen in contact with the insulator 280, the impurities such as hydrogen contained in the insulator 280 can be captured. In particular, using aluminum oxide having an amorphous structure as the insulator 282 is preferable because it may be able to capture or fix hydrogen more effectively. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with favorable characteristics.

[0297] The insulator 282 is preferably formed by sputtering an aluminum oxide film, and more preferably by pulsed DC sputtering using an aluminum target in an oxygen-containing atmosphere. Using pulsed DC sputtering can achieve a more uniform film thickness distribution and improve the sputtering rate and film quality. Here, RF (radio frequency) power may be applied to the substrate. The amount of oxygen implanted into the layer below the insulator 282 can be controlled by the magnitude of the RF power applied to the substrate. For example, the smaller the RF power, the less oxygen is implanted into the layer below the insulator 282, and the more likely the oxygen amount is saturated even if the insulator 282 is thin. Furthermore, the greater the RF power, the greater the amount of oxygen implanted into the layer below the insulator 282.

[0298] The RF power is, for example, 0 W / cm ２ Over 1.86 W / cm ２ That is, the amount of oxygen suitable for the characteristics of the transistor can be changed and injected by changing the RF power when forming the insulator 282. Therefore, the amount of oxygen suitable for improving the reliability of the transistor can be injected.

[0299] The RF frequency is preferably 10 MHz or higher, typically 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0300] 9A to 9D and the like show a structure in which the insulator 282 is a single layer, the present invention is not limited to this, and the insulator 282 may have a stacked structure of two or more layers. For example, the insulator 282 may have a stacked structure of two layers.

[0301] The upper and lower layers of the insulator 282 may be formed using the same material but by different methods. For example, when aluminum oxide is formed as the insulator 282 by pulse DC sputtering using an aluminum target in an atmosphere containing oxygen gas, it is preferable that the RF power applied to the substrate when forming the lower layer of the insulator 282 is different from the RF power applied to the substrate when forming the upper layer of the insulator 282, and it is more preferable that the RF power applied to the substrate when forming the lower layer of the insulator 282 is lower than the RF power applied to the substrate when forming the upper layer of the insulator 282. Specifically, it is preferable that the RF power applied to the substrate when forming the lower layer of the insulator 282 is 0 W / cm ２ 0.62W / cm or more ２ The upper layer of the insulator 282 is formed as follows: ２ More specifically, the lower layer of the insulator 282 is formed under the following conditions: RF power applied to the substrate is 0 W / cm ２ The upper layer of the insulator 282 was formed as a film with an RF power of 0.31 W / cm ２ With this structure, the insulator 282 can have an amorphous structure and the amount of oxygen supplied to the insulator 280 can be adjusted.

[0302] The RF power applied to the substrate when forming the lower layer of the insulator 282 may be higher than the RF power applied to the substrate when forming the upper layer of the insulator 282. Specifically, the RF power applied to the substrate when forming the lower layer of the insulator 282 may be 1.86 W / cm ２ The upper layer of the insulator 282 is formed as follows: ２ 0.62W / cm or more ２More specifically, the lower layer of the insulator 282 is formed at an RF power of 1.86 W / cm ２ The upper layer of the insulator 282 was formed as a film with an RF power of 0.62 W / cm ２ With this structure, the amount of oxygen supplied to the insulator 280 can be increased.

[0303] Furthermore, the film thickness of the lower layer of the insulator 282 is 1 nm or more and 20 nm or less, preferably 1.5 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less, and even more preferably 3 nm or more and 8 nm or less. With this configuration, the lower layer of the insulator 282 can be made to have an amorphous structure regardless of RF power. Furthermore, by making the lower layer of the insulator 282 have an amorphous structure, the upper layer of the insulator 282 is more likely to have an amorphous structure, and the insulator 282 can be made to have an amorphous structure.

[0304] The lower layer and the upper layer of the insulator 282 have a stacked structure containing the same material, but the present invention is not limited to this. The lower layer and the upper layer of the insulator 282 may have a stacked structure containing different materials.

[0305] The above is a description of the transistor 200.

[0306] [Capacitor 150] FIG. 12A shows an enlarged view of the capacitor 150 and its vicinity in FIG. 9B, and FIG. 12B shows an enlarged view of the capacitor 150 and its vicinity in FIG. 9D.

[0307] The capacitor 150 includes a conductor 242b, an insulator 275, an insulator 153, an insulator 154, and a conductor 160 (a conductor 160a and a conductor 160b). The conductor 242b functions as one of a pair of electrodes (also referred to as a lower electrode) of the capacitor 150, the conductor 160 functions as the other of the pair of electrodes (also referred to as an upper electrode) of the capacitor 150, and the insulators 275, 153, and 154 function as dielectrics of the capacitor 150.

[0308] The insulator 153, the insulator 154, the conductor 160a, and the conductor 160b are disposed in an opening 158 formed in the insulator 280. The insulator 153 is disposed on the insulator 275, the insulator 154 is disposed on the insulator 153, the conductor 160a is disposed on the insulator 154, and the conductor 160b is disposed on the conductor 160a.

[0309] As will be described in detail later, the insulator 153, the insulator 154, the conductor 160a, and the conductor 160b that constitute the capacitor 150 can be formed using the same materials and in the same process as the insulators 253, the insulator 254, the conductor 260a, and the conductor 260b that constitute the transistor 200. Therefore, the insulator 153 preferably has the same insulating material as the insulator 253, and the description of the insulator 253 can be referred to for details. The insulator 154 preferably has the same insulating material as the insulator 254, and the description of the insulator 254 can be referred to for details. The conductor 160a preferably has the same conductive material as the conductor 260a, and the description of the conductor 260a can be referred to for details. The conductor 160b preferably has the same conductive material as the conductor 260b, and the description of the conductor 260b can be referred to for details.

[0310] By forming insulator 153, insulator 154, conductor 160a, and conductor 160b using the same material and in the same process as insulator 253, insulator 254, conductor 260a, and conductor 260b, respectively, the number of steps in the manufacturing process of a semiconductor device can be reduced.

[0311] The opening 158 is provided in the insulator 280 so as to reach the insulator 275. In other words, it can be said that the opening 158 has a region that overlaps with the insulator 275.

[0312] 9A , in a plan view, a region where the conductor 160 in the opening 158 intersects with the conductor 242b functions as the capacitor 150. This region overlaps with the oxide 230b that functions as the transistor 200. That is, the capacitor 150 can be provided without excessively increasing the occupied area compared to the occupied area of ​​the transistor 200. This enables miniaturization or high integration of the semiconductor device. For example, when a semiconductor device according to one embodiment of the present invention is used as a memory cell of a memory device, the storage capacity per unit area can be increased.

[0313] The conductor 242b can serve as both the lower electrode of the capacitor 150 and the other of the source electrode and the drain electrode of the transistor 200. Thus, part of the manufacturing process of the transistor 200 can be used in the manufacturing process of the capacitor 150, thereby enabling a highly productive semiconductor device to be provided.

[0314] 12A , the end of the conductor 242b on the capacitor 150 side is preferably positioned outside the end of the oxide 230. In other words, the conductor 242b covers the side surface of the oxide 230 on the capacitor 150 side. Since the conductor 242b functions as one of a pair of electrodes of the capacitor 150, this structure can increase the overlapping area of ​​the pair of electrodes of the capacitor 150. Therefore, the capacitance value of the capacitor 150 can be increased.

[0315] 12A and 12B , opening 158 can also be considered to have a shape in which a part of a structure including insulator 224, oxide 230, conductor 242, and insulator 275 protrudes into an opening having insulator 222 as a bottom surface and insulator 280 as a side surface. Note that, unlike opening 258, opening 158 has an upper surface of oxide 230b covered with conductor 242b and insulator 275, and therefore the upper surface of oxide 230b is not exposed within opening 158.

[0316] 12A and 12B , insulator 153 is provided in contact with the bottom surface and inner wall of opening 158. Thus, insulator 153 is in contact with the upper surface of insulator 275 and the side surface of insulator 280. Furthermore, insulator 154 is provided on insulator 153 in contact with the upper surface of insulator 153, and conductor 160 is provided in contact with the upper surface of insulator 154. Therefore, insulator 153, insulator 154, and conductor 160 are provided so as to cover conductor 242b and insulator 275 that partially protrude into opening 158.

[0317] 12A and 12B , by adopting the above-described structure for the capacitance element 150, the conductor 160 is provided opposite the top surface of the conductor 242b, the side surface of the conductor 242b on the side opposite the conductor 242a (the side surface on the A1 side in the capacitance element 150a and the side surface on the A2 side in the capacitance element 150b), the side surface on the A5 side of the conductor 242b, and the side surface on the A6 side of the conductor 242b, with the insulators 153 and 154 interposed therebetween. This allows the capacitance element 150 to be formed on the above four sides of the conductor 242b, thereby increasing the capacitance per unit area of ​​the capacitance element 150. This allows for miniaturization or high integration of semiconductor devices.

[0318] By optimizing the material used for the insulator functioning as a dielectric, the film thickness of the insulator 280, and the like, the capacitor 150 may have, for example, the shape shown in FIG. 13A . Specifically, the side of the opening 158 on the side opposite the conductor 242a (the side on the A1 side in the capacitor 150a, and the side on the A2 side in the capacitor 150b) may overlap with the oxide 230b. Alternatively, the conductor 160 may be provided opposite the top surface of the conductor 242b, the side on the A5 side of the conductor 242b, and the side on the A6 side of the conductor 242b, with the insulators 153 and 154 interposed therebetween. In this case, the capacitor 150 can be formed on the three sides of the conductor 242b. Alternatively, the capacitor 150 may have, for example, the shape shown in FIG. 13B . Specifically, the opening 158 may be provided in a region that does not overlap with the oxide 230b.

[0319] 12A , 13A , and 13B show a configuration in which the sidewalls of opening 158 are approximately perpendicular to the upper surface of insulator 222, but the present invention is not limited to this. The sidewalls of opening 158 may be tapered. As will be described in detail later, openings 258 and 158 are formed in the same process. For example, as shown in FIG. 11C , if the sidewalls of opening 258 are tapered, the sidewalls of opening 158 are also tapered. By tapering the sidewalls of opening 158, the coverage of insulator 153 and the like can be improved in subsequent processes, and defects such as voids can be reduced.

[0320] The conductor 160 is formed to fill the opening 158 extending in the channel width direction of the transistor 200, and the conductor 160 is also provided extending in the channel width direction of the transistor 200. This allows the conductor 160 to function as wiring when a plurality of transistors 200 and capacitors 150 are provided. In this case, the insulators 153 and 154 are also provided extending along with the conductor 160.

[0321] The insulator 275, the insulator 153, and the insulator 154 function as a dielectric of the capacitor 150. A region of the insulator 153 functioning as a dielectric of the capacitor 150 is sandwiched between the insulator 275 and the insulator 154.

[0322] Furthermore, the region 230bb of the oxide 230b is a region with reduced resistance. Therefore, the region 230bb of the oxide 230b may function as a lower electrode of the capacitor 150. In this case, the area where the pair of electrodes of the capacitor 150 overlap can be increased. Therefore, the capacitance value of the capacitor 150 can be increased.

[0323] The above is the description of the capacitive element 150.

[0324] The conductor 240 is provided in contact with the inner walls of the openings of the insulators 285, 282, 280, 275, conductor 242a, 222, 216, 214, and 212. The conductor 240 also has a region in contact with the top surface of the conductor 209.

[0325] The conductor 240 functions as a plug or wiring for electrically connecting the transistor 200 to circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, wiring, electrodes, or terminals.

[0326] The conductor 240 preferably has a layered structure of the conductor 240a and the conductor 240b. For example, as shown in Fig. 9B, the conductor 240 can have a structure in which the conductor 240a is provided in contact with the inner wall of the opening, and the conductor 240b is provided further inside. In other words, the conductor 240a is disposed near the insulators 285, 282, 280, 275, the conductor 242a, 222, 216, 214, and 212.

[0327] The conductor 240a is preferably made of a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a multilayer structure. Furthermore, impurities such as water and hydrogen contained in layers above the insulator 282 can be suppressed from mixing into the oxide 230 through the conductor 240.

[0328] Furthermore, since the conductor 240 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 240b can be made of a conductive material containing tungsten, copper, or aluminum as a main component.

[0329] Although the transistor 200 shows a structure in which the conductor 240 is formed by stacking the conductor 240a and the conductor 240b, the present invention is not limited to this. For example, the conductor 240 may be formed as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the layers may be distinguished by assigning an ordinal number to indicate the order of formation. Furthermore, although not shown in FIG. 9B , the height of the top surface of the conductor 240 may be higher than the height of the top surface of the insulator 285.

[0330] 10 shows an enlarged view of the region where the conductor 240 and the conductor 242a contact each other and the vicinity thereof. As shown in FIG. 10 , in the A1-A2 direction, the conductor 240 has a region having a width W1 and a region having a width W2. The width W1 corresponds to, for example, the distance between the interface between the insulator 280 and the conductor 240a on the transistor 200a side and the interface between the insulator 280 and the conductor 240a on the transistor 200b side. The width W2 corresponds to the width of the opening in the conductor 242a.

[0331] As shown in FIG. 10 , the width W1 is preferably greater than the width W2. In this configuration, the conductor 240 contacts at least a portion of the top surface and a portion of the side surface of the conductor 242a. Therefore, the area of ​​the region where the conductor 240 and the conductor 242a contact can be increased. Note that in this specification, the contact between the conductor 240 and the conductor 242a may be referred to as a top-side contact. Also, as shown in FIG. 10 , the conductor 240 may contact a portion of the bottom surface of the conductor 242a. With this configuration, the area of ​​the region where the conductor 240 and the conductor 242a contact can be further increased.

[0332] The conductor 209 functions as a part, wiring, electrode, or terminal of a circuit element such as a switch, a transistor, a capacitor, an inductor, a resistor, or a diode.

[0333] The insulator 210 functions as an interlayer film. The insulator 210 may be any of the insulators that can be used for the above-described insulators 214, 216, and the like.

[0334] <Constituent Materials of Semiconductor Device> Constituent materials that can be used in the semiconductor device will be described below.

[0335] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates containing silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include semiconductor substrates having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates containing metal nitrides and substrates containing metal oxides. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or an insulator is provided on a conductive substrate. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0336] <<Insulator>> Examples of insulators include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0337] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select a material depending on the function of the insulator.

[0338] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0339] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0340] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0341] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0342] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0343] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0344] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0345] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0346] <<Metal Oxide>> A metal oxide that functions as a semiconductor (oxide semiconductor) is preferably used as the oxide 230. Metal oxides that can be used as the oxide 230 according to the present invention will be described below.

[0347] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0348] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, an element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, the element M may be a combination of two or more of the above-mentioned elements. In particular, the element M is preferably one or more selected from gallium, aluminum, yttrium, and tin.

[0349] In particular, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) may be used for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (IAGZO or IGAZO) may be used for the semiconductor layer.

[0350] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0351] Hereinafter, an oxide containing indium (In), gallium (Ga), and zinc (Zn) will be described as an example of a metal oxide. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) may be referred to as an In—Ga—Zn oxide.

[0352] <Classification of Crystal Structure> Examples of the crystal structure of an oxide semiconductor include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0353] The crystalline structure of a film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, it can be evaluated using an XRD spectrum obtained by GIXD (Grazing-Incident XRD) measurement. The GIXD method is also called the thin film method or the Seemann-Bohlin method. In the following, the XRD spectrum obtained by GIXD measurement may be simply referred to as the XRD spectrum.

[0354] For example, in the case of a quartz glass substrate, the peak shape of the XRD spectrum is almost symmetrical. On the other hand, in the case of an In-Ga-Zn oxide film having a crystalline structure, the peak shape of the XRD spectrum is asymmetrical. The asymmetrical peak shape of the XRD spectrum clearly indicates the presence of crystals in the film or substrate. In other words, if the peak shape of the XRD spectrum is not symmetrical, the film or substrate cannot be said to be in an amorphous state.

[0355] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, confirming that the quartz glass is in an amorphous state. Furthermore, a spot-like pattern is observed in the diffraction pattern of an In—Ga—Zn oxide film formed at room temperature, rather than a halo. For this reason, it is estimated that the In—Ga—Zn oxide formed at room temperature is neither single crystal nor polycrystalline, nor in an amorphous state, but is in an intermediate state, and it cannot be concluded that it is in an amorphous state.

[0356] <<Structure of Oxide Semiconductor>> Note that oxide semiconductors may be classified differently from the above when focusing on their structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0357] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0358] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0359] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the maximum diameter of the crystalline region may be several tens of nanometers.

[0360] In an In—Ga—Zn oxide, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing gallium (Ga), zinc (Zn), and oxygen (hereinafter referred to as a (Ga, Zn) layer) are stacked. Note that indium and gallium are mutually substituted. Therefore, the (Ga, Zn) layer may contain indium. The In layer may contain gallium. The In layer may contain zinc. The layered structure is observed as a lattice image in a high-resolution transmission electron microscope (TEM) image, for example.

[0361] When a CAAC-OS film is subjected to structural analysis using an XRD apparatus, for example, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0362] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film, and the spots are observed at positions that are point-symmetric with respect to a spot of an incident electron beam that has passed through the sample (also referred to as a direct spot).

[0363] When a crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundary can be identified even near the distortion. This indicates that the distortion in the lattice arrangement suppresses the formation of grain boundaries. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the a-b plane and the change in interatomic bond distance caused by metal atom substitution.

[0364] A crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, and carriers are likely to be trapped, resulting in a decrease in the on-state current of a transistor and a decrease in field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. To form a CAAC-OS, a structure containing Zn is preferable. For example, In—Zn oxide and In—Ga—Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0365] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities, the formation of defects, or the like, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor having the CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having the CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using the CAAC-OS in a transistor having a metal oxide in a channel formation region (sometimes referred to as an OS transistor) can increase the flexibility of the manufacturing process.

[0366] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scanning. When an nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than that of a nanocrystal (e.g., 1 nm to 30 nm), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0367] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0368] <<Structure of Oxide Semiconductor>> Next, the above-described CAC-OS will be described in detail. Note that the CAC-OS relates to a material structure.

[0369] [CAC-OS] CAC-OS is, for example, a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0370] Furthermore, the CAC-OS has a mosaic structure in which a material is separated into a first region and a second region, and the first region is distributed throughout the film (hereinafter also referred to as a cloud structure). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0371] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In—Ga—Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In—Ga—Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0372] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be referred to as a region whose main component is In. The second region can be referred to as a region whose main component is Ga.

[0373] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0374] Furthermore, CAC-OS in In—Ga—Zn oxide refers to a structure in which a mosaic of regions containing Ga as the main component and regions containing In as the main component are randomly arranged in a material composition containing In, Ga, Zn, and O. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed nonuniformly.

[0375] The CAC-OS can be formed by sputtering without heating the substrate. When forming the CAC-OS by sputtering, any one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition, the more preferable it is. For example, the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0376] Furthermore, for example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) can confirm that the CAC-OS has a structure in which a region containing In as a main component (first region) and a region containing Ga as a main component (second region) are unevenly distributed and mixed.

[0377] Here, the first region has higher conductivity than the second region. That is, the flow of carriers through the first region causes the metal oxide to exhibit conductivity. Therefore, the first region is distributed in a cloud-like manner in the metal oxide, thereby achieving a high field-effect mobility (μ).

[0378] On the other hand, the second region has higher insulating properties than the first region. That is, the second region is distributed in the metal oxide, thereby suppressing leakage current.

[0379] Therefore, when a CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (a function of turning on / off). That is, a CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and functions as a semiconductor as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using a CAC-OS in a transistor, a high on-current (I ｏｎ ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0380] Furthermore, a transistor using the CAC-OS has high reliability, and therefore, the CAC-OS is ideal for various semiconductor devices such as display devices.

[0381] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0382] <Transistor Having Oxide Semiconductor> Next, a case where the oxide semiconductor is used for a transistor will be described.

[0383] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0384] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 １７ cm −３ Below 1 × 10, preferably １５ cm −３ More preferably, 1×10 １３ cm −３ Less than 1×10, more preferably 1×10 １１ cm −３ More preferably, 1×10 １０cm −３ is less than 1×10 −９ cm −３ That is all. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0385] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0386] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0387] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0388] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0389] When an oxide semiconductor contains silicon or carbon, which is one of Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) is set to 2×10 １８ atoms / cm ３Below 2 × 10, preferably １７ atoms / cm ３ The following applies.

[0390] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0391] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 １９ atoms / cm ３ Less than 5×10 １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ Do the following:

[0392] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor obtained by SIMS is measured to be 1×10 ２０ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Make it less than.

[0393] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0394] <<Other Semiconductor Materials>> The semiconductor material that can be used for the oxide 230 is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the oxide 230. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also referred to as an atomic layer material, two-dimensional material, etc.) is preferably used as the semiconductor material. In particular, a layered material that functions as a semiconductor is preferably used as the semiconductor material.

[0395] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0396] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0397] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ By applying the above-mentioned transition metal chalcogenide to the oxide 230, a semiconductor device with a large on-current can be provided.

[0398] <Modification of Semiconductor Device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS. 14A to 14D.

[0399] Fig. 14A shows a top view of the semiconductor device. Fig. 14B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 14A. Fig. 14C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 14A. Fig. 14D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in Fig. 14A. In the top view of Fig. 14A, some elements are omitted for clarity.

[0400] 14A to 14D, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration Example of Semiconductor Device>. Note that, in this section as well, the materials described in detail in <Configuration Example of Semiconductor Device> can be used as the constituent materials of the semiconductor device.

[0401] The semiconductor device shown in Figures 14A to 14D is a modified example of the semiconductor device shown in Figures 9A to 9D. The semiconductor device shown in Figures 14A to 14D differs from the semiconductor device shown in Figures 9A to 9D in that it includes an insulator 283 and an insulator 221.

[0402] The insulator 283 is provided between the insulator 282 and the insulator 285. The insulator 283 is preferably an insulator that has a function of suppressing hydrogen diffusion. This can suppress hydrogen diffusion from above the insulator 283 to the transistor 200. Note that the insulator 283 may be any of the insulators that can be used for the insulator 275. For example, the insulator 283 may be a silicon nitride film formed by a sputtering method. By forming the insulator 283 by a sputtering method, a silicon nitride film with high density can be formed. Alternatively, the insulator 283 may be formed by stacking a silicon nitride film formed by a PEALD method or a CVD method on a silicon nitride film formed by a sputtering method.

[0403] By providing the insulator 282, which is in contact with the insulator 280 and has a function of capturing impurities such as hydrogen, in the region sandwiched between the insulators 212 and 283, the impurities such as hydrogen contained in the insulator 280 can be captured and the amount of hydrogen in the region can be kept constant. In particular, using aluminum oxide having an amorphous structure as the insulator 282 is preferable because it can more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with favorable characteristics.

[0404] 14A to 14D show a structure in which the insulator 283 is provided as a single layer, but the present invention is not limited to this. For example, the insulator 283 may have a stacked structure of two or more layers.

[0405] For example, when the insulator 283 has a two-layer stacked structure, a silicon nitride film may be formed as a lower layer of the insulator 283 by sputtering, and a silicon nitride film may be formed as an upper layer of the insulator 283 by ALD. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the lower layer of the insulator 282 can be reduced. Furthermore, if a pinhole or a step is formed in a film deposited by sputtering, the portion overlapping the pinhole or step can be blocked by using a film deposited by ALD, which has good coverage.

[0406] When the insulator 283 has a two-layer laminated structure, a part of the upper surface of the upper layer of the insulator 283 may be removed. Also, it may be difficult to clearly detect the boundary between the upper and lower layers of the insulator 283.

[0407] The insulator 221 is provided between the insulator 216 and the conductor 205 and the insulator 222. The insulator 221 preferably has a function of suppressing hydrogen diffusion. This can suppress hydrogen from diffusing from below the insulator 221 to the transistor 200. Note that the insulator 221 can also have the function of the insulator 212. In such a case, by not providing the insulator 212, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0408] The insulator 221 may be any insulator that can be used for the insulator 275 described above. For example, it is preferable to use silicon nitride formed by an ALD method (particularly a PEALD method) as the insulator 221. By using the ALD method to form the insulator 221, the insulator 221 can be formed with good coverage even if unevenness is formed between the insulator 216 and the conductor 205. Therefore, pinholes or discontinuities can be prevented from forming in the insulator 222 formed on the insulator 221.

[0409] Furthermore, an insulator having a function of suppressing diffusion of hydrogen may be provided between the insulator 222 and the insulator 224. This can suppress diffusion of hydrogen from below the insulator to the transistor 200.

[0410] 14B and 14C, the conductor 205 may have a three-layer structure of conductor 205a, conductor 205b, and conductor 205c. The conductor 205c is provided in contact with the upper surface of the conductor 205b. The side surface of the conductor 205c may be in contact with the conductor 205a. The upper surface of the conductor 205c may be configured to roughly coincide with the top of the conductor 205a.

[0411] Like the conductor 205a, the conductor 205c is preferably made of a conductive material that has the function of reducing hydrogen diffusion. This allows the conductor 205b to be surrounded by the conductors 205a and 205c, thereby preventing impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulators 216 and 224. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductors 205a and 205c, it is possible to suppress oxidation of the conductor 205b and a decrease in conductivity.

[0412] OS transistors such as the transistor 200 have small changes in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. For example, OS transistors can be suitably used in outer space. Specifically, OS transistors can be used as transistors for semiconductor devices installed in space shuttles, artificial satellites, space probes, and the like. Examples of radiation include X-rays and neutron rays. Although outer space refers to an altitude of 100 km or higher, the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0413] Alternatively, for example, the OS transistor can be used as a transistor for a semiconductor device provided in a robot for working at a nuclear power plant or a radioactive waste treatment or disposal site, and particularly as a transistor for a semiconductor device provided in a remote-controlled robot that is remotely operated to dismantle a nuclear reactor facility, remove nuclear fuel or fuel debris, or conduct on-site inspections of spaces containing a lot of radioactive material.

[0414] According to one embodiment of the present invention, a novel transistor can be provided. Alternatively, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, a semiconductor device with favorable frequency characteristics can be provided. Alternatively, a semiconductor device with high operating speed can be provided. Alternatively, a semiconductor device with little variation in transistor characteristics can be provided. Alternatively, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, a semiconductor device with favorable reliability can be provided. Alternatively, a semiconductor device with large on-state current can be provided. Alternatively, a semiconductor device with high field-effect mobility can be provided. Alternatively, a semiconductor device with low power consumption can be provided.

[0415] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0416] 15 illustrates a cross-sectional structure example of a memory device 100 according to one embodiment of the present invention. The memory device 100 illustrated in FIG. 15 includes a plurality of memory layers 60 above a driver circuit layer 50. To avoid repetition of description, description of the memory layer 60 in this embodiment will be omitted.

[0417] 15 illustrates a transistor 400 included in the driver circuit layer 50. The transistor 400 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 400 may be a p-channel transistor or an n-channel transistor. The substrate 311 may be, for example, a single-crystal silicon substrate.

[0418] Here, in the transistor 400 shown in FIG. 15 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 400 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI (silicon-on-insulator) substrate.

[0419] Note that the transistor 400 illustrated in FIG. 15 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or the driving method.

[0420] Between each structure, a wiring layer including an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0421] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 400. A conductor 328 or the like is embedded in the insulators 320 and 322. A conductor 330 or the like is embedded in the insulators 324 and 326. The conductors 328 and 330 function as contact plugs or wirings.

[0422] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0423] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 15 , an insulator 350, an insulator 357, an insulator 352, and an insulator 354 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulator 350, the insulator 357, and the insulator 352. The conductor 356 functions as a contact plug or a wiring.

[0424] An insulator 354 is provided over the insulator 352 and the conductor 356. A conductor 358 is embedded in the insulator 354. The conductor 358 functions as a contact plug or a wiring. For example, the wiring SL and the transistor 400 are electrically connected through the conductor 358, the conductor 356, the conductor 330, and the like.

[0425] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0426] Embodiment Mode 4 In this embodiment mode, an example of an electronic component in which the memory device or the like shown in the above embodiment modes is incorporated will be described.

[0427] <Electronic Component> FIG. 16A is a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in FIG. 16A includes a memory device 100, which is a type of semiconductor device according to one embodiment of the present invention, in a mold 711. FIG. 16A omits some details to illustrate the interior of the electronic component 700. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the memory device 100 via wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0428] As shown in the above embodiment, the memory device 100 includes the drive circuit layer 50 , the memory layer 60 , and the memory array 15 .

[0429] 16B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of memory devices 100 provided on the interposer 731.

[0430] The electronic component 730 shows an example in which the storage device 100 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0431] The package substrate 732 may be made of a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. The interposer 731 may be made of a silicon interposer, a resin interposer, etc.

[0432] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0433] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since wiring formation on a silicon interposer can be performed using a semiconductor process, it is easy to form fine wiring that is difficult to form on a resin interposer.

[0434] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0435] Furthermore, in SiP, MCM, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0436] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 100 and the height of the semiconductor device 735.

[0437] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 16B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0438] The electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0439] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0440] Embodiment 5 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0441] A storage device according to one embodiment of the present invention can be used as a storage device for various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, Internet of Things (IoT), healthcare-related devices, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0442] 17A to 17J and 18A to 18E illustrate examples of electronic devices including an electronic component 700 or an electronic component 730 including the memory device according to one embodiment of the present invention.

[0443] 17A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. The display unit 5511 is provided with a touch panel and the housing 5510 is provided with buttons as input interfaces.

[0444] By applying a storage device according to one embodiment of the present invention, the information terminal 5500 can store temporary files (for example, caches when using a web browser) generated when an application is executed.

[0445] 17B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0446] Like the information terminal 5500 described above, the wearable terminal can store temporary files generated when an application is executed by applying a storage device according to one embodiment of the present invention.

[0447] 17C shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0448] Like the information terminal 5500 described above, the desktop information terminal 5300 can store temporary files generated when an application is executed by applying a storage device according to one embodiment of the present invention.

[0449] 17A to 17C are taken as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0450] 17D also illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, etc. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0451] A storage device according to one embodiment of the present invention can be applied to the electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as food ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the food ingredients to an information terminal or the like via the Internet. The electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in the semiconductor device.

[0452] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0453] 17E shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0454] FIG. 17F further illustrates a stationary game console 7500, an example of a game console. The stationary game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a wired connection. Although not shown in FIG. 17F , the controller 7522 can include a display unit for displaying game images and an input interface other than buttons, such as a touch panel, a stick, a rotary knob, or a sliding knob. The shape of the controller 7522 is not limited to the shape shown in FIG. 17F , and the shape of the controller 7522 may be modified in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. In a music game, for example, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures or voice.

[0455] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0456] A low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized by applying the storage device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0457] Furthermore, by applying the storage device described in the above embodiment to the portable game console 5200 or the stationary game console 7500, temporary files and the like necessary for calculations that occur during game execution can be stored.

[0458] 17E shows a portable game machine as an example of a game machine. Also, FIG. 17F shows a home-use stationary game machine. Note that the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include an arcade game machine installed in an amusement facility (such as an arcade game center or an amusement park) and a pitching machine for batting practice installed in a sports facility.

[0459] [Mobile Body] The storage device described in the above embodiment can be applied to a mobile body such as an automobile and the area around the driver's seat of the automobile.

[0460] FIG. 17G illustrates an automobile 5700 as an example of a moving object.

[0461] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A storage device that displays this information may also be provided around the driver's seat.

[0462] In particular, the display device can enhance safety by displaying an image from an imaging device (not shown) provided on the automobile 5700, thereby compensating for a field of view obstructed by a pillar or the like, a blind spot on the driver's seat, etc. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, blind spots can be compensated for and safety can be enhanced.

[0463] The semiconductor device described in the above embodiment can temporarily store information, and therefore, for example, the storage device can be used to store temporary information required in a system that performs automatic driving, road guidance, hazard prediction, or the like of the automobile 5700. The display device may be configured to display temporary information such as road guidance and hazard prediction. Furthermore, the display device may be configured to store video images from a driving recorder installed in the automobile 5700.

[0464] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, moving objects may include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0465] [Camera] The storage device described in the above embodiment can be applied to a camera.

[0466] 17H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0467] A low-power digital camera 6240 can be realized by applying the storage device described in the above embodiment to the digital camera 6240. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat generation on the circuit itself, peripheral circuits, and modules.

[0468] [Video Camera] The storage device described in the above embodiment can be applied to a video camera.

[0469] 17I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0470] When recording video captured by the video camera 6300, it is necessary to encode the video according to the data recording format. By using the semiconductor device described above, the video camera 6300 can store temporary files generated during encoding.

[0471] [ICD] The storage device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0472] 17J is a cross-sectional schematic diagram showing an example of an ICD. The ICD main body 5400 has at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0473] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0474] The ICD main body 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with an electric shock is administered.

[0475] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store in the electronic component 700 heart rate data acquired by the sensor, the number of pacing treatments performed, the duration of the treatment, and the like.

[0476] Furthermore, power can be received by the antenna 5404, and the power is charged in the battery 5401. Furthermore, the ICD main body 5400 has multiple batteries, thereby improving safety. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 also functions as an auxiliary power source.

[0477] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0478] [Expansion Device for PC] The semiconductor device described in the above embodiment can be applied to an expansion device for a computer such as a PC (Personal Computer) or an information terminal.

[0479] Fig. 18A shows an example of such an expansion device: a portable expansion device 6100 equipped with a chip capable of storing information and externally attached to a PC. The expansion device 6100 can store information using the chip by connecting to a PC via, for example, a USB (Universal Serial Bus). While Fig. 18A illustrates a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this, and may be, for example, a relatively large expansion device equipped with a cooling fan or the like.

[0480] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with a circuit for driving the semiconductor device described in the above embodiment. For example, an electronic component 700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0481] [SD Card] The storage device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0482] FIG. 18B is a schematic diagram of the external appearance of an SD card, and FIG. 18C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. A memory device and a circuit for driving the memory device are provided on the circuit board 5113. For example, an electronic component 700 and a controller chip 5115 are attached to the circuit board 5113. Note that the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the write circuit, row driver, read circuit, and the like provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 700.

[0483] The capacity of the SD card 5110 can be increased by providing the electronic component 700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This enables wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 700.

[0484] [SSD] The storage device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to electronic devices such as information terminals.

[0485] FIG. 18D is a schematic diagram of the SSD's exterior, and FIG. 18E is a schematic diagram of the SSD's internal structure. The SSD 5150 includes a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is provided with a memory device and a circuit for driving the memory device. For example, the circuit board 5153 is equipped with an electronic component 700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing an electronic component 700 on the back side of the circuit board 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0486] 19A is an example of a large-scale computer. The computer 5600 has a rack 5610 and multiple rack-mounted computers 5620 stored in it.

[0487] The computer 5620 can have the configuration shown in the perspective view of Fig. 19B, for example. In Fig. 19B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0488] A PC card 5621 shown in Figure 19C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 5621 includes a board 5622. The board 5622 also includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 19C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for these semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 may be referred to.

[0489] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0490] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0491] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0492] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0493] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0494] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for learning and inference in artificial intelligence, for example.

[0495] By using a storage device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be made smaller and consume less power. Furthermore, the storage device of one embodiment of the present invention consumes less power, which reduces heat generation from the circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using a storage device of one embodiment of the present invention, electronic devices that operate stably even in high-temperature environments can be realized. Therefore, the reliability of the electronic devices can be improved.

[0496] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0497] 10: memory cell, 15: memory array, 100: storage device, 150: capacitance element, 153: insulator, 154: insulator, 158: opening, 160: conductor, 200: transistor

Claims

1. N memory layers (N is an integer equal to or greater than 2); a plurality of first wirings extending in a first direction that is a stacking direction of the N memory layers; a plurality of second wirings extending in the first direction; a plurality of third wirings extending in the first direction; a plurality of fourth wirings extending in a second direction perpendicular to the first direction; a plurality of fifth wirings extending in the second direction; and Each of the N memory layers has a plurality of memory cells arranged in a matrix, Each of the plurality of memory cells includes a first transistor, a second transistor, and a capacitance element; a gate of the first transistor is electrically connected to one of the plurality of fourth wirings; one of a source and a drain of the first transistor is electrically connected to the first wiring via a first conductor; one electrode of the capacitance element is electrically connected to the fifth wiring, the other electrode of the capacitance element is electrically connected to the other of the source and the drain of the first transistor and the gate of the second transistor; one of the source and the drain of the second transistor is electrically connected to the second wiring; the other of the source and the drain of the second transistor is electrically connected to the third wiring; the first conductor has a region in contact with the first wiring on at least one of an upper surface, a side surface, and a lower surface; The second wiring is shared between two memory cells adjacent in the second direction.

2. In claim 1, one of the source and the drain of the second transistor is electrically connected to the second wiring via a second conductor; The second conductor has a region on at least one of its top surface, side surface, and bottom surface that contacts the second wiring.

3. In claim 1 or claim 2, the other of the source and the drain of the second transistor is electrically connected to the third wiring via a third conductor; The third conductor has a region on at least one of its top surface, side surface, and bottom surface that contacts the third wiring.

4. In any one of claims 1 to 3, The memory device, wherein the first transistor is a transistor having a back gate.

5. In any one of claims 1 to 3, The first transistor includes an oxide semiconductor.