Storage device

Abstract

Provided is a storage device that enables miniaturization or high integration. This storage device comprises: a memory cell that includes a capacitive element and a transistor on the capacitive element; a first insulator on the capacitive element; and a second insulator on the first insulator. The transistor comprises a first conductor under the first insulator, an oxide semiconductor disposed in contact with the upper surface of the first conductor, a second conductor disposed between the first insulator and the second insulator and in contact with the oxide semiconductor, a third insulator on the oxide semiconductor, and a third conductor on the third insulator. A first opening reaching the first conductor is formed in the first insulator, the second conductor, and the second insulator. At least a part of the oxide semiconductor, at least a part of the third insulator, and at least a part of the third conductor are disposed in the first opening. The capacitive element includes a fourth conductor, a fourth insulator on the fourth conductor, and the first conductor on the fourth insulator.

Description

storage device

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing the memory device or the semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Another embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0004] In recent years, the development of semiconductor devices has progressed, and large scale integration (LSI), central processing units (CPU), memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed on chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide a plurality of memory cells in a superimposed manner.

[0009] JP 2012-257187 A JP 2011-151383 A International Publication No. 2021 / 053473

[0010] M. Oota et. al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0011] An object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated. Another object is to provide a memory device with high operating speed. Another object is to provide a memory device with good electrical characteristics. Another object is to provide a memory device with little variation in electrical characteristics of transistors. Another object is to provide a memory device with good reliability. Another object is to provide a memory device with high on-state current. Another object is to provide a memory device with low power consumption. Another object is to provide a novel memory device. Another object is to provide a manufacturing method of a novel memory device.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc.

[0013] One embodiment of the present invention is a memory device including a capacitor, a transistor over the capacitor, a first insulator over the capacitor, and a second insulator over the first insulator. The transistor includes a first conductor under the first insulator, an oxide semiconductor arranged in contact with a top surface of the first conductor, a second conductor arranged between the first insulator and the second insulator and in contact with the oxide semiconductor, a third insulator over the oxide semiconductor, and a third conductor over the third insulator. A first opening reaching the first conductor is formed in the first insulator, the second conductor, and the second insulator, and at least part of the oxide semiconductor, at least part of the third insulator, and at least part of the third conductor are disposed in the first opening. The capacitor includes a fourth conductor, a fourth insulator over the fourth conductor, and the first conductor over the fourth insulator.

[0014] Another embodiment of the present invention provides a transistor including a first layer and a second layer, each of which includes a capacitor, a transistor over the capacitor, a first insulator over the capacitor, and a second insulator over the first insulator. The second layer is stacked on the first layer. The transistor includes a first conductor under the first insulator, an oxide semiconductor disposed in contact with a top surface of the first conductor, a second conductor disposed between the first insulator and the second insulator and in contact with the oxide semiconductor, a third insulator over the oxide semiconductor, and a third conductor over the third insulator. a first opening is formed in a second insulator of the first layer, the first opening reaching the first conductor, and at least a portion of the oxide semiconductor, at least a portion of the third insulator, and at least a portion of the third conductor are disposed in the first opening; a capacitive element has a fourth conductor, a fourth insulator on the fourth conductor, and a first conductor on the fourth insulator; a second opening is formed in the second insulator of the first layer and the first insulator of the second layer, and a fifth conductor is disposed in the second opening, and the fifth conductor is in contact with an upper surface of the second conductor of the first layer and a lower surface of the second conductor of the second layer.

[0015] In the above memory device, it is preferable that a sixth conductor is in contact with the upper surface of the third conductor, the second conductor is formed to extend in a first direction, the sixth conductor is formed to extend in a second direction, and the first direction and the second direction intersect each other.

[0016] In the above memory device, it is preferable that the first conductor functions as one of a source electrode and a drain electrode, the second conductor functions as the other of the source electrode and the drain electrode, and the third conductor functions as a gate electrode.

[0017] In the above memory device, part of the oxide semiconductor, part of the third insulator, and part of the third conductor are preferably located over the second insulator.

[0018] In the memory device, it is preferable that a side edge of the oxide semiconductor and a side edge of the third insulator substantially coincide with each other in a plan view.

[0019] In the above memory device, it is preferable that a side edge of the third conductor be located inside a side edge of the oxide semiconductor and a side edge of the third insulator in a plan view.

[0020] In the memory device, it is preferable that a fifth insulator be provided between the third insulator and the third conductor, and that the fifth insulator cover side edges of the oxide semiconductor and the third insulator. In the memory device, it is preferable that the fifth insulator be silicon nitride.

[0021] In the memory device, the oxide semiconductor preferably contains one or more selected from In, Ga, and Zn. In the memory device, the oxide semiconductor preferably has layered crystals that are substantially parallel to the sidewalls of the first opening. In the memory device, the oxide semiconductor preferably has a carbon concentration of 1×10 ２０ atoms / cm ３ It is preferable that the ratio is less than 1 / 2.

[0022] According to one embodiment of the present invention, a memory device that can be miniaturized or highly integrated can be provided. Alternatively, a memory device with high operating speed can be provided. Alternatively, a memory device with high reliability can be provided. Alternatively, a memory device with little variation in electrical characteristics of transistors can be provided. Alternatively, a memory device with good electrical characteristics can be provided. Alternatively, a memory device with high on-state current can be provided. Alternatively, a memory device with low power consumption can be provided. Alternatively, a novel memory device can be provided. Alternatively, a manufacturing method of a novel memory device can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc.

[0024] FIG. 1A is a plan view of a memory device according to one embodiment of the present invention. FIGS. 1B to 1D are cross-sectional views of the memory device according to one embodiment of the present invention. FIG. 1E is a circuit diagram illustrating a configuration of a memory device according to one embodiment of the present invention. FIG. 2A is a plan view illustrating a method for manufacturing a memory device according to one embodiment of the present invention. FIGS. 2B and 2C are cross-sectional views illustrating the method for manufacturing a memory device according to one embodiment of the present invention. FIG. 3A is a plan view illustrating a method for manufacturing a memory device according to one embodiment of the present invention. FIGS. 3B and 3C are cross-sectional views illustrating the method for manufacturing a memory device according to one embodiment of the present invention. FIG. 4A is a plan view illustrating a method for manufacturing a memory device according to one embodiment of the present invention. FIGS. 4B and 4C are cross-sectional views illustrating the method for manufacturing a memory device according to one embodiment of the present invention. FIG. 5A is a plan view illustrating a method for manufacturing a memory device according to one embodiment of the present invention. FIGS. 5B and 5C are cross-sectional views illustrating the method for manufacturing a memory device according to one embodiment of the present invention. FIG. 6A is a plan view illustrating a method for manufacturing a memory device according to one embodiment of the present invention. FIGS. 6B and 6C are cross-sectional views illustrating the method for manufacturing a memory device according to one embodiment of the present invention. FIG. 7A is a plan view illustrating a method for manufacturing a memory device according to one embodiment of the present invention. 7B and 7C are cross-sectional views illustrating a method for manufacturing a memory device according to one embodiment of the present invention. FIG. 8A is a plan view illustrating a method for manufacturing a memory device according to one embodiment of the present invention. FIGS. 8B and 8C are cross-sectional views illustrating a method for manufacturing a memory device according to one embodiment of the present invention. FIGS. 9A to 9C are cross-sectional views of a memory device according to one embodiment of the present invention. FIG. 10A is a plan view of a memory device according to one embodiment of the present invention. FIG. 10B is a cross-sectional view of a memory device according to one embodiment of the present invention. FIG. 11A is a plan view of a memory device according to one embodiment of the present invention. FIG. 11B is a cross-sectional view of a memory device according to one embodiment of the present invention. FIGS. 12A to 12E are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIGS. 13A to 13D are cross-sectional views of a metal oxide film according to one embodiment of the present invention. FIGS. 14A to 14D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIGS. 15A to 15C are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIG. 16 is a block diagram illustrating a configuration example of a memory device. 17A and 17B are a schematic diagram and a circuit diagram illustrating an example of the configuration of a memory device.18A and 18B are schematic diagrams illustrating a configuration example of a memory device. FIG. 19 is a circuit diagram illustrating a configuration example of a memory device. FIGS. 20A and 20B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. FIGS. 21A and 21B are diagrams illustrating an example of an electronic component. FIGS. 22A to 22E are schematic diagrams of a memory device according to one embodiment of the present invention. FIGS. 23A to 23H are diagrams illustrating electronic devices according to one embodiment of the present invention. FIG. 24 is a diagram illustrating an example of space equipment.

[0025] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0026] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks may be unintentionally thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same reference numerals may be used in common between different drawings for identical parts or parts having similar functions, and repeated explanations may be omitted. When referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0027] In order to make the invention easier to understand, particularly in plan views (also called "top views") and perspective views, some components may be omitted from the drawings, and some hidden lines may be omitted.

[0028] In addition, in this specification and the like, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for explanation. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification and the like.

[0029] Furthermore, in this specification, terms indicating position, such as "above" and "below," are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0030] For example, in this specification, "X and Y are connected" refers to an electrical connection between X and Y. Here, "X and Y are electrically connected" refers to a connection in which an electrical signal can be transmitted between X and Y when an object (such as a switch, transistor element, or diode, or a circuit including such an object and wiring) is present between X and Y. Note that "X and Y are electrically connected" also includes a case in which X and Y are directly connected. Here, "X and Y are directly connected" refers to a connection in which an electrical signal can be transmitted between X and Y via wiring (or electrodes) or the like, without passing through the object. In other words, a direct connection refers to a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.

[0031] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0032] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0033] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor, reduce the crystallinity, and so on. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. Ｏ In some cases, oxygen vacancies (also called oxygen vacancies) may be formed.

[0034] In this specification and the like, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen. Silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen. Aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen. Aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen. Hafnium oxynitride refers to a material whose composition contains more oxygen than nitrogen. Hafnium nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0035] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0036] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0037] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0038] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, “[n]”, or “[m, n]” may be added to the symbol.

[0039] In this specification, the term "having the same or approximately the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in the manufacturing process of a memory device, a planarization process (typically a CMP process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces processed by the CMP process have a configuration in which the heights from the reference surface are equal. However, the heights of multiple layers may differ depending on the processing equipment, processing method, or material of the processed surface during the CMP process. In this specification, this case is also treated as "having the same or approximately the same height." For example, in the case of a structure having two layers (here, a first layer and a second layer) with different heights relative to a reference surface, the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less is also referred to as "having the same or approximately the same height."

[0040] In this specification, "edges that coincide or approximately coincide" means that, in a plan view, at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "edges that coincide or approximately coincide" is also used.

[0041] 1 to 11. The memory device according to one embodiment of the present invention includes a transistor and a capacitor.

[0042] <Configuration Example of Memory Device> The configuration of a memory device including a transistor and a capacitor will be described with reference to FIG. 1. FIGS. 1A to 1D are plan views and cross-sectional views of a memory device including a transistor 200 and a capacitor 100. FIG. 1A is a plan view of the memory device. FIGS. 1B to 1D are cross-sectional views of the memory device. Here, FIG. 1B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 1A. FIG. 1C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 1A. FIG. 1D is a cross-sectional view of a portion of a transistor 200. Note that some elements are omitted from the plan view of FIG. 1A for clarity.

[0043] 1A is parallel to the channel length direction of the transistor 200, the Y direction is perpendicular to the Z direction, and the X direction is perpendicular to the Z direction and the Y direction. The X direction, Y direction, and Z direction shown in FIG. 1A are also shown in FIGS. 1B to 1D.

[0044] A memory device of one embodiment of the present invention includes an insulator 140 over a substrate (not shown), a capacitor 100 over the insulator 140, a transistor 200 over the capacitor 100, an insulator 280 over the insulator 140 and the capacitor 100, an insulator 281 and a conductor 240 over the insulator 280, an insulator 285 over the insulator 281 and the conductor 240, an insulator 287 over the insulator 285, and an insulator 289 and a conductor 265 over the insulator 287. The insulator 140, the insulator 280, the insulator 281, the insulator 285, the insulator 287, and the insulator 289 function as interlayer films.

[0045] The transistor 200 includes a conductor 120 under an insulator 280, an oxide semiconductor 230 arranged in contact with the top surface of the conductor 120, a conductor 240 in contact with part of the oxide semiconductor, an insulator 250 on the oxide semiconductor 230, and a conductor 260 on the insulator 250. Here, the oxide semiconductor 230 functions as a semiconductor layer, the conductor 260 functions as a gate electrode, the conductor 120 functions as one of a source electrode and a drain electrode, the conductor 240 functions as the other of the source electrode and drain electrode, and the insulator 250 functions as a gate insulator.

[0046] 1B and 1C , an opening 290 reaching the conductor 120 is formed in the insulator 280, the conductor 240, and the insulator 285. At least a portion of the oxide semiconductor 230, at least a portion of the insulator 250, and at least a portion of the conductor 260 are disposed in the opening 290.

[0047] The capacitor 100 has a conductor 110 on an insulator 140, an insulator 130 on the conductor 110, and a conductor 120 on the insulator 130. The conductor 110 functions as a lower electrode, the conductor 120 functions as an upper electrode, and the insulator 130 functions as a dielectric. In other words, the capacitor 100 constitutes a metal-insulator-metal (MIM) capacitor.

[0048] The transistor 200 and the capacitor 100 described in this embodiment can be used as memory cells of a memory device (hereinafter, sometimes referred to as memory cells 150). Here, as shown in FIGS. 1B and 1C , the transistor 200 is provided to overlap with the capacitor 100. In particular, the conductor 120 functions as one of the source electrode and the drain electrode of the transistor 200 and also functions as the upper electrode of the capacitor 100; therefore, the transistor 200 and the capacitor 100 share part of their structures. With such a structure, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This allows the area of ​​the memory cell 150 to be reduced, thereby enabling the memory cells 150 to be arranged at high density and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0049] 1E is a circuit diagram of the memory device described in this embodiment. As shown in FIG. 1E, the configurations shown in FIGS. 1A to 1C function as memory cells of the memory device. The memory cell includes a transistor Tr and a capacitor C. Here, the transistor Tr corresponds to the transistor 200, and the capacitor C corresponds to the capacitor 100.

[0050] In the memory cell, one of the source and drain of the transistor Tr is connected to one electrode of the capacitor C. The other of the source and drain of the transistor Tr is connected to a wiring BL. The gate of the transistor Tr is connected to a wiring WL. The other electrode of the capacitor C is connected to a wiring PL.

[0051] Here, the wiring BL corresponds to the conductor 240, the wiring WL corresponds to the conductor 265, and the wiring PL corresponds to the conductor 110. As shown in FIGS. 1A to 1C, it is preferable that the conductor 265 is formed to extend in the Y direction, and the conductor 240 is formed to extend in the X direction. With this configuration, the wiring BL and the wiring WL are provided to intersect with each other. Also, in FIG. 1E, the wiring PL is provided parallel to the wiring WL, but the present invention is not limited to this. For example, the wiring PL (the conductor 110) may be provided parallel to the wiring BL, or the wiring PL (the conductor 110) may be provided in a planar shape.

[0052] The memory cells will be described in detail in a later embodiment.

[0053] [Transistor 200] As shown in FIGS. 1A to 1C , the transistor 200 can have a structure including a conductor 120 provided on and in contact with the insulator 130, an oxide semiconductor 230 provided in contact with the top surface of the conductor 120, a side surface of the insulator 280, a side surface of the conductor 240, and a side surface and top surface of the insulator 285, an insulator 250 provided in contact with the top surface of the oxide semiconductor 230, the conductor 240 provided so as to be embedded in the insulator 281, a conductor 260 provided in contact with the top surface of the insulator 250, and a conductor 265 provided in contact with the top surface of the conductor 260 and embedded in the insulator 289.

[0054] At least a portion of the transistor 200 is disposed within the opening 290. The opening 290 may be cylindrical, as shown in FIGS. 1A to 1D . In this case, the opening 290 is circular in plan view and rectangular in cross-sectional view. Here, the bottom surface of the opening 290 is the top surface of the conductor 120, and the sidewalls of the opening 290 are the side surfaces of the insulator 280, the conductor 240, and the insulator 285.

[0055] In this embodiment, the opening 290 is provided so that the sidewall of the opening 290 is approximately perpendicular to the top surface of the conductor 120; however, the present invention is not limited to this. For example, the sidewall of the opening 290 may have a tapered shape. Tapering the sidewall of the opening 290 improves coverage with the oxide semiconductor 230, the insulator 250, or the like, and can reduce defects such as voids.

[0056] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, the angle between the inclined side surface and the substrate surface (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side surface of the structure and the substrate surface do not necessarily need to be completely flat, but may be substantially planar with a slight curvature or a slight unevenness.

[0057] Furthermore, in the present embodiment, an example has been shown in which opening 290 is circular in plan view, but the present invention is not limited to this. For example, opening 290 may be approximately circular in plan view, such as an ellipse, polygonal in shape, such as a rectangle, or polygonal in shape with rounded corners.

[0058] The portions of the oxide semiconductor 230, the insulator 250, and the conductor 260 that are arranged inside the opening 290 are provided to reflect the shape of the opening 290. Thus, the oxide semiconductor 230 is provided so as to cover the bottom surface and sidewall of the opening 290, the insulator 250 is provided so as to cover the oxide semiconductor 230, and the conductor 260 is provided so as to fill a recess in the insulator 250 that reflects the shape of the opening 290. Here, the oxide semiconductor 230 contacts the top surface of the conductor 120 at the bottom of the opening 290, and contacts the side surface of the conductor 240 at the sidewall of the opening 290.

[0059] As described above, the conductor 260 functions as the gate electrode of the transistor 200, the conductor 120 functions as one of the source electrode and drain electrode of the transistor 200, and the conductor 240 functions as the other of the source electrode and drain electrode of the transistor 200. Therefore, the region of the oxide semiconductor 230 in contact with the conductor 120 and at least a portion of its vicinity functions as one of the source region and drain region, and the region of the oxide semiconductor 230 in contact with the conductor 240 and at least a portion of its vicinity functions as the other of the source region and drain region. Here, FIG. 1D is a cross-sectional view in the XY plane including the conductor 240. As shown in FIG. 1D , the conductor 240 contacts the entire periphery of the oxide semiconductor 230. Therefore, the other of the source region and drain region of the transistor 200 can be formed on the entire periphery of a portion of the oxide semiconductor 230 that is formed in the same layer as the conductor 240.

[0060] At least part of a region of the oxide semiconductor 230 between a region serving as one of the source region and the drain region and a region serving as the other of the source region and the drain region functions as a channel formation region.

[0061] Here, the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 between the conductor 120 and the conductor 240. Alternatively, the channel formation region of the transistor 200 can be located in a region of the oxide semiconductor 230 that is in contact with the insulator 280 or in the vicinity of the region. In other words, the channel length of the transistor 200 can be determined by the thickness of the insulator 280 over the conductor 120.

[0062] In conventional transistors, the channel length is set by the exposure limit of photolithography. However, in the present invention, the channel length can be set by the film thickness of the insulator 280. Therefore, the channel length of the transistor 200 can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200, thereby improving frequency characteristics. Therefore, the read speed and write speed of the memory cell 150 can be improved, and a memory device with high operating speed can be provided.

[0063] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 290. This allows the area occupied by the transistor 200 to be reduced compared to conventional transistors in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows for higher integration of the memory device, thereby increasing the memory capacity per unit area.

[0064] 1D , the oxide semiconductor 230, the insulator 250, and the conductor 260 are also arranged concentrically in the XY plane including the channel formation region of the oxide semiconductor 230. Therefore, the side surface of the conductor 260 provided at the center faces the side surface of the oxide semiconductor 230 with the insulator 250 interposed therebetween. That is, in a plan view, the entire periphery of the oxide semiconductor 230 becomes the channel formation region. In this case, for example, the channel width of the transistor 200 is determined by the periphery length of the oxide semiconductor 230. By providing the oxide semiconductor 230, the insulator 250, and the conductor 260 in this manner, the channel width per unit area can be increased, and the on-current can be increased.

[0065] Furthermore, by forming the opening 290 so as to have a circular shape in a plan view, the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged concentrically. This makes the distance between the conductor 260 and the oxide semiconductor 230 approximately uniform, allowing a gate electric field to be applied to the oxide semiconductor 230 approximately uniformly.

[0066] The channel formation region of the transistor 200 preferably has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source and drain regions. Ｏ H) and generate electrons that become carriers. Therefore, in the channel formation region, V Ｏ It is preferable that H is also reduced. As such, the channel formation region of the transistor 200 is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor 200 can be said to be i-type (intrinsic) or substantially i-type.

[0067] In addition, the source and drain regions of the transistor 200 have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of the transistor 200 are n-type regions with a high carrier concentration and low resistance compared to the channel formation region, due to a high concentration of H or a high concentration of impurities such as hydrogen, nitrogen, or metal elements.

[0068] Part of the oxide semiconductor 230, part of the insulator 250, and part of the conductor 260 are located outside the opening 290, that is, on the insulator 285. Here, a structure in which part of the oxide semiconductor 230 is in contact with the top surface of the insulator 285 can be used. Alternatively, as shown in FIGS. 1B and 1C , a structure in which the side edge of the oxide semiconductor 230 and the side edge of the insulator 250 are approximately aligned may be used. With such a structure, the oxide semiconductor 230 and the insulator 250 can be formed using the same mask, which simplifies the manufacturing process of the memory device.

[0069] Alternatively, the insulator 250 may cover the side edge of the oxide semiconductor 230. This can prevent the conductor 260 and the oxide semiconductor 230 from shorting out.

[0070] 1B and 1C , the side edge of the conductor 260 is preferably located inside the side edge of the oxide semiconductor 230 and the side edge of the insulator 250. This can prevent the conductor 260 and the oxide semiconductor 230 from shorting out.

[0071] The band gap of the metal oxide used for the oxide semiconductor 230 is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced. Because the off-state current of the transistor 200 is small, stored data can be retained for a long period of time by using the transistor 200 in a memory cell. In other words, refresh operation is not required or is performed very infrequently, and therefore the power consumption of the memory device can be sufficiently reduced.

[0072] The oxide semiconductor 230 preferably includes a metal oxide such as indium oxide, gallium oxide, or zinc oxide. The oxide semiconductor 230 preferably includes a metal oxide containing two or three elements selected from the group consisting of indium, element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. The element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin. A metal oxide containing indium, element M, and zinc may be referred to as an In-M-Zn oxide.

[0073] In particular, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), gallium (Ga), zinc (Zn), and tin (Sn) (IGZTO) may be used for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) may be used for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (IAGZO or IGAZO) may be used for the semiconductor layer of the transistor.

[0074] Note that the oxide semiconductor 230 may have a stacked structure of a plurality of oxide layers having different chemical compositions. For example, a structure in which a plurality of kinds of oxides selected from the above metal oxides are appropriately stacked may be used.

[0075] Alternatively, the oxide semiconductor 230 may be a metal oxide having an atomic ratio of In:M:Zn = 1:3:4 or a composition thereof, an atomic ratio of In:M:Zn = 1:1:0.5 or a composition thereof, an atomic ratio of In:M:Zn = 1:1:1 or a composition thereof, an atomic ratio of In:M:Zn = 1:1:1.2 or a composition thereof, an atomic ratio of In:M:Zn = 1:1:2 or a composition thereof, or an atomic ratio of In:M:Zn = 4:2:3 or a composition thereof. Note that a composition having a similar atomic ratio includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M.

[0076] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0077] The oxide semiconductor 230 preferably has crystallinity. In particular, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide semiconductor 230.

[0078] The CAAC-OS preferably has multiple layered crystalline regions whose c-axes are oriented in the normal direction to the surface where the oxide semiconductor 230 is formed. For example, the oxide semiconductor 230 preferably has layered crystals that are substantially parallel to the sidewall of the opening 290, particularly to the side surface of the insulator 280. With this structure, the layered crystals of the oxide semiconductor 230 are formed substantially parallel to the channel length direction of the transistor 200, which enables the on-state current of the transistor to be increased.

[0079] CAAC-OS is a metal oxide having a highly crystalline and dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide is not polycrystallized after formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0080] Furthermore, since it is difficult to identify clear crystal boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to crystal boundaries is unlikely to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0081] Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide semiconductor 230, it is possible to reduce extraction of oxygen from the oxide semiconductor 230 by the source electrode or the drain electrode. Thus, even when heat treatment is performed, oxygen can be reduced from being extracted from the oxide semiconductor 230, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0082] The insulator 250 functions as a gate insulator. As the insulator 250, any of the insulators described in the "Insulators" section below can be used as a single layer or a stacked layer. For example, silicon oxide or silicon oxynitride can be used as the insulator 250. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.

[0083] Furthermore, an insulator with a high relative dielectric constant, a so-called high-k material, as described in the section <<Insulator>> below, may be used as the insulator 250. For example, hafnium oxide or aluminum oxide may be used.

[0084] The thickness of the insulator 250 is preferably 1 nm to 20 nm, more preferably 0.5 nm to 15 nm, and even more preferably 0.5 nm to 10 nm. The insulator 250 may have a region with the above thickness at least in part.

[0085] The concentration of impurities such as water and hydrogen in the insulator 250 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.

[0086] The conductor 260 functions as a gate electrode. The conductors described in the section "Conductors" below can be used as a single layer or a stacked layer as the conductor 260. For example, a conductive material with high conductivity, such as tungsten, can be used as the conductor 260.

[0087] Furthermore, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductor 260. Examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductor 260. Furthermore, the conductor 260 may have a layered structure, for example, a structure in which tungsten is layered on titanium nitride.

[0088] The conductor 260 is preferably provided so as to be embedded in the insulator 287. In this case, it is preferable that the height of the upper surface of the conductor 260 and the height of the upper surface of the insulator 287 are the same or approximately the same.

[0089] 1B and 1C, the conductor 260 is provided so as to fill the opening 290, but the present invention is not limited to this. For example, a recess that reflects the shape of the opening 290 may be formed in the center of the conductor 260. Alternatively, the recess may be filled with an inorganic insulating material or the like.

[0090] The conductor 120 functions as one of a source electrode and a drain electrode and also as an upper electrode of the capacitor 100. As the conductor 120, a conductor described in the section <<Conductor>> described later can be used in a single layer or a stacked layer.

[0091] Like the conductor 260, the conductor 120 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. Alternatively, for example, a structure in which tantalum nitride is stacked on titanium nitride may be used. In this case, the titanium nitride is in contact with the insulator 130, and the tantalum nitride is in contact with the oxide semiconductor 230.

[0092] The conductor 120 having the above structure can reduce excessive oxidation of the conductor 120 by the oxide semiconductor 230. Furthermore, when an oxide insulator is used for the insulator 130, excessive oxidation of the conductor 120 by the insulator 130 can be reduced.

[0093] 1B and 1C show a configuration in which the top surface of the conductor 120 is flattened, but the present invention is not limited to this. A configuration in which a recess overlapping the opening 290 is formed on the top surface of the conductor 120 may be used. By forming at least a part of the oxide semiconductor 230, the insulator 250, and the conductor 260 so as to fill the recess, it becomes easier to apply the gate electric field of the conductor 260 up to the vicinity of the conductor 120 of the oxide semiconductor 230.

[0094] The conductor 240 functions as the other of the source electrode and the drain electrode. The conductors described in the section <<Conductors>> below can be used as the conductor 240 in a single layer or a stacked layer. For example, the conductor 240 can be a conductive material with high conductivity, such as tungsten.

[0095] Similarly to the conductor 260, the conductor 240 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. With such a structure, excessive oxidation of the conductor 240 by the oxide semiconductor 230 can be reduced.

[0096] Alternatively, for example, a structure in which tungsten is stacked on titanium nitride may be used. By stacking tungsten in this manner, the conductivity of the conductor 240 can be improved, allowing the conductor 240 to function sufficiently as the wiring BL.

[0097] The conductor 240 is preferably provided so as to be embedded in the insulator 281. In this case, it is preferable that the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 are the same or approximately the same.

[0098] The conductor 265 functions as a wiring WL electrically connected to the gate of the transistor 200. The conductor 265 can be a single layer or a stacked layer of any of the conductors described in the <<Conductors>> section below. For example, the conductor 265 can be a conductive material with high conductivity, such as tungsten.

[0099] The conductor 265 is preferably provided so as to be embedded in the insulator 289. In this case, it is preferable that the height of the upper surface of the conductor 265 and the height of the upper surface of the insulator 289 are the same or approximately the same.

[0100] 1B, the side edge of the conductor 265 is roughly aligned with the side edge of the conductor 260, but the present invention is not limited to this. For example, the side edge of the conductor 265 may be positioned outside the side edge of the conductor 260, or may be positioned inside the side edge of the conductor 260.

[0101] The insulators 140, 280, 281, 285, 287, and 289 preferably have a low dielectric constant because they function as interlayer films. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. As the insulators 140, 280, 281, 285, 287, and 289, insulators with low dielectric constants, as described in the "Insulators" section below, can be used in a single layer or stacked layers. For example, silicon oxide, silicon oxynitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with vacancies, and the like can be used. Silicon oxide and silicon oxynitride are particularly preferred because of their thermal stability.

[0102] The concentrations of impurities such as water and hydrogen are preferably reduced in the insulators 140, 280, 281, 285, 287, and 289. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.

[0103] The insulator 280 disposed near the channel formation region preferably contains oxygen that is released by heating (hereinafter may be referred to as excess oxygen). By performing heat treatment on the insulator 280 containing excess oxygen, oxygen is supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, and oxygen vacancies and V Ｏ It is possible to reduce H. This makes it possible to stabilize the electrical characteristics of the transistor 200 and improve its reliability.

[0104] [Capacitor 100] The capacitor 100 includes a conductor 110, an insulator 130, and a conductor 120. The conductor 110 functions as one of a pair of electrodes (also referred to as a lower electrode) of the capacitor 100, the conductor 120 functions as the other of the pair of electrodes (also referred to as an upper electrode) of the capacitor 100, and the insulator 130 functions as a dielectric of the capacitor 100.

[0105] The conductor 110 is provided on the insulator 140. The conductor 110 functions as a wiring PL and can be provided extending in the Y direction, for example. The conductors described in the section <<Conductors>> below can be used as the conductor 110 in a single layer or a stacked layer. For example, a conductive material with high conductivity, such as tungsten, can be used as the conductor 110. By using such a conductive material with high conductivity, the conductivity of the conductor 110 can be improved, allowing it to function sufficiently as a wiring PL.

[0106] Furthermore, the conductor 110 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion, and is laminated. For example, a structure in which titanium nitride is laminated on tungsten may be used. By using such a structure, excessive oxidation of the conductor 110 by the insulator 130 can be reduced.

[0107] The insulator 130 is provided on the conductor 110. It is preferable that the insulator 130 be made of a high dielectric constant (high-k) material (a material with a high relative dielectric constant).

[0108] The high-dielectric-constant (high-k) insulator may be an oxide, oxynitride, oxynitride, or nitride containing one or more metal elements selected from aluminum, hafnium, zirconium, gallium, etc. Silicon may also be contained in the oxide, oxynitride, oxynitride, or nitride. Insulating layers made of the above materials may also be stacked.

[0109] For example, examples of high-dielectric-constant (high-k) insulators that can be used include aluminum oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, oxides containing silicon and zirconium, oxynitrides containing silicon and zirconium, oxides containing hafnium and zirconium, oxynitrides containing hafnium and zirconium, etc. Using such high-k materials makes it possible to thicken the insulator 130 to a degree that can suppress leakage current and ensure sufficient capacitance of the capacitor element 100.

[0110] It is also preferable to use a laminated insulating layer made of the above materials, and it is preferable to use a laminated structure of a high-dielectric constant (high-k) material and a material having a higher dielectric strength than the high-dielectric constant (high-k) material. For example, an insulating film formed by laminating zirconium oxide, aluminum oxide, and zirconium oxide in this order can be used as the insulator 130. Alternatively, for example, an insulating film formed by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order can be used. Alternatively, for example, an insulating film formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order can be used. By using a laminated insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0111] Alternatively, the side edge of the conductor 110 may be substantially aligned with the side edge of the insulator 130. By adopting such a structure, the conductor 110 and the insulator 130 can be formed using the same mask, thereby simplifying the manufacturing process of the memory device.

[0112] Alternatively, the insulator 130 may be configured to cover the side end of the conductor 110. This can prevent the conductor 110 and the conductor 120 from shorting out.

[0113] The conductor 120 may be provided as described in the section on [Transistor 200]. Here, since the capacitance of the capacitor 100 depends on the area of ​​the conductor 120, the area of ​​the island-shaped conductor 120 may be appropriately set according to the design value of the capacitor 100. For example, the capacitance of the capacitor 100 can be increased by increasing the area of ​​the island-shaped conductor 120. In this way, by increasing the capacitance per unit area of ​​the capacitor 100, the read operation of the memory device can be stabilized.

[0114] <Constituent Materials of Storage Device> Constituent materials that can be used for the storage device will be described below.

[0115] <<Substrate>> The substrate on which the transistor 200 and the capacitor 100 are formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates containing metal nitrides and substrates containing metal oxides. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or an insulator is provided on a conductive substrate. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0116] <<Insulator>> Examples of insulators include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0117] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select a material depending on the function of the insulator.

[0118] Examples of insulators with a high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0119] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or resin.

[0120] The insulator functioning as the gate insulator preferably has a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide semiconductor 230, oxygen vacancies in the oxide semiconductor 230 can be compensated for.

[0121] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0122] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0123] <<Metal Oxide>> A metal oxide (oxide semiconductor) that functions as a semiconductor is preferably used as the oxide semiconductor 230. In the following, the above description can be referred to for metal oxides that can be used for the oxide semiconductor 230 according to the present invention.

[0124] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0125] Hereinafter, an oxide containing indium (In), gallium (Ga), and zinc (Zn) will be described as an example of a metal oxide. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) may be referred to as an In—Ga—Zn oxide.

[0126] <Classification of Crystal Structure> Examples of the crystal structure of an oxide semiconductor include amorphous (including completely amorphous), c-axis-aligned crystalline (CAAC), nanocrystalline (nc), single crystal, and polycrystalline.

[0127] The crystalline structure of a film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, it can be evaluated using an XRD spectrum obtained by GIXD (Grazing-Incident XRD) measurement. The GIXD method is also called the thin film method or the Seemann-Bohlin method. In the following, the XRD spectrum obtained by GIXD measurement may be simply referred to as the XRD spectrum.

[0128] For example, in the case of a quartz glass substrate, the peak shape of the XRD spectrum is almost symmetrical. On the other hand, in the case of an In-Ga-Zn oxide film having a crystalline structure, the peak shape of the XRD spectrum is asymmetrical. The asymmetrical peak shape of the XRD spectrum clearly indicates the presence of crystals in the film or substrate. In other words, if the peak shape of the XRD spectrum is not symmetrical, the film or substrate cannot be said to be in an amorphous state.

[0129] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, confirming that the quartz glass is in an amorphous state. Furthermore, a spot-like pattern is observed in the diffraction pattern of an In—Ga—Zn oxide film formed at room temperature, rather than a halo. For this reason, it is estimated that the In—Ga—Zn oxide formed at room temperature is neither single crystal nor polycrystalline, nor in an amorphous state, but is in an intermediate state, and it cannot be concluded that it is in an amorphous state.

[0130] <<Structure of Oxide Semiconductor>> Note that oxide semiconductors may be classified differently from the above when focusing on their structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0131] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0132] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0133] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the maximum diameter of the crystalline region may be several tens of nanometers.

[0134] In an In—Ga—Zn oxide, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing gallium (Ga), zinc (Zn), and oxygen (hereinafter referred to as a (Ga, Zn) layer) are stacked. Note that indium and gallium are mutually substituted. Therefore, the (Ga, Zn) layer may contain indium. The In layer may contain gallium. The In layer may contain zinc. The layered structure is observed as a lattice image in a high-resolution transmission electron microscope (TEM) image, for example.

[0135] When a CAAC-OS film is subjected to structural analysis using an XRD apparatus, for example, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0136] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film, and the spots are observed at positions that are point-symmetric with respect to a spot of an incident electron beam that has passed through the sample (also referred to as a direct spot).

[0137] When a crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundary can be identified even near the distortion. This indicates that the distortion in the lattice arrangement suppresses the formation of grain boundaries. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the a-b plane and the change in interatomic bond distance caused by metal atom substitution.

[0138] Note that a crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, and are likely to trap carriers, resulting in a decrease in the on-state current of a transistor and a decrease in field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that a structure containing Zn is preferable for forming a CAAC-OS. For example, In—Zn oxide and In—Ga—Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0139] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities, the formation of defects, or the like, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor having the CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having the CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using the CAAC-OS in a transistor having a metal oxide in a channel formation region (sometimes referred to as an OS transistor) can increase the flexibility of the manufacturing process.

[0140] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scanning. When an nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than that of a nanocrystal (e.g., 1 nm to 30 nm), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0141] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0142] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0143] <Transistor Having Oxide Semiconductor> By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0144] For a channel formation region of a transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of an oxide semiconductor is 1×10 １７ cm −３ Below 1 × 10, preferably １５ cm −３ More preferably, 1×10 １３ cm −３ or less, more preferably 1 × 10 １１ cm −３ More preferably, 1×10 １０ cm −３ is less than 1×10 −９ cm −３ Note that in order to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states.

[0145] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0146] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0147] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0148] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0149] When an oxide semiconductor contains silicon or carbon, which is one of Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) is set to 2×10 １８ atoms / cm ３ Below 2 × 10, preferably １７ atoms / cm ３ The following applies.

[0150] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0151] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 １９ atoms / cm ３ Less than 5×10 １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ Do the following:

[0152] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor obtained by SIMS is measured to be 1×10 ２０ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Make it less than.

[0153] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0154] <<Other Semiconductor Materials>> The semiconductor material that can be used for the oxide semiconductor 230 is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the oxide semiconductor 230. For example, a semiconductor of an element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, or the like) is preferably used as the semiconductor material. In particular, a layered material that functions as a semiconductor is preferably used as the semiconductor material.

[0155] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0156] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0157] For example, a transition metal chalcogenide that functions as a semiconductor is preferably used as the oxide semiconductor 230. Specific examples of transition metal chalcogenides that can be used as the oxide semiconductor 230 include molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ By applying the above-described transition metal chalcogenide to the oxide semiconductor 230, a memory device with a large on-state current can be provided.

[0158] <Example of Manufacturing Method of Memory Device> Next, a manufacturing method of the memory device of one embodiment of the present invention illustrated in FIGS. 1A to 1D will be described with reference to FIGS. 2A to 8C.

[0159] A in each figure shows a plan view. B in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in A of each figure. C in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in A of each figure. Note that in the plan view A in each figure, some elements are omitted for clarity.

[0160] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0161] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0162] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0163] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that does not use plasma and can reduce plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a memory device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the memory device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of memory devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0164] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0165] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0166] Furthermore, in the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the raw material gases. For example, in the CVD method, by changing the flow rate ratio of the raw material gases while forming a film, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers, since no time is required for transport or pressure adjustment. Therefore, the productivity of memory devices can be improved in some cases.

[0167] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0168] First, a substrate (not shown) is prepared, and an insulator 140 is formed over the substrate (see FIGS. 2A to 2C). The insulating material described above may be used as appropriate for the insulator 140. The insulator 140 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.

[0169] Next, the conductor 110 is formed on the insulator 140. The above-mentioned conductive material may be used as appropriate for the conductor 110. The conductor 110 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, the conductor 110 may be formed as a stacked film in which tungsten and titanium nitride are deposited in this order using a CVD method.

[0170] The conductor 110 may be processed to have a shape extending in the X direction or the Y direction. The conductor 110 may be processed by lithography. The processing may be performed by dry etching or wet etching. The dry etching method is suitable for microfabrication.

[0171] Next, the insulator 130 is formed on the conductor 110. The insulator 130 may be formed using any of the above-mentioned high-k materials as appropriate. The insulator 130 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, the insulator 130 may be formed by using an ALD method to form a stacked film in which zirconium oxide, aluminum oxide, and zirconium oxide are deposited in this order.

[0172] Next, a conductive film that becomes the conductor 120 is formed on the insulator 130. The conductive film that becomes the conductor 120 may be formed using any of the conductive materials described above as appropriate. The conductive film that becomes the conductor 120 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, the conductive film that becomes the conductor 120 may be formed by a CVD method to have a stacked film in which titanium nitride and tantalum nitride are deposited in this order.

[0173] Next, the conductive film that will become the conductor 120 is processed to form the conductor 120 (see FIGS. 2A to 2C). The conductor 120 may be formed using lithography. The above processing may be performed using dry etching or wet etching. Processing using dry etching is suitable for microfabrication. Here, the conductor 120 may be formed in an island shape. Since the capacitance of the capacitor 100 depends on the area of ​​the conductor 120, the area of ​​the island-shaped conductor 120 may be appropriately set in accordance with the design value of the capacitor 100.

[0174] In this manner, the capacitor 100 including the conductor 110, the insulator 130, and the conductor 120 can be formed.

[0175] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. Then, etching is performed through the resist mask to process a conductor, semiconductor, or insulator into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or ion beam may also be used instead of the light described above. When an electron beam or ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0176] Furthermore, a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes can be used as the dry etching apparatus. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

[0177] Next, the insulator 280 is formed over the insulator 130 and the conductor 120 (see FIGS. 3A to 3C ). The insulator 280 may be formed using any of the insulating materials described above as appropriate. The insulator 280 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, the insulator 280 may be formed as a silicon oxide film by a sputtering method. Note that the insulator 280 is preferably planarized by performing CMP (Chemical Mechanical Polishing) treatment after the formation thereof.

[0178] Here, since the thickness of the insulator 280 on the conductor 120 corresponds to the channel length of the transistor 200 , the thickness of the insulator 280 can be set appropriately according to the design value of the channel length of the transistor 200 .

[0179] Furthermore, the insulator 280 containing excess oxygen can be formed by depositing the insulator 280 by a sputtering method in an atmosphere containing oxygen. Furthermore, by using a sputtering method in which hydrogen-containing molecules are not used as a deposition gas, the hydrogen concentration in the insulator 280 can be reduced. By depositing the insulator 280 in this manner, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, thereby reducing oxygen vacancies and VoH.

[0180] Next, the insulator 281 is formed over the insulator 280. As with the insulator 280, the insulator 281 may be formed using any of the insulating materials described above as appropriate. The insulator 281 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, a silicon oxide film may be formed by a sputtering method as the insulator 281. Note that the insulator 281 is preferably planarized by performing CMP treatment after the formation thereof.

[0181] Next, a groove-shaped opening is formed in the insulator 281, reaching the insulator 280 (see FIGS. 3A to 3C). The conductor 240, which functions as a wiring, is formed in the opening, so the opening may be provided to extend in the X direction. The opening may be formed by lithography. Furthermore, dry etching or wet etching may be used for etching the opening. Processing by dry etching is suitable for microfabrication.

[0182] The insulator 280 may have a layered structure, and an insulator that functions as an etching stopper film may be provided on the top surface of the insulator 280. For example, when silicon oxide or silicon oxynitride is used for the insulator 281 that forms the groove, silicon nitride, aluminum oxide, hafnium oxide, or the like may be used as the etching stopper film.

[0183] Next, a conductive film that becomes the conductor 240 is formed so as to fill the opening of the insulator 281. The conductive film that becomes the conductor 240 may be formed using any of the conductive materials described above as appropriate. The conductive film that becomes the conductor 240 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, the conductive film that becomes the conductor 240 may be formed by using a sputtering method to form a stacked film in which tantalum nitride and tungsten are deposited in this order.

[0184] Next, a portion of the conductive film on the insulator 281 that will become the conductor 240 is removed to form the conductor 240 in the opening of the insulator 281 (see FIGS. 3A to 3C). The conductor 240 can be formed by performing CMP treatment on the conductive film that will become the conductor 240 until the top surface of the insulator 281 is exposed.

[0185] Next, the insulator 285 is formed over the conductor 240 and the insulator 281. As with the insulator 280, the insulator 285 may be formed using any of the insulating materials described above as appropriate. The insulator 285 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, the insulator 285 may be formed as a silicon oxide film by a sputtering method. Note that the insulator 285 is preferably planarized by performing CMP treatment after the formation thereof.

[0186] Next, a portion of the insulator 285, a portion of the conductor 240, and a portion of the insulator 280 are processed to form an opening 290 that reaches the conductor 120 (see FIGS. 4A to 4C ). The opening 290 may be formed using lithography. Note that, although the shape of the opening 290 in FIG. 4A is circular in plan view, this is not limiting. For example, the opening may have a substantially circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners in plan view.

[0187] The width of the opening 290 is preferably very small. For example, the width of the opening 290 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and is preferably 1 nm or more, or 5 nm or more. In this way, to process the opening 290 very finely, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.

[0188] Because the opening 290 has a large aspect ratio, it is preferable to use anisotropic etching to process a portion of the insulator 285, a portion of the conductor 240, and a portion of the insulator 280. In particular, processing by dry etching is preferable because it is suitable for fine processing. Furthermore, the processing may be performed under different conditions.

[0189] Subsequently, heat treatment may be performed. The heat treatment may be performed at a temperature of 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be approximately 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, and then in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher to compensate for desorbed oxygen. By performing the above heat treatment, impurities such as water contained in the insulator 280 or the like can be reduced before the formation of the oxide semiconductor film 230A described later.

[0190] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into the insulator 280, etc., as much as possible.

[0191] Next, an oxide semiconductor film 230A is formed in contact with the bottom surface and inner wall of the opening 290 (see FIGS. 5A to 5C ). The oxide semiconductor film 230A may be formed using any of the metal oxides that can be used for the oxide semiconductor 230 described above. The oxide semiconductor film 230A may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide semiconductor film 230A is preferably formed in contact with the bottom surface and inner wall of the opening 290, which has a large aspect ratio. Therefore, the oxide semiconductor film 230A is preferably formed using a film formation method with good coverage, and more preferably using a CVD method or an ALD method. For example, an In—Ga—Zn oxide film may be formed as the oxide semiconductor film 230A by an ALD method. Details of the metal oxide film formation method using the ALD method will be described in a later embodiment.

[0192] Here, the oxide semiconductor film 230A is preferably formed in contact with the top surface of the conductor 120, the side surface of the insulator 280, the side surface of the conductor 240, the side surface of the insulator 285, and the top surface of the insulator 285. When the oxide semiconductor film 230A is formed in contact with the conductor 120, the conductor 120 functions as one of the source electrode and the drain electrode of the transistor 200. When the oxide semiconductor film 230A is formed in contact with the conductor 240, the conductor 240 functions as the other of the source electrode and the drain electrode of the transistor 200.

[0193] Next, the insulating film 250A is formed in contact with the top surface of the oxide semiconductor film 230A (see FIGS. 5A to 5C ). The insulating film 250A may be formed using any of the above-described insulating materials as appropriate. The insulating film 250A may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. The insulating film 250A is preferably formed in contact with the oxide semiconductor film 230A provided inside the opening 290 with a large aspect ratio. Therefore, the insulating film 250A is preferably formed using a film formation method with good coverage, and more preferably using a CVD method, an ALD method, or the like. For example, the insulating film 250A may be formed using silicon oxide by an ALD method.

[0194] Here, the insulating film 250A is preferably formed successively from the formation of the oxide semiconductor film 230A without exposure to the air. For example, a multi-chamber film formation apparatus may be used. This can reduce the incorporation of impurities such as hydrogen into the oxide semiconductor film 230A and the insulating film 250A between film formation steps.

[0195] Next, heat treatment is preferably performed. The heat treatment may be performed at a temperature range in which the oxide semiconductor film 230A does not become polycrystallized, such as 250° C. to 650° C., preferably 400° C. to 600° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, and then in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for desorbed oxygen.

[0196] The gas used in the heat treatment is preferably highly purified. For example, the gas used in the heat treatment may contain moisture of 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor film 230A and the like as much as possible.

[0197] Here, the heat treatment is preferably performed in a state where the insulator 280 containing excess oxygen is in contact with the oxide semiconductor film 230A. By performing the heat treatment in this manner, oxygen can be supplied from the insulator 280 to a channel formation region of the oxide semiconductor 230, thereby reducing oxygen vacancies and VoH.

[0198] In the above description, the heat treatment is performed after the insulating film 250A is formed, but the present invention is not limited to this. The heat treatment may be performed in a later step.

[0199] Next, the oxide semiconductor film 230A and the insulating film 250A are processed by lithography to form the oxide semiconductor 230 and the insulator 250 (see FIGS. 6A to 6C ). As a result, part of the oxide semiconductor 230 is formed over the opening 290 and is in contact with part of the top surface of the insulator 285. In addition, part of the insulator 250 is formed over the opening 290. By forming the oxide semiconductor 230 and the insulator 250 together in this manner, as shown in FIG. 6A , the side edges of the oxide semiconductor 230 and the insulator 250 roughly coincide with each other in a plan view. With this structure, the oxide semiconductor 230 and the insulator 250 can be formed using the same mask, which simplifies the manufacturing process of the memory device.

[0200] In the above description, the oxide semiconductor 230 and the insulator 250 are formed together after the oxide semiconductor film 230A and the insulating film 250A have been formed, but the present invention is not limited to this. For example, the insulating film 250A may be formed after the oxide semiconductor 230 is formed. In this case, the side edge of the oxide semiconductor 230 is covered with the insulating film 250A, which can prevent a short circuit between the oxide semiconductor 230 and the conductor 260.

[0201] Next, a conductive film that becomes the conductor 260 is formed so as to fill the recessed portion of the insulator 250. The conductive film that becomes the conductor 260 may be formed using any of the conductive materials described above as appropriate. The conductive film that becomes the conductor 260 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. Here, the conductive film that becomes the conductor 260 is preferably formed in contact with the insulator 250 provided inside the opening 290 with a large aspect ratio. Therefore, the conductive film that becomes the conductor 260 is preferably formed using a film formation method that has good coverage or embedding properties, and more preferably using a CVD method, an ALD method, or the like. For example, the conductive film that becomes the conductor 260 may be formed using a CVD method or an ALD method to form a titanium nitride film.

[0202] When the conductive film to be the conductor 260 is formed by a CVD method, the average surface roughness of the upper surface of the conductive film to be the conductor 260 may become large. In this case, it is preferable to planarize the conductive film to be the conductor 260 by a CMP method. At this time, before performing the CMP treatment, a silicon oxide film or a silicon oxynitride film may be formed on the conductive film to be the conductor 260, and the CMP treatment may be performed until the silicon oxide film or the silicon oxynitride film is removed.

[0203] In the above description, the conductive film that will become the conductor 260 is provided so as to fill the opening 290, but the present invention is not limited to this. For example, a recess that reflects the shape of the opening 290 may be formed in the center of the conductive film that will become the conductor 260. Alternatively, the recess may be filled with an inorganic insulating material or the like.

[0204] Next, the conductive film that will become the conductor 260 is processed to form the conductor 260 (see FIGS. 7A to 7C). The conductor 260 may be formed by lithography. The above processing can be performed by dry etching or wet etching. Processing by dry etching is suitable for fine processing.

[0205] 7A , the side edge of the conductor 260 is preferably located inside the side edge of the oxide semiconductor 230 and the side edge of the insulator 250 in plan view, which can prevent the conductor 260 and the oxide semiconductor 230 from shorting out.

[0206] In this manner, the transistor 200 including the conductor 120, the conductor 240, the oxide semiconductor 230, the insulator 250, and the conductor 260 can be formed.

[0207] Note that in the above description, the oxide semiconductor film 230A and the insulating film 250A are formed, and then the oxide semiconductor 230 and the insulator 250 are formed, and then the conductive film that becomes the conductor 260 is formed. However, the present invention is not limited to this. For example, the oxide semiconductor film 230A, the insulating film 250A, and the conductive film that becomes the conductor 260 may be successively formed, and then the oxide semiconductor 230, the insulator 250, and the conductor 260 may be patterned. In this case, it is preferable that after the oxide semiconductor 230, the insulator 250, and the conductor 260 are formed by photolithography, another photolithography step is performed to process the conductor 260 so that the side edge of the conductor 260 is located inside the oxide semiconductor 230 and the insulator 250.

[0208] Next, an insulating film to be the insulator 287 is formed to cover the conductor 260, the insulator 250, the oxide semiconductor 230, and the insulator 285. The insulating film to be the insulator 287 may be formed using any of the above-described insulating materials as appropriate, similar to the insulator 280. The insulating film to be the insulator 287 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, a silicon oxide film may be formed by a sputtering method as the insulating film to be the insulator 287.

[0209] Next, the insulating film to be the insulator 287 is subjected to CMP treatment to form the insulator 287 (see FIGS. 8A to 8C). The CMP treatment may be performed until the top surface of the conductor 260 is exposed. At this time, it is preferable that the height of the top surface of the conductor 260 and the height of the top surface of the insulator 287 are the same or approximately the same.

[0210] Next, an insulator 289 is formed over the insulator 287 and the conductor 260. As with the insulator 280, the insulator 289 may be formed using any of the insulating materials described above as appropriate. The insulator 289 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, a silicon oxide film may be formed by a sputtering method as the insulator 289. Note that the insulator 289 is preferably planarized by performing CMP treatment after the formation thereof.

[0211] Next, a groove-shaped opening is formed in the insulator 289, reaching the conductor 260 and the insulator 287 (see FIGS. 1A to 1C). The conductor 265, which functions as a wiring, is formed in the opening, so the opening may be provided extending in the Y direction. The opening may be formed by lithography. Furthermore, dry etching or wet etching can be used for etching the opening. Processing by dry etching is suitable for microfabrication.

[0212] Next, a conductive film to be the conductor 265 is formed so as to fill the opening of the insulator 289. The conductive film to be the conductor 265 may be formed using any of the above-mentioned conductive materials as appropriate. The conductive film to be the conductor 265 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, the conductive film to be the conductor 265 may be formed by a CVD method as a stacked film in which titanium nitride and tungsten are deposited in this order.

[0213] Next, a portion of the conductive film on the insulator 289 that will become the conductor 265 is removed to form the conductor 265 in the opening of the insulator 289 (see FIGS. 1A to 1C). The conductor 265 can be formed by performing CMP treatment on the conductive film that will become the conductor 265 until the top surface of the insulator 289 is exposed.

[0214] Through the above steps, a memory device including the transistor 200 and the capacitor 100 shown in FIGS. 1A to 1D can be manufactured.

[0215] <Modification of Storage Device> An example of a storage device according to one embodiment of the present invention will be described below with reference to FIGS.

[0216] The memory device shown in Figures 9A to 9C is a modified example of the memory device shown in Figures 1A to 1D. Figures 9A to 9C correspond to Figures 1B to 1D, and in the memory device shown in Figure 9, structures having the same functions as the structures constituting the memory device shown in Figure 1 are denoted by the same reference numerals. Note that in this section as well, the materials described in detail in <Configuration example of memory device> can be used as the constituent materials of the memory device.

[0217] 9A to 9C differs from the memory device shown in Figures 1A to 1D in that it includes an insulator 254. The insulator 254 functions as a gate insulator together with the insulator 250.

[0218] The insulator 254 is provided between the insulator 250 and the conductor 260. The insulator 254 is preferably provided to cover the side end portions of the oxide semiconductor 230 and the side end portions of the insulator 250. In this case, the insulator 254 is preferably in contact with the top surface and side surface of the insulator 250, the side surface of the oxide semiconductor 230, the top surface of the insulator 285, the bottom surface of the conductor 260, and the bottom surface of the insulator 287.

[0219] The insulator 254 preferably has a barrier property against oxygen. Furthermore, the insulator 254 more preferably has a barrier property against hydrogen. Such an insulator may be an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum, and may be used in a single layer or a stacked layer. Specifically, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, indium gallium zinc oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate), as well as metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride, may be used.

[0220] In this specification and the like, the term "barrier property" refers to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability), or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0221] The insulator 254 has a barrier property against oxygen, which can prevent oxygen contained in the insulator 250 and the channel formation region of the oxide semiconductor 230 from diffusing to the conductor 260 and thereby prevent oxygen vacancies from being formed in the channel formation region of the oxide semiconductor 230. Furthermore, the insulator 254 can prevent oxygen contained in the insulator 250 and the channel formation region of the oxide semiconductor 230 from diffusing to the conductor 260 and thereby prevent the conductor 260 from being oxidized. Here, the insulator 254 is required to be at least less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride formed by a PEALD method as the insulator 254.

[0222] Furthermore, since the insulator 254 has a barrier property against hydrogen, diffusion of impurities such as hydrogen from layers above the insulator 254 into the channel formation region of the oxide semiconductor 230 can be reduced. Ｏ It is possible to reduce H. This makes it possible to stabilize the electrical characteristics of the transistor 200 and improve its reliability.

[0223] The above-described insulator having a barrier property against at least one of oxygen and hydrogen (hereinafter sometimes referred to as a barrier insulating film) may be stacked on one or more of the insulators 140, 280, 281, 285, 287, and 289, which function as interlayer films. For example, the barrier insulating film may be provided on the lower surface of the insulator 280. In this case, the barrier insulating film is provided in contact with the upper surface of the insulator 130, the upper surface of the conductor 120, and the side surface of the conductor 120. Alternatively, the barrier insulating film may be provided on the upper surface of the insulator 140. In this case, the barrier insulating film is provided in contact with the lower surface of the conductor 110. Providing the barrier insulating film in this manner can reduce diffusion of impurities such as hydrogen from layers below the insulator 140 into the channel formation region of the oxide semiconductor 230.

[0224] According to one embodiment of the present invention, a novel transistor, a novel semiconductor device, and a novel memory device can be provided. Alternatively, a memory device that can be miniaturized or highly integrated can be provided. Alternatively, a memory device with favorable frequency characteristics can be provided. Alternatively, a memory device with high operating speed can be provided. Alternatively, a memory device with favorable reliability can be provided. Alternatively, a memory device with low power consumption can be provided. Alternatively, a memory device including a transistor with large on-state current can be provided. Alternatively, a memory device with little variation in transistor characteristics can be provided. Alternatively, a memory device with favorable electrical characteristics can be provided.

[0225] The memory cell 150 including the transistor 200 and the capacitor 100 described in this embodiment can be used as a memory cell of a storage device. The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 200 has a low off-state current; therefore, when used in a storage device, the stored data can be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the storage device can be sufficiently reduced. Furthermore, the high frequency characteristics of the transistor 200 enable high-speed reading and writing of data from and to the storage device.

[0226] 10A and 10B will be used to explain an example of a memory device in which two memory cells 150 (hereinafter referred to as memory cell 150a and memory cell 150b) are connected to a common wiring. FIG. 10A is a plan view of the memory device. FIG. 10B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in FIG. 10A. Note that some elements are omitted from the plan view of FIG. 10A for clarity.

[0227] 10A and 10B have the same configuration as the memory cell 150. The memory cell 150a includes a capacitor 100a and a transistor 200a, and the memory cell 150b includes a capacitor 100b and a transistor 200b. Therefore, in the memory device shown in FIGS. 10A and 10B, structures having the same functions as those of the structures constituting the memory device shown in FIG. 1 are denoted by the same reference numerals. Note that, in this section as well, the materials described in detail in <Structural Example of Memory Device> can be used as materials constituting the memory device.

[0228] 10A and 10B , a conductor 265 functioning as a wiring WL is provided in each of the memory cells 150a and 150b. A conductor 240 functioning as part of a wiring BL is provided in common to the memory cells 150a and 150b. That is, the conductor 240 is in contact with the oxide semiconductor 230 in the memory cell 150a and the oxide semiconductor 230 in the memory cell 150b.

[0229] 10A and 10B includes conductors 245 and 246 that are electrically connected to the memory cell 150a and the memory cell 150b and function as plugs (which can also be called connection electrodes). The conductor 245 is disposed in openings formed in the insulators 280 and 140 and contacts the bottom surface of the conductor 240. The conductor 246 is disposed in openings formed in the insulators 289, 287, and 285 and contacts the top surface of the conductor 240. Note that the conductors 245 and 246 can be made of a conductive material that can be used for the conductor 240.

[0230] Here, the conductor 245 and the conductor 246 function as plugs or wirings for electrically connecting circuit elements, wirings, electrodes, or terminals such as switches, transistors, capacitors, inductors, resistors, and diodes to the memory cells 150a and 150b. For example, a configuration can be used in which the conductor 245 is electrically connected to a sense amplifier provided below the memory device shown in FIG. 10, and the conductor 246 is electrically connected to a similar memory device provided above the memory device shown in FIG. 10. In this case, the conductors 245 and 246 function as part of the wiring BL. In this way, by providing a memory device above or below the memory device shown in FIG. 10, the memory capacity per unit area can be increased.

[0231] Furthermore, the memory cell 150a and the memory cell 150b are configured to be line-symmetrical with respect to the perpendicular bisector of the dashed-dotted line A1-A2 as the axis of symmetry. Therefore, the transistors 200a and 200b are also arranged in line-symmetrical positions with the conductors 245 and 246 sandwiched between them. Here, the conductor 240 serves as both the source electrode and the drain electrode of the transistor 200a and the source electrode and the drain electrode of the transistor 200b. The transistors 200a and 200b also share the conductors 245 and 246, which function as plugs. By configuring the connections between the two transistors and the plugs as described above, a memory device that can be miniaturized or highly integrated can be provided.

[0232] Note that the conductor 110 functioning as the wiring PL may be provided in each of the memory cells 150 a and 150 b, or may be provided in common to the memory cells 150 a and 150 b. However, as shown in FIG. 10B , the conductor 110 is provided apart from the conductor 245 to prevent the conductor 110 and the conductor 245 from shorting out.

[0233] Furthermore, a memory cell array can be configured by arranging the memory cells 150 in a three-dimensional matrix. As an example of a memory cell array, FIGS. 11A and 11B show an example of a memory device in which 4×2×2 memory cells 150 are arranged in the X, Y, and Z directions. FIG. 11A is a plan view of the memory device. FIG. 11B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in FIG. 11A. Note that some elements have been omitted from the plan view of FIG. 11A for clarity.

[0234] 11A and 11B have the same configuration as the memory cell 150. The memory cell 150a includes a capacitor 100a and a transistor 200a, the memory cell 150b includes a capacitor 100b and a transistor 200b, the memory cell 150c includes a capacitor 100c and a transistor 200c, and the memory cell 150d includes a capacitor 100d and a transistor 200d. Therefore, in the memory device shown in FIGS. 11A and 11B, structures having the same functions as those of the structures constituting the memory device shown in FIG. 1 are denoted by the same reference numerals. Note that, in this section, the materials described in detail in <Structural Example of Memory Device> can also be used as materials constituting the memory device.

[0235] Hereinafter, a memory device consisting of memory cells 150a to 150d will be referred to as a memory unit. The memory device shown in Figures 11A and 11B has memory units 160a to 160d. Note that, below, memory units 160a to 160d may be collectively referred to as memory units 160. Memory unit 160b is provided on memory unit 160a. Memory unit 160c is provided adjacent to memory unit 160a in the y-axis direction. Memory unit 160d is provided on memory unit 160c.

[0236] 11B, memory unit 160 has memory cell 150c arranged outside memory cell 150a and memory cell 150d arranged outside memory cell 150b, with conductor 245 at the center. In other words, it can be said that this is a memory device in which memory cell 150c is provided adjacent to memory cell 150a and memory cell 150d is provided adjacent to memory cell 150b in the memory device shown in FIG.

[0237] 11A and 11B , the conductor 265 functioning as the wiring WL is shared by the memory cells 150 adjacent in the Y direction. The conductor 240 functioning as part of the wiring BL is shared within the same memory unit. The conductor 240 is provided in common to the memory cells 150a to 150d. That is, the conductor 240 is in contact with the oxide semiconductor 230 of each of the memory cells 150a to 150d.

[0238] A conductor 245 is provided between the conductors 240 of memory units adjacent in the Z-axis direction. For example, as shown in FIG. 11B , the conductor 245 is provided in contact with the upper surface of the conductor 240 of memory unit 160a and the lower surface of the conductor 240 of memory unit 160b. In this manner, the conductors 240 and 245 provided in each memory unit 160 form a wiring BL. The conductor 245 is electrically connected to a sense amplifier provided below the memory device shown in FIG. 11 . In this manner, by stacking multiple memory units in the memory device shown in FIG. 11 , the memory capacity per unit area can be increased.

[0239] The memory cells 150a and 150c and the memory cells 150b and 150d are configured to be line-symmetric with respect to the perpendicular bisector of the dashed-dotted line A1-A2. Therefore, the transistors 200a and 200c and the transistors 200b and 200d are also arranged line-symmetrically with respect to the conductor 245. The conductor 240 serves as one of the source electrode and the drain electrode of each of the transistors 200a to 200d. The transistors 200a to 200d share the conductor 245, which functions as a plug. By configuring the connections between the four transistors and the plugs as described above, a memory device that can be miniaturized or highly integrated can be provided.

[0240] 11, by stacking a plurality of memory cells, it is possible to integrate and arrange the cells without increasing the area occupied by the memory cell array, that is, it is possible to configure a 3D memory cell array.

[0241] The memory device having a 3D memory cell array will be described in detail in a later embodiment.

[0242] At least part of the structures, methods, and the like described in this embodiment can be implemented in appropriate combination with other embodiment modes described in this specification.

[0243] Embodiment 2 In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor or oxide) that can be used for a semiconductor layer of a transistor in the memory device described in the above embodiment and a method for forming the metal oxide will be described with reference to FIGS.

[0244] In a semiconductor device according to one embodiment of the present invention, a metal oxide having high crystallinity is preferably used for the metal oxide including the channel formation region. Furthermore, the crystal preferably has a crystal structure in which multiple layers (e.g., a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also referred to as a layered crystal or a layered structure). In this case, the c-axis of the crystal is oriented in the direction in which the multiple layers are stacked.

[0245] To form the metal oxide having the layered crystal structure, it is preferable to deposit atoms layer by layer, for example, ALD (Atomic Layer Deposition) can be used as a method for forming the metal oxide.

[0246] The ALD method utilizes the self-regulating properties of precursor molecules or atoms contained in the precursor to deposit atoms layer by layer, thereby enabling the formation of ultrathin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. The ALD method also includes thermal ALD, a film formation method that utilizes heat, and plasma-enhanced ALD (PEALD), a film formation method that utilizes plasma. The use of plasma may enable film formation at lower temperatures, which may be preferable. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be determined by X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry.

[0247] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0248] <Method for forming a metal oxide film by an ALD method> Here, a method for forming a metal oxide film by an ALD method, which can be used in one embodiment of the present invention, will be described.

[0249] Here, an example of a method for forming a metal oxide film having a three-layered crystal structure using the ALD method will be described with reference to FIGS. 12A to 12E . First, a precursor 611a is introduced into a chamber and adsorbed onto the surface of a substrate 610 (see FIG. 12A ; hereinafter, this process may be referred to as the first step). As shown in FIG. 12A , the adsorption of the precursor 611a onto the surface of the substrate 610 activates a self-limiting mechanism for the surface chemical reaction, preventing further adsorption of the precursor 611a onto the layer of the precursor 611a on the substrate 610. The appropriate substrate temperature range within which the self-limiting mechanism for the surface chemical reaction operates is also referred to as the ALD window. The ALD window is determined by the temperature characteristics, vapor pressure, decomposition temperature, etc. of the precursor, and may be, for example, 100° C. to 600° C., preferably 200° C. to 400° C.

[0250] Next, an inert gas (argon, helium, nitrogen, or the like) is introduced into the chamber to evacuate the excess precursor 611a and reaction products from the chamber (hereinafter, this step may be referred to as the second step). Alternatively, instead of introducing an inert gas into the chamber, the excess precursor and reaction products may be evacuated from the chamber by vacuum evacuation. The second step is also called purging.

[0251] Next, reactant 612a (e.g., oxidant (ozone (O ３ ), oxygen (O ２ ), water (H ２ O), and their plasma, radicals, ions, etc.) are introduced into the chamber and reacted with precursor 611a adsorbed on the surface of substrate 610, causing some of the components contained in precursor 611a to be desorbed while leaving the constituent molecules of precursor 611a adsorbed on substrate 610 (see FIG. 12B ; hereinafter, this step may be referred to as the third step). As a result, a layer of oxide 613a formed by oxidizing part of precursor 611a is formed on the surface of substrate 610.

[0252] Next, excess reactant 612a or reaction products are discharged from the chamber by introducing an inert gas or evacuating (hereinafter, this step may be referred to as the fourth step).

[0253] Next, precursor 611b having a metal element different from precursor 611a is introduced, and a process similar to the first step is performed to adsorb precursor 611b onto the surface of oxide 613a (see FIG. 12C). Here, as shown in FIG. 12C, the adsorption of precursor 611b onto the oxide 613a layer triggers a self-limiting mechanism of the surface chemical reaction, and precursor 611b is not further adsorbed onto the layer of precursor 611b on substrate 610.

[0254] Next, as in the second step, excess precursor 611b and reaction products are discharged from the chamber by introducing an inert gas or evacuating the chamber.

[0255] Next, as in the third step, reactant 612b is introduced into the chamber. Here, reactant 612b may be the same as reactant 612a or may be different (see FIG. 12D). As a result, a layer of oxide 613b, which is formed by oxidizing a portion of precursor 611b, is formed on the layer of oxide 613a.

[0256] Next, as in the fourth step, excess reactant 612b and reaction products are discharged from the chamber by introducing an inert gas or by vacuum evacuation.

[0257] Furthermore, by performing the first to fourth steps in a similar manner, a layer of oxide 613c can be formed on the layer of oxide 613b. In this manner, by repeatedly performing the steps of forming the oxides 613a to 613c, a metal oxide having a layered crystal structure in which the stacked structure of the oxides 613a to 613c is repeated can be formed (see FIG. 12E). That is, an oxide layer can be formed by performing the first to fourth steps as one set, and by repeating this set, a layered crystal structure in which multiple oxide layers are stacked can be formed.

[0258] The thickness of the metal oxide having a layered crystal structure may be 1 nm or more and less than 100 nm, preferably 3 nm or more and less than 20 nm.

[0259] 12 is preferably performed while heating the substrate. For example, the substrate temperature may be set to 200° C. or higher and 600° C. or lower, preferably 300° C. or higher and lower than the decomposition temperature of the precursor. When forming a film by the ALD method using multiple precursors of different types, the substrate temperature is preferably set to lower than the decomposition temperature of the lowest precursor among the multiple precursors. This allows the multiple precursors used to be adsorbed onto the target (e.g., substrate) without being decomposed during film formation by the ALD method.

[0260] By performing the above film formation while heating the substrate in such a temperature range, impurities such as hydrogen or carbon contained in the precursor and reactant can be removed from the metal oxide in each process of steps 1 to 4. For example, carbon in the metal oxide can be removed by converting it into CO ２ and CO, and hydrogen in the metal oxide is released as H ２ Furthermore, at the same time as the removal of the impurities, the metal atoms and oxygen atoms are rearranged, and the layers of the oxides can be arranged in a highly ordered manner. Therefore, a metal oxide with a highly crystalline layered crystal structure can be formed.

[0261] In order to perform film formation while heating the substrate within the above temperature range, it is preferable that the precursor used in the film formation has a high decomposition temperature. For example, the decomposition temperature of the precursor is preferably 200°C or higher and 700°C or lower, and more preferably 300°C or higher and 600°C or lower. As a precursor with such a high decomposition temperature, it is preferable to use a precursor formed from an inorganic substance (hereinafter referred to as an inorganic precursor). Inorganic precursors generally tend to have a higher decomposition temperature than precursors formed from organic substances (hereinafter referred to as organic precursors), and therefore some have an ALD window within the above temperature range. Furthermore, since inorganic precursors do not contain impurities such as hydrogen or carbon, an increase in the concentration of impurities such as hydrogen or carbon in the metal oxide film can be prevented.

[0262] Furthermore, it is preferable to perform heat treatment after the formation of the metal oxide film. In particular, it is preferable to perform heat treatment without exposing the film to the open air after the film formation by the ALD method. The heat treatment may be performed at a temperature of 100°C to 1200°C, preferably 200°C to 1000°C, more preferably 250°C to 650°C, even more preferably 300°C to 600°C, even more preferably 400°C to 550°C, and even more preferably 420°C to 480°C. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0263] By carrying out the heat treatment in this manner, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be converted to CO ２ and CO, and hydrogen in the metal oxide is released as H ２The impurities can be removed by the reaction of the metal atoms and oxygen atoms, and the metal atoms and oxygen atoms can be released as O. Furthermore, at the same time as the removal of the impurities, the rearrangement of metal atoms and oxygen atoms can be carried out, improving the crystallinity. Therefore, a metal oxide with a highly crystalline layered crystal structure can be formed.

[0264] After the metal oxide film is formed, it is preferable to perform microwave treatment in an oxygen-containing atmosphere to reduce the impurity concentration in the metal oxide. The impurities include hydrogen and carbon. Here, the microwave treatment refers to a treatment using a device with a power source that generates high-density plasma using microwaves.

[0265] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be converted into plasma using microwaves or high-frequency waves such as RF, and the oxygen plasma can be used to act on the metal oxide. Oxygen acting on the metal oxide can take various forms, including oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also known as O radicals, which are atoms, molecules, or ions with unpaired electrons). The oxygen acting on the metal oxide may take one or more of the above forms, and oxygen radicals are particularly preferred.

[0266] Furthermore, when microwave treatment is performed in the above-described oxygen-containing atmosphere, it is preferable to heat the substrate, since this can further reduce the impurity concentration in the metal oxide. The substrate may be heated to a temperature of 100° C. to 650° C., preferably 200° C. to 600° C., and more preferably 300° C. to 450° C.

[0267] By heating the substrate during microwave treatment in the above-mentioned oxygen-containing atmosphere, the carbon concentration in the metal oxide obtained by SIMS was increased to 1×10 ２０ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 1×10 １８ atoms / cm ３ It can be less than.

[0268] In the above, a configuration in which microwave treatment is performed on a metal oxide in an atmosphere containing oxygen has been exemplified, but the present invention is not limited to this. For example, microwave treatment may be performed on an insulating film, more specifically, a silicon oxide film, located near the metal oxide in an atmosphere containing oxygen. For example, in the process shown in FIG. 5 according to the above embodiment, microwave treatment may be performed after the insulating film 250A is formed. By performing microwave treatment on a silicon oxide film in an atmosphere containing oxygen, hydrogen contained in the silicon oxide film is converted into H ２ The hydrogen can be released to the outside as O. By releasing hydrogen from the silicon oxide film located in the vicinity of the metal oxide, a highly reliable semiconductor device can be provided.

[0269] 12, the structure in which the stacked structure of the oxides 613a to 613c is repeated is described, but the present invention is not limited to this. For example, a metal oxide in which a single layer, two layers, or four or more oxide layers are repeatedly formed may be used.

[0270] Furthermore, unless otherwise specified, in the present specification and the like, when ozone, oxygen, or water is used as a reactant or oxidant, these are not limited to gaseous or molecular states, but also include plasma, radical, and ionic states. When forming a film using an oxidant in a plasma, radical, or ionic state, a radical ALD apparatus or a plasma ALD apparatus, which will be described later, may be used.

[0271] To remove impurities such as carbon or hydrogen contained in the precursor, it is preferable to allow the precursor to react sufficiently with the oxidizing agent. For example, the pulse time for introducing the oxidizing agent may be increased. Alternatively, the oxidizing agent may be introduced multiple times. When introducing the oxidizing agent multiple times, the same type of oxidizing agent may be introduced, or different types of oxidizing agents may be introduced. For example, water may be introduced into the chamber as a first oxidizing agent, followed by evacuation, and ozone or oxygen containing no hydrogen may be introduced into the chamber as a second oxidizing agent, followed by evacuation.

[0272] In this way, by repeatedly introducing an oxidizing agent and an inert gas (or evacuating) into the chamber multiple times in a short period of time, excess hydrogen atoms, carbon atoms, chlorine atoms, etc. can be more reliably removed from the precursor adsorbed on the substrate surface and expelled to the outside of the chamber. Furthermore, by increasing the number of types of oxidizing agents to two, more excess hydrogen atoms, etc. can be removed from the precursor adsorbed on the substrate surface. In this way, by preventing hydrogen atoms from being incorporated into the film during film formation, the amount of water, hydrogen, etc. contained in the formed film can be reduced.

[0273] The ALD method is a film formation method in which precursors and reactants are reacted using thermal energy. The temperature required for the reaction of the precursors and reactants is determined by their temperature characteristics, vapor pressure, decomposition temperature, etc., but is generally 100°C to 600°C, preferably 200°C to 600°C, and more preferably 300°C to 600°C.

[0274] Furthermore, an ALD method in which, in addition to the reaction between the precursor and reactant, a plasma-excited reactant is introduced into the chamber as a third source gas is sometimes called a plasma ALD method. In this case, a plasma generating device is provided at the introduction point of the third source gas. Inductively coupled plasma can be used to generate the plasma. In contrast, an ALD method in which the reaction between the precursor and reactant is carried out using thermal energy is sometimes called a thermal ALD method.

[0275] In the plasma ALD method, a plasma-excited reactant is introduced in the third step to form a film. Alternatively, the first to fourth steps are repeatedly performed while a plasma-excited reactant (second reactant) is introduced, thereby forming a film. In this case, the reactant introduced in the third step is called the first reactant. In the plasma ALD method, the second reactant used in the third source gas can be the same material as the oxidizer. That is, plasma-excited ozone, oxygen, and water can be used as the second reactant. In addition to the oxidizer, a nitriding agent may also be used as the second reactant. Nitrogen (N ２ ) or ammonia (NH ３ ) can be used. Nitrogen (N ２ ) and hydrogen (H ２ ) can be used as a nitriding agent. ２ ) 5%, hydrogen (H ２ A 95% mixed gas of nitrogen and ammonia can be used as a nitriding agent. By conducting film formation while introducing plasma-excited nitrogen or ammonia, a nitride film such as a metal nitride film can be formed.

[0276] The carrier gas for the second reactant may be argon (Ar), helium (He), or nitrogen (N ２ ) may also be used. Using a carrier gas such as argon, helium, or nitrogen is preferable because it facilitates plasma discharge and facilitates the generation of a plasma-excited second reactant. Note that when forming an oxide film such as a metal oxide film using the plasma ALD method, using nitrogen as the carrier gas may result in nitrogen being mixed into the film, making it impossible to obtain the desired film quality. In this case, it is preferable to use argon or helium as the carrier gas.

[0277] The ALD method can deposit extremely thin films with uniform thickness and has a high surface coverage even on uneven surfaces.

[0278] Here, the atomic arrangement in the crystal when the metal oxide with a layered crystal structure is In-M-Zn oxide will be described with reference to Figures 13A to 13D. In Figures 13B and 13D, atoms are represented by spheres (circles), and bonds between metal atoms and oxygen atoms are represented by lines. In Figures 13B and 13D, the c-axis direction in the crystal structure of In-M-Zn oxide is represented by an arrow. The a-b plane direction in the crystal structure of In-M-Zn oxide is perpendicular to the c-axis direction represented by the arrow in Figures 13B and 13D.

[0279] 13A is a diagram showing an oxide 660 having an In-M-Zn oxide formed in a structure 650. Here, the structure refers to an element constituting a semiconductor device such as a transistor. The structure 650 includes a substrate, a conductor such as a gate electrode, a source electrode, and a drain electrode, an insulator such as a gate insulating film, an interlayer insulating film, and a base insulating film, a metal oxide, and a semiconductor such as silicon. FIG. 13A shows a case where the surface to be deposited of the structure 650 is arranged parallel to the substrate (or base, not shown).

[0280] 13B is an enlarged view showing the atomic arrangement in the crystal in a region 653, which is a part of the oxide 660 in FIG. 13A. The composition of the oxide 660 shown in FIGS. 13A and 13B is In:M:Zn=1:1:1 [atomic ratio], and the crystal structure is YbFe ２ O ４ The element M is a metal element with a valence of +3.

[0281] 13B , the crystals of the oxide 660 are formed by repeatedly stacking a layer 621 containing indium (In) and oxygen, a layer 631 containing the element M and oxygen, and a layer 641 containing zinc (Zn) and oxygen, in this order. The layer 621, the layer 631, and the layer 641 are arranged substantially parallel to the deposition surface of the structure 650. That is, the a-b plane of the oxide 660 is substantially parallel to the deposition surface of the structure 650, and the c-axis of the oxide 660 is substantially parallel to the normal direction of the deposition surface of the structure 650.

[0282] As shown in FIG. 13B, each of layers 621, 631, and 641 of the crystal is composed of one metal element and oxygen, and is arranged with good crystallinity, thereby increasing the mobility of the metal oxide.

[0283] Note that the In-M-Zn oxide with an atomic ratio of In:M:Zn=1:1:1 is not limited to the structure shown in FIG. 13B . The stacking order of the layers 621, 631, and 641 may be changed. For example, the layers 621, 641, and 631 may be repeatedly stacked in this order. Alternatively, the layers 621, 631, 641, 621, 641, and 631 may be repeatedly stacked in this order. Furthermore, part of the element M in the layer 631 may be substituted with zinc, and part of the zinc in the layer 641 may be substituted with the element M.

[0284] In the above, an example of forming an In-M-Zn oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] was shown. （１＋α） M （１−α） O ３ (ZnO) ｍ (α is a real number greater than 0 and less than 1, and m is a positive number) can similarly have a layered crystal structure. As an example, an In-M-Zn oxide with a composition of In:M:Zn=1:3:4 [atomic ratio] is shown in FIGS. 13C and 13D.

[0285] Figure 13C shows an oxide 662 having an In-M-Zn oxide formed on the structure 650. Figure 13D is an enlarged view showing the atomic arrangement in the crystal in a region 654 that is part of the oxide 662 in Figure 13C.

[0286] 13D , the crystals of the oxide 662 include a layer 622 containing indium (In), the element M, and oxygen, a layer 641 containing zinc (Zn) and oxygen, and a layer 631 containing the element M and oxygen. In the oxide 662, multiple layers are repeatedly stacked in the order of the layer 622, the layer 641, the layer 631, and the layer 641. The layers 622, 631, and 641 are arranged approximately parallel to the deposition surface of the structure 650. That is, the a-b plane of the oxide 662 is approximately parallel to the deposition surface of the structure 650, and the c-axis of the oxide 662 is approximately parallel to the normal direction of the deposition surface of the structure 650.

[0287] 13D , the In-M-Zn oxide with an atomic ratio of In:M:Zn=1:3:4 may have a structure that is different from that shown in FIG. 13D within the range of the atomic ratio of In:M:Zn=1:3:4. For example, the stacking order of the layers 622, 631, and 641 may be changed. Furthermore, part of the element M in the layer 631 may be substituted with zinc, and part of the zinc in the layer 641 may be substituted with the element M. Furthermore, the layer 621 or the layer 631 may be formed instead of the layer 622.

[0288] Next, a method for forming the oxide 660 having the In-M-Zn oxide shown in FIGS. 13A and 13B will be described in detail with reference to FIGS. 14A to 15C.

[0289] First, a source gas containing an indium-containing precursor is introduced into the chamber, and the precursor is adsorbed onto the surface of the structure 650 (see FIG. 14A ). Here, the source gas contains a carrier gas such as argon, helium, or nitrogen in addition to the precursor. Examples of precursors that can be used include trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, and (3-(dimethylamino)propyl)dimethylindium.

[0290] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the indium-containing precursor. Examples of the inorganic precursor containing indium include halogen-based indium compounds such as indium trichloride, indium tribromide, and indium triiodide. The decomposition temperature of indium trichloride is approximately 500°C or higher and 700°C or lower. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 400°C or higher and 600°C or lower, for example, at 500°C.

[0291] Next, the introduction of the source gas is stopped, and the chamber is purged to discharge excess precursors and reaction products from the chamber.

[0292] Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than indium while leaving indium adsorbed on the substrate, thereby forming a layer 621 in which indium and oxygen are combined (see FIG. 14B). Examples of the oxidizing agent that can be used include ozone, oxygen, and water. Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to remove excess reactant and reaction products from the chamber.

[0293] Next, a source gas containing a precursor having element M is introduced into the chamber, and the precursor is adsorbed onto layer 621 (see FIG. 14C ). The source gas contains a carrier gas such as argon, helium, or nitrogen in addition to the precursor. When gallium is used as element M, examples of precursors that can be used include trimethylgallium, triethylgallium, tris(dimethylamido)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and dimethylgallium isopropoxide.

[0294] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the gallium-containing precursor. Examples of the gallium-containing inorganic precursor include halogen-based gallium compounds such as gallium trichloride, gallium tribromide, and gallium triiodide. Gallium trichloride has a decomposition temperature of approximately 550°C to 700°C. Therefore, by using gallium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 450°C to 650°C, for example, 550°C.

[0295] Next, the introduction of the source gas is stopped, and the chamber is purged to discharge excess precursors and reaction products from the chamber.

[0296] Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming layer 631 in which element M and oxygen are combined (see FIG. 14D). At this time, some of the oxygen constituting layer 641 may be adsorbed onto layer 631. Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge excess reactant, reaction products, etc. from the chamber.

[0297] Next, a source gas containing a zinc-containing precursor is introduced into the chamber, and the precursor is adsorbed onto layer 631 (see FIG. 15A ). At this time, a portion of layer 641 in which zinc and oxygen are combined may be formed. The source gas contains, in addition to the precursor, a carrier gas such as argon, helium, or nitrogen. Examples of zinc-containing precursors that can be used include dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc acetate.

[0298] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the zinc-containing precursor. Examples of the zinc-containing inorganic precursor include halogen-based zinc compounds such as zinc dichloride, zinc dibromide, and zinc diiodide. The decomposition temperature of zinc dichloride is approximately 450°C to 700°C. Therefore, by using zinc dichloride, film formation can be performed by the ALD method while heating the substrate at approximately 350°C to 550°C, for example, at 450°C.

[0299] Next, the introduction of the source gas is stopped, and the chamber is purged to discharge excess precursors and reaction products from the chamber.

[0300] Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, and components other than zinc are desorbed while zinc remains adsorbed on the substrate, thereby forming a layer 641 in which zinc and oxygen are combined (see FIG. 15B). Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge excess reactant and reaction products from the chamber.

[0301] Next, the layer 621 is formed again on the layer 641 by the above-described method (see FIG. 15C). By repeating the above-described method, an oxide 660 can be formed on the substrate or the structure.

[0302] The precursors may contain one or both of carbon and chlorine in addition to the metal element. A film formed using a precursor containing carbon may contain carbon. A film formed using a precursor containing a halogen such as chlorine may contain halogen such as chlorine.

[0303] As described above, by forming the oxide 660 using the ALD method, a metal oxide can be formed whose c-axis is oriented approximately parallel to the normal direction of the deposition surface. For example, in the oxide semiconductor 230 shown in FIGS. 1B and 1C according to the above embodiment, layered crystals can be formed that are approximately parallel to the sidewall of the opening 290, particularly to the side surface of the insulator 280. With this structure, the layered crystals of the oxide semiconductor 230 are formed approximately parallel to the channel length direction of the transistor 200, thereby increasing the on-state current of the transistor.

[0304] 14A to 15C are preferably performed while heating the substrate, for example, at a substrate temperature of 200° C. to 600° C., preferably 300° C. to the decomposition temperature of the precursor.

[0305] In order to form a film while heating the substrate within the above temperature range, it is preferable that the precursor used in the film formation has a high decomposition temperature. For example, the decomposition temperature of the precursor is preferably 200°C or higher and 700°C or lower, and more preferably 300°C or higher and 600°C or lower. As a precursor with such a high decomposition temperature, it is preferable to use an inorganic precursor. Inorganic precursors generally tend to have a higher decomposition temperature than organic precursors, so that the precursor is less likely to decompose even when film formation is performed while heating the substrate as described above.

[0306] Examples of inorganic precursors that can be used include the aforementioned indium trichloride, gallium trichloride, and zinc dichloride. As described above, these precursors have decomposition temperatures of approximately 350°C or higher and 700°C or lower, which is significantly higher than the decomposition temperatures of typical organic precursors. However, as described above, the decomposition temperatures of indium trichloride, gallium trichloride, and zinc dichloride are different from one another. When performing film formation by ALD using multiple different types of precursors, it is preferable to set the substrate temperature below the decomposition temperature of the lowest precursor among the multiple precursors. In the above example, the substrate temperature may be set within a range in which zinc dichloride, the precursor with the lowest decomposition temperature, does not decompose. This allows other indium trichloride and gallium trichloride to be adsorbed onto the target (e.g., a substrate) without decomposing.

[0307] 14A to 15C show an example in which the layer 621 containing indium is formed, the layer 631 containing the element M is formed thereon, and the layer 641 containing zinc is further formed thereon, but this embodiment is not limited to this. One of the layer 631 and the layer 641 may be formed, the layer 621 may be formed thereon, and the other of the layer 631 and the layer 641 may be further formed thereon. Alternatively, one of the layer 631 and the layer 641 may be formed, the other of the layer 631 and the layer 641 may be formed thereon, and the layer 621 may be further formed thereon.

[0308] Furthermore, when forming a metal oxide having an atomic ratio different from In:M:Zn=1:1:1 (atomic ratio), the layers 621, 631, and 641 may be formed appropriately according to the atomic ratio. For example, as shown in FIG. 15A , the formation of the layer 641 may be repeated multiple times before and after the formation of the layer 631, thereby forming a stack of the layers 631 and 641 between the two layers 621, with the desired number of atoms, number of layers, and thickness.

[0309] In this embodiment, a configuration example of a memory device using the memory cells described in the above embodiment will be described. In this embodiment, a configuration example of a memory device in which a layer having a functional circuit that has a function of amplifying and outputting a data potential held in the memory cell is provided between layers having stacked memory cells will be described.

[0310] 16 is a block diagram illustrating a configuration example of a memory device 300 according to one embodiment of the present invention. The memory device 300 illustrated in FIG. 16 includes a driver circuit 21 and a memory array 20. The memory array 20 includes a functional layer 50 including a plurality of memory cells 10 and a plurality of functional circuits 51.

[0311] 16 shows an example in which the memory array 20 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more). Also, as an example, a functional circuit 51 is provided for each wiring BL that functions as a bit line. In FIG. 16, an example in which a plurality of functional circuits 51 are provided corresponding to n wirings BL is shown.

[0312] In FIG. 16 , the memory cell 10 in the first row and first column is indicated as memory cell 10[1,1], and the memory cell 10 in the mth row and nth column is indicated as memory cell 10[m,n]. In addition, in the present embodiment and the like, an arbitrary row may be referred to as row i. In addition, an arbitrary column may be referred to as column j. Therefore, i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to n. In addition, in the present embodiment and the like, the memory cell 10 in the ith row and jth column is indicated as memory cell 10[i,j]. In addition, in the present embodiment and the like, when "i+α" (α is a positive or negative integer) is indicated, "i+α" is not less than 1 or more than m. Similarly, when "j+α" is indicated, "j+α" is not less than 1 or more than n.

[0313] The memory array 20 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment and the like, the first wiring WL (first row) is referred to as wiring WL[1], and the mth wiring WL (mth row) is referred to as wiring WL[m]. Similarly, the first wiring PL (first row) is referred to as wiring PL[1], and the mth wiring PL (mth row) is referred to as wiring PL[m]. Similarly, the first wiring BL (first column) is referred to as wiring BL[1], and the nth wiring BL (nth column) is referred to as wiring BL[n].

[0314] The memory cells 10 in the i-th row are electrically connected to the wiring WL in the i-th row (wiring WL[i]) and the wiring PL in the i-th row (wiring PL[i]). The memory cells 10 in the j-th column are electrically connected to the wiring BL in the j-th column (wiring BL[j]).

[0315] The memory array 20 may be a DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM having 1T (transistor) 1C (capacitor) type memory cells, with the access transistor being an OS transistor. An OS transistor has extremely low leakage current, i.e., the current flowing between the source and drain in the off state. By turning off (non-conducting) the access transistor, DOSRAM can retain charge corresponding to the data stored in the capacitance element (capacitor) for a long period of time. Therefore, DOSRAM can reduce the frequency of refresh operations compared to DRAM configured with transistors having silicon in the channel formation region (hereinafter also referred to as "Si transistors"). As a result, power consumption can be reduced.

[0316] Furthermore, as described in Embodiment 1 and the like, the memory cells 10 can be stacked by arranging OS transistors in a stacked manner. For example, in the memory array 20 shown in FIG. 16, multiple memory arrays 20[1] to 20[m] can be stacked. The memory arrays 20[1] to 20[m] included in the memory array 20 can be arranged in the vertical direction of the substrate surface on which the driver circuit 21 is provided, thereby improving the memory density of the memory cells 10. Furthermore, the memory array 20 can be manufactured by repeatedly using the same manufacturing process in the vertical direction. The memory device 300 can reduce the manufacturing cost of the memory array 20.

[0317] The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on / off (conducting state or non-conducting state) of an access transistor functioning as a switch. The wiring PL functions as a constant potential line connected to a capacitor.

[0318] The memory cells 10 included in each of the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 via wiring BL. The wiring BL can be arranged perpendicular to the surface of the substrate on which the driver circuit 21 is provided. By arranging the wiring BL extending from the memory cells 10 included in the memory arrays 20[1] to 20[m] perpendicular to the surface of the substrate, the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened. This shortens the signal propagation distance between two circuits connected to the bit line, significantly reducing the resistance and parasitic capacitance of the bit line, thereby realizing reduced power consumption and signal delay. Furthermore, the memory cells 10 can operate even if the capacitance of the capacitive element included in the memory array 20 is reduced.

[0319] The functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 of the driver circuit 21 via a wiring GBL (not shown), which will be described later. This configuration allows a slight potential difference in the wiring BL to be amplified when reading data. The wiring GBL can be arranged in a direction perpendicular to the surface of the substrate on which the driver circuit 21 is provided, similar to the wiring BL. By arranging the wirings BL and GBL extending from the memory cells 10 of the memory arrays 20[1] to 20[m] in a direction perpendicular to the surface of the substrate, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, the signal propagation distance between two circuits connected to the wiring GBL can be shortened, and the resistance and parasitic capacitance of the wiring GBL are significantly reduced, thereby realizing reduced power consumption and signal delay.

[0320] The wiring BL is provided in contact with the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in contact with a region functioning as the source or drain of the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in contact with a conductor provided in contact with a region functioning as the source or drain of the semiconductor layer of the transistor included in the memory cell 10. In other words, the wiring BL can be said to be a wiring for electrically connecting one of the source or the drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51 in the vertical direction.

[0321] The memory array 20 can be provided overlapping the drive circuit 21. By providing the drive circuit 21 and the memory array 20 overlapping, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. This reduces the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20, thereby realizing reductions in power consumption and signal delay. Furthermore, the storage device 300 can be made smaller.

[0322] The functional circuit 51 is configured with OS transistors similar to the transistors included in the DOSRAM memory cells 10, and can be freely arranged on a circuit using Si transistors similar to the memory arrays 20[1] to 20[m], thereby facilitating integration. The signal amplification configuration in the functional circuit 51 allows for the miniaturization of subsequent circuits such as the sense amplifier 46, thereby enabling the miniaturization of the memory device 300.

[0323] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0324] In the storage device 300, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0325] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 32.

[0326] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0327] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0328] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cells 10. The peripheral circuit 41 is also a circuit for outputting various signals for controlling the functional circuit 51. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0329] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cell 10, the function of reading data from the memory cell 10, the function of holding the read data, etc.

[0330] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is a signal RDA.

[0331] The PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. The PSW23 has a function of controlling the supply of VHM to the row driver 43. In this example, the high power supply voltage of the memory device 300 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW22 is controlled by the signal PON1, and the on / off of the PSW23 is controlled by the signal PON2. In FIG. 16, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0332] The memory array 20 having memory arrays 20[1] to 20[m] (m is an integer of 2 or more) and functional layers 50 can be provided by stacking multiple layers of memory arrays 20 on the drive circuit 21. By stacking multiple layers of memory arrays 20, the memory density of the memory cells 10 can be increased. Figure 17A shows a perspective view of a storage device 300 showing how five layers (m = 5) of memory arrays 20[1] to 20[5] and functional layers 50 are stacked on the drive circuit 21.

[0333] In FIG. 17A , the memory array 20 provided in the first layer is indicated as memory array 20[1], the memory array 20 provided in the second layer is indicated as memory array 20[2], and the memory array 20 provided in the fifth layer is indicated as memory array 20[5]. Also shown in FIG. 17A are wirings WL and PL extending in the X direction, and wirings BL extending in the Z direction (the direction perpendicular to the substrate surface on which the drive circuits are provided). Note that, for clarity of the drawing, the wirings WL and PL of each memory array 20 are partially omitted. Note that, although FIG. 17A illustrates a configuration in which the wirings PL extend in the X direction, the present invention is not limited thereto. For example, the wirings PL may extend in the Y direction, or the wirings PL may extend in both the X and Y directions, e.g., the wirings PL may be planar.

[0334] 17B is a schematic diagram illustrating a configuration example of a functional circuit 51 connected to the wiring BL illustrated in FIG. 17A and memory cells 10 included in memory arrays 20[1] to 20[5] connected to the wiring BL. Also, FIG. 17B illustrates a wiring GBL provided between the functional circuit 51 and the driver circuit 21. Note that a configuration in which multiple memory cells (memory cells 10) are electrically connected to one wiring BL is also referred to as a "memory string." Note that in the drawings, the wiring GBL may be illustrated with a thick line to improve visibility.

[0335] 17B illustrates an example of a circuit configuration of a memory cell 10 connected to a wiring BL. The memory cell 10 includes a transistor 11 and a capacitor 12. The transistor 11, the capacitor 12, and each wiring (BL, WL, etc.) may also be referred to as a wiring BL[1] and a wiring WL[1], for example.

[0336] In the memory cell 10, one of the source and the drain of the transistor 11 is connected to a wiring BL. The other of the source and the drain of the transistor 11 is connected to one electrode of a capacitor 12. The other electrode of the capacitor 12 is connected to a wiring PL. The gate of the transistor 11 is connected to a wiring WL.

[0337] For example, two memory cells 10 connected to a common wiring BL in the same layer can have the structure shown in FIG. 10 according to the first embodiment.

[0338] 17B and other figures show a configuration in which two memory cells 10 are connected to a common wiring BL in the same layer, but the present invention is not limited to this. For example, a configuration in which four memory cells 10 are connected to a common wiring BL in the same layer may be used, or a configuration in which eight memory cells 10 are connected to a common wiring BL in the same layer may be used. For example, when four memory cells 10 are connected to a common wiring BL in the same layer, the structure shown in FIG. 11 according to the first embodiment may be used.

[0339] The wiring PL is a wiring that applies a constant potential for maintaining the potential of the capacitor 12 .

[0340] The wiring GBL shown in Fig. 17B is provided to electrically connect the driver circuit 21 and the functional layer 50. Fig. 18A shows a schematic diagram of a memory device 300 in which a functional circuit 51 and memory arrays 20[1] to 20[m] are repeated as a repeating unit 70. Note that, although Fig. 18A shows one wiring GBL, the wiring GBL may be provided as needed depending on the number of functional circuits 51 provided in the functional layer 50.

[0341] The wiring GBL is provided in contact with a semiconductor layer of a transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in contact with a region that functions as a source or a drain of a semiconductor layer of a transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in contact with a conductor that is provided in contact with a region that functions as a source or a drain of a semiconductor layer of a transistor included in the functional circuit 51. In other words, the wiring GBL can be said to be a wiring for electrically connecting one of the source or the drain of a transistor included in the functional circuit 51 in the functional layer 50 to the driver circuit 21 in the vertical direction.

[0342] The repeating unit 70 including the functional circuit 51 and the memory arrays 20[1] to 20[m] may be further stacked. The memory device 300A of one embodiment of the present invention can have repeating units 70[1] to 70[p] (p is an integer of 2 or more) as illustrated in FIG. 18B . The wiring GBL is connected to the functional layer 50 included in the repeating unit 70. The wiring GBL may be provided as appropriate depending on the number of functional circuits 51.

[0343] In one embodiment of the present invention, OS transistors are stacked, and wirings functioning as bit lines are arranged perpendicular to the surface of a substrate on which the driver circuit 21 is provided. By providing the wirings functioning as bit lines extending from the memory array 20 perpendicular to the surface of the substrate, the length of the wiring between the memory array 20 and the driver circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit lines can be significantly reduced.

[0344] In one embodiment of the present invention, a layer in which the memory array 20 is provided includes a functional layer 50 having a functional circuit 51 that has a function of amplifying and outputting a data potential held in the memory cell 10. With this configuration, a slight potential difference of the wiring BL that functions as a bit line can be amplified when reading data, and the sense amplifier 46 included in the driver circuit 21 can be driven. Since circuits such as the sense amplifier can be miniaturized, the memory device 300 can be miniaturized. Furthermore, the memory device 300 can operate even if the capacitance of the capacitor 12 included in the memory cell 10 is reduced.

[0345] 19 will be used to describe a configuration example of the functional circuit 51 described with reference to FIGS. 16 to 18 , and a configuration example of the sense amplifier 46 included in the memory array 20 and the driver circuit 21. FIG. 19 illustrates a driver circuit 21 connected to wirings GBL (GBL_A, GBL_B) that are connected to functional circuits 51 (51_A, 51_B) that are connected to memory cells 10 (10_A, 10_B) that are connected to different wirings BL (BL_A, BL_B). The driver circuit 21 illustrated in FIG. 19 includes a sense amplifier 46, a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write / read circuit 73.

[0346] 19 are OS transistors similar to the transistor 11 included in the memory cell 10. The functional layer 50 including the functional circuit 51 can be stacked in the same manner as the memory arrays 20[1] to 20[m].

[0347] The wirings BL_A and BL_B are connected to the gates of the transistors 52_a and 52_b. The wirings GBL_A and GBL_B are connected to one of the sources or drains of the transistors 53_a, 53_b, 54_a, and 54_b. The wirings GBL_A and GBL_B are provided in the vertical direction like the wirings BL_A and BL_B, and are connected to the transistors included in the driver circuit 21. As shown in FIG. 19 , control signals WE, RE, and MUX are applied to the gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b.

[0348] 19, transistors 81_1 to 81_6 and 82_1 to 82_4 constituting sense amplifier 46, precharge circuit 71_A, and precharge circuit 71_B are configured with Si transistors. Switches 83_A to 83_D constituting switch circuits 72_A and 72_B can also be configured with Si transistors. One of the sources or drains of transistors 53_a, 53_b, 54_a, and 54_b is connected to the transistors or switches constituting precharge circuit 71_A, precharge circuit 71_B, sense amplifier 46, and switch circuit 72_A.

[0349] The precharge circuit 71_A includes n-channel transistors 81_1 to 81_3. The precharge circuit 71_A is a circuit for precharging the wirings BL_A and BL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in response to a precharge signal applied to a precharge line PCL1.

[0350] The precharge circuit 71_B includes n-channel transistors 81_4 to 81_6. The precharge circuit 71_B is a circuit for precharging the wirings GBL_A and GBL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in response to a precharge signal applied to a precharge line PCL2.

[0351] The sense amplifier 46 includes p-channel transistors 82_1 and 82_2 and n-channel transistors 82_3 and 82_4 connected to a wiring VHH or a wiring VLL. The wiring VHH or the wiring VLL provides VDD or VSS. The transistors 82_1 to 82_4 form an inverter loop. The potentials of the precharged wirings BL_A and BL_B change when the memory cells 10_A and 10_B are selected. Depending on the change, the potentials of the wirings GBL_A and GBL_B are set to the high power supply potential VDD or the low power supply potential VSS. The potentials of the wirings GBL_A and GBL_B can be output to the outside via the switches 83_C and 83_D and the write / read circuit 73. The wirings BL_A and BL_B, as well as the wirings GBL_A and GBL_B, correspond to bit line pairs. The write / read circuit 73 controls the writing of data signals in response to the signal EN_data.

[0352] The switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wiring GBL_A and wiring GBL_B. The switch circuit 72_A is switched on or off under the control of a switching signal CSEL1. When the switches 83_A and 83_B are n-channel transistors, the switching signal CSEL1 is turned on at a high level and turned off at a low level. The switch circuit 72_B is a circuit for controlling the conduction state between the write / read circuit 73 and the bit line pair connected to the sense amplifier 46. The switch circuit 72_B is switched on or off under the control of a switching signal CSEL2. The switches 83_C and 83_D may be configured in the same manner as the switches 83_A and 83_B.

[0353] 19 , the memory device 300 can be configured such that the memory cells 10, the functional circuits 51, and the sense amplifiers 46 are connected via wirings BL and GBL that are provided in the vertical direction, which is the shortest distance. Although the number of functional layers 50 having transistors that configure the functional circuits 51 increases, the load on the wirings BL is reduced, which shortens the write time and makes it easier to read data.

[0354] 19 , each transistor included in the functional circuits 51_A and 51_B is controlled in response to control signals WE and RE and a selection signal MUX. In response to the control signal and the selection signal, each transistor can output the potential of the wiring BL to the driver circuit 21 via the wiring GBL. The functional circuits 51_A and 51_B can function as sense amplifiers formed of OS transistors. This configuration allows a slight potential difference in the wiring BL to be amplified during read operation, thereby driving the sense amplifier 46 using Si transistors.

[0355] As described above, by stacking a plurality of memory cell arrays and driver circuits, it is possible to increase the integration density of a memory device and the storage capacity thereof.

[0356] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0357] 20A and 20B show an example of a chip 1200 on which a memory device of the present invention is mounted. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0358] As shown in FIG. 20A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0359] 20B, the chip 1200 is provided with bumps (not shown), which are connected to a first surface of a package substrate 1201. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201, which are connected to a motherboard 1203.

[0360] The motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222. For example, the DOSRAM described in the above embodiment can be used as the DRAM 1221. This allows the DRAM 1221 to have low power consumption, high speed, and large capacity.

[0361] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing or multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0362] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0363] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0364] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0365] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a Universal Serial Bus (USB) or a High-Definition Multimedia Interface (HDMI (registered trademark)) can be used.

[0366] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0367] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0368] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0369] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a smaller size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0370] At least part of the structures, methods, and the like described in this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0371] Embodiment 5 This embodiment describes an example of an electronic component and an electronic device in which the memory device described in the above embodiment is incorporated. By using the memory device described in the above embodiment in the following electronic component and electronic device, the electronic component and electronic device can have low power consumption and high speed.

[0372] <Electronic Component> First, an example of an electronic component incorporating the memory device 720 will be described with reference to FIGS. 21A and 21B.

[0373] FIG. 21A shows a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in FIG. 21A has a memory device 720 inside a mold 711. FIG. 21A omits a portion of the interior of the electronic component 700 to show it. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the memory device 720 by wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0374] The memory device 720 includes a driver circuit layer 721 and a memory circuit layer 722 .

[0375] 21B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a system in package (SiP) or a multi-chip module (MCM). The electronic component 730 includes an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of memory devices 720 provided on the interposer 731. Using the memory device described in any of the above embodiments as the memory device 720 can reduce power consumption and increase speed.

[0376] The semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0377] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. The interposer 731 may be a silicon interposer, a resin interposer, etc.

[0378] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0379] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since wiring formation on a silicon interposer can be performed using a semiconductor process, it is easy to form fine wiring that is difficult to form on a resin interposer.

[0380] Furthermore, in SiP, MCM, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0381] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 720 and the height of the semiconductor device 735.

[0382] Electrodes 733 may be provided on the bottom of the package substrate 732 in order to mount the electronic component 730 on another substrate. FIG. 21B shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0383] The electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0384] The structures and methods described in this embodiment can be used in appropriate combination with other structures and methods described in this embodiment or structures and methods described in other embodiments.

[0385] Embodiment 6 In this embodiment, an application example of a storage device using the storage device described in the previous embodiment will be described. The storage device described in the previous embodiment can be applied to various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording / playback devices, navigation systems, and the like). By using the storage device described in the above embodiment as a storage device for the electronic device, the electronic device can be made to have low power consumption and high speed. Note that the term "computer" here refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system. Alternatively, the storage device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and solid-state drives (SSDs). FIGS. 22A to 22E schematically show several configuration examples of removable storage devices. For example, the storage device described in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0386] 22A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The memory device described in the above embodiment can be incorporated into the memory chip 1105 or the like.

[0387] FIG. 22B is a schematic diagram of the external appearance of an SD card, and FIG. 22C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. A wireless chip with wireless communication capabilities may also be provided on the substrate 1113. This enables data to be read from and written to the memory chip 1114 via wireless communication between the host device and the SD card 1110. The memory device described in the above embodiment can be incorporated into the memory chip 1114 or the like.

[0388] FIG. 22D is a schematic diagram of the appearance of an SSD, and FIG. 22E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The board 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the board 1153. The memory chip 1155 is a work memory for the controller chip 1156, and may be, for example, a DOSRAM chip. The capacity of the SSD 1150 can be increased by providing a memory chip 1154 on the back side of the board 1153. The memory device shown in the previous embodiment can be incorporated into the memory chip 1154 or the like.

[0389] At least part of the structures, methods, and the like described in this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0390] Embodiment 7 A memory device according to one embodiment of the present invention can be used in a processor such as a CPU or a GPU, or a chip. By using such a processor such as a CPU or a GPU, or a chip in an electronic device, the electronic device can have low power consumption and high speed. Specific examples of electronic devices including a processor such as a CPU or a GPU, or a chip using the memory device are shown in FIGS. 23A to 23H .

[0391] <Electronic Devices and Systems> A GPU or chip according to one embodiment of the present invention can be mounted in various electronic devices. Examples of electronic devices include electronic devices with relatively large screens, such as televisions, monitors for desktop or notebook information terminals, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Furthermore, by providing an electronic device with a GPU or chip according to one embodiment of the present invention, it is possible to mount artificial intelligence on the electronic device.

[0392] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0393] An electronic device according to one embodiment of the present invention may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).

[0394] An electronic device of one embodiment of the present invention can have various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on a display portion, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc. Examples of electronic devices are shown in FIGS. 23A to 23H .

[0395] 23A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 includes a housing 5101 and a display unit 5102. The display unit 5102 is provided with a touch panel and the housing 5101 is provided with buttons as input interfaces.

[0396] The application of a chip of one embodiment of the present invention to the information terminal 5100 enables low power consumption and high speed.

[0397] 23B shows a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0398] Like the above-described information terminal 5100, the notebook information terminal 5200 can have low power consumption and high speed by applying a chip of one embodiment of the present invention.

[0399] 23A and 23B are taken as examples of electronic devices, but information terminals other than smartphones and notebook information terminals can also be applied. Examples of information terminals other than smartphones and notebook information terminals include personal digital assistants (PDAs), desktop information terminals, and workstations.

[0400] 23C illustrates a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connecting portion 5305, an operation key 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. By attaching the connecting portion 5305 of the housing 5301 to another housing (not shown), the video displayed on the display portion 5304 can be output to another video device (not shown). In this case, the housing 5302 and the housing 5303 can each function as an operation portion. This allows multiple players to play a game at the same time. The chips described in the above embodiments can be incorporated into the substrates of the housings 5301, 5302, and 5303.

[0401] 23D shows a stationary game machine 5400, which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wired connection.

[0402] A game machine with low power consumption can be realized by applying the GPU or chip of one embodiment of the present invention to a game machine such as the portable game machine 5300 or the stationary game machine 5400. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0403] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5300, power consumption can be reduced and speed can be increased.

[0404] 23C and 23D illustrate a portable game machine and a stationary game machine as examples of game machines, but game machines to which the GPU or chip of one embodiment of the present invention is applied are not limited to these. Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0405] [Mainframe Computer] The GPU or chip according to one aspect of the present invention can be applied to a mainframe computer.

[0406] Fig. 23E is a diagram showing a supercomputer 5500, which is an example of a large computer. Fig. 23F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0407] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and the GPU or chip described in the above embodiment can be mounted on the boards.

[0408] The supercomputer 5500 is a large-scale computer mainly used for scientific and technological calculations. Scientific and technological calculations require high-speed processing of enormous amounts of calculations, resulting in high power consumption and large amounts of heat generated by the chip. By applying a GPU or chip according to one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. Furthermore, low power consumption can reduce heat generation from circuits, thereby reducing the impact of heat generation on the circuits themselves, peripheral circuits, and modules.

[0409] 23E and 23F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of mainframe computers to which the GPU or chip of one embodiment of the present invention is applied include computers that provide services (servers), large general-purpose computers (mainframes), etc.

[0410] [Mobile Body] The GPU or chip according to one embodiment of the present invention can be applied to a mobile body such as an automobile and the area around the driver's seat of the automobile.

[0411] Fig. 23G is a diagram showing the area around the windshield in the interior of an automobile, which is an example of a moving body, showing display panels 5701, 5702, and 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0412] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, air conditioning settings, etc. In addition, the display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, thereby improving the design. The display panels 5701 to 5703 can also be used as lighting devices.

[0413] The display panel 5704 can display an image from an imaging device (not shown) installed in the vehicle to complement the view (blind spot) blocked by the pillar. That is, by displaying an image from an imaging device installed outside the vehicle, the blind spot can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0414] Since the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system for automobiles. The chip can also be used in a system that provides road guidance, hazard prediction, etc. The display panels 5701 to 5704 may be configured to display information such as road guidance and hazard prediction.

[0415] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, moving objects may include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets). The chip of one embodiment of the present invention can be applied to these moving objects to provide a system using artificial intelligence.

[0416] 23H shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0417] The electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800, expiration dates of the ingredients, and the like, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0418] Although an electric refrigerator-freezer has been described as an example of an electrical appliance, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audiovisual equipment.

[0419] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with descriptions of other electronic devices.

[0420] At least part of the structures, methods, and the like described in this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0421] Embodiment 8 A memory device of one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. In this embodiment, a specific example in which the memory device of one embodiment of the present invention is applied to space equipment will be described with reference to FIG. 24 .

[0422] Fig. 24 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 24, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0423] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0424] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0425] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0426] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a storage device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0427] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0428] Although an artificial satellite is used as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the storage device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0429] ADDR: signal, BL[1]: wiring, BL[j]: wiring, BL[n]: wiring, BL_A: wiring, BL_B: wiring, BL: wiring, BW: signal, CE: signal, CLK: signal, EN_data: signal, GBL_A: wiring, GBL_B: wiring, GBL: wiring, GW: signal, MUX: selection signal, PL[1]: wiring, PL[i]: wiring, PL[m]: wiring, PL: wiring, RDA: signal, RE: control signal, Tr: transistor, VDD: high power supply potential, VHH: wiring, VLL: wiring, VPC: intermediate potential, VSS: low power supply potential, WAKE: signal, WDA: signal, WE: control Signal, WL[1]: wiring, WL[i]: wiring, WL[m]: wiring, WL: wiring, 10_A: memory cell, 10_B: memory cell, 10: memory cell, 11: transistor, 12: capacitor, 20: memory array, 21: driver circuit, 22: PSW, 23: PSW, 31: peripheral circuit, 32: control circuit, 33: voltage generation circuit, 41: peripheral circuit, 42: row decoder, 43: row driver, 44: column decoder, 45: column driver, 46: sense amplifier, 47: input circuit, 48: output circuit, 50: functional layer, 51_A: functional circuit, 51_B: functional circuit, 51: function Circuit, 52_a: transistor, 52_b: transistor, 53_a: transistor, 53_b: transistor, 54_a: transistor, 54_b: transistor, 55_a: transistor, 55_b: transistor, 70: repeating unit, 71_A: precharge circuit, 71_B: precharge circuit, 72_A: switch circuit, 72_B: switch circuit, 73: write / read circuit, 81_1: transistor, 81_3: transistor, 81_4: transistor, 81_6: transistor, 82_1: transistor, 82_2: transistor, 82 _3: transistor, 82_4: transistor, 83_A: switch, 83_B: switch, 83_C: switch, 83_D: switch, 100a: capacitor, 100b: capacitor, 100c: capacitor, 100d: capacitor, 100: capacitor, 110: conductor, 120: conductor, 130: insulator, 140: insulator, 150a: memory cell, 150b: memory cell, 150c: memory cell, 150d: memory cell, 150: memory cell, 160a: memory unit, 160b: memory unit, 160c: memory unit, 160d: memory unit,160: memory unit, 200a: transistor, 200b: transistor, 200c: transistor, 200d: transistor, 200: transistor, 230A: oxide semiconductor film, 230: oxide semiconductor, 240: conductor, 245: conductor, 246: conductor, 250A: insulating film, 250: insulator, 254: insulator, 260: conductor, 265: conductor, 280: insulator, 281: insulator, 285: insulator, 287: insulator, 289: insulator, 290: opening, 300A: storage device, 300: storage device, 610: substrate, 611a: precursor, 611b: Precursor, 612a: reactant, 612b: reactant, 613a: oxide, 613b: oxide, 613c: oxide, 621: layer, 622: layer, 631: layer, 641: layer, 650: structure, 653: region, 654: region, 660: oxide, 662: oxide, 700: electronic component, 702: printed circuit board, 704: mounting substrate, 711: mold, 712: land, 713: electrode pad, 714: wire, 720: memory device, 721: drive circuit layer, 722: memory circuit layer, 730: electronic component, 731: interposer, 732: package substrate, 733: Electrode, 735: semiconductor device, 1100: USB memory, 1101: housing, 1102: cap, 1103: USB connector, 1104: substrate, 1105: memory chip, 1106: controller chip, 1110: SD card, 1111: housing, 1112: connector, 1113: substrate, 1114: memory chip, 1115: controller chip, 1150: SSD, 1151: housing, 1152: connector, 1153: substrate, 1154: memory chip, 1155: memory chip, 1156: controller chip, 1200: chip, 1201: package substrate board, 1202: bump, 1203: motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: analog calculation unit, 1214: memory controller, 1215: interface, 1216: network circuit, 1221: DRAM, 1222: flash memory, 5100: information terminal, 5101: housing, 5102: display unit, 5200: notebook information terminal, 5201: main body, 5202: display unit, 5203: keyboard, 5300: portable game console, 5301: housing, 5302: housing, 5303: housing, 5304: display unit,5305: connection part, 5306: operation keys, 5400: stationary game machine, 5402: controller, 5500: supercomputer, 5501: rack, 5502: calculator, 5504: circuit board, 5701: display panel, 5702: display panel, 5703: display panel, 5704: display panel, 5800: electric refrigerator-freezer, 5801: housing, 5802: refrigerator compartment door, 5803: freezer compartment door, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device,

Claims

1. a capacitor, a transistor on the capacitor, a first insulator on the capacitor, and a second insulator on the first insulator; The transistor is a first conductor beneath the first insulator; an oxide semiconductor disposed in contact with an upper surface of the first conductor; a second conductor disposed between the first insulator and the second insulator and in contact with the oxide semiconductor; a third insulator on the oxide semiconductor; a third conductor on the third insulator; and a fourth insulator between the third insulator and the third conductor; a first opening reaching the first conductor is formed in the first insulator, the second conductor, and the second insulator; at least a portion of the oxide semiconductor, at least a portion of the third insulator, and at least a portion of the third conductor are disposed in the first opening; the fourth insulator covers a side edge of the oxide semiconductor and a side edge of the third insulator; The capacitive element is a fourth conductor; and a fifth insulator on the fourth conductor; and the first conductor on the fifth insulator, storage device.

2. a first layer and a second layer, each layer including a capacitive element, a transistor on the capacitive element, a first insulator on the capacitive element, and a second insulator on the first insulator; the second layer is laminated on the first layer; The transistor is a first conductor beneath the first insulator; an oxide semiconductor disposed in contact with an upper surface of the first conductor; a second conductor disposed between the first insulator and the second insulator and in contact with the oxide semiconductor; a third insulator on the oxide semiconductor; a third conductor on the third insulator; and a fourth insulator between the third insulator and the third conductor; a first opening reaching the first conductor is formed in the first insulator, the second conductor, and the second insulator; at least a portion of the oxide semiconductor, at least a portion of the third insulator, and at least a portion of the third conductor are disposed in the first opening; the fourth insulator covers a side edge of the oxide semiconductor and a side edge of the third insulator; The capacitive element is a fourth conductor; and a fifth insulator on the fourth conductor; and the first conductor on the fifth insulator; a second opening is formed in the second insulator of the first layer and the first insulator of the second layer; a fifth conductor in the second opening; the fifth conductor is in contact with an upper surface of the second conductor of the first layer and in contact with a lower surface of the second conductor of the second layer; storage device.

3. In claim 1 or claim 2, a sixth conductor in contact with an upper surface of the third conductor; the second conductor is formed to extend in a first direction, the sixth conductor is formed to extend in a second direction; the first direction and the second direction intersect with each other. storage device.

4. In claim 1 or claim 2, the first conductor functions as one of a source electrode and a drain electrode; the second conductor functions as the other of the source electrode and the drain electrode; the third conductor functions as a gate electrode. storage device.

5. In claim 1 or claim 2, a portion of the oxide semiconductor, a portion of the third insulator, and a portion of the third conductor are located on the second insulator; storage device.

6. In claim 1 or claim 2, a side edge of the oxide semiconductor and a side edge of the third insulator are substantially aligned in a plan view; storage device.

7. In claim 1 or claim 2, a side edge of the third conductor is located inside a side edge of the oxide semiconductor and a side edge of the third insulator in a plan view; storage device.

8. In claim 1 or claim 2, In a plan view, the first opening has a circular or substantially circular shape. storage device.

9. In claim 1 or claim 2, the fourth insulator is silicon nitride; storage device.

10. In claim 1 or claim 2, the oxide semiconductor contains one or more selected from In, Ga, and Zn; storage device.

11. In claim 1 or claim 2, the oxide semiconductor has layered crystals that are substantially parallel to a sidewall of the first opening; storage device.

12. In claim 1 or claim 2, The oxide semiconductor has a carbon concentration of 1×10 ２０ atoms / cm ３ is less than storage device.