Electronic component and method for producing same

Abstract

An electronic component according to the present invention includes: a semiconductor layer having a first principal surface and a second principal surface that is on the reverse side of the first principal surface; a lower insulating layer formed on the first principal surface of the semiconductor layer; a resistance layer that is formed on the lower insulating layer and that has a notch section extending in a prescribed first direction from a portion of the periphery of the resistance layer; an upper insulating layer formed on the lower insulating layer so as to cover the resistance layer; and an asperity structure formed in a prescribed region on the first principal surface of the semiconductor layer, said prescribed region including at least a region directly below the resistance layer. The asperity structure includes: a plurality of grooves that are arranged at equal intervals in a second direction, which is a direction along the first principal surface and is orthogonal to the first direction, and that extend parallel to the first direction; and protrusions each of which is a portion between two neighboring grooves.

Description

Electronic components and their manufacturing method

[0001] The present disclosure relates to electronic components and methods for manufacturing the same.

[0002] Patent Document 1 discloses a semiconductor device including a silicon substrate, an insulating layer formed on the silicon substrate, a polysilicon resistor element formed on the insulating layer, and wiring connected to the polysilicon resistor element on the polysilicon resistor element.

[0003] JP 2015-012259 A

[0004] An object of the present disclosure is to provide an electronic component that facilitates the formation of appropriate notches in a resistive layer, and a method for manufacturing the same.

[0005] One embodiment of the present disclosure provides an electronic component including: a semiconductor layer having a first main surface and a second main surface opposite to the first main surface; a lower insulating layer formed on the first main surface of the semiconductor layer; a resistive layer formed on the lower insulating layer and having a notch extending from a portion of its periphery in a predetermined first direction; an upper insulating layer formed on the lower insulating layer so as to cover the resistive layer; and a concavo-convex structure formed in a predetermined region on the first main surface of the semiconductor layer that includes at least a region directly below the resistive layer, the concavo-convex structure being arranged at equal intervals in a direction along the first main surface and in a second direction perpendicular to the first direction, and including a plurality of grooves extending parallel to the first direction, and a convex portion between two adjacent grooves.

[0006] This configuration makes it easier to form appropriate notches in the resistance layer.

[0007] One embodiment of the present disclosure provides a method for manufacturing an electronic component, the method comprising the steps of: forming a concave-convex structure in a predetermined region of a first main surface of a semiconductor layer having a first main surface and a second main surface opposite the first main surface; forming a lower insulating film on the first main surface of the semiconductor layer; forming a resistive layer on the lower insulating film; forming an upper insulating film on the lower insulating film so as to cover the resistive layer; and forming a notch in the resistive layer, the notch extending in a predetermined first direction from a portion of a periphery of the resistive layer, by irradiating the resistive layer with laser light through the upper insulating film, wherein the predetermined region is a region that includes at least a region directly below the resistive layer on the first main surface of the semiconductor layer; and the concave-convex structure is formed by forming a plurality of grooves in the predetermined region that extend parallel to the first direction and are equally spaced in a direction along the first main surface and a second direction perpendicular to the first direction.

[0008] This manufacturing method makes it possible to manufacture an electronic component in which appropriate notches are more likely to be formed in the resistance layer.

[0009] The above and other objects, features, and advantages of the present disclosure will become apparent from the following description of the embodiments with reference to the accompanying drawings.

[0010] FIG. 1 is a schematic plan view showing an electronic component according to an embodiment of the present invention, illustrating a configuration in which a resistive layer is incorporated. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is an enlarged view of region III in FIG. 2. FIG. 4 is an enlarged plan view illustrating the planar shape of the resistive layer. FIG. 5 is an enlarged plan view illustrating a portion of a first main surface of a semiconductor layer. FIG. 6A is a cross-sectional view illustrating a portion of a manufacturing process of the electronic component shown in FIG. 1, corresponding to the cross section of FIG. 2. FIG. 6B is a cross-sectional view illustrating a step subsequent to FIG. 6A. FIG. 6C is a cross-sectional view illustrating a step subsequent to FIG. 6B. FIG. 6D is a cross-sectional view illustrating a step subsequent to FIG. 6C. FIG. 6E is a cross-sectional view illustrating a step subsequent to FIG. 6D. FIG. 6F is a cross-sectional view illustrating a step subsequent to FIG. 6E. FIG. 6G is a cross-sectional view illustrating a step subsequent to FIG. 6F. FIG. 6H is a cross-sectional view illustrating a step subsequent to FIG. 6G. FIG. 6I is a cross-sectional view illustrating a step subsequent to FIG. 6H. FIG. 6J is a cross-sectional view illustrating a step subsequent to FIG. 6I. FIG. 6K is a cross-sectional view showing a step subsequent to FIG. 6J. FIG. 6L is a cross-sectional view showing a step subsequent to FIG. 6K. FIG. 6M is a cross-sectional view showing a step subsequent to FIG. 6L. FIG. 6L is a cross-sectional view showing a step subsequent to FIG. 6M. FIG. 6O is a cross-sectional view showing a step subsequent to FIG. 6N. FIG. 6P is a cross-sectional view showing a step subsequent to FIG. 6O. FIG. 6Q is a cross-sectional view showing a step subsequent to FIG. 6P. FIG. 6R is a cross-sectional view showing a step subsequent to FIG. 6Q. FIG. 6S is a cross-sectional view showing a step subsequent to FIG. 6R. FIG. 7 is a plan view illustrating the concavo-convex structure of the first sample. FIG. 8 is a plan view illustrating the concavo-convex structures of the second to seventh samples. FIG. 9 is a plan view illustrating the concavo-convex structures of the eighth and ninth samples. FIG. 10 is a plan view illustrating the concavo-convex structures of the tenth and eleventh samples. FIG. 11 is a plan view illustrating the concavo-convex structures of the twelfth and thirteenth samples.

[0011] [Description of an embodiment of the present disclosure] One embodiment of the present disclosure provides an electronic component including: a semiconductor layer having a first main surface and a second main surface opposite to the first main surface; a lower insulating layer formed on the first main surface of the semiconductor layer; a resistive layer formed on the lower insulating layer and having a notch extending from a portion of its periphery in a predetermined first direction; an upper insulating layer formed on the lower insulating layer so as to cover the resistive layer; and a concavo-convex structure formed in a predetermined region on the first main surface of the semiconductor layer that includes at least a region immediately below the resistive layer, the concavo-convex structure being arranged at equal intervals in a direction along the first main surface and in a second direction orthogonal to the first direction, and including a plurality of grooves extending parallel to the first direction, and a convex portion that is a portion between two adjacent grooves.

[0012] This configuration makes it easier to form appropriate notches in the resistance layer.

[0013] In one embodiment of the present disclosure, the resistive layer has a rectangular shape in a planar view having first opposing sides consisting of two sides parallel to the second direction and second opposing sides consisting of two sides parallel to the first direction, and the cutout portion extends from the middle of the length of one of the first opposing sides toward the other of the first opposing sides.

[0014] One embodiment of the present disclosure includes a first via electrode embedded in the lower insulating layer and having an upper end connected to a portion of the resistive layer near one of the second opposing sides, and a second via electrode embedded in the lower insulating layer and having an upper end connected to a portion of the resistive layer near the other of the second opposing sides.

[0015] One embodiment of the present disclosure includes a first lower wiring layer formed in a region on the lower insulating layer side of the resistive layer and electrically connected to the first via electrode, and a second lower wiring layer formed in a region on the lower insulating layer side of the resistive layer and electrically connected to the second via electrode.

[0016] In one embodiment of the present disclosure, the first lower wiring layer extends from the inside to the outside of the resistance layer relative to one of the second opposing sides in a planar view, and the second lower wiring layer extends from the inside to the outside of the resistance layer relative to the other of the second opposing sides in a planar view, and the first lower wiring layer and the second lower wiring layer are arranged at a distance in the second direction in a planar view.

[0017] In an embodiment of the present disclosure, the resistive layer is connected in series to the first lower wiring layer and the second lower wiring layer.

[0018] One embodiment of the present disclosure includes a first upper wiring layer formed on the upper insulating layer and electrically connected to the first lower wiring layer, and a second upper wiring layer formed on the upper insulating layer and electrically connected to the second lower wiring layer.

[0019] In an embodiment of the present disclosure, the resistive layer is connected in series to the first upper wiring layer and the second upper wiring layer.

[0020] One embodiment of the present disclosure includes a first long via electrode that penetrates the upper insulating layer and a portion of the lower insulating layer and is electrically connected to the first lower wiring layer and the first upper wiring layer, and a second long via electrode that penetrates the upper insulating layer and a portion of the lower insulating layer and is electrically connected to the second lower wiring layer and the second upper wiring layer.

[0021] In an embodiment of the present disclosure, the resistive layer is located on a straight line connecting the first long via electrode and the second long via electrode in a plan view.

[0022] In one embodiment of the present disclosure, the semiconductor layer includes a device region in which a functional device is formed and an outer region outside the device region, and the resistive layer is formed in the outer region in a plan view.

[0023] In one embodiment of the present disclosure, the resistive layer is made of a metal thin film containing at least one of CrSi, CrSiO, and CrSiN.

[0024] In one embodiment of the present disclosure, the depth of the groove is 100 nm or more and 300 nm or less, and the width of the groove and the interval between the grooves are 0.2 μm or more and 1 μm or less.

[0025] In one embodiment of the present disclosure, the depth of the groove is 150 nm or more and 300 nm or less, and the width of the groove and the interval between the grooves are 0.2 μm or more and 1 μm or less.

[0026] In one embodiment of the present disclosure, the lower insulating layer includes a plurality of stacked lower silicon oxide films, and the upper insulating layer includes an upper silicon oxide film formed on the lower insulating layer to cover the resistive film.

[0027] One embodiment of the present disclosure provides a method for manufacturing an electronic component, the method comprising the steps of: forming a concave-convex structure in a predetermined region of a first main surface of a semiconductor layer having a first main surface and a second main surface opposite the first main surface; forming a lower insulating film on the first main surface of the semiconductor layer; forming a resistive layer on the lower insulating film; forming an upper insulating film on the lower insulating film so as to cover the resistive layer; and forming a notch in the resistive layer, the notch extending in a predetermined first direction from a portion of a periphery of the resistive layer, by irradiating the resistive layer with laser light through the upper insulating film, wherein the predetermined region is a region that includes at least a region directly below the resistive layer on the first main surface of the semiconductor layer; and the concave-convex structure is formed by forming a plurality of grooves in the predetermined region that extend parallel to the first direction and are equally spaced in a direction along the first main surface and a second direction perpendicular to the first direction.

[0028] This manufacturing method makes it possible to manufacture an electronic component in which appropriate notches are more likely to be formed in the resistance layer.

[0029] DETAILED DESCRIPTION OF EMBODIMENTS OF THE PRESENT DISCLOSURE Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0030] FIG. 1 is a schematic plan view showing an electronic component 1 according to one embodiment of the present invention, in which a resistive layer 10 is incorporated.

[0031] For ease of explanation, the +X direction, −X direction, +Y direction, and −Y direction shown in FIGS. 1 and 2 may be used below. The +X direction is a predetermined direction along the surface of the semiconductor layer 2 in a plan view, and the +Y direction is a direction along the surface of the semiconductor layer 2 in a plan view, and is a direction perpendicular to the +X direction. The −X direction is the direction opposite to the +X direction, and the −Y direction is the direction opposite to the +Y direction. The +X direction and −X direction are referred to collectively simply as the “X direction.” The +Y direction and −Y direction are referred to collectively simply as the “Y direction.”

[0032] The electronic component 1 is a semiconductor device including various functional devices formed using a conductive material or a semiconductor material, or utilizing the properties of the semiconductor material. The electronic component 1 includes a chip-like semiconductor layer 2 formed in a rectangular parallelepiped shape. The semiconductor layer 2 includes a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4.

[0033] The first main surface 3 is a device formation surface. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape (a square shape in this embodiment) in a plan view (hereinafter simply referred to as a “plan view”) seen from the normal direction of the first main surface 3 and the second main surface 4.

[0034] The semiconductor layer 2 may be a Si semiconductor layer containing Si (silicon) as an example of a semiconductor material. The Si semiconductor layer may have a stacked structure including a Si semiconductor substrate and a Si epitaxial layer. The Si semiconductor layer may have a single-layer structure made of a Si semiconductor substrate. In this embodiment, the semiconductor layer 2 is made of a Si semiconductor substrate.

[0035] The semiconductor layer 2 may be a SiC semiconductor layer containing SiC (silicon carbide) as an example of a semiconductor material. The SiC semiconductor layer may have a layered structure including a SiC semiconductor substrate and a SiC epitaxial layer. The SiC semiconductor layer may have a single-layer structure made of a SiC semiconductor substrate.

[0036] The semiconductor layer 2 may be a compound semiconductor layer containing a compound semiconductor material, which is an example of a semiconductor material. The compound semiconductor layer may have a stacked structure including a compound semiconductor substrate and a compound semiconductor epitaxial layer. The compound semiconductor layer may have a single-layer structure made of a compound semiconductor substrate. The compound semiconductor material may be a III-V compound semiconductor material. The semiconductor layer 2 may contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide), which are examples of III-V compound semiconductor materials.

[0037] The semiconductor layer 2 includes a device region 6 and an outer region 7. The device region 6 is a region in which functional devices are formed. The device region 6 is formed in an inner region at a distance from the side surfaces 5A to 5D of the semiconductor layer 2. In this embodiment, the device region 6 is formed in an L-shape in plan view. The planar shape of the device region 6 is arbitrary and is not limited to the planar shape shown in FIG. 1 .

[0038] The functional device is formed in the semiconductor layer 2. More specifically, the functional device is formed by utilizing the first main surface 3 of the semiconductor layer 2 and / or a surface layer portion of the first main surface 3. The functional device may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The passive device may include a semiconductor passive device.

[0039] The passive device (semiconductor passive device) may include at least one of a resistor, a capacitor, and a coil. The semiconductor rectifying device may include at least one of a pn junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode.

[0040] The semiconductor switching device may include at least one of a bipolar junction transistor (BJT), a metal insulator field effect transistor (MISFET), an insulated gate bipolar junction transistor (IGBT), and a junction field effect transistor (JFET).

[0041] The functional devices may include circuitry that selectively combines at least two of passive devices (semiconductor passive devices), semiconductor rectifying devices, and semiconductor switching devices. The circuitry may form part or all of an integrated circuit.

[0042] The integrated circuit may include small scale integration (SSI), large scale integration (LSI), medium scale integration (MSI), very large scale integration (VLSI), and ultra-very large scale integration (ULSI).

[0043] The outer region 7 is a region outside the device region 6. The outer region 7 does not include any functional devices. In this embodiment, the outer region 7 is defined as a region between the side surfaces 5A to 5D of the semiconductor layer 2 and the device region 6. In this embodiment, the outer region 7 is formed in a quadrangular shape in a plan view.

[0044] The planar shape of the outer region 7 is arbitrary and is not limited to the planar shape shown in Fig. 1. The arrangement and planar shape of the outer region 7 are arbitrary and are not limited to the arrangement and planar shape shown in Fig. 1. The outer region 7 may be formed in the center of the first main surface 3 in a plan view.

[0045] In the outer region 7, a resistance circuit 11 including a resistance layer 10 made of a metal thin film is formed at a distance from the first main surface 3 of the semiconductor layer 2. That is, in this embodiment, the resistance circuit 11 (resistance layer 10) is formed so as to avoid the device region 6 in plan view. The resistance circuit 11 (resistance layer 10) is electrically connected to the functional device.

[0046] By disposing the resistance circuit 11 (resistance layer 10) in the outer region 7, it is possible to suppress the electrical influence of the resistance circuit 11 on the device region 6 and to suppress the electrical influence of the device region 6 on the resistance circuit 11. As an example, it is possible to suppress the parasitic capacitance between the device region 6 and the resistance circuit 11. In other words, it is possible to reduce noise and improve the Q value.

[0047] In this embodiment, an example will be described in which the resistance circuit 11 includes one resistance layer 10, but the resistance circuit 11 may include a plurality (two or more) of resistance layers 10. The resistance layer 10 (resistance circuit 11) will be specifically described below with reference to Figures 2 to 5 in addition to Figure 1.

[0048] Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1. Fig. 3 is an enlarged view of region III in Fig. 2. Fig. 4 is a plan view for explaining the planar shape of the resistance layer 10. Fig. 5 is an enlarged plan view showing a part of the first main surface of the semiconductor layer.

[0049] In the device region 6 and the outer region 7, a multilayer wiring structure 12 is formed on the first main surface 3 of the semiconductor layer 2. The multilayer wiring structure 12 has a stacked structure in which a plurality of insulating layers are stacked, and includes a plurality of wiring layers selectively formed within the plurality of insulating layers.

[0050] The multilayer wiring structure 12 includes, for example, a first insulating layer 13, a second insulating layer 14, a third insulating layer 15, and a fourth insulating layer 16 stacked in this order from the first main surface 3 side of the semiconductor layer 2. The terms "first," "second," "third," and "fourth" associated with the first to fourth insulating layers 13 to 16 are used to identify the insulating layers in the figure and are not intended to imply any permutation.

[0051] The number of insulating layers stacked in the multilayer wiring structure 12 is arbitrary and is not limited to the number of layers shown in Fig. 2. Therefore, the multilayer wiring structure 12 may include less than four insulating layers, or may include five or more insulating layers.

[0052] The first to fourth insulating layers 13 to 16 each have a main surface. The main surfaces of the first to fourth insulating layers 13 to 16 are each formed flat. The main surfaces of the first to fourth insulating layers 13 to 16 each extend parallel to the first main surface 3 of the semiconductor layer 2. The main surfaces of the first to fourth insulating layers 13 to 16 may each be ground surfaces. In this embodiment, the fourth insulating layer 16 is an example of an "upper insulating layer" in the present disclosure. The insulating layers 13, 14, and 15 interposed between the semiconductor layer 2 and the fourth insulating layer 16 correspond to a "lower insulating layer" in the present disclosure.

[0053] The first to fourth insulating layers 13 to 16 may each have a stacked structure including a silicon oxide film and a silicon nitride film. In this case, a silicon nitride film may be formed on a silicon oxide film, or a silicon oxide film may be formed on a silicon nitride film.

[0054] The first to fourth insulating layers 13 to 16 may each have a single-layer structure made of a silicon oxide film or a silicon nitride film. The first to fourth insulating layers 13 to 16 are preferably formed of the same insulating material. In this embodiment, the first to fourth insulating layers 13 to 16 each have a single-layer structure made of a silicon oxide film.

[0055] The thickness of each of the first to fourth insulating layers 13 to 16 may be 100 nm or more and 3500 nm or less. The thickness of each of the first to fourth insulating layers 13 to 16 may be 100 nm or more and 500 nm or less, 500 nm or more and 1000 nm or less, 1000 nm or more and 1500 nm or less, 1500 nm or more and 2000 nm or less, 2000 nm or more and 2500 nm or less, 2500 nm or more and 3000 nm or more and 3500 nm or less. The thickness of each of the first to fourth insulating layers 13 to 16 is preferably 100 nm or more and 1500 nm or less. The thicknesses of the first to fourth insulating layers 13 to 16 may be equal to or different from one another.

[0056] In this embodiment, the multilayer wiring structure 12 includes a connection circuit forming layer 21 and a resistance circuit forming layer 22 formed in different layers.

[0057] The connection circuit formation layer 21 is formed on the first main surface 3 side of the semiconductor layer 2. The connection circuit formation layer 21 includes a first insulating layer 13 and a second insulating layer 14. The connection circuit formation layer 21 is a layer whose one purpose is to electrically connect the device region 6 (functional device) and the outer region 7 (resistance circuit 11). The specific structure of the connection circuit formation layer 21 will be described later.

[0058] The resistor circuit formation layer 22 is formed on the connection circuit formation layer 21. The resistor circuit formation layer 22 includes a third insulating layer 15 and a fourth insulating layer 16. One of the purposes of the resistor circuit formation layer 22 is to form the resistor circuit 11 (resistance layer 10) in the outer region 7.

[0059] The resistance circuit 11 includes a first lower wiring layer 31, a second lower wiring layer 32, a resistance layer 10, a first via electrode 41, a second via electrode 42, a first upper wiring layer 51, a second upper wiring layer 52, a first long via electrode 61 and a second long via electrode 62.

[0060] The first lower wiring layer 31 and the second lower wiring layer 32 are arranged on the connection circuit formation layer 21 (second insulating layer 14) at an interval in the X direction. The first lower wiring layer 31 and the second lower wiring layer 32 are covered with the third insulating layer 15.

[0061] In this embodiment, the first lower wiring layer 31 has a laminated structure in which a plurality of electrode layers are laminated, and includes a first barrier layer 33, a main body layer 34, and a second barrier layer 35, which are laminated in this order on the connection circuit-forming layer 21 (fourth insulating layer 16).

[0062] In this embodiment, the first barrier layer 33 has a laminated structure including a Ti layer and a TiN layer laminated in this order on the connection circuit formation layer 21 (second insulating layer 14). The first barrier layer 33 may have a single layer structure made of a Ti layer or a TiN layer.

[0063] The main body layer 34 has a resistance value that is less than the resistance value of the first barrier layer 33 and the resistance value of the second barrier layer 35. The main body layer 34 has a thickness that is greater than the thickness of the first barrier layer 33 and the thickness of the second barrier layer 35. The main body layer 34 may contain at least one of Al, Cu, an AlSiCu alloy, an AlSi alloy, and an AlCu alloy. In this embodiment, the main body layer 34 has a single-layer structure made of an AlCu alloy layer.

[0064] In this embodiment, the second barrier layer 35 has a layered structure including a Ti layer and a TiN layer stacked in this order on the main body layer 34. The second barrier layer 35 may also have a single-layer structure made of a Ti layer or a TiN layer.

[0065] The second lower wiring layer 32 is disposed on the +X side with respect to the second lower wiring layer 32. In this embodiment, the second lower wiring layer 32 has a laminated structure in which a plurality of electrode layers are stacked. The second lower wiring layer 32 includes a first barrier layer 36, a main body layer 37, and a second barrier layer 38, which are stacked in this order from above the connection circuit-forming layer 21 (second insulating layer 14).

[0066] In this embodiment, the first barrier layer 36 has a laminated structure including a Ti layer and a TiN layer laminated in this order on the connection circuit formation layer 21 (second insulating layer 14). The first barrier layer 36 may also have a single layer structure made of a Ti layer or a TiN layer.

[0067] The main body layer 37 has a resistance value that is less than the resistance value of the first barrier layer 36 and the resistance value of the second barrier layer 38. The main body layer 37 has a thickness that is greater than the thickness of the first barrier layer 36 and the thickness of the second barrier layer 38. The main body layer 37 may contain at least one of Al, Cu, an AlSiCu alloy, an AlSi alloy, and an AlCu alloy. In this embodiment, the main body layer 37 has a single-layer structure made of an AlCu alloy layer.

[0068] In this embodiment, the second barrier layer 38 has a layered structure including a Ti layer and a TiN layer stacked in this order on the main body layer 37. The second barrier layer 38 may also have a single-layer structure made of a Ti layer or a TiN layer.

[0069] The resistive layer 10 is disposed on the third insulating layer 15. As shown in Fig. 4 , the resistive layer 10 has a quadrangular shape (rectangular shape) that is long in the X direction in plan view, and has a pair of first opposing sides 101 that are parallel to the X direction and a pair of second opposing sides 102 that are parallel to the Y direction. The resistive layer 10 is disposed so as to straddle the first lower wiring layer 31 and the second lower wiring layer 32 in plan view.

[0070] The resistive layer 10 includes a first end 10a on the −X side, a second end 10b on the +X side, and a connection portion 10c connecting the first end 10a and the second end 10b. The first end 10a of the resistive layer 10 is disposed on the +X side end of the surface of the first lower wiring layer 31. The second end 10b of the resistive layer 10 is disposed on the −X side end of the surface of the second lower wiring layer 32.

[0071] The resistance layer 10 includes one notch 110 formed in the connection portion 10c. The notch 110 extends in a direction (Y direction) intersecting the direction in which the connection portion 10c extends. In this embodiment, the notch 110 extends in the Y direction from one side 101 to the other side 101 of the first opposing sides 101 of the resistance layer 10 that are parallel to the X direction. Note that the notch 110 is omitted in FIGS. 1 to 3.

[0072] The notch 110 is a laser processing mark formed by melting a portion of the connection portion 10c by irradiating the connection portion 10c with laser light. The notch 110 extends the current path of the resistance layer 10, thereby increasing the resistance value of the resistance layer 10. The resistance value of the resistance layer 10 can be adjusted to increase by the notch 110.

[0073] The connecting portion 10c extends in a strip-like shape in the region between the first end 10a and the second end 10b. The connecting portion 10c extends in a strip-like shape along a straight line connecting the first end 10a and the second end 10b. In this embodiment, the first end 10a, the second end 10b, and the connecting portion 10c of the resistive layer 10 are formed with a uniform width.

[0074] The resistive layer 10 is preferably made of a metal thin film containing at least one of CrSi (chromium silicon alloy), CrSiO (chromium silicon oxide alloy), and CrSiN (chromium silicon nitride alloy). It is particularly preferable that the resistive layer 10 contains CrSi. The resistive layer 10 may have a single-layer structure made of a CrSi film, a CrSiO film, or a CrSiN film. In this embodiment, the resistive layer 10 has a single-layer structure made of a CrSi film.

[0075] The resistive layer 10 may be made of a metal thin film containing at least one of CrSi (chromium silicon alloy), TaN (tantalum nitride), and TiN (titanium nitride), or may have a single layer structure made of a TaN film or a TiN film.

[0076] The resistive layer 10 may have a layered structure including a CrSi film and a TaN film stacked in any order. The resistive layer 10 may have a layered structure including a CrSi film and a TiN film stacked in any order. The resistive layer 10 may have a layered structure including a TaN film and a TiN film stacked in any order. The resistive layer 10 may have a layered structure including a CrSi film, a TaN film, and a TiN film stacked in any order.

[0077] The thickness of the resistive layer 10 may be 0.1 nm or more and 100 nm or less. The thickness of the resistive layer 10 may be 0.1 nm or more and 10 nm or less, 10 nm or more and 20 nm or less, 20 nm or more and 30 nm or less, 30 nm or more and 40 nm or less, 40 nm or more and 50 nm or less, 50 nm or more and 60 nm or less, 60 nm or more and 70 nm or less, 70 nm or more and 80 nm or less, 80 nm or more and 90 nm or less, or 90 nm or more and 100 nm or less. The thickness of the resistive layer 10 is preferably 1 nm or more and 20 nm or less.

[0078] The resistive layer 10 is interposed in the region between the third insulating layer 15 and the fourth insulating layer 16. More specifically, the resistive layer 10 is formed in the form of a film on the main surface of the third insulating layer 15. No film-like or layer-like wiring other than the resistive layer 10 is formed on the main surface of the third insulating layer 15 in the device region 6 and the outer region 7. The third insulating layer 15 is provided for the purpose of forming the resistive layer 10.

[0079] By disposing the resistive layer 10 in the outer region 7, it is possible to suppress the electrical influence of the resistive layer 10 on the device region 6 and to suppress the electrical influence of the device region 6 on the resistive layer 10. As an example, it is possible to suppress the parasitic capacitance between the device region 6 and the resistive layer 10. In other words, it is possible to reduce noise and improve the Q value.

[0080] The first via electrode 41 is electrically connected to the resistance layer 10 and the first lower wiring layer 31. The second via electrode 42 is electrically connected to the resistance layer 10 and the second lower wiring layer 32.

[0081] The first via electrode 41 is embedded in the third insulating layer 15 and exposed from the main surface of the third insulating layer 15. The second via electrode 42 is embedded in the third insulating layer 15 at a distance from the first via electrode 41 in the X direction and exposed from the main surface of the third insulating layer 15. The second via electrode 42 is arranged on the +X side with respect to the first via electrode 41.

[0082] An upper end of the first via electrode 41 is electrically connected to a first end 10a of the resistance layer 10. A lower end of the first via electrode 41 is electrically connected to a +X side end of the first lower wiring layer 31. An upper end of the second via electrode 42 is electrically connected to a second end 10b of the resistance layer 10. A lower end of the second via electrode 42 is electrically connected to a −X side end of the second lower wiring layer 32.

[0083] As a result, the resistance layer 10 is electrically connected to the first via electrode 41 and the second via electrode 42. Furthermore, a first end 10a of the resistance layer 10 is electrically connected to the first lower wiring layer 31 through the first via electrode 41. Furthermore, a second end 10b of the resistance layer 10 is electrically connected to the second lower wiring layer 32 through the second via electrode 42. As a result, the resistance layer 10 is connected in series to the first lower wiring layer 31 and the second lower wiring layer 32.

[0084] In this embodiment, the first via electrode 41 is formed in a circular shape in a planar view. The planar shape of the first via electrode 41 is arbitrary. Instead of a circular shape, the first via electrode 41 may be formed in a polygonal shape such as a triangular shape, a rectangular shape, or a hexagonal shape in a planar view, or an elliptical shape. The first via electrode 41 is formed in a tapered shape in a cross-sectional view, the width of which narrows from the upper end to the lower end.

[0085] The first via electrode 41 has a laminated structure including a main body layer 43 and a barrier layer 44. The main body layer 43 is embedded in the third insulating layer 15. The main body layer 43 may contain tungsten (W) or copper (Cu). In this embodiment, the main body layer 43 has a single-layer structure made of a tungsten layer.

[0086] The barrier layer 44 is interposed between the third insulating layer 15 and the main body layer 43. In this embodiment, the barrier layer 44 has a laminated structure in which a plurality of electrode layers are stacked. In this embodiment, the barrier layer 44 includes a Ti layer and a TiN layer formed in this order on the third insulating layer 15. The barrier layer 44 may also have a single-layer structure made of a Ti layer or a TiN layer.

[0087] In this embodiment, the second via electrode 42 is formed in a circular shape in a plan view. The planar shape of the second via electrode 42 is arbitrary. Instead of a circular shape, the second via electrode 42 may be formed in a polygonal shape such as a triangular shape, a rectangular shape, or a hexagonal shape in a plan view, or in an elliptical shape. The second via electrode 42 is formed in a tapered shape in a cross-sectional view, the width of which narrows from the upper end to the lower end.

[0088] The second via electrode 42 has a laminated structure including a main body layer 45 and a barrier layer 46. The main body layer 45 is embedded in the third insulating layer 15. The main body layer 45 may contain tungsten (W) or copper (Cu). In this embodiment, the main body layer 45 has a single-layer structure made of a tungsten layer.

[0089] The barrier layer 46 is interposed between the third insulating layer 15 and the main body layer 45. In this embodiment, the barrier layer 46 has a layered structure in which a plurality of electrode layers are stacked. In this embodiment, the barrier layer 46 includes a Ti layer and a TiN layer formed in this order on the third insulating layer 15. The barrier layer 46 may also have a single-layer structure made of a Ti layer or a TiN layer.

[0090] The first upper wiring layer 51 is formed on the fourth insulating layer 16. The first upper wiring layer 51 forms one of the uppermost wiring layers of the multilayer wiring structure 12. The first upper wiring layer 51 is electrically connected to the first lower wiring layer 31.

[0091] The second upper wiring layer 52 is formed on the fourth insulating layer 16 at a distance in the X direction from the first upper wiring layer 51. In a plan view, the first upper wiring layer 51 is disposed on the −X side with respect to the resistance layer 10, and the second upper wiring layer 52 is disposed on the +X side with respect to the resistance layer 10. The second upper wiring layer 52 forms one of the uppermost wiring layers of the multilayer wiring structure 12. The second upper wiring layer 52 is electrically connected to the second lower wiring layer 32.

[0092] As a result, the resistance layer 10 is electrically connected to the first upper wiring layer 51 via the first lower wiring layer 31. The resistance layer 10 is also electrically connected to the second upper wiring layer 52 via the second lower wiring layer 32. The resistance layer 10 is connected in series to the first upper wiring layer 51 and the second upper wiring layer 52 via the first lower wiring layer 31 and the second lower wiring layer 32.

[0093] The first upper wiring layer 51 is formed at a distance from the resistance layer 10 in a plan view. The first upper wiring layer 51 does not overlap the resistance layer 10 in a plan view. The entire resistance layer 10 is exposed from the first upper wiring layer 51 in a plan view.

[0094] The second upper wiring layer 52 is formed at a distance from the resistance layer 10 in a plan view. The second upper wiring layer 52 does not overlap the resistance layer 10 in a plan view. The entire resistance layer 10 is exposed from the second upper wiring layer 52 in a plan view.

[0095] That is, the resistive layer 10 is formed in a region between the first upper wiring layer 51 and the second upper wiring layer 52 in a plan view. This makes it possible to suppress parasitic capacitance in the region between the resistive layer 10 and the first upper wiring layer 51. Furthermore, it is possible to suppress parasitic capacitance in the region between the resistive layer 10 and the second upper wiring layer 52.

[0096] In this embodiment, the resistive layer 10 is formed at a distance from the first upper wiring layer 51 and the second upper wiring layer 52 in a plan view. This makes it possible to appropriately suppress parasitic capacitance in the region between the resistive layer 10 and the first upper wiring layer 51. Furthermore, it is possible to appropriately suppress parasitic capacitance in the region between the resistive layer 10 and the second upper wiring layer 52.

[0097] The thickness of the first upper wiring layer 51 and the second upper wiring layer 52 may be 100 nm or more and 15,000 nm or less. The thickness of the first upper wiring layer 51 and the second upper wiring layer 52 may be 100 nm or more and 1,500 nm or less, 1,500 nm or more and 3,000 nm or less, 3,000 nm or more and 4,500 nm or less, 4,500 nm or more and 6,000 nm or less, 6,000 nm or more and 7,500 nm or less, 7,500 nm or more and 9,000 nm or less, 9,000 nm or more and 10,500 nm or less, 10,500 nm or more and 12,000 nm or less, 12,000 nm or more and 13,500 nm or less, or 13,500 nm or more and 15,000 nm or less. In this embodiment, the thickness of the first upper wiring layer 51 and the second upper wiring layer 52 is approximately 2,200 nm.

[0098] In this embodiment, the first upper wiring layer 51 has a laminated structure in which a plurality of electrode layers are laminated, including a first barrier layer 53, a main body layer 54, and a second barrier layer 55, which are laminated in this order from above the fourth insulating layer 16.

[0099] In this embodiment, the first barrier layer 53 has a laminated structure including a Ti layer and a TiN layer laminated in this order on the fourth insulating layer 16. The first barrier layer 53 may have a single-layer structure made of a Ti layer or a TiN layer.

[0100] The main body layer 54 has a resistance value that is less than the resistance value of the first barrier layer 53 and the resistance value of the second barrier layer 55. The main body layer 54 has a thickness that is greater than the thickness of the first barrier layer 53 and the thickness of the second barrier layer 55. The main body layer 54 may contain at least one of Al, Cu, an AlSiCu alloy, an AlSi alloy, and an AlCu alloy. In this embodiment, the main body layer 54 has a single-layer structure made of an AlCu alloy layer.

[0101] In this embodiment, the second barrier layer 55 has a layered structure including a Ti layer and a TiN layer stacked in this order on the main body layer 54. The second barrier layer 55 may also have a single-layer structure made of a Ti layer or a TiN layer.

[0102] In this embodiment, the second upper wiring layer 52 has a laminated structure in which a plurality of electrode layers are laminated, and includes a first barrier layer 56, a main body layer 57, and a second barrier layer 58, which are laminated in this order from above the fourth insulating layer 16.

[0103] In this embodiment, the first barrier layer 56 has a layered structure including a Ti layer and a TiN layer stacked in this order on the fourth insulating layer 16. The first barrier layer 56 may also have a single-layer structure made of a Ti layer or a TiN layer.

[0104] The main body layer 57 has a resistance value that is less than the resistance value of the first barrier layer 56 and the resistance value of the second barrier layer 58. The main body layer 57 has a thickness that is greater than the thickness of the first barrier layer 56 and the thickness of the second barrier layer 58. The main body layer 57 may contain at least one of Al, Cu, an AlSiCu alloy, an AlSi alloy, and an AlCu alloy. In this embodiment, the main body layer 57 has a single-layer structure made of an AlCu alloy layer.

[0105] In this embodiment, the second barrier layer 58 has a layered structure including a Ti layer and a TiN layer stacked in this order on the main body layer 57. The second barrier layer 58 may also have a single-layer structure consisting of a Ti layer or a TiN layer.

[0106] The first long via electrode 61 is electrically connected to the first lower wiring layer 31 and the first upper wiring layer 51. The second long via electrode 62 is electrically connected to the second lower wiring layer 32 and the second upper wiring layer 52.

[0107] As a result, the resistance layer 10 is electrically connected to the first upper wiring layer 51 via the first via electrode 41, the first lower wiring layer 31, and the first long via electrode 61. The resistance layer 10 is also electrically connected to the second upper wiring layer 52 via the second via electrode 42, the second lower wiring layer 32, and the second long via electrode 62.

[0108] The first long via electrode 61 is formed on the side (−X side) of the resistance layer 10. In this embodiment, the first long via electrode 61 is located on a straight line connecting the first via electrode 41 and the second via electrode 42.

[0109] The second long via electrode 62 is formed on the side (+X side) of the resistance layer 10 at a distance from the first long via electrode 61 in the X direction. In this embodiment, the second long via electrode 62 faces the first long via electrode 61 across the resistance layer 10. The second long via electrode 62 is located on a straight line connecting the first via electrode 41 and the second via electrode 42.

[0110] As a result, the resistive layer 10 is located on a straight line connecting the first long via electrode 61 and the second long via electrode 62. The resistive layer 10 is located on a straight line connecting the first via electrode 41, the second via electrode 42, the first long via electrode 61, and the second long via electrode 62. In this embodiment, the resistive layer 10 extends along the straight line connecting the first long via electrode 61 and the second long via electrode 62.

[0111] In this embodiment, the first long via electrode 61 is formed in a circular shape in a plan view. The planar shape of the first long via electrode 61 is arbitrary. Instead of a circular shape, the first long via electrode 61 may be formed in a polygonal shape such as a triangular shape, a rectangular shape, or a hexagonal shape, or an elliptical shape in a plan view.

[0112] The first long via electrode 61 penetrates the third insulating layer 15 and the fourth insulating layer 16 to be embedded in the third insulating layer 15 and the fourth insulating layer 16 , and is exposed from the main surface of the fourth insulating layer 16 .

[0113] An upper end of the first long via electrode 61 is electrically connected to the +X direction end of the first upper wiring layer 51. A lower end of the first long via electrode 61 is electrically connected to the −X direction end of the first lower wiring layer 31. The first long via electrode 61 is formed in a tapered shape whose width narrows from the upper end to the lower end in a cross-sectional view.

[0114] The first long via electrode 61 has a laminated structure including a main layer 63 and a barrier layer 64. The main layer 63 is embedded in a third insulating layer 15 and a fourth insulating layer 16. The main layer 63 may contain tungsten (W) or copper (Cu). In this embodiment, the main layer 63 has a single-layer structure made of a tungsten layer.

[0115] The barrier layer 64 is interposed between the main layer 63 and the third insulating layer 15 and between the main layer 63 and the fourth insulating layer 16. In this embodiment, the barrier layer 64 has a laminated structure in which a plurality of electrode layers are stacked. In this embodiment, the barrier layer 64 includes a Ti layer and a TiN layer formed in this order on the third insulating layer 15. The barrier layer may also have a single-layer structure made of a Ti layer or a TiN layer.

[0116] In this embodiment, the second long via electrode 62 is formed in a circular shape in a plan view. The planar shape of the second long via electrode 62 is arbitrary. Instead of a circular shape, the second long via electrode 62 may be formed in a polygonal shape such as a triangular shape, a rectangular shape, or a hexagonal shape, or an elliptical shape in a plan view.

[0117] The second long via electrode 62 penetrates the third insulating layer 15 and the fourth insulating layer 16 to be embedded in the third insulating layer 15 and the fourth insulating layer 16 , and is exposed from the main surface of the fourth insulating layer 16 .

[0118] The upper end of the second long via electrode 62 is electrically connected to the −X side end of the second upper wiring layer 52. The lower end of the second long via electrode 62 is electrically connected to the +X side end of the second lower wiring layer 32. The second long via electrode 62 is formed in a tapered shape whose width narrows from the upper end to the lower end in a cross-sectional view.

[0119] The second long via electrode 62 has a laminated structure including a body layer 65 and a barrier layer 66. The body layer 65 is embedded in the third insulating layer 15 and the fourth insulating layer 16. The body layer 65 may contain tungsten (W) or copper (Cu). In this embodiment, the body layer 65 has a single-layer structure made of a tungsten layer.

[0120] The barrier layer 66 is interposed between the main layer 65 and the third insulating layer 15 and between the main layer 65 and the fourth insulating layer 16. In this embodiment, the barrier layer 66 has a laminated structure in which a plurality of electrode layers are stacked. In this embodiment, the barrier layer 66 includes a Ti layer and a TiN layer formed in this order on the third insulating layer 15. The barrier layer 66 may also have a single-layer structure made of a Ti layer or a TiN layer.

[0121] 2 , the connection circuit formation layer 21 includes wiring 71 that electrically connects the functional device and the resistance layer 10. The wiring 71 is selectively formed in the first insulating layer 13 and the second insulating layer 14, and is routed from the device region 6 to the outer region 7.

[0122] More specifically, the wiring 71 includes one or more connection wiring layers 72 electrically connected to the functional devices in the device region 6. The one or more connection wiring layers 72 are formed on either or both of the first insulating layer 13 and the second insulating layer 14. FIG. 2 shows an example in which two connection wiring layers 72 are formed on the first insulating layer 13.

[0123] One or more connection wiring layers 72 are selectively routed from the device region 6 to the outer region 7. The connection wiring layer 72 has a laminated structure similar to that of the first lower wiring layer 31 (second lower wiring layer 32) and the first upper wiring layer 51 (second upper wiring layer 52). A detailed description of the connection wiring layer 72 will be omitted.

[0124] The wiring 71 includes one or more connection via electrodes 73. The one or more connection via electrodes 73 connect one or more connection wiring layers 72 to any one of the first lower wiring layers 31 (second lower wiring layers 32) or any one of the first upper wiring layers 51 (second upper wiring layers 52).

[0125] One or more connection via electrodes 73 are formed on either or both of the first insulating layer 13 and the second insulating layer 14. In Fig. 2, an example is shown in which one connection wiring layer 72 is connected to the first lower wiring layer 31 by two connection via electrodes 73.

[0126] The connection via electrode 73 has a laminated structure similar to that of the first via electrode 41 (second via electrode 42) and the first long via electrode 61 (second long via electrode 62). A detailed description of the connection via electrode 73 will be omitted.

[0127] 2 , a top insulating layer 81 is formed on the multilayer wiring structure 12. The top insulating layer 81 selectively covers the first upper wiring layer 51 and the second upper wiring layer 52. In a plan view, the top insulating layer 81 covers the connection portion between the first upper wiring layer 51 and the first long via electrode 61. In a plan view, the top insulating layer 81 covers the connection portion between the second upper wiring layer 52 and the second long via electrode 62.

[0128] In the outer region 7, a first pad opening 82 and a second pad opening 83 are formed in the top insulating layer 81. The first pad opening 82 exposes a partial region of the first upper wiring layer 51 as a first pad region 84. More specifically, the first pad opening 82 exposes a region of the first upper wiring layer 51 other than the connection portion between the first upper wiring layer 51 and the first long via electrode 61 as the first pad region 84.

[0129] The second pad opening 83 exposes a partial region of the second upper wiring layer 52 as a second pad region 85. More specifically, the second pad opening 83 exposes a region of the second upper wiring layer 52 other than the connection portion between the second upper wiring layer 52 and the second long via electrode 62 as the second pad region 85.

[0130] In this embodiment, the uppermost insulating layer 81 has a laminated structure including a passivation layer 86 and a resin layer 87. For clarity, the resin layer 87 is shown by hatching in FIG. 1 . The resin layer 87 has an opening 88 for laser trimming, which is used to form a notch 110 in the resistor layer 10, formed in the region between the first upper wiring layer 51 and the second upper wiring layer 52 in a plan view. The opening 88 is formed directly above a region including the connection portion 10c of the resistor layer 10 and its surrounding area.

[0131] The passivation layer 86 may have a layered structure including a silicon oxide film and a silicon nitride film. In this case, the silicon nitride film may be formed on the silicon oxide film, or the silicon oxide film may be formed on the silicon nitride film.

[0132] The passivation layer 86 may have a single layer structure made of a silicon oxide film or a silicon nitride film. The passivation layer 86 is preferably formed of an insulating material different from that of the multilayer wiring structure 12. In this embodiment, the passivation layer 86 has a single layer structure made of a silicon nitride film.

[0133] The resin layer 87 may contain a photosensitive resin. The photosensitive resin may be a positive type or a negative type. In this embodiment, the resin layer 87 contains polyimide, which is an example of a negative type photosensitive resin. The resin layer 87 may also contain polybenzoxazole, which is an example of a positive type photosensitive resin.

[0134] Hereinafter, the direction in which the cutout portion 110 of the resistance layer 10 extends (Y direction in this example) may be referred to as a first direction, and the direction along the main surface of the resistance layer 10 and perpendicular to the first direction (X direction in this example) may be referred to as a second direction. As shown in Figures 2, 3 and 5, a recessed / protruding structure 121 is formed in a region of the first main surface 3 of the semiconductor layer 2 that includes at least a region directly below the resistance layer 10 (hereinafter referred to as a "recessed / protruding region 120"). In this embodiment, the recessed / protruding region 120 is set in a region directly below the resistance layer 10 on the first main surface 3 of the semiconductor layer 2.

[0135] The concave-convex structure 121 includes a plurality of grooves 122 that extend parallel to the first direction (Y direction) at equal intervals in the second direction (X direction), and convex portions 123 that are the portions between adjacent grooves 122.

[0136] The width L of the grooves 122 is preferably 0.2 nm or more and 1 μm or less. The spacing S of the grooves 122 (the width of the convex portions 123) is preferably 0.2 nm or more and 1 μm or less. The width L of the grooves 122 and the spacing S of the grooves 122 are preferably equal. In other words, it is preferable that the width L of the grooves 122 and the spacing S of the grooves 122 are the same, and that the width L of the grooves 122 and the spacing S of the grooves 122 are 0.2 nm or more and 1 μm or less. In this embodiment, the width L of the grooves 122 and the spacing S of the grooves 122 are 0.5 μm.

[0137] The depth of the groove 122 is preferably 100 nm or more and 300 nm or less, and more preferably 150 nm or more and 300 nm or less. In this embodiment, the depth of the groove 122 is 250 nm.

[0138] Note that a region wider than the region directly below the resistance layer 10 on the first main surface 3 of the semiconductor layer 2 may be set as the irregularity formation region 120. For example, a region including the region directly below the resistance layer 10 on the first main surface 3 of the semiconductor layer 2 and a region in the vicinity thereof may be set as the irregularity formation region 120. Furthermore, a region of the first main surface 3 of the semiconductor layer 2 that belongs to the outer region 6 may be set as the irregularity formation region 120.

[0139] 6A to 6S are cross-sectional views for explaining an example of a method for manufacturing the electronic component 1 shown in Fig. 1. Fig. 6A to 6S are cross-sectional views of a portion corresponding to Fig. 2.

[0140] A silicon wafer (not shown) is prepared as the original substrate for the semiconductor layer 2. A plurality of component formation regions corresponding to a plurality of electronic components 1 are arranged in a matrix on the surface of the silicon wafer. Boundary regions (scribe lines) are provided between adjacent component formation regions. The boundary regions are strip-shaped regions with a substantially constant width, and are formed in a grid pattern extending in two perpendicular directions. After the necessary processes are performed on the silicon wafer, the silicon wafer is cut along the boundary regions to obtain a plurality of electronic components 1.

[0141] 6A , in manufacturing electronic component 1, first, semiconductor layer (silicon wafer) 2 is prepared, in which device region 6 and outer region 7 are formed. Then, unevenness structure 121 is formed in unevenness formation region 120 including the region that is to be directly below resistance layer 10 on first main surface 3 of semiconductor layer 2.

[0142] In this step, first, a mask (not shown) having a predetermined pattern is formed on the first main surface 3 of the semiconductor layer 2. The mask has a plurality of openings that expose regions of the first main surface 3 of the semiconductor layer 2 where the plurality of grooves 122 are to be formed.

[0143] Next, unnecessary portions of the semiconductor layer 2 are removed by etching using a mask. As a result, a plurality of grooves 122 are formed in the irregularity formation region 120 on the first main surface 3 of the semiconductor layer 2. As a result, an irregularity structure 121 is formed in the irregularity formation region 120, the irregularity structure including a plurality of grooves 122 extending parallel to the first direction (Y direction) and protrusions 123 between adjacent grooves 122. The mask is then removed.

[0144] Next, a connection circuit formation layer 21 of the multilayer wiring structure 12 is formed on the first main surface 3 of the semiconductor layer 2. The connection circuit formation layer 21 includes a first insulating layer 13, a second insulating layer 14, one or more connection wiring layers 72, and one or more connection via electrodes 73. The first insulating layer 13 and the second insulating layer 14 are planarized by a chemical mechanical polishing (CMP) method using an abrasive (abrasive grains). A detailed description of the process of forming the connection circuit formation layer 21 will be omitted.

[0145] 6B , a first base wiring layer 151, which serves as a base for the first lower wiring layer 31 and the second lower wiring layer 32, is formed on the connection circuit forming layer 21. The step of forming the first base wiring layer 151 includes the steps of forming a first barrier layer 152, a main body layer 153, and a second barrier layer 154 in this order on the connection circuit forming layer 21.

[0146] The step of forming the first barrier layer 152 includes a step of forming a Ti layer and a TiN layer in this order on the connection circuit formation layer 21. The Ti layer and the TiN layer may each be formed by a sputtering method. The step of forming the main body layer 153 includes a step of forming an AlCu alloy layer on the first barrier layer 152. The AlCu alloy layer may be formed by a sputtering method.

[0147] The step of forming the second barrier layer 154 includes the step of forming a Ti layer and a TiN layer in this order on the main body layer 153. The Ti layer and the TiN layer may each be formed by sputtering.

[0148] 6C , a mask 155 having a predetermined pattern is formed on the first base wiring layer 151. The mask 155 covers regions of the first base wiring layer 151 where the first lower wiring layer 31 and the second lower wiring layer 32 are to be formed, and has openings 156 that expose other regions.

[0149] Next, unnecessary portions of the first base wiring layer 151 are removed by etching using the mask 155. This divides the first base wiring layer 151 into the first lower wiring layer 31 and the second lower wiring layer 32. The mask 155 is then removed.

[0150] 6D , a third insulating layer 15 that covers the first lower wiring layer 31 and the second lower wiring layer 32 is formed on the connection circuit formation layer 21. The third insulating layer 15 may be formed by a CVD (Chemical Vapor Deposition) method.

[0151] Next, referring to FIG. 6E, a first via hole 157 exposing the first lower wiring layer 31 and a second via hole 158 exposing the second lower wiring layer 32 are formed in the third insulating layer 15 .

[0152] In this step, first, a mask 159 having a predetermined pattern is formed on the third insulating layer 15. The mask 159 has a plurality of openings 160 that expose regions of the third insulating layer 15 where the first via holes 157 and the second via holes 158 are to be formed.

[0153] Next, unnecessary portions of the third insulating layer 15 are removed by etching through the mask 159. As a result, a first via hole 157 and a second via hole 158 are formed in the third insulating layer 15. The mask 159 is then removed.

[0154] 6F , a base electrode layer 161 that serves as a base for the first via electrode 41 and the second via electrode 42 is formed on the third insulating layer 15. The step of forming the base electrode layer 161 includes the steps of forming a barrier layer 162 and a main body layer 163 in this order on the third insulating layer 15.

[0155] The step of forming the barrier layer 162 includes a step of forming a Ti layer and a TiN layer in this order on the third insulating layer 15. The Ti layer and the TiN layer may each be formed by a sputtering method. The step of forming the main body layer 163 includes a step of forming a tungsten layer on the barrier layer 162. The tungsten layer may be formed by a CVD method.

[0156] 6G, a step of removing the base electrode layer 161 is performed. The base electrode layer 161 is removed until the third insulating layer 15 is exposed. The step of removing the base electrode layer 161 may include a step of removing the base electrode layer 161 by grinding.

[0157] In this embodiment, the grinding step of the base electrode layer 161 is performed by a chemical mechanical polishing (CMP) method using an abrasive (abrasive grains). The grinding step of the base electrode layer 161 may include a step of planarizing the main surface of the third insulating layer 15. As a result, the first via electrode 41 is formed in the first via hole 157. Furthermore, the second via electrode 42 is formed in the second via hole 158.

[0158] 6H , the abrasive (abrasive grains) adhering to the main surface of third insulating layer 15 is removed by cleaning with a chemical solution. In this step, a portion of third insulating layer 15 is removed by the chemical solution together with the abrasive (abrasive grains).

[0159] 6I, a base resistor layer 164, which serves as a base for the resistor layer 10, is formed on the main surface of the third insulating layer 15. The base resistor layer 164 includes CrSi. The base resistor layer 164 may be formed by a sputtering method.

[0160] Next, the base resistor layer 164 (CrSi) is crystallized. The crystallization process of the base resistor layer 164 includes annealing the base resistor layer 164 (CrSi) at a temperature and for a time period that crystallizes the base resistor layer 164. The base resistor layer 164 may be heated at a temperature of 400° C. to 600° C. for a period of 60 minutes to 120 minutes.

[0161] 6J, a mask 166 having a predetermined pattern is formed on the base resistor layer 164. The mask 166 covers the region of the base resistor layer 164 where the resistor layer 10 is to be formed, and has openings 167 that expose the other regions.

[0162] Next, unnecessary portions of the base resistor layer 164 are removed by etching using the mask 166 as a mask, thereby forming the resistor layer 10. The mask 166 is then removed.

[0163] 6K, a fourth insulating layer 16 covering the resistive layer 10 is formed on the third insulating layer 15. The fourth insulating layer 16 may be formed by a CVD method.

[0164] Next, referring to FIG. 6L, a first via hole 168 exposing the first lower wiring layer 31 and a second via hole 169 exposing the second lower wiring layer 32 are formed in the third insulating layer 15 and the fourth insulating layer 16.

[0165] In this process, first, a mask 170 having a predetermined pattern is formed on the fourth insulating layer 16. The mask 170 has a plurality of openings 171 that expose areas of the fourth insulating layer 16 where the first via hole 168 and the second via hole 169 are to be formed.

[0166] Next, unnecessary portions of the third insulating layer 15 and the fourth insulating layer 16 are removed by etching using the mask 170. As a result, a first via hole 168 and a second via hole 169 are formed in the third insulating layer 15 and the fourth insulating layer 16. The mask 170 is then removed.

[0167] 6M , a base electrode layer 172 serving as a base for the first long via electrode 61 and the second long via electrode 62 is formed on the fourth insulating layer 16. The process of forming the base electrode layer 172 includes a process of forming a barrier layer 173 and a main body layer 174 in this order on the fourth insulating layer 16.

[0168] The step of forming the barrier layer 173 includes a step of forming a Ti layer and a TiN layer in this order on the fourth insulating layer 16. The Ti layer and the TiN layer may each be formed by a sputtering method. The step of forming the main body layer 174 includes a step of forming a tungsten layer on the barrier layer 173. The tungsten layer may be formed by a CVD method.

[0169] 6N, a step of removing the base electrode layer 172 is performed. The base electrode layer 172 is removed until the fourth insulating layer 16 is exposed. The step of removing the base electrode layer 172 may include a step of removing the base electrode layer 172 by grinding.

[0170] In this embodiment, the grinding process of the base electrode layer 172 is performed by a CMP method using an abrasive (abrasive grains). The grinding process of the base electrode layer 172 may include a planarization process of the main surface of the fourth insulating layer 16. As a result, the first long via electrode 61 and the second long via electrode 62 are formed in the first via hole 168 and the second via hole 169, respectively.

[0171] After the grinding process of the base electrode layer 172, the abrasive (abrasive grains) adhering to the main surface of the fourth insulating layer 16 may be removed by cleaning with a chemical solution. A part of the fourth insulating layer 16 may be removed together with the abrasive (abrasive grains) by the chemical solution.

[0172] 6O , a second base wiring layer 175, which serves as a base for the first upper wiring layer 51 and the second upper wiring layer 52, is formed on the fourth insulating layer 16. The step of forming the second base wiring layer 175 includes the steps of forming a first barrier layer 176, a main body layer 177, and a second barrier layer 178 in this order on the fourth insulating layer 16.

[0173] The step of forming the first barrier layer 176 includes a step of forming a Ti layer and a TiN layer in this order on the fourth insulating layer 16. The Ti layer and the TiN layer may each be formed by a sputtering method. The step of forming the main body layer 177 includes a step of forming an AlCu alloy layer on the first barrier layer 176. The AlCu alloy layer may be formed by a sputtering method.

[0174] The step of forming the second barrier layer 178 includes the step of forming a Ti layer and a TiN layer in this order on the main body layer 177. The Ti layer and the TiN layer may each be formed by sputtering.

[0175] 6P, a mask 179 having a predetermined pattern is formed on the second base wiring layer 175. The mask 179 covers the regions of the second base wiring layer 175 in the outer region 7 where the first upper wiring layer 51 and the second upper wiring layer 52 are to be formed, and has openings 180 that expose the other regions.

[0176] Next, unnecessary portions of the second base wiring layer 175 are removed by etching using the mask 179. This divides the second base wiring layer 175 into the first upper wiring layer 51 and the second upper wiring layer 52. This also forms a multilayer wiring structure 12 including the connection circuit formation layer 21 and the resistor circuit formation layer 22 on the first main surface 3 of the semiconductor layer 2. The mask 179 is then removed.

[0177] 6Q, a passivation layer 86 is formed on the multilayer wiring structure 12. The passivation layer 86 includes silicon nitride. The passivation layer 86 may be formed by a CVD method.

[0178] Next, a resin layer 87 is applied onto the passivation layer 86. The resin layer 87 may contain polyimide, which is an example of a negative-type photosensitive resin.

[0179] 6R, the resin layer 87 is selectively exposed to light and then developed, thereby forming an opening 88 for laser trimming and a plurality of openings 181 that serve as bases for the first pad opening 82 and the second pad opening 83 in the resin layer 87.

[0180] 6S, unnecessary portions of the passivation layer 86 are removed by etching via the resin layer 87. This forms a first pad opening 82 and a second pad opening 83 that expose the first upper wiring layer 51 and the second upper wiring layer 52, respectively.

[0181] After this, notches 110 are formed in the resistive layer 10 by laser trimming. In this process, laser light is irradiated from the openings 88 in the resin layer 87 toward the resistive layer 10. The laser light is then scanned in a first direction (Y direction), thereby forming notches in the resistive layer 10. When the resistance value reaches the target resistance value, trimming is stopped. The electronic component 1 is manufactured through the processes including those described above.

[0182] An electronic component having almost the same configuration as this embodiment will be referred to as a reference example, in which, in the outer region 7 where the resistance circuit 11 is formed, the uneven structure 121 is not formed in a predetermined region (unevenness-forming region 120) including the region directly below the resistance layer 10 on the first main surface 3 of the semiconductor layer 2. In the reference example, in the outer region 7 where the resistance circuit 11 is formed, the first main surface of the semiconductor layer 2 is formed as a flat surface over the entire region.

[0183] In the reference example, during laser trimming, the incident laser light interferes with the light reflected from the first main surface 3 of the semiconductor layer 2. As a result, areas of high electric field strength and areas of low electric field strength appear alternately in the thickness direction within the multilayer wiring structure 12. The height positions where the electric field strength is high and the height positions where the electric field strength is low are determined by the wavelength of the laser light and the materials (refractive index) of the members constituting the multilayer wiring structure 12.

[0184] To form the notch 110 in the resistive layer 10, the resistive layer 10 needs to be positioned in the multilayer wiring structure 12 at a thickness-wise position where the electric field strength is high. However, because there is variation in the film thickness of the insulating layer (lower insulating layer) between the semiconductor layer 2 and the resistive layer 10 within the wafer surface, there is also variation in the distance between the resistive layer 10 and the semiconductor layer 2 in each component formation region. As a result, among the multiple component formation regions on the wafer surface, the resistive layer 10 is positioned at a position where the electric field strength is low, and in some cases the notch 110 cannot be formed in the resistive layer 10.

[0185] In this embodiment, a concave-convex structure 121 is formed in a concave-convex formation region 120 including a region directly below the resistance layer 10 on the first main surface 3 of the semiconductor layer 2. The concave-convex structure 121 includes a plurality of grooves 122 that are equally spaced apart in the second direction (X direction) and extend parallel to the first direction (Y direction), and a convex portion 123 that is a portion between two adjacent grooves 122. This distributes the intensity of the electric field within the multilayer wiring structure 12 during laser trimming, and therefore, the proportion of electronic components in which an appropriate cutout 110 cannot be formed can be reduced among all electronic components cut out from one wafer.

[0186] In order to confirm the effect of this embodiment, the following experiment was carried out.

[0187] First, a plurality of samples were prepared corresponding to a plurality of types of resistor components having substantially the same structure as that shown in Fig. 2 but different uneven structures in the unevenness-forming region 120. However, the resistive layer 10 used had lengths of 50 µm in the X and Y directions. In addition, the region directly below the resistive layer 10 on the first main surface 3 of the semiconductor layer 2 was set as the unevenness-forming region 120A.

[0188] Samples corresponding to a certain type of resistor component were created by preparing a wafer with multiple component formation areas and fabricating the corresponding type of resistor component in each component formation area. Specifically, the following samples 1 to 13 were prepared.

[0189] 7, the concave-convex structure 121A is composed of one recess 130 formed in the concave-convex region 120A. The planar area of ​​the recess 130 is approximately equal to the planar area of ​​the concave-convex region 120A. The depth of the recess 130 is 250 nm.

[0190] As shown in FIG. 8 , the concave-convex structure 121B has a plurality of first grooves 131 extending parallel to the X direction at equal intervals in the Y direction, a plurality of second grooves 132 extending parallel to the Y direction at equal intervals in the X direction, and a plurality of convex portions 133 having a square shape in plan view and surrounded by the first grooves 131 and the second grooves 132. The distance between two adjacent first grooves 131 is equal to the distance between two adjacent second grooves 132. The depth of the first grooves 131 and the second grooves 132 is 250 nm. The differences between the second to seventh samples are as follows:

[0191] Second sample: In plan view, the length of one side of the convex portion 133 is 1 μm, and the ratio of the total area of ​​the upper surfaces of the convex portions 133 to the entire concave-convex forming region 80 is 75%.

[0192] Third sample: In plan view, the length of one side of the convex portion 133 is 1 μm, and the ratio of the total area of ​​the upper surfaces of the convex portions 133 to the entire concave-convex forming region 80 is 50%.

[0193] Fourth sample: In plan view, the length of one side of the convex portion 133 is 1 μm, and the ratio of the total area of ​​the upper surfaces of the convex portions 133 to the entire concave-convex region 80 is 25%.

[0194] Fifth sample: In plan view, the length of one side of the convex portion 133 is 0.5 μm, and the ratio of the total area of ​​the upper surfaces of the convex portions 133 to the entire concave-convex region 80 is 50%.

[0195] Sixth sample: In plan view, the length of one side of the convex portion 133 is 0.5 μm, and the ratio of the total area of ​​the upper surfaces of the convex portions 133 to the entire concave-convex region 80 is 25%.

[0196] Seventh sample: In plan view, the length of one side of the convex portion 133 is 0.35 μm, and the ratio of the total area of ​​the upper surfaces of the convex portions 133 to the entire concave-convex region 80 is 37%.

[0197] Eighth and ninth samples: As shown in FIG. 9 , the unevenness 121C has a plurality of first grooves 134 extending parallel to the X direction at equal intervals in the Y direction, a plurality of second grooves 135 extending parallel to the Y direction at equal intervals in the X direction, and a plurality of convex portions 136 that are circular in plan view and surrounded by the first grooves 134 and the second grooves 135. The distance between two adjacent first grooves 134 is equal to the distance between two adjacent second grooves 135. The multiple convex portions 136 are arranged at equal intervals in the X direction and the Y direction. The depth of the first grooves 134 and the second grooves 135 is 250 nm. The differences between the eighth to ninth samples are as follows.

[0198] Eighth sample: In plan view, the diameter of the convex portion 136 is 1 μm, and the distance between two convex portions 136 adjacent to each other in the X direction (the distance between two convex portions 136 adjacent to each other in the Y direction) is 0.5 μm.

[0199] Ninth sample: In plan view, the diameter of the convex portion 136 is 1 μm, and the distance between two convex portions 136 adjacent to each other in the X direction (the distance between two convex portions 136 adjacent to each other in the Y direction) is 0.26 μm.

[0200] Tenth and eleventh samples: As shown in Fig. 10, the concave-convex structure 121D is composed of a plurality of grooves 141 that are equally spaced in the first direction (Y direction) and extend parallel to the second direction (X direction), and convex portions 142 that are the portions between two adjacent grooves 141. The depth of the grooves 141 is 250 nm. The differences between the tenth to eleventh samples are as follows.

[0201] Tenth sample: The width L of the groove 141 and the interval S between the grooves 141 (the width of the convex portion 142) are 1 μm.

[0202] Eleventh sample: The width L of the groove 141 and the interval S between the grooves 141 (the width of the convex portion 142) are 0.5 μm.

[0203] 11, the concave-convex structure 121E is composed of a plurality of grooves 143 extending parallel to the first direction (Y direction) at equal intervals in the second direction (X direction), and a convex portion 144 between two adjacent grooves 143, similar to the concave-convex structure 121 of the present embodiment. The depth of the groove 143 is 250 nm. The differences between the twelfth to thirteenth samples are as follows.

[0204] Twelfth sample: The width L of the groove 143 and the interval S between the grooves 143 (the width of the convex portion 144) are 1 μm.

[0205] Thirteenth sample: The width L of the groove 143 and the interval S between the grooves 143 (the width of the convex portion 144) are 0.5 μm.

[0206] For each of the plurality of resistor components preselected for each sample, a laser beam was irradiated perpendicularly to the center of the length of the main surface of the resistor layer 10 in the second direction (X direction), and the laser beam was scanned in the first direction (Y direction). Whether the resistor layer 10 was successfully cut was determined based on whether the resistance value changed. The wavelength of the laser beam was 1064 nm.

[0207] For the first, twelfth and thirteenth samples, 20 preselected resistor components were examined to see if the resistor layer 10 could be cut.

[0208] For the second to eleventh samples, six pre-selected resistor components were examined to see if the resistor layer 10 could be cut.

[0209] The results of each evaluation were as follows:

[0210] First sample: In all 20 samples, the resistive layer 10 could not be cut (20NG / 20).

[0211] Second sample: In three out of six samples, the resistive layer 10 could not be cut (3NG / 6).

[0212] Third to seventh samples: In six out of six samples, the resistive layer 10 could not be cut (6NG / 6).

[0213] Eighth sample: In five out of six samples, the resistive layer 10 could not be cut (5NG / 6).

[0214] Ninth sample: In six out of six samples, the resistive layer 10 could not be cut (6NG / 6).

[0215] Tenth sample: In five out of six samples, the resistive layer 10 could not be cut (5NG / 6).

[0216] Eleventh sample: In six out of six samples, the resistive layer 10 could not be cut (6NG / 6).

[0217] Twelfth sample: In 11 out of 20 samples, the resistive layer 10 could not be cut (11NG / 20).

[0218] Thirteenth sample: In one out of 20 samples, the resistive layer 10 could not be cut (1 NG / 20).

[0219] From the above results, it can be seen that the 12th and 13th samples had a lower ratio of resistive components whose resistive layer 10 could not be cut to the total number of components to be inspected than the other 1st to 11th samples.

[0220] In other words, if the cutting direction for the resistive layer 10 is defined as the first direction (Y direction), and the direction along the main surface of the resistive layer 10 that is perpendicular to the first direction is defined as the second direction (X direction), it can be seen that by forming a plurality of grooves 141 extending in the first direction (Y direction) at intervals in the second direction (X direction) in the unevenness forming region 120, the proportion of resistive components whose resistive layer 10 cannot be cut can be reduced.

[0221] It can also be seen that the proportion of resistor components whose resistive layer 10 cannot be cut can be reduced more when the width L and spacing S of the grooves 141 are set to 0.5 μm than when they are set to 1 μm.

[0222] That is, according to this embodiment, it is possible to reduce the proportion of electronic components in which the appropriate notch 110 cannot be formed, out of all the electronic components cut out from one wafer.

[0223] Although the embodiments of the present disclosure have been described in detail, these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be construed as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims.

[0224] This application corresponds to Patent Application No. 2022-52630 filed with the Japan Patent Office on March 28, 2022, the entire disclosures of which are incorporated herein by reference.

[0225] 1 Electronic component 2 Semiconductor layer 3 First main surface 4 Second main surface 5A to 5D Side surface 6 Device region 7 Outer region 10 Resistive layer 10a First end 10b Second end 10c Connection portion 11 Resistive circuit 12 Multilayer wiring structure 13 to 16 First to fourth insulating layers 21 Connection circuit forming layer 22 Resistive circuit forming layer 31 First lower wiring layer 32 Second lower wiring layer 33 First barrier layer 34 Main body layer 35 Second barrier layer 36 First barrier layer 37 Main body layer 38 Second barrier layer 41 First via electrode 42 Second via electrode 43 Main body layer 44 Barrier layer 45 Main body layer 46 Barrier layer 51 First upper wiring layer 52 Second upper wiring layer 61 First long via electrode 62 Second long via electrode 71 Wiring 72 Connection wiring layer 73 Connection via electrode 81 Top insulating layer 82 First pad opening 83 Second pad opening 84 First pad region 85 Second pad region 86 Passivation layer 87 Resin layer 88 Opening 101 First opposing edge 102 Second opposing edge 110 Notch 120, 120A Relief formation region 121, 121A to 121E Relief structure 122 Groove 123 Convex portion 130 Convex portion 131, 132, 134, 135, 141, 143 Groove 133, 136, 142, 144 Convex portion 151 First base wiring layer 152 First barrier layer 153 Main body layer 154 Second barrier layer 155 Mask 156 Opening 157 First via hole 158 Second via hole 159 Mask 160 Opening 161 Base electrode layer 162 Barrier layer 163 Main body layer 164 Base resistor layer 166 Mask 167 Opening 168 First via hole 169 Second via hole 170 Mask 171 Opening 172 Base electrode layer 173 Barrier layer 174 Main body layer 175 Second base wiring layer 176 First barrier layer 177 Main body layer 178 Second barrier layer 179 Mask 180 Opening

Claims

1. a semiconductor layer having a first major surface and an opposite second major surface; a lower insulating layer formed on the first major surface of the semiconductor layer; a resistive layer formed on the lower insulating layer and having a notch extending from a portion of its periphery in a predetermined first direction; an upper insulating layer formed on the lower insulating layer so as to cover the resistive layer; a concave-convex structure formed in a predetermined region including at least a region immediately below the resistance layer on the first main surface of the semiconductor layer, The uneven structure includes a plurality of grooves arranged at equal intervals in a direction along the first main surface and in a second direction perpendicular to the first direction, the grooves extending parallel to the first direction, and a convex portion between two adjacent grooves.

2. the resistance layer has a quadrangular shape in a plan view having first opposing sides consisting of two sides parallel to the second direction and second opposing sides consisting of two sides parallel to the first direction, The electronic component according to claim 1 , wherein the cutout portion extends from a midpoint of one of the first opposing sides toward the other of the first opposing sides.

3. a first via electrode embedded in the lower insulating layer, the upper end of the first via electrode being connected to a portion of the resistance layer near one of the second opposing sides; The electronic component according to claim 2 , further comprising: a second via electrode embedded in the lower insulating layer, the upper end of the second via electrode being connected to a portion of the resistive layer closer to the other of the second opposing sides.

4. a first lower wiring layer formed in a region on the lower insulating layer side with respect to the resistive layer and electrically connected to the first via electrode; The electronic component according to claim 3 , further comprising: a second lower wiring layer formed in a region on the lower insulating layer side with respect to the resistive layer and electrically connected to the second via electrode.

5. the first lower wiring layer extends from an inner side to an outer side of the resistance layer with respect to one of the second opposing sides in a plan view, the second lower wiring layer extends from an inner side to an outer side of the resistance layer with respect to the other side of the second opposing sides in a plan view, The electronic component according to claim 4 , wherein the first lower wiring layer and the second lower wiring layer are disposed at an interval in the second direction in a plan view.

6. The electronic component according to claim 5 , wherein the resistive layer is connected in series to the first lower wiring layer and the second lower wiring layer.

7. a first upper wiring layer formed on the upper insulating layer and electrically connected to the first lower wiring layer; 7. The electronic component according to claim 6, further comprising: a second upper wiring layer formed on said upper insulating layer and electrically connected to said second lower wiring layer.

8. The electronic component according to claim 7 , wherein the resistive layer is connected in series to the first upper wiring layer and the second upper wiring layer.

9. a first long via electrode that penetrates the upper insulating layer and a portion of the lower insulating layer and is electrically connected to the first lower wiring layer and the first upper wiring layer; The electronic component according to claim 8 , further comprising: a second long via electrode that penetrates the upper insulating layer and a portion of the lower insulating layer and is electrically connected to the second lower wiring layer and the second upper wiring layer.

10. The electronic component according to claim 9 , wherein the resistive layer is located on a straight line connecting the first long via electrode and the second long via electrode in a plan view.

11. the semiconductor layer includes a device region in which a functional device is formed and an outer region outside the device region; The electronic component according to claim 1 , wherein the resistive layer is formed in the outer region in a plan view.

12. 11. The electronic component according to claim 1, wherein the resistive layer is made of a metal thin film containing at least one of CrSi, CrSiO, and CrSiN.

13. The depth of the groove is 100 nm or more and 300 nm or less, The electronic component according to any one of claims 1 to 10, wherein the width of the groove and the spacing between the grooves are 0.2 µm or more and 1 µm or less.

14. The depth of the groove is 150 nm or more and 300 nm or less, The electronic component according to any one of claims 1 to 10, wherein the width of the groove and the spacing between the grooves are 0.2 µm or more and 1 µm or less.

15. the lower insulating layer includes a plurality of stacked lower silicon oxide films; 11. The electronic component according to claim 1, wherein the upper insulating layer includes an upper silicon oxide film formed on the lower insulating layer so as to cover the resistive layer.

16. forming a concave-convex structure in a predetermined region of a first main surface of a semiconductor layer having a first main surface and a second main surface opposite to the first main surface; forming a lower insulating layer on the first major surface of the semiconductor layer; forming a resistive layer on the lower insulating layer; forming an upper insulating layer on the lower insulating layer so as to cover the resistive layer; forming a notch in the resistive layer, the notch extending in a first direction from a portion of a periphery of the resistive layer by irradiating the resistive layer with laser light through the upper insulating layer; the predetermined region includes at least a region immediately below the resistance layer on the first main surface of the semiconductor layer, A method for manufacturing an electronic component, in which, in the step of forming the uneven structure, the uneven structure is formed by forming a plurality of grooves in the specified region, the grooves extending parallel to the first direction, at equal intervals in a direction along the first main surface and in a second direction perpendicular to the first direction.