Semiconductor light emitting device

Abstract

This semiconductor light emitting device comprises: a substrate that has a first principal surface on one side and a second principal surface on the other side; a plurality of via electrodes embedded in the substrate at intervals such that the occupying ratio with respect to the surface area of the first principal surface in plan view is 10%-60%; an electrode membrane collectively covering the plurality of via electrodes on the first principal surface; and a semiconductor light emitting chip disposed on the electrode membrane so as to face the plurality of via electrodes.

Description

Semiconductor light-emitting device Related Applications

[0001] This application corresponds to Patent Application No. 2022-061325 filed with the Japan Patent Office on March 31, 2022, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor light emitting devices.

[0003] Patent Document 1 discloses a semiconductor light-emitting device including a substrate, a plurality of first plated conductive portions, a plurality of second plated conductive portions, a first intermediate conductive portion, a second intermediate conductive portion, a third plated conductive portion, a fourth plated conductive portion, and a plurality of LED chips. The semiconductor light-emitting device of Patent Document 1 further includes first plated wiring and second plated wiring. Each of the first plated wiring and the second plated wiring extends from a first edge of the substrate to a second edge of the substrate. When viewed in the thickness direction, the plurality of LED chips are sandwiched between the first plated wiring and the second plated wiring in the first direction. The first plated wiring and the second plated wiring are interposed between the surface of the substrate and a frame portion of the substrate. When viewed in the thickness direction, the first plated wiring and the second plated wiring are located away from a recess in the substrate.

[0004] Japanese Patent Application Laid-Open No. 2022-33187

[0005] An embodiment of the present disclosure provides a semiconductor light emitting device capable of improving heat dissipation.

[0006] A semiconductor light-emitting device according to one embodiment of the present disclosure includes a substrate having a first main surface on one side and a second main surface on the other side, a plurality of via electrodes embedded in the substrate at intervals so that their occupancy rate relative to the surface area of ​​the first main surface is 10% or more and 60% or less in a planar view, an electrode film that collectively covers the plurality of via electrodes on the first main surface, and a semiconductor light-emitting chip arranged on the electrode film so as to face the plurality of via electrodes.

[0007] FIG. 1 is a schematic plan view of a semiconductor light emitting device according to an embodiment of the present disclosure. FIG. 2 is a schematic bottom view of the semiconductor light emitting device. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1. FIG. 4A is a plan view of the semiconductor light emitting device showing a first via arrangement pattern. FIG. 4B is a bottom view of the semiconductor light emitting device showing the first via arrangement pattern. FIG. 5A is a plan view of the semiconductor light emitting device showing a second via arrangement pattern. FIG. 5B is a bottom view of the semiconductor light emitting device showing the second via arrangement pattern. FIG. 6A is a plan view of the semiconductor light emitting device showing a third via arrangement pattern. FIG. 6B is a bottom view of the semiconductor light emitting device showing the third via arrangement pattern. FIG. 7A is a plan view of the semiconductor light emitting device showing a fourth via arrangement pattern. FIG. 7B is a bottom view of the semiconductor light emitting device showing the fourth via arrangement pattern. FIG. 8A is a plan view of the semiconductor light emitting device showing a fifth via arrangement pattern. FIG. 8B is a bottom view of the semiconductor light emitting device showing the fifth via arrangement pattern. FIG. 9 is a graph showing the relationship between via area ratio and heat dissipation performance. Fig. 10 is a diagram showing the relationship between the thickness of the substrate and the heat dissipation performance, and Fig. 11 is a diagram showing the relationship between the thickness of the electrode film and the heat dissipation performance.

[0008] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. [Overall Structure of Semiconductor Light-Emitting Device 1] Fig. 1 is a schematic plan view of a semiconductor light-emitting device 1 according to one embodiment of the present disclosure. Fig. 2 is a schematic bottom view of the semiconductor light-emitting device 1. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1.

[0009] The semiconductor light emitting device 1 includes a case 2, a semiconductor light emitting chip 3, a diode chip 4, and a sealing resin 5. For ease of understanding, the sealing resin 5 is omitted from Fig. 1 .

[0010] The case 2 is the base of the semiconductor light-emitting device 1 and includes a substrate 6 as an example of a substrate, and wiring 7. The size of the case 2 is approximately 5 to 10 mm square in a plan view, and a thickness T1 (the thickness between the first main surface 9 and the second main surface 10) of 50 μm to 500 μm. The substrate 6 is a thick plate that is generally rectangular in a plan view, and is made of, for example, a resin substrate or a ceramic substrate such as alumina. In this embodiment, a resin substrate is used as the substrate 6, and preferably a build-up substrate (multilayer substrate) made of resin is used. A resin substrate can reduce costs compared to a ceramic substrate.

[0011] An accommodating recess 8 is formed in the center of the substrate 6. The accommodating recess 8 accommodates the semiconductor light emitting chip 3 and the diode chip 4, and has a rectangular shape in a plan view. The substrate 6 has a first main surface 9 and a second main surface 10. In this embodiment, the depth of the accommodating recess 8 is, for example, about 500 μm.

[0012] The wiring 7 is used as a path for supplying DC power to the semiconductor light-emitting chip 3. The wiring 7 has a surface layer 11 as an example of an electrode film, an intermediate layer 12, a back layer 13, and a through wiring 14.

[0013] The surface layer 11 includes a plurality of anode pads 15 and a plurality of cathode pads 16. Referring to Fig. 1, the plurality of anode pads 15 and the plurality of cathode pads 16 are arranged as sets of adjacent pairs of anode pads 15 and cathode pads 16, respectively. The plurality of anode pads 15 and the plurality of cathode pads 16 may include a set of a first anode pad 17 and a first cathode pad 18, and a set of a second anode pad 19 and a second cathode pad 20. In this embodiment, the first anode pad 17 and the first cathode pad 18 may be used to mount the semiconductor light-emitting chip 3, and the second anode pad 19 and the second cathode pad 20 may be used to mount the diode chip 4.

[0014] The first cathode pad 18 includes a cathode island portion 21 to which the semiconductor light-emitting chip 3 is die-bonded, and a cathode extension portion 22 extending from the cathode island portion 21. The cathode island portion 21 is formed approximately in the center of the first main surface 9 of the substrate 6. The cathode extension portion 22 is integrally connected to the cathode island portion 21. In FIG. 1 , the cathode extension portion 22 is formed in a substantially L-shape in plan view. The cathode extension portion 22 has linear portions 23 extending along the first and second peripheral edges of the substrate 6. In this embodiment, a pair of cathode extension portions 22 are formed extending from the cathode island portion 21 in opposite directions (directions along the third and fourth peripheral edges of the substrate 6). Diode regions 24 for the second anode pad 19 and the second cathode pad 20 are defined between the pair of cathode extension portions 22 (linear portions 23).

[0015] The first anode pad 17 includes an anode pad portion 25 to which a wiring 7 member (for example, a wire 44 described later) extending from the semiconductor light-emitting chip 3 is joined, and an anode extension portion 26 extending from the anode pad portion 25. The anode pad portion 25 is formed linearly along the third peripheral edge of the substrate 6 on the side of the cathode island portion 21. The anode extension portion 26 includes a pair of linear anode extension portions 26 extending from the anode pad portion 25 along the first and second peripheral edges of the substrate 6. The anode extension portion 26 is formed adjacent to the cathode extension portion 22 so as to be positioned on the same straight line as the linear portion 23 of the cathode extension portion 22.

[0016] The second anode pad 19 and the second cathode pad 20 are disposed in the diode region 24. The second anode pad 19 and the second cathode pad 20 are both formed in an island shape, and are formed along the fourth peripheral edge of the substrate 6 at intervals from each other.

[0017] 3, the surface layer 11 may be formed of a plurality of conductive layers. In this embodiment, the surface layer 11 includes a first conductive layer 27 and a second conductive layer 28. The first conductive layer 27 may be made of, for example, Cu and may be a Cu-plated layer. The second conductive layer 28 may be made of, for example, Au and may be an Au-plated layer. The first conductive layer 27 has a thickness T2 of, for example, 10 μm or more and 200 μm or less. The second conductive layer 28 has a thickness T3.

[0018] 3 , the intermediate layer 12 is formed between the first main surface 9 and the second main surface 10 in the thickness direction of the substrate 6. The intermediate layer 12 is made of, for example, Cu. The intermediate layer 12 includes a first relay wiring 29 and a second relay wiring 30. The first relay wiring 29 is electrically connected to the first anode pad 17 and the first cathode pad 18. The second relay wiring 30 is electrically connected to the second anode pad 19 and the second cathode pad 20. Note that FIG. 3 only shows the first relay wiring 29 connected to the first cathode pad 18 and the second relay wiring 30 connected to the second cathode pad 20.

[0019] The back surface layer 13 is formed on the second main surface 10 of the substrate 6, and includes a plurality of anode mounting electrodes 31 and a plurality of cathode mounting electrodes 32. The plurality of anode mounting electrodes 31 and the plurality of cathode mounting electrodes 32 are used to surface-mount the semiconductor light-emitting device 1 on, for example, a circuit board. In this embodiment, the plurality of anode mounting electrodes 31 and the plurality of cathode mounting electrodes 32 are made of Au.

[0020] The multiple anode mounting electrodes 31 and the multiple cathode mounting electrodes 32 are each arranged as a pair of adjacent anode mounting electrodes 31 and cathode mounting electrodes 32. The multiple anode mounting electrodes 31 and the multiple cathode mounting electrodes 32 may include a pair of a first anode mounting electrode 33 and a first cathode mounting electrode 34, and a pair of a second anode mounting electrode 35 and a second cathode mounting electrode 36. In this embodiment, the first anode mounting electrode 33 and the first cathode mounting electrode 34 are electrically connected to the first anode pad 17 and the first cathode pad 18, respectively. The second anode mounting electrode 35 and the second cathode mounting electrode 36 are electrically connected to the second anode pad 19 and the second cathode pad 20, respectively.

[0021] The through wiring 14 penetrates the substrate 6 in the thickness direction and electrically connects between the front surface layer 11 and the back surface layer 13. The through wiring 14 is exposed from both the first main surface 9 and the second main surface 10 of the substrate 6. The through wiring 14 may electrically connect between the front surface layer 11 and the back surface layer 13 via the intermediate layer 12. In this embodiment, the through wiring 14 is made of Cu. The through wiring 14 may also be referred to as a "via electrode," "through via," "connection via," or "buried via" based on its shape. The through wiring 14 includes a plurality of first through wirings 37 and a plurality of second through wirings 38.

[0022] Some of the plurality of first through wires 37 electrically connect the first anode pad 17 and the first anode mounting electrode 33. The rest of the plurality of first through wires 37 may electrically connect the first cathode pad 18 and the first cathode mounting electrode 34. Some of the plurality of second through wires 38 electrically connect the second anode pad 19 and the second anode mounting electrode 35. The rest of the plurality of second through wires 38 may electrically connect the second cathode pad 20 and the second cathode mounting electrode 36.

[0023] In this embodiment, the semiconductor light-emitting chip 3 is a vertical cavity surface-emitting laser chip. The semiconductor light-emitting chip 3 may be a VCSEL (Vertical Cavity Surface Emitting Laser). The semiconductor light-emitting chip 3 has a first main surface 39 and a second main surface 40. The first main surface 39 is the laser emission end face. The semiconductor light-emitting chip 3 has an anode electrode 41 on the first main surface 39 and a cathode electrode 42 (not shown in FIG. 3 ) on the second main surface 40. The semiconductor light-emitting chip 3 is die-bonded to the first cathode pad 18 by bonding the cathode electrode 42 to the first cathode pad 18 via a conductive bonding material layer 43 (e.g., an Ag adhesive layer). The anode electrode 41 of the semiconductor light-emitting chip 3 is connected to the first anode pad 17 via a plurality of wires 44.

[0024] In this embodiment, the diode chip 4 is a photodiode chip and has a first main surface 45 and a second main surface 46. The first main surface 45 is the light-receiving surface of the photodiode. The diode chip 4 has an anode electrode 47 on the first main surface 45 and a cathode electrode 48 (omitted in FIG. 3 ) on the second main surface 46. The diode chip 4 is mounted on the second cathode pad 20 by bonding the cathode electrode 48 to the second cathode pad 20 via a conductive bonding material layer 49 (e.g., an Ag adhesive layer). The anode electrode 47 of the diode chip 4 is connected to the second anode pad 19 via a plurality of wires 50.

[0025] The sealing resin 5 fills the accommodating recess 8 of the case 2 and covers the multiple semiconductor light-emitting chips 3. The sealing resin 5 is made of a transparent epoxy resin or silicone resin mixed with a fluorescent material. [Explanation of the Arrangement Pattern of Through Wires 14 (Via)] The through wires 14 electrically connect the front surface layer 11 and the back surface layer 13 and also transfer heat generated in the semiconductor light-emitting chips 3 and the diode chips 4 from the first main surface 9 to the second main surface 10 of the substrate 6. Heat from the first main surface 9 is transferred to the anode mounting electrode 31 and the cathode mounting electrode 32 via the through wires 14. This allows heat inside the case 2 to be diffused to the mounting substrate (not shown). In other words, the through wires 14 contribute to the heat dissipation of the semiconductor light-emitting device 1. Below, a detailed description of a preferred arrangement pattern of the through wires 14 will be provided with regard to the heat dissipation of the semiconductor light-emitting device 1. (1) First Arrangement Pattern FIG. 4A is a plan view of the semiconductor light-emitting device 1 showing a first arrangement pattern of the through wires 14 (vias). 4B is a bottom view of the semiconductor light emitting device 1 showing a first arrangement pattern of the through wirings (vias) 14. For clarity, the arrangement position of the semiconductor light emitting chip 3 is shown by a dashed line only in FIG.

[0026] 4A and 4B , in the semiconductor light emitting device 1 of this example, a diode chip 4 is not mounted, and pads and electrodes related to the diode chip 4 are omitted. In the first arrangement pattern, the through wiring 14 includes a plurality of via electrodes 51. Each via electrode 51 is formed in a circular shape in a planar view. The width (diameter) of each via electrode 51 in a planar view may be, for example, not less than 50 μm and not more than 200 μm.

[0027] The multiple via electrodes 51 include a first via electrode 52 and a second via electrode 53. The first via electrode 52 connects the first cathode pad 18 and the first cathode mounting electrode 34 and may be referred to as a cathode via electrode. The second via electrode 53 connects the first anode pad 17 and the first anode mounting electrode 33 and may be referred to as an anode via electrode.

[0028] The multiple first via electrodes 52 are provided over almost the entire area of ​​the first cathode pad 18 and the first cathode mounting electrode 34. The multiple first via electrodes 52 are arranged in a staggered pattern at intervals in a first direction X (a direction along the first and second peripheries) and a second direction Y (a direction along the third and fourth peripheries) intersecting the first direction X in a plan view. The pitch between the multiple first via electrodes 52 may be, for example, 50 μm or more and 200 μm or less. Referring to FIG. 4B , the semiconductor light-emitting chip 3 is arranged to face the multiple first via electrodes 52.

[0029] The multiple second via electrodes 53 are arranged in a row at intervals along the longitudinal direction of the first anode pad 17 and the first anode mounting electrode 33. More specifically, they are arranged along the longitudinal direction of the anode pad portion 25. The pitch of the multiple second via electrodes 53 may be, for example, not less than 50 μm and not more than 200 μm.

[0030] In the first arrangement pattern, the total area occupancy of the plurality of first via electrodes 52 and the plurality of second via electrodes 53 is 10% to 60%, preferably 25% to 35%. The area occupancy is the ratio of the total planar area of ​​each via electrode 51 to the surface area of ​​the first main surface 9 of the base material 6. If the area occupancy of the via electrodes 51 is within the above range, the heat dissipation performance of the semiconductor light emitting device 1 can be improved.

[0031] Furthermore, when comparing the area occupation rate of the multiple first via electrodes 52 with the area occupation rate of the multiple second via electrodes 53, the area occupation rate of the second via electrodes 53 is smaller. By increasing the occupation rate of the vias on the cathode side, which is the electrode on which the semiconductor light emitting chip 3 is mounted, the heat dissipation performance of the semiconductor light emitting device 1 can be further improved. (2) Second Arrangement Pattern Figure 5A is a plan view of the semiconductor light emitting device 1 showing a second arrangement pattern of the through wirings 14 (vias). Figure 5B is a bottom view of the semiconductor light emitting device 1 showing the second arrangement pattern of the through wirings 14 (vias). For clarity, the arrangement position of the semiconductor light emitting chip 3 is shown by dashed lines only in Figure 5B.

[0032] 5A and 5B , in the semiconductor light-emitting device 1 of this example, the diode chip 4 is not mounted, and the pads and electrodes related to the diode chip 4 are omitted. In the second arrangement pattern, the through wiring 14 includes a plurality of via electrodes 61. The plurality of via electrodes 61 include a first via electrode 62 and a second via electrode 63. The first via electrode 62 connects the first cathode pad 18 and the first cathode mounting electrode 34, and may also be referred to as a cathode via electrode. The second via electrode 63 connects the first anode pad 17 and the first anode mounting electrode 33, and may also be referred to as an anode via electrode.

[0033] Each first via electrode 62 is formed in an elliptical shape in a planar view. The shape of each first via electrode 62 may be expressed as an elliptical shape in a planar view or a band shape in a planar view. That is, each first via electrode 62 has a long peripheral edge 64 in the longitudinal direction having a relatively long width W1 and a short peripheral edge 65 in a direction perpendicular to the longitudinal direction having a relatively short width W2. The width W2 of each first via electrode 62 in a planar view may be, for example, 50 μm or more and 200 μm or less.

[0034] The multiple first via electrodes 62 can be further divided into first-type via electrodes 66 and second-type via electrodes 67 based on the arrangement direction. For clarity, in Fig. 5A, the first-type via electrodes 66 are hatched and the second-type via electrodes 67 are shown as white.

[0035] The multiple first-type via electrodes 66 are arranged so that their long peripheries 64 are parallel to the first direction X. Therefore, each first-type via electrode 66 is formed in a strip shape extending in the first direction X. On the other hand, the multiple second-type via electrodes 67 are arranged so that their long peripheries 64 are parallel to the second direction Y. In other words, the second-type via electrodes 67 are arranged in a manner that rotates the first-type via electrodes 66 by 90 degrees.

[0036] Consider a case where a plurality of lines L1, L2 extending in a lattice pattern so as to intersect both the first direction X and the second direction Y are set on the first main surface 9. The plurality of first lines L1 are lines parallel to the first direction X, and the plurality of second lines L2 are lines parallel to the second direction Y. The plurality of first lines L1 and the plurality of second lines L2 are each set in a stripe pattern with intervals between them. At least one first-type via electrode 66 and one second-type via electrode 67 are arranged in a partitioned region 68 corresponding to a window portion of the lattice surrounded by the plurality of lines L1, L2.

[0037] Looking at the first-type via electrodes 66 and the second-type via electrodes 67 individually, the multiple first-type via electrodes 66 are arranged at intervals along each of the first line L1 and the second line L2. The multiple first-type via electrodes 66 along the first line L1 are arranged so that adjacent short peripheral edges 65 face each other. The multiple first-type via electrodes 66 along the second line L2 are arranged so that adjacent long peripheral edges 64 face each other. The multiple second-type via electrodes 67 are arranged at intervals along each of the first line L1 and the second line L2. The multiple second-type via electrodes 67 along the first line L1 are arranged so that adjacent long peripheral edges 64 face each other. The multiple second-type via electrodes 67 along the second line L2 are arranged so that adjacent short peripheral edges 65 face each other. 5B , the semiconductor light-emitting chip 3 is disposed to face the plurality of first-type via electrodes 66 and the plurality of second-type via electrodes 67. The pitch of the plurality of first-type via electrodes 66 and the plurality of second-type via electrodes 67 may be, for example, not less than 50 μm and not more than 200 μm.

[0038] The multiple second via electrodes 63 are arranged in a row at intervals along the longitudinal direction of the first anode pad 17 and the first anode mounting electrode 33. More specifically, they are arranged along the longitudinal direction of the anode pad portion 25. Each second via electrode 63 is formed in a circular shape in a planar view. The width (diameter) of each second via electrode 63 in a planar view may be, for example, 50 μm or more and 200 μm or less. The pitch between the multiple second via electrodes 63 may be, for example, 50 μm or more and 200 μm or less.

[0039] In the second arrangement pattern, the total area occupancy of the plurality of first via electrodes 62 and the plurality of second via electrodes 63 is 10% to 60%, preferably 40% to 50%. The area occupancy is the ratio of the total planar area of ​​each via electrode 61 to the surface area of ​​the first main surface 9 of the base material 6. If the area occupancy of the via electrodes 61 is within the above range, the heat dissipation performance of the semiconductor light emitting device 1 can be improved.

[0040] Furthermore, when the area occupation rate of the plurality of first via electrodes 62 is compared with the area occupation rate of the plurality of second via electrodes 63, the area occupation rate of the second via electrodes 63 is smaller. By increasing the occupation rate of the vias on the cathode side, which is the electrode on which the semiconductor light emitting chip 3 is mounted, the heat dissipation performance of the semiconductor light emitting device 1 can be further improved.

[0041] Furthermore, by mixing first-type via electrodes 66 and second-type via electrodes 67 extending in different directions with respect to the first via electrodes 62, it is possible to distribute stress applied to the substrate 6 in multiple directions. (3) Third Arrangement Pattern Fig. 6A is a plan view of the semiconductor light-emitting device 1 showing a third arrangement pattern of the through wirings 14 (vias). Fig. 6B is a bottom view of the semiconductor light-emitting device 1 showing the third arrangement pattern of the through wirings 14 (vias). For clarity, the arrangement positions of the semiconductor light-emitting chips 3 are shown by dashed lines only in Fig. 6B.

[0042] The third arrangement pattern is the same as the first arrangement pattern except that the total area occupancy of the plurality of first via electrodes 52 and the plurality of second via electrodes 53 is larger than that of the first arrangement pattern. In the third arrangement pattern, the total area occupancy of the plurality of first via electrodes 52 and the plurality of second via electrodes 53 may be 10% or more and 60% or less, preferably 30% or more and 40% or less. (4) Fourth Arrangement Pattern Figure 7A is a plan view of the semiconductor light-emitting device 1 showing a fourth arrangement pattern of the through wirings 14 (vias). Figure 7B is a bottom view of the semiconductor light-emitting device 1 showing the fourth arrangement pattern of the through wirings 14 (vias). For clarity, the arrangement positions of the semiconductor light-emitting chips 3 are indicated by dashed lines only in Figure 7B.

[0043] The fourth arrangement pattern is a modified example of the second arrangement pattern. Specifically, the arrangement direction of the first-type via electrodes 66 and the second-type via electrodes 67 includes, in addition to the direction along the first line L1 and the second line L2, a direction along a third line L3 that extends in a direction intersecting the first line L1 and the second line L2 (a direction intersecting the third line L3 at 45° in FIG. 7A ). As a result, the first-type via electrodes 66 and the second-type via electrodes 67 are also arranged at intervals in the diagonal direction along the third line L3.

[0044] Furthermore, the total area occupancy of the plurality of first via electrodes 62 and the plurality of second via electrodes 63 is larger than that of the second arrangement pattern. For example, in the fourth arrangement pattern, the total area occupancy of the plurality of first via electrodes 62 and the plurality of second via electrodes 63 may be 10% or more and 60% or less, preferably 45% or more and 55% or less. (5) Fifth Arrangement Pattern Figure 8A is a plan view of a semiconductor light emitting device showing a fifth arrangement pattern of the through wirings 14 (vias). Figure 8B is a bottom view of a semiconductor light emitting device showing the fifth arrangement pattern of the through wirings 14 (vias). For clarity, the arrangement positions of the semiconductor light emitting chip 3 and the diode chip 4 are indicated by dashed lines only in Figure 8B.

[0045] The fifth arrangement pattern is a modification of the second arrangement pattern. Specifically, the arrangement directions of the first-type via electrodes 66 and the second-type via electrodes 67 include, in addition to the direction along the first line L1 and the second line L2, a direction along a third line L3 that extends in a direction intersecting the first line L1 and the second line L2 (a direction intersecting the third line L3 at 45° in FIG. 8A ). As a result, the first-type via electrodes 66 and the second-type via electrodes 67 are also arranged at intervals in the diagonal direction along the third line L3.

[0046] Furthermore, the multiple via electrodes 61 include a third via electrode 69 and a fourth via electrode 70. The third via electrode 69 connects the second cathode pad 20 and the second cathode mounting electrode 36 and may be referred to as a second cathode via electrode. The fourth via electrode 70 connects the second anode pad 19 and the second anode mounting electrode 35 and may be referred to as a second anode via electrode. Referring to FIG. 8B , the diode chip 4 is disposed so as to face the multiple third via electrodes 69.

[0047] Each third via electrode 69 and each fourth via electrode 70 is formed in a circular shape in a plan view. The width (diameter) of each third via electrode 69 and each fourth via electrode 70 in a plan view may be, for example, 50 μm or more and 200 μm or less. The pitch between the multiple third via electrodes 69 and the multiple fourth via electrodes 70 may be, for example, 50 μm or more and 200 μm or less.

[0048] In the fifth arrangement pattern, the total area occupancy of the multiple via electrodes 62, 63, 69, and 70 is 10% or more and 60% or less. [Simulation Results of Heat Dissipation] Next, a simulation was conducted to investigate the relationship between the area occupancy of the through wirings 14 (vias) on the first main surface 9, the thickness T1 of the base material 6 (substrate) (see FIG. 3), and the thickness T2+T3 of the surface layer 11 (see FIG. 3), and the heat dissipation of the semiconductor light emitting device 1. In the following simulation, a resin build-up substrate (multilayer substrate) was used as the base material 6 of the sample.

[0049] First, referring to FIG. 9 , the relationship between the area occupancy of the through wirings 14 (vias) on the first main surface 9 and heat dissipation is shown. FIG. 9 shows a reference example in which an AlN substrate (without through wirings) is used as the base material 6. The samples had the area occupancy of the through wirings 14 (vias) set to 8.3%, 9.3%, 12.3%, 26.1%, 33.5%, and 40.2%. The results in FIG. 9 show that increasing the area occupancy of the through wirings 14 (vias) can reduce the temperature of the base material 6 (substrate) and improve heat dissipation.

[0050] Next, referring to FIG. 10 , the relationship between the thickness T1 of the substrate 6 (substrate) and heat dissipation is shown. FIG. 10 shows a reference example in which an AlN substrate (without through-hole wiring) is used as the substrate 6. The samples had an area occupancy of the through-hole wiring 14 (vias) set to 40.2%, and the thicknesses of the substrate 6 were set to 100 μm and 225 μm. The results in FIG. 10 reveal that the temperature of the substrate 6 (substrate) barely changes even when the thickness of the substrate 6 is increased.

[0051] Next, referring to FIG. 11 , the relationship between the thickness of the surface layer 11 and heat dissipation is shown. FIG. 11 shows a reference example in which an AlN substrate (without through-hole wiring, substrate thickness 225 μm) was used as the substrate 6. In Samples 1 and 2, the area occupancy of the through-hole wiring 14 (vias) was set to 40.2%, and the thickness of the substrate 6 was set to 100 μm (Sample 1) and 225 μm (Sample 2). Furthermore, a single-layer Cu structure was used as the surface layer 11. The results in FIG. 11 indicate that, for a resin substrate 6, the thicker the surface layer 11 (Cu pattern), the more the heat dissipation can be improved. On the other hand, for the AlN substrate of the reference example, it was found that the temperature of the substrate 6 (substrate) hardly changed even when the surface layer 11 was thickened.

[0052] 9 to 11, it was found that even when a resin substrate having a thermal conductivity significantly lower than that of an AlN substrate is used as the base material 6, the heat dissipation performance can be made to approach that of an AlN substrate by adjusting the area occupancy of the through wiring 14 (vias) on the first main surface 9 to 10% or more and 60% or less. It was also found that further improvement in heat dissipation performance can be achieved by appropriately adjusting the thickness of the surface layer 11 (Cu pattern).

[0053] From this simulation, the area occupancy rate of the through wirings 14 (vias) on the first main surface 9 is preferably 10% to 60%, more preferably 25% to 60%. The thickness of the surface layer 11 (Cu pattern) is preferably 10 μm to 200 μm, more preferably 60 μm to 200 μm.

[0054] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0055] The embodiments of the present disclosure are to be considered as illustrative in all respects and not restrictive, and are intended to include modifications in all respects.

[0056] The following characteristics can be extracted from the description of this specification and the drawings.

[0057] [Appendix 1-1] A semiconductor light emitting device comprising: a substrate having a first main surface on one side and a second main surface on the other side; a plurality of via electrodes embedded in the substrate at intervals so that their occupancy rate relative to a surface area of ​​the first main surface is 10% or more and 60% or less in a plan view; an electrode film collectively covering the plurality of via electrodes on the first main surface; and a semiconductor light emitting chip arranged on the electrode film so as to face the plurality of via electrodes.

[0058] [Supplementary Note 1-2] The semiconductor light-emitting device according to Supplementary Note 1-1, wherein the semiconductor light-emitting chip includes a vertical-cavity surface-emitting laser chip.

[0059] [Supplementary Note 1-3] The semiconductor light-emitting device according to Supplementary Note 1-1 or Supplementary Note 1-2, wherein the plurality of via electrodes are exposed from the first main surface and the second main surface.

[0060] [Appendix 1-4] The semiconductor light-emitting device according to any one of Appendices 1-1 to 1-3, wherein the plurality of via electrodes have at least one of a polygonal shape, a circular shape, an elliptical shape, and an oblong shape in a planar view.

[0061] [Appendix 1-5] The semiconductor light-emitting device according to any one of Appendices 1-1 to 1-4, wherein the plurality of via electrodes are arranged in a matrix or staggered pattern at intervals in a first direction and a second direction intersecting the first direction when viewed in a plan view.

[0062] [Supplementary Note 1-6] The semiconductor light-emitting device according to any one of Supplementary Note 1-1 to Supplementary Note 1-5, wherein the plurality of via electrodes are arranged at a pitch of 50 μm or more and 200 μm or less.

[0063] [Supplementary Note 1-7] The semiconductor light emitting device according to any one of Supplementary Note 1-1 to Supplementary Note 1-6, wherein each of the plurality of via electrodes has a portion formed with a width of 50 μm or more and 200 μm or less in plan view.

[0064] [Appendix 1-8] The semiconductor light-emitting device according to any one of Appendices 1-1 to 1-7, wherein the electrode film has a thickness of 10 μm or more and 200 μm or less.

[0065] [Appendix 1-9] A semiconductor light-emitting device according to any one of Appendices 1-1 to 1-8, further comprising: a plurality of second via electrodes embedded in the substrate at intervals from the plurality of via electrodes; a second electrode film covering the plurality of second via electrodes at intervals from the electrode film on the first main surface; and a conductor connecting the semiconductor light-emitting chip and the second electrode film.

[0066] [Appendix 1-10] The semiconductor light-emitting device described in Appendix 1-9, wherein the plurality of second via electrodes are embedded in the substrate so that their occupancy rate relative to the surface area of ​​the first main surface in a planar view is smaller than the occupancy rate of the plurality of via electrodes.

[0067] [Appendix 1-11] The semiconductor light emitting device according to any one of Appendices 1-1 to 1-10, further comprising a conductive bonding material layer interposed between the semiconductor light emitting chip and the electrode film.

[0068] [Appendix 1-12] The semiconductor light-emitting device according to Appendix 1-11, wherein the conductive adhesive layer is an Ag adhesive layer.

[0069] [Appendix 1-13] The semiconductor light-emitting device according to any one of Appendices 1-1 to 1-12, wherein the substrate includes a resin substrate.

[0070] [Supplementary Note 1-14] The semiconductor light-emitting device according to any one of Supplementary Note 1-1 to Supplementary Note 1-13, wherein at least one of the plurality of via electrodes and the electrode film contains a Cu-based metal.

[0071] [Supplementary Note 1-15] A semiconductor light emitting device comprising: a substrate having a first main surface on one side and a second main surface on the other side; a plurality of first-type via electrodes each formed in a strip shape extending in a first direction along the first main surface in a plan view and embedded in the substrate; a plurality of second-type via electrodes each formed in a strip shape extending in a second direction intersecting the first direction along the first main surface in a plan view and embedded in the substrate at a distance from the plurality of first-type via electrodes so as to face at least one of the first-type via electrodes in the first direction; an electrode film collectively covering the plurality of first-type via electrodes and the plurality of second-type via electrodes on the first main surface; and a semiconductor light emitting chip arranged on the electrode film so as to face the plurality of first-type via electrodes and the plurality of second-type via electrodes.

[0072] [Appendix 1-16] The semiconductor light-emitting device according to Appendix 1-15, wherein when a plurality of lines extending in a stripe pattern in the second direction in a planar view are set on the first main surface, the plurality of first-type via electrodes are arranged at intervals on the plurality of lines.

[0073] [Appendix 1-17] The semiconductor light-emitting device according to Appendix 1-15, wherein when a plurality of lines extending in a grid pattern so as to intersect both the first direction and the second direction in a planar view are set on the first main surface, the plurality of first-type via electrodes are arranged at intervals on the plurality of lines.

[0074] [Supplementary Note 1-18] The semiconductor light-emitting device according to Supplementary Note 1-17, wherein at least one of the second-type via electrodes is disposed within an area surrounded by the plurality of lines.

[0075] [Supplementary Note 1-19] The semiconductor light-emitting device according to Supplementary Note 1-17 or Supplementary Note 1-18, wherein at least one of the first-type via electrodes is disposed within a region surrounded by the plurality of lines.

[0076] [Appendix 1-20] The semiconductor light-emitting device according to any one of Appendices 1-15 to 1-19, wherein a total occupancy rate of the plurality of first-type via electrodes and the plurality of second-type via electrodes relative to a surface area of ​​the first main surface in a planar view is 10% or more and 50% or less.

[0077] REFERENCE SIGNS LIST 1: Semiconductor light emitting device 2: Case 3: Semiconductor light emitting chip 4: Diode chip 5: Sealing resin 6: Base material 7: Wiring 8: Accommodating recess 9: First main surface 10: Second main surface 11: Surface layer 12: Intermediate layer 13: Back surface layer 14: Through wiring 15: Anode pad 16: Cathode pad 17: First anode pad 18: First cathode pad 19: Second anode pad 20: Second cathode pad 21: Cathode island portion 22: Cathode extension portion 23: Straight portion 24: Diode region 25: Anode pad portion 26: Anode extension portion 27: First conductive layer 28: Second conductive layer 29: First relay wiring 30: Second relay wiring 31 : Anode mounting electrode 32 : Cathode mounting electrode 33 : First anode mounting electrode 34 : First cathode mounting electrode 35 : Second anode mounting electrode 36 : Second cathode mounting electrode 37 : First through wire 38 : Second through wire 39 : First main surface 40 : Second main surface 41 : Anode electrode 42 : Cathode electrode 43 : Conductive bonding material layer 44 : Wire 45 : First main surface 46 : Second main surface 47 : Anode electrode 48 : Cathode electrode 49 : Conductive bonding material layer 50 : Wire 51 : Via electrode 52 : First via electrode 53 : Second via electrode 61 : Via electrode 62 : First via electrode 63 : Second via electrode 64 : Long peripheral edge 65 : Short peripheral edge 66: First type via electrode 67: Second type via electrode 68: Partitioned area 69: Third via electrode 70: Fourth via electrode L1: First line L2: Second line L3: Third line T1: Thickness T2: Thickness T3: Thickness W1: Width W2: Width

Claims

1. a substrate having a first main surface on one side and a second main surface on the other side; a plurality of via electrodes embedded in the substrate at intervals such that an occupancy rate of the surface area of ​​the first main surface in a plan view is 10% or more and 60% or less; an electrode film collectively covering the plurality of via electrodes on the first main surface; a semiconductor light emitting chip disposed on the electrode film so as to face the plurality of via electrodes.

2. 2. The semiconductor light emitting device of claim 1, wherein the semiconductor light emitting chip comprises a vertical cavity surface emitting laser chip.

3. The semiconductor light emitting device according to claim 1 , wherein the plurality of via electrodes are exposed from the first main surface and the second main surface.

4. The semiconductor light emitting device according to claim 1 , wherein the plurality of via electrodes have at least one of a polygonal shape, a circular shape, an elliptical shape, and an oval shape in a plan view.

5. The semiconductor light emitting device according to claim 1 , wherein the plurality of via electrodes are arranged in a matrix or staggered pattern at intervals in a first direction and a second direction intersecting the first direction in a plan view.

6. The semiconductor light emitting device according to claim 1 , wherein the plurality of via electrodes are arranged at a pitch of 50 μm or more and 200 μm or less.

7. The semiconductor light emitting device according to claim 1 , wherein each of the plurality of via electrodes has a portion formed with a width of 50 μm or more and 200 μm or less in a plan view.

8. The semiconductor light emitting device according to claim 1 , wherein the electrode film has a thickness of 10 μm or more and 200 μm or less.

9. a plurality of second via electrodes embedded in the substrate at intervals from the plurality of via electrodes; a second electrode film covering the second via electrodes at a distance from the electrode film on the first main surface; The semiconductor light emitting device according to claim 1 , further comprising a conductive wire connecting said semiconductor light emitting chip and said second electrode film.

10. The semiconductor light emitting device according to claim 9 , wherein the plurality of second via electrodes are embedded in the substrate such that an occupancy rate of the plurality of via electrodes relative to a surface area of ​​the first main surface in a plan view is smaller than an occupancy rate of the plurality of via electrodes.

11. The semiconductor light emitting device according to claim 1 , further comprising a conductive adhesive layer interposed between the semiconductor light emitting chip and the electrode film.

12. The semiconductor light emitting device according to claim 11 , wherein the conductive adhesive layer is made of an Ag adhesive layer.

13. The semiconductor light emitting device according to claim 1 , wherein the substrate includes a resin substrate.

14. 14. The semiconductor light emitting device according to claim 1, wherein at least one of the plurality of via electrodes and the electrode film contains a Cu-based metal.

15. a substrate having a first main surface on one side and a second main surface on the other side; a plurality of first-type via electrodes each formed in a strip shape extending in a first direction along the first main surface in a plan view and embedded in the substrate; a plurality of second-type via electrodes each formed in a strip shape extending in a second direction intersecting the first direction along the first main surface in a plan view, the second-type via electrodes being embedded in the substrate at a distance from the plurality of first-type via electrodes so as to face at least one of the first-type via electrodes in the first direction; an electrode film collectively covering the first type via electrodes and the second type via electrodes on the first main surface; a semiconductor light emitting chip disposed on the electrode film so as to face the plurality of first type via electrodes and the plurality of second type via electrodes.

16. The semiconductor light-emitting device of claim 15, wherein when a plurality of lines extending in a stripe shape in the second direction in a planar view are set on the first main surface, the plurality of first type via electrodes are arranged at intervals on the plurality of lines.

17. 16. The semiconductor light-emitting device of claim 15, wherein when a plurality of lines extending in a grid pattern so as to intersect both the first direction and the second direction in a planar view are set on the first main surface, the plurality of first type via electrodes are arranged at intervals on the plurality of lines.

18. The semiconductor light emitting device according to claim 17 , wherein at least one of the second type via electrodes is disposed within an area surrounded by the plurality of the lines.

19. The semiconductor light emitting device according to claim 17 or 18, wherein at least one of the first type via electrodes is disposed within an area surrounded by the plurality of the lines.

20. The semiconductor light-emitting device according to any one of claims 15 to 18, wherein a total occupancy rate of the plurality of first type via electrodes and the plurality of second type via electrodes relative to a surface area of ​​the first main surface in a planar view is 10% or more and 50% or less.