Semiconductor substrate and semiconductor epitaxial substrate

Abstract

This semiconductor substrate comprises a main surface, a reference mark, and an epitaxial growth-inhibiting film. The reference mark is composed of a recess formed on the main surface, and serves as a reference for in-plane coordinates. The epitaxial growth-inhibiting film is provided in at least a part of the inside of the recess. At least two or more reference marks are provided on the main surface. The main surface is composed of a semiconductor material. The epitaxial growth-inhibiting film is composed of a material different from the semiconductor material.

Description

Semiconductor substrate and semiconductor epitaxial substrate

[0001] The present disclosure relates to a semiconductor substrate and a semiconductor epitaxial substrate. This application claims priority to Japanese Patent Application No. 2022-051805, filed on March 28, 2022. The entire contents of the Japanese patent application are incorporated herein by reference.

[0002] Japanese Patent Laid-Open Publication No. 4-62858 (Patent Document 1) describes a method for observing and analyzing foreign matter, in which a coordinate system is set by providing a coordinate reference on a wafer.

[0003] Japanese Patent Laid-Open Publication No. 2000-269286 (Patent Document 2) describes a method for identifying the location of a defect in a semiconductor substrate, in which the location of the defect is identified based on affine transformation and coordinate values ​​in the coordinate system of a defect evaluation device.

[0004] Japanese Patent Application Laid-Open No. 4-62858 Japanese Patent Application Laid-Open No. 2000-269286

[0005] The semiconductor substrate according to the present disclosure comprises a main surface, a reference mark, and an epitaxial growth suppression film. The reference mark is configured by a recess formed in the main surface and serves as a reference for in-plane coordinates. The epitaxial growth suppression film is provided in at least a portion of the interior of the recess. At least two or more reference marks are provided on the main surface. The main surface is made of a semiconductor material. The epitaxial growth suppression film is made of a material different from the semiconductor material.

[0006] FIG. 1 is a schematic plan view showing the configuration of a semiconductor substrate according to a first embodiment. FIG. 2 is an enlarged plan view showing region II of FIG. 1. FIG. 3 is a schematic cross-sectional view taken along line III-III of FIG. 2. FIG. 4 is a schematic cross-sectional view showing the configuration of a semiconductor substrate according to a second embodiment. FIG. 5 is a schematic cross-sectional view showing the configuration of a semiconductor substrate according to a third embodiment. FIG. 6 is a schematic cross-sectional view showing the configuration of a semiconductor epitaxial substrate according to a fourth embodiment. FIG. 7 is a schematic cross-sectional view showing the configuration of a semiconductor epitaxial substrate according to a fifth embodiment. FIG. 8 is a schematic cross-sectional view showing the configuration of a semiconductor epitaxial substrate according to a sixth embodiment. FIG. 9 is a schematic cross-sectional view showing the configuration of a semiconductor epitaxial substrate according to a seventh embodiment. FIG. 10 is a schematic cross-sectional view showing the configuration of a semiconductor epitaxial substrate according to an eighth embodiment. FIG. 11 is a schematic cross-sectional view showing the configuration of a semiconductor epitaxial substrate according to a ninth embodiment. FIG. 12 is an enlarged plan view showing region XII of FIG. 11. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12. FIG. 14 is a cross-sectional view showing the configuration of a semiconductor epitaxial substrate according to the tenth embodiment. FIG. 15 is a cross-sectional view showing the configuration of a semiconductor epitaxial substrate according to the eleventh embodiment. FIG. 16 is a cross-sectional view showing the configuration of a semiconductor epitaxial substrate according to the twelfth embodiment. FIG. 17 is a cross-sectional view showing the configuration of a semiconductor epitaxial substrate according to the thirteenth embodiment. FIG. 18 is a cross-sectional view showing the configuration of a semiconductor epitaxial substrate according to the fourteenth embodiment. FIG. 19 is a cross-sectional view showing the configuration of a semiconductor epitaxial substrate according to the fifteenth embodiment. FIG. 20 is a cross-sectional view showing the configuration of a semiconductor epitaxial substrate according to the sixteenth embodiment. FIG. 21 is a flow chart showing a first method for manufacturing a semiconductor substrate according to the second embodiment. FIG. 22 is a cross-sectional view showing the step of preparing a semiconductor substrate. FIG. 23 is a cross-sectional view showing the step of applying a resist. Fig. 24 is a cross-sectional view showing a step of forming an opening by photolithography. Fig. 25 is a cross-sectional view showing a step of etching the semiconductor substrate in the opening. Fig. 26 is a first cross-sectional view showing a step of forming an epitaxial growth suppression film. Fig. 27 is a flow chart showing a second method for manufacturing a semiconductor substrate according to the second embodiment.Fig. 28 is a second schematic cross-sectional view showing a step of forming an epitaxial growth suppression film. Fig. 29 is a flow chart generally showing a third method for manufacturing a semiconductor substrate according to the second embodiment. Fig. 30 is a schematic cross-sectional view showing a step of performing laser processing on a semiconductor base material. Fig. 31 is a flow chart generally showing a fourth method for manufacturing a semiconductor substrate according to the second embodiment.

[0007] [Problem to be Solved by the Present Disclosure] An object of the present disclosure is to provide a semiconductor substrate and a semiconductor epitaxial substrate that can suppress deterioration of the visibility of the fiducial marks. [Advantages of the Present Disclosure] According to the present disclosure, it is possible to provide a semiconductor substrate and a semiconductor epitaxial substrate that can suppress deterioration of the visibility of the fiducial marks.

[0008] [Outline of the embodiment of the present disclosure] First, an outline of the embodiment of the present disclosure will be described.

[0009] (1) A semiconductor substrate 100 according to the present disclosure includes a main surface 1, a fiducial mark 3, and an epitaxial growth suppression film 30. The fiducial mark 3 is configured as a recess 24 formed in the main surface 1, and serves as a reference for in-plane coordinates. The epitaxial growth suppression film 30 is provided in at least a portion of the interior of the recess 24. At least two fiducial marks 3 are provided on the main surface 1. The main surface 1 is made of a semiconductor material. The epitaxial growth suppression film 30 is made of a material different from the semiconductor material.

[0010] (2) In the semiconductor substrate 100 according to (1) above, the depth of the recess 24 may be greater than 0.5 μm and less than 100 μm.

[0011] (3) In the semiconductor substrate 100 according to (1) or (2) above, the recess 24 may be configured with a side surface 22 and a bottom surface 23 continuous with the side surface 22. The epitaxial growth suppression film 30 may be in contact with the bottom surface 23.

[0012] (4) In the semiconductor substrate 100 according to (1) or (2) above, the recess 24 may be configured with a side surface 22 and a bottom surface 23 continuous with the side surface 22. The epitaxial growth suppression film 30 may be in contact with each of the side surface 22 and the bottom surface 23. The epitaxial growth suppression film 30 may form a depression.

[0013] (5) In the semiconductor substrate 100 according to (1) or (2) above, the recess 24 may be filled with an epitaxial growth suppression film 30 .

[0014] (6) In the semiconductor substrate 100 according to any one of (1) to (5) above, the epitaxial growth suppression film 30 may be made of a material containing boron, carbon, nitrogen, or oxygen and having a melting point of 1700° C. or higher.

[0015] (7) In the semiconductor substrate 100 according to any one of (1) to (5) above, the epitaxial growth suppression film 30 may be made of a material containing titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, magnesium, yttrium, aluminum, nickel, zinc, or gallium.

[0016] (8) In the semiconductor substrate 100 according to any one of (1) to (7) above, the semiconductor material may be silicon carbide.

[0017] (9) In the semiconductor substrate 100 according to any one of (1) to (8) above, the thickness of the epitaxial growth suppression film 30 may be 0.25 times or more the depth of the recess 24 .

[0018] (10) A semiconductor epitaxial substrate 200 according to the present disclosure may include the semiconductor substrate 100 described in any one of (1) to (9) above, a semiconductor layer 90 formed on the epitaxial growth suppression film 30, and an epitaxial layer 40 provided on at least a portion of the main surface 1. The thickness of the epitaxial layer 40 may be greater than the minimum thickness of the semiconductor layer 90.

[0019] (11) A semiconductor epitaxial substrate 200 according to the present disclosure may include the semiconductor substrate 100 according to any one of (1) to (9) above, the semiconductor substrate 100 according to any one of (1) to (9) above, and an epitaxial layer 40 provided on at least a portion of the main surface 1. The epitaxial layer 40 does not have to be formed on the epitaxial growth suppression film 30.

[0020] (12) The semiconductor epitaxial substrate 200 according to the present disclosure includes a semiconductor substrate 105, a first epitaxial layer 71, a main surface 5, a reference mark 3, and an epitaxial growth suppression film 30. The first epitaxial layer 71 is provided on the semiconductor substrate 105. The main surface 5 is formed by the first epitaxial layer 71. The reference mark 3 is formed by a recess 24 formed in the main surface 5 and serves as a reference for in-plane coordinates. The epitaxial growth suppression film 30 is provided in at least a portion of the interior of the recess 24. At least two reference marks 3 are provided on the main surface 5. The main surface 5 is made of a semiconductor material. The epitaxial growth suppression film 30 is made of a material different from the semiconductor material.

[0021] (13) The semiconductor epitaxial substrate 200 according to (12) above may include a semiconductor layer 90 formed on the epitaxial growth suppression film 30, and a second epitaxial layer 72 provided on at least a portion of the main surface 5. The thickness of the second epitaxial layer 72 may be greater than the minimum thickness of the semiconductor layer 90.

[0022] (14) The semiconductor epitaxial substrate 200 according to (12) above includes a second epitaxial layer 72 provided on at least a portion of the main surface 5. The second epitaxial layer 72 does not have to be formed on the epitaxial growth suppression film 30.

[0023] [Details of the embodiment of the present disclosure] Hereinafter, the details of the embodiment of the present disclosure (hereinafter also referred to as the present embodiment) will be described with reference to the drawings. Note that the same or corresponding parts in the following drawings will be given the same reference numerals, and the description thereof will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. Furthermore, for negative indices, in crystallography, a "-" (bar) is placed before the number, but in this specification, a negative sign is placed before the number.

[0024] First Embodiment First, the configuration of a semiconductor substrate 100 according to a first embodiment will be described.

[0025] FIG. 1 is a schematic plan view showing the configuration of a semiconductor substrate 100 according to the first embodiment. As shown in FIG. 1, the semiconductor substrate 100 according to the first embodiment mainly has a first main surface 1 and an outer peripheral edge 9. When viewed in a direction perpendicular to the first main surface 1, the first main surface 1 is surrounded by the outer peripheral edge 9. The first main surface 1 is composed of a first central region 11 and a first outer peripheral region 12. The first outer peripheral region 12 is a region within 5 mm from the outer peripheral edge 9. The first central region 11 is surrounded by the first outer peripheral region 12. In the radial direction of the first main surface 1, a distance A2 between the boundary between the first central region 11 and the first outer peripheral region 12 and the outer peripheral edge 9 is 5 mm.

[0026] The outer peripheral edge 9 has, for example, an orientation flat 8 and an arc-shaped portion 7. The orientation flat 8 extends along a first direction 101. As shown in FIG. 1 , the orientation flat 8 is linear when viewed in a direction perpendicular to the first main surface 1. The arc-shaped portion 7 is continuous with the orientation flat 8. The arc-shaped portion 7 is arc-shaped when viewed in a direction perpendicular to the first main surface 1.

[0027] 1 , when viewed in a direction perpendicular to the first main surface 1, the first main surface 1 extends along a first direction 101 and a second direction 102. When viewed in a direction perpendicular to the first main surface 1, the second direction 102 is a direction perpendicular to the first direction 101.

[0028] The maximum diameter A1 of the first main surface 1 is, for example, 100 mm (4 inches) or more. The maximum diameter A1 of the first main surface 1 may be 150 mm (6 inches) or more, or 200 mm (8 inches) or more. The maximum diameter A1 of the first main surface 1 is not particularly limited, but may be, for example, 400 mm (16 inches) or less. The maximum diameter A1 of the first main surface 1 is the longest linear distance between two different points on the outer circumferential edge 9.

[0029] In this specification, 4 inches refers to 100 mm or 101.6 mm (4 inches x 25.4 mm / inch). 6 inches refers to 150 mm or 152.4 mm (6 inches x 25.4 mm / inch). 8 inches refers to 200 mm or 203.2 mm (8 inches x 25.4 mm / inch). 16 inches refers to 400 mm or 406.4 mm (16 inches x 25.4 mm / inch).

[0030] As shown in FIG. 1 , the semiconductor substrate 100 has a reference mark 3. At least two reference marks 3 are provided on the first main surface 1. As shown in FIG. 1 , for example, two reference marks 3 are provided in the first outer peripheral region 12. Each of the two or more reference marks 3 serves as a reference for two-dimensional position coordinates. As shown in FIG. 1 , when viewed in a direction perpendicular to the first main surface 1, each of the two or more reference marks 3 may be located in a region (first outer peripheral region 12) within 5 mm from the orientation flat. The number of reference marks 3 is not particularly limited, but may be, for example, three or more, or four or more.

[0031] 1 , when viewed in a direction perpendicular to the first main surface 1, the distance A3 between the two reference marks 3 is, for example, 30 mm or more. The distance A3 between the two reference marks 3 is not particularly limited, but may be, for example, 40 mm or more, or 50 mm or more. The distance A3 between the two reference marks 3 is not particularly limited, but may be, for example, 200 mm or less, or 150 mm or less.

[0032] 1 , each of the two or more reference marks 3 may have a cross shape when viewed in a direction perpendicular to the first main surface 1. The two or more reference marks 3 include, for example, a first reference mark 13 and a second reference mark 14. A distance A3 between the first reference mark 13 and the second reference mark 14 is the distance from the center of the first reference mark 13 to the center of the second reference mark 14.

[0033] 2 is an enlarged plan view showing region II in FIG. 1. As shown in FIG. 2, the reference mark 3 is configured by a recess 24 formed in the first main surface 1 and serves as a reference for in-plane coordinates. When viewed in a direction perpendicular to the first main surface 1, the shape of the reference mark 3 is, for example, axially symmetric. The shape of the reference mark 3 is, for example, a cross shape. For example, two recesses 24 may be provided so as to intersect perpendicularly at the center. The reference mark 3 may be formed by a single recess 24, or may be formed by a plurality of recesses 24, for example, like a collection of processing marks.

[0034] The shape of the reference mark 3 is not limited to a cross shape. The shape of the reference mark 3 may be a polygon, an axisymmetric rectangle (rectangle, square), or a circle. The reference mark 3 has a shape that can be surrounded by, for example, a virtual circle. The smallest virtual circle that surrounds the reference mark 3 is, for example, the circumscribing circle of the reference mark 3. The center of the reference mark 3 is the center of the circumscribing circle.

[0035] When viewed in a direction perpendicular to the first main surface 1, the radius of the smallest imaginary circle (first imaginary circle R1) surrounding each of the multiple reference marks 3 is, for example, greater than 10 μm and less than 3 mm. The radius of the first imaginary circle R1 is not particularly limited, but may be, for example, 50 μm or more, or 100 μm or more. The radius of the first imaginary circle R1 is not particularly limited, but may be, for example, 1 mm or less, or 0.5 mm or less.

[0036] 2, the largest imaginary circle (second imaginary circle R2) enclosed by the reference mark 3 is, for example, the inscribed circle of the reference mark 3. The center of the inscribed circle of the reference mark 3 may coincide with the center of the circumscribed circle of the reference mark 3. When viewed in a direction perpendicular to the first main surface 1, the radius of the second imaginary circle R2 is, for example, less than 15 μm.

[0037] The fiducial mark 3 serves as the reference for in-plane coordinates. The X-axis is a line passing through the center of the first fiducial mark 13 and the center of the second fiducial mark 14. The Y-axis is a line parallel to the first principal surface 1 and perpendicular to the X-axis. The midpoint between the center of the first fiducial mark 13 and the center of the second fiducial mark 14 is, for example, the origin of the two-dimensional position coordinates. The direction from the origin toward the first fiducial mark 13 is, for example, the negative X-axis. The direction from the origin toward the second fiducial mark 14 is, for example, the positive X-axis. The direction from the origin toward the orientation flat 8 is, for example, the negative Y-axis. The direction opposite to the direction from the origin toward the orientation flat 8 is, for example, the positive Y-axis. For example, as described above, a virtual two-dimensional position coordinate system is determined based on the first fiducial mark 13 and the second fiducial mark 14.

[0038] FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG. 2. As shown in FIG. 3, the semiconductor substrate 100 according to the first embodiment includes a semiconductor substrate 105 and an epitaxial growth suppression film 30. The semiconductor substrate 105 includes a first main surface 1 and a second main surface 2. The second main surface 2 is located on the opposite side of the first main surface 1. The recess 24 is provided so as to open to the first main surface 1. The recess 24 includes a first side surface 22 and a first bottom surface 23. The first bottom surface 23 is continuous with the first side surface 22. The first main surface 1 includes a first flat surface 21. The first side surface 22 is continuous with the first flat surface 21. The first flat surface 21 may be parallel to the second main surface 2. In the thickness direction of the semiconductor substrate 105, the first bottom surface 23 of the recess 24 is located between the first flat surface 21 and the second main surface 2.

[0039] The semiconductor substrate 105 is made of a semiconductor material. The semiconductor material is, for example, silicon carbide (SiC). The semiconductor material may be a semiconductor other than silicon carbide. The semiconductor material may be, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), gallium oxide (GaO), or diamond. Each of the first main surface 1 and the second main surface 2 is made of a semiconductor material.

[0040] When the semiconductor substrate 105 is made of silicon carbide, the semiconductor substrate 105 may be a conductive substrate or a semi-insulating substrate. When the semiconductor substrate 105 is a conductive substrate, the polytype of the silicon carbide may be 4H. When the semiconductor substrate 105 is a semi-insulating substrate, the polytype of the silicon carbide may be 4H or 6H. The thickness of the semiconductor substrate 105 is, for example, 350 μm or more and 500 μm or less. The semiconductor substrate 105 contains, for example, an n-type impurity such as nitrogen (N). The conductivity type of the semiconductor substrate 105 is, for example, n-type.

[0041] When the semiconductor substrate 105 is made of hexagonal silicon carbide, the first direction 101 is, for example, the <11-20> direction. The first direction 101 may be, for example, the [11-20] direction. The first direction 101 may be, for example, a direction obtained by projecting the <11-20> direction onto the first main surface 1. From another perspective, the first direction 101 may be, for example, a direction including a <11-20> direction component.

[0042] The second direction 102 is, for example, the <1-100> direction. The second direction 102 may be, for example, the [1-100] direction. The second direction 102 may be, for example, a direction obtained by projecting the <1-100> direction onto the first main surface 1. From another perspective, the second direction 102 may be, for example, a direction including a <1-100> direction component.

[0043] First main surface 1 may be a {0001} plane or a plane inclined with respect to the {0001} plane. When first main surface 1 is inclined with respect to the {0001} plane, the inclination angle (off angle) with respect to the {0001} plane is, for example, 1° or more and 8° or less. When first main surface 1 is inclined with respect to the {0001} plane, the inclination direction (off direction) of first main surface 1 is, for example, the <11-20> direction.

[0044] The epitaxial growth suppression film 30 is provided on at least a portion of the interior of the recess 24. The epitaxial growth suppression film 30 is in contact with, for example, the first bottom surface 23. The epitaxial growth suppression film 30 may also be in contact with a portion of the first side surface 22.

[0045] The epitaxial growth suppression film 30 is made of a material different from the semiconductor material that makes up the first main surface 1 of the semiconductor substrate 105. The lattice constant of the material that makes up the epitaxial growth suppression film 30 is different from the lattice constant of the semiconductor material. The material that makes up the epitaxial growth suppression film 30 may be amorphous or polycrystalline. It is desirable that the material that makes up the epitaxial growth suppression film 30 does not decompose in the temperature range in which the semiconductor material is formed by epitaxial growth. The melting point of the material that makes up the epitaxial growth suppression film 30 is, for example, 1700°C or higher.

[0046] The melting point of the material constituting the epitaxial growth suppression film 30 is not particularly limited, but may be, for example, 2000° C. or higher, 2500° C. or higher, or 3000° C. or higher. The melting point of the material constituting the epitaxial growth suppression film 30 is not particularly limited, but may be, for example, 4500° C. or lower, 4000° C. or lower, or 3500° C. or lower. In particular, when the semiconductor layer is made of SiC, epitaxial growth occurs at a high temperature of about 1600° C., so it is preferable that the melting point of the material constituting the epitaxial growth suppression film 30 be high.

[0047] The material constituting the epitaxial growth suppression film 30 contains, for example, boron, carbon, nitrogen, or oxygen. The material constituting the epitaxial growth suppression film 30 is, for example, graphite, diamond, silicon dioxide (SiO), silicon nitride (SiN), or boron nitride (BN). The melting points of graphite, diamond, silicon dioxide, silicon nitride, and boron nitride are 3700°C or higher and 4300°C or lower, 3548°C, 1732°C, 1900°C, and 2700°C, respectively.

[0048] The epitaxial growth suppression film 30 may be made of a material containing a metal element such as titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), magnesium (Mg), yttrium (Y), aluminum (Al), nickel (Ni), zinc (Zn), or gallium (Ga). Specifically, the epitaxial growth suppression film 30 is an oxide, nitride, carbide, or boride of the above metal element or a compound with another element.

[0049] The depth (first depth B1) of the recess 24 may be, for example, greater than 0.5 μm and less than 100 μm. The first depth B1 is not particularly limited, but may be, for example, greater than 1 μm or greater than 10 μm. The first depth B1 is not particularly limited, but may be, for example, less than 90 μm or less than 80 μm. The first depth B1 is the distance between the first bottom surface 23 and the first flat surface 21 in the thickness direction of the semiconductor substrate 105.

[0050] The shape of the recess 24 may be, for example, a forward taper. Specifically, the width of the recess 24 may increase from the first main surface 1 toward the second main surface 2. The shape of the recess 24 may be an inverse taper. Specifically, the width of the recess 24 may decrease from the first main surface 1 toward the second main surface 2. The first side surface 22 of the recess 24 may be perpendicular to the first bottom surface 23 of the recess 24.

[0051] The thickness of the epitaxial growth suppression film 30 (third thickness B3) may be, for example, 0.25 times or more the depth of the recess 24 (first depth B1). The third thickness B3 is not particularly limited, but may be, for example, 0.3 times or more the first depth B1, or 0.35 times or more the first depth B1. The third thickness B3 is not particularly limited, but may be, for example, 1 time or less the first depth B1, or 0.8 times or less the first depth B1.

[0052] Second Embodiment Next, the configuration of a semiconductor substrate 100 according to a second embodiment will be described. The semiconductor substrate 100 according to the second embodiment differs from the semiconductor substrate 100 according to the first embodiment mainly in that the epitaxial growth suppression film 30 is in contact with each of the side surface 22 and the bottom surface 23 of the recess 24, but is otherwise similar to the semiconductor substrate 100 according to the first embodiment. The following description will focus on the configuration that differs from the semiconductor substrate 100 according to the first embodiment.

[0053] 4 is a cross-sectional view showing a configuration of a semiconductor substrate 100 according to the second embodiment. As shown in FIG. 4, the epitaxial growth suppression film 30 of the semiconductor substrate 100 according to the second embodiment is in contact with each of the side surface 22 and the bottom surface 23 of the recess 24. The epitaxial growth suppression film 30 may be formed along the entire surface of the side surface 22. The epitaxial growth suppression film 30 may be in contact with the entire surface of the side surface 22.

[0054] 4 , a depression (first depression 34) may be formed by the epitaxial growth suppression film 30. Specifically, the epitaxial growth suppression film 30 has a second side surface 32, a second bottom surface 33, and a first top surface 35. The second side surface 32 is continuous with the second bottom surface 33. The first top surface 35 is continuous with the second side surface 32. The first top surface 35 may be formed along the first flat surface 21.

[0055] The first recess 34 is composed of a second side surface 32 and a second bottom surface 33. The second side surface 32 faces the first side surface 22. The second bottom surface 33 faces the first bottom surface 23. The width (second width W2) of the first recess 34 may be smaller than the width (first width W1) of the recess 24. The depth (second depth B2) of the first recess 34 may be smaller than the depth (first depth B1) of the recess 24.

[0056] Third Embodiment Next, the configuration of a semiconductor substrate 100 according to a third embodiment will be described. The semiconductor substrate 100 according to the third embodiment differs from the semiconductor substrate 100 according to the first embodiment mainly in that the recesses 24 are filled with an epitaxial growth suppression film 30, but is otherwise similar to the semiconductor substrate 100 according to the first embodiment. The following description will focus on the configuration that differs from the semiconductor substrate 100 according to the first embodiment.

[0057] 5 is a cross-sectional view schematically illustrating a configuration of a semiconductor substrate 100 according to the third embodiment. As illustrated in FIG. 5 , the recess 24 may be filled with an epitaxial growth suppression film 30. The epitaxial growth suppression film 30 contacts each of the first side surface 22 and the first bottom surface 23 of the recess 24. The epitaxial growth suppression film 30 may completely fill the recess 24. The epitaxial growth suppression film 30 has a first top surface 35. The first top surface 35 may be formed along the first flat surface 21.

[0058] Fourth Embodiment Next, the configuration of a semiconductor epitaxial substrate 200 according to the fourth embodiment will be described. Fig. 6 is a cross-sectional schematic diagram showing the configuration of the semiconductor epitaxial substrate 200 according to the fourth embodiment. As shown in Fig. 6, the semiconductor epitaxial substrate 200 according to the fourth embodiment has the semiconductor substrate 100 according to the first embodiment and an epitaxial layer 40. The epitaxial layer 40 is provided on at least a portion of the first main surface 1 of the semiconductor substrate 100.

[0059] The epitaxial layer 40 has a third main surface 41, a fourth main surface 42, and a third side surface 43. The fourth main surface 42 is located opposite the third main surface 41. The third side surface 43 is continuous with each of the third main surface 41 and the fourth main surface 42. The fourth main surface 42 is in contact with the first main surface 1. The third side surface 43 may be formed along the first side surface 22. The epitaxial layer 40 may be a homostructure epitaxial layer 40 or a heterostructure epitaxial layer 40. The epitaxial layer 40 may be a single layer or two or more layers.

[0060] In the semiconductor epitaxial substrate 200 according to the fourth embodiment, the epitaxial layer 40 is not formed on the epitaxial growth suppression film 30. From another perspective, the epitaxial layer 40 is spaced apart from the epitaxial growth suppression film 30.

[0061] Fifth Embodiment Next, the configuration of a semiconductor epitaxial substrate 200 according to the fifth embodiment will be described. Fig. 7 is a cross-sectional schematic view showing the configuration of the semiconductor epitaxial substrate 200 according to the fifth embodiment. As shown in Fig. 7, the semiconductor epitaxial substrate 200 according to the fifth embodiment has the semiconductor substrate 100 according to the second embodiment and an epitaxial layer 40. The epitaxial layer 40 is provided on at least a portion of the first main surface 1 of the semiconductor substrate 100.

[0062] The epitaxial layer 40 has a third main surface 41, a fourth main surface 42, and a third side surface 43. The fourth main surface 42 is located opposite the third main surface 41. The third side surface 43 is continuous with each of the third main surface 41 and the fourth main surface 42. The fourth main surface 42 is in contact with the first main surface 1. The third side surface 43 may be formed along the first side surface 22. In the semiconductor epitaxial substrate 200 according to the fifth embodiment, the epitaxial layer 40 is not formed on the epitaxial growth suppression film 30.

[0063] Sixth Embodiment Next, the configuration of a semiconductor epitaxial substrate 200 according to the sixth embodiment will be described. Fig. 8 is a cross-sectional schematic diagram showing the configuration of the semiconductor epitaxial substrate 200 according to the sixth embodiment. As shown in Fig. 8, the semiconductor epitaxial substrate 200 according to the sixth embodiment has the semiconductor substrate 100 according to the third embodiment and an epitaxial layer 40. The epitaxial layer 40 is provided on at least a portion of the first main surface 1 of the semiconductor substrate 100.

[0064] The epitaxial layer 40 has a third main surface 41, a fourth main surface 42, and a third side surface 43. The fourth main surface 42 is located opposite the third main surface 41. The third side surface 43 is continuous with each of the third main surface 41 and the fourth main surface 42. The fourth main surface 42 is in contact with the first main surface 1. The third side surface 43 may be formed along the first side surface 22. In the semiconductor epitaxial substrate 200 according to the sixth embodiment, the epitaxial layer 40 is not formed on the epitaxial growth suppression film 30.

[0065] Seventh Embodiment Next, the configuration of a semiconductor epitaxial substrate 200 according to the seventh embodiment will be described. Fig. 9 is a cross-sectional schematic view showing the configuration of the semiconductor epitaxial substrate 200 according to the seventh embodiment. As shown in Fig. 9, the semiconductor epitaxial substrate 200 according to the seventh embodiment has the semiconductor substrate 100 according to the third embodiment, an epitaxial layer 40, and a semiconductor layer 90. The epitaxial layer 40 is provided on at least a part of the first main surface 1 of the semiconductor substrate 100.

[0066] The epitaxial layer 40 has a third major surface 41 and a fourth major surface 42. The fourth major surface 42 is located opposite the third major surface 41. The fourth major surface 42 is in contact with the first major surface 1.

[0067] The semiconductor layer 90 is formed on the epitaxial growth suppression film 30. The semiconductor layer 90 is a layer formed by suppressing epitaxial growth. The semiconductor layer 90 may be, for example, polycrystalline or amorphous. The material constituting the semiconductor layer 90 is the same as the material constituting the epitaxial layer 40.

[0068] The semiconductor layer 90 may be continuous with the epitaxial layer 40. The thickness (first thickness H1) of the epitaxial layer 40 may be greater than the minimum thickness (second thickness H2) of the semiconductor layer 90. A second recess 94 may be provided in the semiconductor layer 90. The second recess 94 is configured with a fourth side surface 92 and a fourth bottom surface 93. The fourth bottom surface 93 is continuous with the fourth side surface 92. The fourth side surface 92 may be curved so as to be convex outward. The fourth side surface 92 may be continuous with the third main surface 41.

[0069] In the above, the semiconductor epitaxial substrate 200 according to the seventh embodiment has been described as having a configuration including the semiconductor substrate 100 according to the third embodiment, the epitaxial layer 40, and the semiconductor layer 90. However, the present disclosure is not limited to the above configuration. The semiconductor epitaxial substrate 200 according to the seventh embodiment may have the semiconductor substrate 100, the epitaxial layer 40, and the semiconductor layer 90 according to the first embodiment, or may have the semiconductor substrate 100, the epitaxial layer 40, and the semiconductor layer 90 according to the second embodiment.

[0070] Eighth Embodiment Next, the configuration of a semiconductor epitaxial substrate 200 according to an eighth embodiment will be described. The semiconductor epitaxial substrate 200 according to the eighth embodiment differs from the semiconductor epitaxial substrate 200 according to the seventh embodiment mainly in that a portion of the epitaxial growth suppression film 30 is exposed from the semiconductor layer 90, but is otherwise similar to the semiconductor epitaxial substrate 200 according to the seventh embodiment. The following description will focus on the configuration that differs from the semiconductor epitaxial substrate 200 according to the seventh embodiment.

[0071] 10 is a cross-sectional view schematically illustrating the configuration of a semiconductor epitaxial substrate 200 according to the eighth embodiment. As shown in FIG. 10, a portion of the epitaxial growth suppression film 30 is exposed from the semiconductor layer 90. The second recess 94 is composed of a fourth side surface 92 and a first top surface 35. The fourth side surface 92 is formed by the semiconductor layer 90. The first top surface 35 is formed by the epitaxial growth suppression film 30.

[0072] Ninth Embodiment Next, the configuration of a semiconductor epitaxial substrate 200 according to a ninth embodiment will be described. The semiconductor epitaxial substrate 200 according to the ninth embodiment differs from the semiconductor substrate 100 according to the first embodiment mainly in that the reference marks 3 are formed in the first epitaxial layer 71, but is otherwise similar to the semiconductor substrate 100 according to the first embodiment. The following description will focus on the configuration that differs from the semiconductor substrate 100 according to the first embodiment.

[0073] 11 is a plan view schematically illustrating the configuration of a semiconductor epitaxial substrate 200 according to the ninth embodiment. As illustrated in FIG. 11 , the semiconductor epitaxial substrate 200 according to the ninth embodiment mainly includes a fifth main surface 5 and an outer peripheral edge 9. When viewed in a direction perpendicular to the fifth main surface 5, the fifth main surface 5 is surrounded by the outer peripheral edge 9. The fifth main surface 5 is composed of a second central region 51 and a second outer peripheral region 52. The second outer peripheral region 52 is a region within 5 mm from the outer peripheral edge 9. The second central region 51 is surrounded by the second outer peripheral region 52. In the radial direction of the fifth main surface 5, a distance A2 between the boundary between the second central region 51 and the second outer peripheral region 52 and the outer peripheral edge 9 is 5 mm.

[0074] 11 , when viewed in a direction perpendicular to the fifth main surface 5, the fifth main surface 5 extends along each of a first direction 101 and a second direction 102. When viewed in a direction perpendicular to the fifth main surface 5, the second direction 102 is a direction perpendicular to the first direction 101. The maximum diameter A1 of the fifth main surface 5 is substantially the same as the maximum diameter A1 of the first main surface 1.

[0075] As shown in FIG. 11 , the semiconductor epitaxial substrate 200 has a reference mark 3. At least two reference marks 3 are provided on the fifth main surface 5. For example, two reference marks 3 are provided in the second outer peripheral region 52. Each of the two or more reference marks 3 serves as a reference for two-dimensional position coordinates. As shown in FIG. 11 , when viewed in a direction perpendicular to the fifth main surface 5, each of the two or more reference marks 3 may be located in a region (second outer peripheral region 52) within 5 mm from the orientation flat 8.

[0076] The fifth main surface 5 may be a {0001} plane or a plane inclined with respect to the {0001} plane. When the fifth main surface 5 is inclined with respect to the {0001} plane, the inclination angle (off angle) with respect to the {0001} plane is, for example, 1° or more and 8° or less. When the fifth main surface 5 is inclined with respect to the {0001} plane, the inclination direction (off direction) of the fifth main surface 5 is, for example, the <11-20> direction.

[0077] 12 is an enlarged plan view showing region XII in FIG. 11. As shown in FIG. 12, the reference mark 3 is configured by a recess 24 formed in the fifth main surface 5 and serves as a reference for in-plane coordinates. When viewed in a direction perpendicular to the fifth main surface 5, the shape of the reference mark 3 is, for example, axially symmetric. The shape of the reference mark 3 is, for example, a cross shape. For example, two recesses 24 may be provided so as to intersect perpendicularly at the center. The reference mark 3 may be formed by a single recess 24, or may be formed by a plurality of recesses 24, for example, like a collection of processing marks.

[0078] 13 is a schematic cross-sectional view taken along line XIII-XIII in FIG. 12. As shown in FIG. 13, the semiconductor epitaxial substrate 200 according to the ninth embodiment includes a semiconductor substrate 105, a first epitaxial layer 71, and an epitaxial growth suppression film 30. The semiconductor substrate 105 includes a first main surface 1 and a second main surface 2. The second main surface 2 is located opposite the first main surface 1. The first epitaxial layer 71 is provided on the semiconductor substrate 105. The fifth main surface 5 is formed by the first epitaxial layer 71. The first epitaxial layer 71 includes a sixth main surface 6. The sixth main surface 6 is located opposite the fifth main surface 5. The sixth main surface 6 is in contact with the first main surface 1.

[0079] The recess 24 is provided so as to open to the fifth main surface 5. The recess 24 is composed of a first side surface 22 and a first bottom surface 23. The first bottom surface 23 is continuous with the first side surface 22. The fifth main surface 5 has a second flat surface 61. The first side surface 22 is continuous with the second flat surface 61. The second flat surface 61 may be parallel to the sixth main surface 6. In the thickness direction of the semiconductor substrate 105, the first bottom surface 23 of the recess 24 is located between the second flat surface 61 and the sixth main surface 6.

[0080] The semiconductor substrate 105 is made of a semiconductor material. Specific examples of the semiconductor material are as described above. The epitaxial growth suppression film 30 is made of a material different from the semiconductor material of the fifth main surface 5 of the semiconductor substrate 105. Specific examples of the material that makes up the epitaxial growth suppression film 30 are as described above.

[0081] The epitaxial growth suppression film 30 is provided in at least a portion of the interior of the recess 24. The epitaxial growth suppression film 30 is in contact with, for example, the first bottom surface 23. The epitaxial growth suppression film 30 may also be in contact with a portion of the first side surface 22. The configurations of the recess 24 and the epitaxial growth suppression film 30 are as described above.

[0082] Tenth Embodiment Next, the configuration of a semiconductor epitaxial substrate 200 according to a tenth embodiment will be described. The semiconductor epitaxial substrate 200 according to the tenth embodiment differs from the semiconductor epitaxial substrate 200 according to the ninth embodiment mainly in that the epitaxial growth suppression film 30 is in contact with each of the side surface 22 and the bottom surface 23 of the recess 24, but is otherwise similar to the semiconductor epitaxial substrate 200 according to the ninth embodiment. The following description will focus on the configuration that differs from the semiconductor epitaxial substrate 200 according to the ninth embodiment.

[0083] 14 is a cross-sectional view schematically illustrating the configuration of a semiconductor epitaxial substrate 200 according to the tenth embodiment. As shown in FIG. 14 , the epitaxial growth suppression film 30 of the semiconductor epitaxial substrate 200 according to the tenth embodiment is in contact with each of the first side surface 22 and the first bottom surface 23 of the recess 24. The epitaxial growth suppression film 30 may be formed along the entire surface of the first side surface 22. The epitaxial growth suppression film 30 may be in contact with the entire surface of the first side surface 22.

[0084] Eleventh Embodiment Next, the configuration of a semiconductor epitaxial substrate 200 according to an eleventh embodiment will be described. The semiconductor epitaxial substrate 200 according to the eleventh embodiment differs from the semiconductor epitaxial substrate 200 according to the tenth embodiment mainly in that the recesses 24 are filled with an epitaxial growth suppression film 30, but is otherwise similar to the semiconductor epitaxial substrate 200 according to the tenth embodiment. The following description will focus on the configuration that differs from the semiconductor epitaxial substrate 200 according to the tenth embodiment.

[0085] 15 is a cross-sectional view schematically illustrating the configuration of a semiconductor epitaxial substrate 200 according to the eleventh embodiment. As illustrated in FIG. 15 , the recess 24 may be filled with an epitaxial growth suppression film 30. The epitaxial growth suppression film 30 contacts each of the first side surface 22 and the first bottom surface 23 of the recess 24. The epitaxial growth suppression film 30 may completely fill the recess 24. The first top surface 35 of the epitaxial growth suppression film 30 may be formed along the second flat surface 61.

[0086] Twelfth Embodiment Next, the configuration of a semiconductor epitaxial substrate 200 according to a twelfth embodiment will be described. The semiconductor epitaxial substrate 200 according to the twelfth embodiment differs from the semiconductor epitaxial substrate 200 according to the ninth embodiment mainly in that it has a second epitaxial layer 72, but is otherwise similar to the semiconductor epitaxial substrate 200 according to the ninth embodiment. The following description will focus on the configuration that differs from the semiconductor epitaxial substrate 200 according to the ninth embodiment.

[0087] 16 is a cross-sectional view schematically illustrating the configuration of a semiconductor epitaxial substrate 200 according to the twelfth embodiment. As illustrated in FIG. 16, the semiconductor epitaxial substrate 200 according to the twelfth embodiment further includes a second epitaxial layer 72. The second epitaxial layer 72 is provided on at least a portion of the fifth main surface 5. As illustrated in FIG. 16, the second epitaxial layer 72 does not have to be formed on the epitaxial growth suppression film 30. From another perspective, the second epitaxial layer 72 may be spaced apart from the epitaxial growth suppression film 30.

[0088] Thirteenth Embodiment Next, the configuration of a semiconductor epitaxial substrate 200 according to a thirteenth embodiment will be described. The semiconductor epitaxial substrate 200 according to the thirteenth embodiment differs from the semiconductor epitaxial substrate 200 according to the tenth embodiment mainly in that it has a second epitaxial layer 72, but is otherwise similar to the semiconductor epitaxial substrate 200 according to the tenth embodiment. The following description will focus on the configuration that differs from the semiconductor epitaxial substrate 200 according to the tenth embodiment.

[0089] 17 is a cross-sectional view schematically illustrating the configuration of a semiconductor epitaxial substrate 200 according to the thirteenth embodiment. As illustrated in FIG. 17 , the semiconductor epitaxial substrate 200 according to the thirteenth embodiment further includes a second epitaxial layer 72. The second epitaxial layer 72 is provided on at least a portion of the fifth main surface 5. As illustrated in FIG. 17 , the second epitaxial layer 72 does not have to be formed on the epitaxial growth suppression film 30. From another perspective, the second epitaxial layer 72 may be spaced apart from the epitaxial growth suppression film 30.

[0090] Fourteenth Embodiment Next, the configuration of a semiconductor epitaxial substrate 200 according to a fourteenth embodiment will be described. The semiconductor epitaxial substrate 200 according to the fourteenth embodiment differs from the semiconductor epitaxial substrate 200 according to the eleventh embodiment mainly in that it has a second epitaxial layer 72, but is otherwise similar to the semiconductor epitaxial substrate 200 according to the eleventh embodiment. The following description will focus on the configuration that differs from the semiconductor epitaxial substrate 200 according to the eleventh embodiment.

[0091] 18 is a cross-sectional view schematically illustrating the configuration of a semiconductor epitaxial substrate 200 according to the fourteenth embodiment. As illustrated in FIG. 18 , the semiconductor epitaxial substrate 200 according to the fourteenth embodiment further includes a second epitaxial layer 72. The second epitaxial layer 72 is provided on at least a portion of the fifth main surface 5. As illustrated in FIG. 18 , the second epitaxial layer 72 does not have to be formed on the epitaxial growth suppression film 30. From another perspective, the second epitaxial layer 72 may be spaced apart from the epitaxial growth suppression film 30.

[0092] Fifteenth Embodiment Next, the configuration of a semiconductor epitaxial substrate 200 according to the fifteenth embodiment will be described. Fig. 19 is a cross-sectional schematic view showing the configuration of the semiconductor epitaxial substrate 200 according to the fifteenth embodiment. As shown in Fig. 19, the semiconductor epitaxial substrate 200 according to the fifteenth embodiment has the semiconductor epitaxial substrate 200 according to the eleventh embodiment, a second epitaxial layer 72, and a semiconductor layer 90. The second epitaxial layer 72 is provided on at least a part of the fifth main surface 5 of the first epitaxial layer 71.

[0093] The second epitaxial layer 72 has a seventh major surface 81 and an eighth major surface 82. The eighth major surface 82 is located opposite the seventh major surface 81. The eighth major surface 82 is in contact with the fifth major surface 5.

[0094] The semiconductor layer 90 is formed on the epitaxial growth suppression film 30. The semiconductor layer 90 is a layer formed by suppressing epitaxial growth. The semiconductor layer 90 may be, for example, polycrystalline or amorphous. The material constituting the semiconductor layer 90 is the same as the material constituting the epitaxial layer 40.

[0095] The semiconductor layer 90 may be continuous with the second epitaxial layer 72. The thickness (first thickness H1) of the second epitaxial layer 72 may be greater than the minimum thickness (second thickness H2) of the semiconductor layer 90. A second recess 94 may be provided in the semiconductor layer 90. The second recess 94 is configured with a fourth side surface 92 and a fourth bottom surface 93. The fourth bottom surface 93 is continuous with the fourth side surface 92. The fourth side surface 92 may be curved so as to be convex outward. The fourth side surface 92 may be continuous with the seventh main surface 81.

[0096] In the above, the semiconductor epitaxial substrate 200 according to the fifteenth embodiment has been described as having a configuration including the semiconductor epitaxial substrate 200 according to the eleventh embodiment, the second epitaxial layer 72, and the semiconductor layer 90. However, the present disclosure is not limited to the above configuration. The semiconductor epitaxial substrate 200 according to the fifteenth embodiment may have the semiconductor epitaxial substrate 200 according to the twelfth embodiment, the second epitaxial layer 72, and the semiconductor layer 90, or may have the semiconductor epitaxial substrate 200 according to the thirteenth embodiment, the second epitaxial layer 72, and the semiconductor layer 90.

[0097] Sixteenth Embodiment Next, the configuration of a semiconductor epitaxial substrate 200 according to a sixteenth embodiment will be described. The semiconductor epitaxial substrate 200 according to the sixteenth embodiment differs from the semiconductor epitaxial substrate 200 according to the fifteenth embodiment mainly in that a portion of the epitaxial growth suppression film 30 is exposed from the semiconductor layer 90, but is otherwise similar to the semiconductor epitaxial substrate 200 according to the fifteenth embodiment. The following description will focus on the configuration that differs from the semiconductor epitaxial substrate 200 according to the fifteenth embodiment.

[0098] 20 is a cross-sectional view schematically illustrating the configuration of a semiconductor epitaxial substrate 200 according to the sixteenth embodiment. As shown in FIG. 20 , a portion of the epitaxial growth suppression film 30 is exposed from the semiconductor layer 90. The second recess 94 is composed of a fourth side surface 92 and a first top surface 35. The fourth side surface 92 is formed by the semiconductor layer 90. The first top surface 35 is formed by the epitaxial growth suppression film 30.

[0099] (Method for Manufacturing Semiconductor Substrate) Next, a first method for manufacturing the semiconductor substrate 100 according to the second embodiment will be described.

[0100] <Lift-off method> Fig. 21 is a flow diagram that schematically shows a first manufacturing method for the semiconductor substrate 100 according to the second embodiment. As shown in Fig. 21, the first manufacturing method for the semiconductor substrate 100 according to the second embodiment mainly includes a step (S11) of preparing a semiconductor substrate 105, a step (S12) of applying a resist, a step (S13) of forming an opening by photolithography, a step (S14) of etching the semiconductor substrate 105 in the opening, a step (S15) of forming an epitaxial growth suppression film 30, and a step (S16) of performing lift-off.

[0101] First, a step (S11) of preparing a semiconductor substrate 105 is performed. For example, a silicon carbide single crystal of polytype 4H is produced by sublimation deposition. Next, the silicon carbide single crystal is sliced ​​using, for example, a wire saw to prepare the semiconductor substrate 105. FIG. 22 is a cross-sectional schematic diagram showing the step of preparing the semiconductor substrate. As shown in FIG. 22, the semiconductor substrate 105 has a first main surface 1 and a second main surface 2. The second main surface 2 is located on the opposite side of the first main surface 1. After slicing the semiconductor substrate 105, the first main surface 1 or the second main surface 2 may be polished, or the semiconductor substrate 105 may be cleaned.

[0102] Next, a resist application step (S12) is performed. Fig. 23 is a schematic cross-sectional view showing the resist application step. As shown in Fig. 23, a resist layer 106 is applied onto the semiconductor substrate 105. The resist layer 106 is formed on the first main surface 1 of the semiconductor substrate 105.

[0103] Next, a step (S13) of forming an opening by photolithography is performed. Fig. 24 is a cross-sectional view showing the step of forming an opening by photolithography. As shown in Fig. 24, an opening 103 is formed in the resist layer 106 by using a photolithography method. A portion of the first main surface 1 of the semiconductor substrate 105 is exposed in the opening 103 formed in the resist layer 106.

[0104] Next, a step (S14) of etching the semiconductor substrate 105 in the opening 103 is performed. FIG. 25 is a schematic cross-sectional view showing the step of etching the semiconductor substrate in the opening 103. As shown in FIG. 25 , a portion of the semiconductor substrate 105 is etched in the opening 103 by using an etching method. As a result, a recess 24 is formed in the first main surface 1 of the semiconductor substrate 105. The recess 24 is formed so as to open to the first main surface 1. The recess 24 is composed of a first side surface 22 and a first bottom surface 23. The first bottom surface 23 is continuous with the first side surface 22.

[0105] Next, a step (S15) of forming an epitaxial growth suppression film 30 is performed. Fig. 26 is a first schematic cross-sectional view showing the step of forming the epitaxial growth suppression film 30. As shown in Fig. 26, the epitaxial growth suppression film 30 is formed on the semiconductor substrate 105. The epitaxial growth suppression film 30 is formed on the resist layer 106 and inside the recess 24. The epitaxial growth suppression film 30 may be formed so as to contact each of the first side surface 22 and the first bottom surface 23.

[0106] The epitaxial growth suppression film 30 can be formed by physical vapor deposition (PVD) methods such as vacuum deposition, sputtering, and ion plating, or by chemical vapor deposition (CVD). From the perspective of improving the embedding performance of the epitaxial growth suppression film 30, it is desirable to use, among the above-mentioned formation methods, ion plating, which has high adhesion, or chemical vapor deposition (CVD), which has high coverage or adhesion even when the surface is uneven. The above-mentioned method for forming the epitaxial growth suppression film 30 can also be applied to polishing method 1 and polishing method 2, which will be described later.

[0107] Next, a lift-off step (S16) is performed. In the lift-off step (S16), the resist layer 106 is removed from the semiconductor substrate 105 by lift-off. The epitaxial growth suppression film 30 formed on the resist layer 106 is removed together with the resist layer 106. The epitaxial growth suppression film 30 formed in the recess 24 is left in the recess 24. In this way, the semiconductor substrate 100 according to the second embodiment is manufactured (see FIG. 4 ).

[0108] Next, a second manufacturing method for the semiconductor substrate 100 according to the second embodiment will be described. <Polishing Method 1> Fig. 27 is a flow chart that schematically shows the second manufacturing method for the semiconductor substrate 100 according to the second embodiment. As shown in Fig. 27, the second manufacturing method for the semiconductor substrate 100 according to the second embodiment mainly includes the steps of preparing a semiconductor substrate 105 (S21), applying a resist (S22), forming an opening 103 by photolithography (S23), etching the semiconductor substrate 105 in the opening 103 (S24), forming an epitaxial growth suppression film 30 (S25), and performing a surface polishing process (S26).

[0109] First, a step (S21) of preparing a semiconductor substrate 105 is performed. After slicing the semiconductor substrate 105, the first main surface 1 or the second main surface 2 may be polished, or the semiconductor substrate 105 may be cleaned. The step (S21) of preparing a semiconductor substrate 105 in the second manufacturing method is the same as the step (S11) of preparing a semiconductor substrate 105 in the first manufacturing method (see FIG. 22). Next, a step (S22) of applying a resist is performed. The step (S22) of applying a resist in the second manufacturing method is the same as the step (S12) of applying a resist in the first manufacturing method (see FIG. 23).

[0110] Next, a step (S23) of forming the opening 103 by photolithography is performed. The step (S23) of forming the opening 103 by photolithography in the second manufacturing method is the same as the step (S13) of forming the opening 103 by photolithography in the first manufacturing method (see FIG. 24). Next, a step (S24) of etching the semiconductor substrate 105 in the opening 103 is performed. The step (S24) of etching the semiconductor substrate 105 in the opening 103 in the second manufacturing method is the same as the step (S14) of etching the semiconductor substrate 105 in the opening 103 in the first manufacturing method (see FIG. 25). After forming the recess 24 in the first main surface 1 by etching the semiconductor substrate 105, the resist layer 106 is removed from the first main surface 1.

[0111] Next, a step (S25) of forming an epitaxial growth suppression film 30 is performed. Fig. 28 is a second schematic cross-sectional view showing the step of forming the epitaxial growth suppression film 30. As shown in Fig. 28, the epitaxial growth suppression film 30 is formed on the semiconductor substrate 105. The epitaxial growth suppression film 30 is formed on the first main surface 1. Specifically, the epitaxial growth suppression film 30 is formed so as to contact each of the first flat surface 21, the first side surface 22, and the first bottom surface 23.

[0112] Next, a surface processing and polishing step (S26) is performed. In the surface processing and polishing step (S26), a portion of the epitaxial growth suppression film 30 is polished. This removes a portion of the epitaxial growth suppression film 30 formed on the first flat surface 21. The epitaxial growth suppression film 30 formed in the recess 24 is left in the recess 24. In this manner, the semiconductor substrate 100 according to the second embodiment is manufactured (see FIG. 4).

[0113] Next, a third manufacturing method for the semiconductor substrate 100 according to the second embodiment will be described. <Polishing Method 2> Fig. 29 is a flow chart that schematically shows the third manufacturing method for the semiconductor substrate 100 according to the second embodiment. As shown in Fig. 29, the third manufacturing method for the semiconductor substrate 100 according to the second embodiment mainly includes a step (S31) of preparing a semiconductor substrate 105, a step (S32) of performing laser processing on the semiconductor substrate 105, a step (S33) of forming an epitaxial growth suppression film 30, and a step (S34) of performing surface polishing.

[0114] First, a step (S31) of preparing a semiconductor substrate 105 is performed. After slicing the semiconductor substrate 105, the first main surface 1 or the second main surface 2 may be polished, or the semiconductor substrate 105 may be cleaned. The step (S31) of preparing a semiconductor substrate 105 in the third manufacturing method is the same as the step (S11) of preparing a semiconductor substrate 105 in the first manufacturing method (see FIG. 22 ).

[0115] Next, a step (S32) of performing laser processing on the semiconductor substrate 105 is performed. FIG. 30 is a cross-sectional schematic diagram showing the step of performing laser processing on the semiconductor substrate. As shown in FIG. 30 , laser processing is performed on the semiconductor substrate 105, thereby removing a portion of the semiconductor substrate 105. As a result, a recess 24 is formed in the first main surface 1 of the semiconductor substrate 105. The recess 24 is formed so as to open to the first main surface 1. The recess 24 is composed of a first side surface 22 and a first bottom surface 23. The first bottom surface 23 is continuous with the first side surface 22.

[0116] Next, a step (S33) of forming epitaxial growth suppression film 30 is performed. The step (S33) of forming epitaxial growth suppression film 30 in the third manufacturing method is the same as the step (S25) of forming epitaxial growth suppression film 30 in the second manufacturing method (see FIG. 28 ).

[0117] Next, a surface processing and polishing step (S34) is performed. The surface processing and polishing step (S34) of the third manufacturing method is the same as the surface processing and polishing step (S26) of the second manufacturing method. In this way, the semiconductor substrate 100 according to the second embodiment is manufactured (see FIG. 4).

[0118] Next, a fourth manufacturing method for the semiconductor substrate 100 according to the second embodiment will be described. <Polishing Method 3> Figure 31 is a flow chart that schematically shows the fourth manufacturing method for the semiconductor substrate 100 according to the second embodiment. As shown in Figure 31, the fourth manufacturing method for the semiconductor substrate 100 according to the second embodiment mainly includes the steps of preparing a semiconductor substrate 105 (S41), performing laser processing on the semiconductor substrate 105 (S42), forming an epitaxial growth suppression film 30 (S43), performing heat treatment (S44), and performing surface polishing (S45).

[0119] First, a step (S41) of preparing a semiconductor substrate 105 is performed. After slicing the semiconductor substrate 105, the first main surface 1 or the second main surface 2 may be polished, or the semiconductor substrate 105 may be cleaned. The step (S41) of preparing a semiconductor substrate 105 in the fourth manufacturing method is the same as the step (S11) of preparing a semiconductor substrate 105 in the first manufacturing method (see FIG. 22). Next, a step (S42) of performing laser processing on the semiconductor substrate 105 is performed. The step (S42) of performing laser processing on the semiconductor substrate 105 in the fourth manufacturing method is the same as the step (S32) of performing laser processing on the semiconductor substrate 105 in the third manufacturing method (see FIG. 30).

[0120] Next, a step (S43) of applying the epitaxial growth suppression film 30 is performed. First, a coating liquid in which the material constituting the epitaxial growth suppression film 30 is dissolved in a solvent is applied onto the first main surface 1 of the semiconductor substrate 105 using a spin coater. As the semiconductor substrate 105 rotates, the coating liquid spreads over the first main surface 1 due to centrifugal force. The coating liquid may be applied to the entire surface of the first main surface 1, or may be applied only to the portion that has been subjected to laser processing. The coating method is not particularly limited. The coating method may be a method using a dispenser or a method using inkjet technology.

[0121] Next, a heat treatment step (S44) is performed. Specifically, the epitaxial growth suppression film 30 is heated to evaporate the solvent contained in the epitaxial growth suppression film 30. As a result, the solvent is removed from the epitaxial growth suppression film 30, and the epitaxial growth suppression film 30 is solidified.

[0122] Next, a surface processing and polishing step (S45) is performed. The surface processing and polishing step (S45) of the fourth manufacturing method is the same as the surface processing and polishing step (S26) of the second manufacturing method. In this way, the semiconductor substrate 100 according to the second embodiment is manufactured (see FIG. 4).

[0123] Next, the effects of the semiconductor substrate 100 and the semiconductor epitaxial substrate 200 according to the above embodiment will be described.

[0124] For example, defects caused by the material can be a cause of defects in elements made of semiconductor materials such as silicon carbide. Defects caused by the material include defects occurring in the epitaxial layer 40, which is the active region of the element, and defects occurring in the semiconductor substrate 105, which is the substrate underlying the epitaxial layer 40. If the position coordinates of the defect within the wafer surface are known in advance, it is possible to classify elements into good and bad products in advance. Furthermore, by predicting the defect rate of elements in advance, it becomes possible to optimally design element structures or element layouts.

[0125] In order to link the plane coordinates where a defect exists with the plane coordinates of an element, it is effective to form a fiducial mark 3 in advance on the substrate as a reference for the plane coordinates. This allows for accurate identification of defective elements caused by defects. The recessed fiducial mark 3 can be formed by laser processing or etching. However, if an epitaxial layer 40 is formed on the semiconductor substrate 105 on which the recessed fiducial mark 3 is formed, the epitaxial layer 40 is also formed inside the recessed fiducial mark 3, and a portion of the recessed fiducial mark 3 is buried by the epitaxial layer 40. This reduces the visibility of the fiducial mark 3. This makes it difficult to accurately link the plane coordinates where a defect exists with the plane coordinates of an element.

[0126] In the semiconductor substrate 100 or the semiconductor epitaxial substrate 200 according to the present disclosure, the epitaxial growth suppression film 30 is provided in at least a portion of the interior of the recess 24 that constitutes the fiducial mark 3. This makes it possible to suppress the growth of the epitaxial layer 40 on the recess 24 that constitutes the fiducial mark 3. As a result, it is possible to suppress the deterioration of the visibility of the fiducial mark 3 after epitaxial growth.

[0127] In the semiconductor substrate 100 or the semiconductor epitaxial substrate 200 according to the present disclosure, the depth of the recess 24 may be greater than 0.5 μm and less than 100 μm, which further prevents the visibility of the fiducial mark 3 from being deteriorated.

[0128] In the semiconductor substrate 100 or the semiconductor epitaxial substrate 200 according to the present disclosure, the recess 24 may be configured with a side surface 22 and a bottom surface 23 continuous with the side surface 22. The epitaxial growth suppression film 30 may be in contact with the bottom surface 23. This makes it possible to suppress the growth of the epitaxial layer 40 on the bottom surface 23 of the recess 24.

[0129] In the semiconductor substrate 100 or the semiconductor epitaxial substrate 200 according to the present disclosure, the recess 24 may be configured with a side surface 22 and a bottom surface 23 continuous with the side surface 22. The epitaxial growth suppression film 30 may be in contact with each of the side surface 22 and the bottom surface 23. A depression may be formed by the epitaxial growth suppression film 30. This makes it possible to suppress the growth of the epitaxial layer 40 on each of the bottom surface 23 and the side surface 22 of the recess 24.

[0130] In the semiconductor substrate 100 or the semiconductor epitaxial substrate 200 according to the present disclosure, the recess 24 may be filled with the epitaxial growth suppression film 30. This can suppress the growth of the epitaxial layer 40 above the recess 24.

[0131] In the semiconductor substrate 100 or the semiconductor epitaxial substrate 200 according to the present disclosure, the epitaxial growth suppression film 30 may be made of a material containing boron, carbon, nitrogen, or oxygen and having a melting point of 1700° C. or higher. This makes it possible to suppress decomposition of the epitaxial growth suppression film 30 in the temperature range in which the epitaxial layer 40 is formed.

[0132] In the semiconductor substrate 100 or the semiconductor epitaxial substrate 200 according to the present disclosure, the epitaxial growth suppression film 30 may be made of a material containing titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, magnesium, yttrium, aluminum, nickel, zinc, or gallium, which can suppress decomposition of the epitaxial growth suppression film 30 in the temperature range in which the epitaxial layer 40 is formed.

[0133] In the semiconductor substrate 100 or the semiconductor epitaxial substrate 200 according to the present disclosure, the semiconductor material may be silicon carbide, which makes it possible to suppress deterioration of visibility, particularly in the manufacturing process of a silicon carbide semiconductor device using a silicon carbide substrate or a silicon carbide epitaxial substrate.

[0134] In the semiconductor substrate 100 or the semiconductor epitaxial substrate 200 according to the present disclosure, the thickness of the epitaxial growth suppression film 30 may be 0.25 times or more the depth of the recess 24. This makes it possible to more reliably prevent the visibility of the fiducial mark 3 from being deteriorated.

[0135] The embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the claims, not by the above description, and is intended to include meanings equivalent to the claims and all modifications within the scope thereof.

[0136] 1 First main surface (main surface), 2 Second main surface, 3 Reference mark, 5 Fifth main surface (main surface), 6 Sixth main surface, 7 Arc-shaped portion, 8 Orientation flat, 9 Outer periphery, 11 First central region, 12 First outer peripheral region, 13 First reference mark, 14 Second reference mark, 21 First flat surface, 22 First side surface (side surface), 23 First bottom surface (bottom surface), 24 Recess, 30 Epitaxial growth suppression film, 32 Second side surface, 33 Second bottom surface, 34 First recess, 35 First top surface, 40 Epitaxial layer, 41 Third main surface, 42 Fourth main surface, 43 Third side surface, 51 Second central region, 52 Second outer peripheral region, 61 Second flat surface, 71 First epitaxial layer, 72 Second epitaxial layer, 81 Seventh main surface, 82 Eighth main surface, 83 Fifth side surface, 90 Semiconductor layer, 92 fourth side surface, 93 fourth bottom surface, 94 second recess, 100 semiconductor substrate, 101 first direction, 102 second direction, 103 opening, 105 semiconductor base material, 106 resist layer, 200 semiconductor epitaxial substrate, A1 maximum diameter, A2 spacing, A3 distance, B1 first depth, B2 second depth, B3 third thickness, H1 first thickness, H2 second thickness, R1 first virtual circle, R2 second virtual circle, W1 first width, W2 second width.

Claims

1. A main surface; a reference mark formed by a recess formed on the main surface and serving as a reference for in-plane coordinates; an epitaxial growth suppression film provided in at least a portion of the inside of the recess; At least two of the reference marks are provided on the main surface, the main surface is made of a semiconductor material, A semiconductor substrate, wherein the epitaxial growth suppression film is made of a material different from the semiconductor material.

2. The semiconductor substrate according to claim 1 , wherein the depth of the recess is greater than 0.5 μm and less than 100 μm.

3. The recess includes a side surface and a bottom surface that is continuous with the side surface, 3. The semiconductor substrate according to claim 1, wherein the epitaxial growth suppression film is in contact with the bottom surface.

4. The recess includes a side surface and a bottom surface that is continuous with the side surface, the epitaxial growth suppression film is in contact with each of the side surface and the bottom surface, 3. The semiconductor substrate according to claim 1, wherein a recess is formed by said epitaxial growth suppression film.

5. 3. The semiconductor substrate according to claim 1, wherein the recess is filled with the epitaxial growth suppression film.

6. 3. The semiconductor substrate according to claim 1, wherein said epitaxial growth suppression film is made of a material containing boron, carbon, nitrogen or oxygen and having a melting point of 1700[deg.] C. or higher.

7. 3. The semiconductor substrate according to claim 1, wherein the epitaxial growth suppression film is made of a material containing titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, magnesium, yttrium, aluminum, nickel, zinc or gallium.

8. The semiconductor substrate according to claim 1 or 2, wherein the semiconductor material is silicon carbide.

9. 3. The semiconductor substrate according to claim 1, wherein the thickness of the epitaxial growth suppression film is at least 0.25 times the depth of the recess.

10. A semiconductor substrate according to claim 1 or 2, a semiconductor layer formed on the epitaxial growth suppression film; an epitaxial layer provided on at least a portion of the main surface; A semiconductor epitaxial substrate, wherein the thickness of the epitaxial layer is greater than the minimum thickness of the semiconductor layer.

11. A semiconductor substrate according to claim 1 or 2, an epitaxial layer provided on at least a portion of the main surface; A semiconductor epitaxial substrate, wherein the epitaxial layer is not formed on the epitaxial growth suppression film.

12. A semiconductor substrate; a first epitaxial layer disposed on the semiconductor substrate; a main surface formed by the first epitaxial layer; a reference mark formed by a recess formed on the main surface and serving as a reference for in-plane coordinates; an epitaxial growth suppression film provided in at least a portion of the inside of the recess; At least two of the reference marks are provided on the main surface, the main surface is made of a semiconductor material, A semiconductor epitaxial substrate, wherein the epitaxial growth suppression film is made of a material different from the semiconductor material.

13. a semiconductor layer formed on the epitaxial growth suppression film; a second epitaxial layer provided on at least a portion of the main surface; The semiconductor epitaxial substrate according to claim 12 , wherein the thickness of the second epitaxial layer is greater than a minimum thickness of the semiconductor layer.

14. a second epitaxial layer provided on at least a portion of the main surface; The semiconductor epitaxial substrate according to claim 12 , wherein the second epitaxial layer is not formed on the epitaxial growth suppression film.