Printed circuit board and method for manufacturing same, and semiconductor device

Abstract

This printed circuit board comprises: a wiring portion including a wiring layer; and electrode pads provided on the wiring portion and connected to the wiring layer. A connection surface of the electrode pads on the opposite side from the wiring portion has an arithmetic mean roughness Ra of 0.5–2.0 μm inclusive. The printed circuit board may further comprise a surface insulating resin layer provided on the surface of the wiring portion on the side of the electrode pads and having openings through which the electrode pads are exposed.

Description

Wiring board, manufacturing method thereof, and semiconductor device

[0001] The present disclosure relates to a wiring board, a connection method therefor, and a semiconductor device.

[0002] In a wiring board having a wiring layer and an insulating layer, cracks may occur at the interface between the wiring layer and the insulating layer due to thermal stress caused by mounting a semiconductor chip or the like (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2017-157666

[0004] One aspect of the present disclosure relates to suppressing the occurrence of defects in an insulating resin layer due to temperature changes in a wiring board having electrode pads exposed in openings in the insulating resin layer.

[0005] One aspect of the present disclosure relates to a wiring substrate including a wiring section including a wiring layer, and an electrode pad provided on the wiring section and connected to the wiring layer, wherein a connection surface of the electrode pad opposite the wiring section has an arithmetic mean roughness Ra of 0.5 μm to 2.0 μm.

[0006] Another aspect of the present disclosure relates to a semiconductor device including the above wiring board and a semiconductor chip mounted on the wiring board.

[0007] Yet another aspect of the present disclosure relates to a method for manufacturing a wiring substrate, including: preparing a wiring structure including a wiring portion including a wiring layer and an electrode pad provided on the wiring portion; and processing a connection surface of the electrode pad opposite the wiring portion to have an arithmetic mean roughness Ra of 0.5 μm or more and 2.0 μm or less.

[0008] In a wiring substrate having electrode pads exposed in openings in an insulating resin layer, the occurrence of defects in the insulating resin layer due to temperature changes can be suppressed, and therefore high insulation reliability can be easily maintained even when the semiconductor device has fine wiring.

[0009] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, and are not intended to be limiting of the invention, as claimed.

[0010] The present invention is not limited to the following examples. In the following description, the same or equivalent parts are given the same reference numerals, and duplicated descriptions may be omitted. Positional relationships such as up, down, left, and right are based on the positional relationships shown in the drawings unless otherwise specified. The dimensional ratios of the drawings are not limited to those shown. Terms such as "left," "right," "front," "back," "top," "bottom," "upper," and "lower" do not necessarily mean that their relative positions do not change. The term "layer" encompasses not only a structure with a shape formed over the entire surface when observed in a plan view, but also a structure with a shape formed only on a portion of the surface.

[0011] 1 and 2 are process diagrams showing an example of a method for manufacturing a wiring substrate. The method shown in Fig. 1 and 2 can include preparing a wiring substrate 10 (wiring structure) including a substrate 1, a wiring portion 3 provided on the substrate 1, and an electrode pad 5 provided on the surface of the wiring portion 3 opposite the substrate 1, and processing a connection surface 5S of the electrode pad 5 opposite the wiring portion 3 so that the connection surface 5S has an arithmetic mean roughness Ra of 0.5 μm to 2.0 μm. In this specification, the wiring substrate before the connection surface is processed may be referred to as a wiring structure.

[0012] Preparing the wiring board 10 includes forming a wiring section 3 including an insulating resin layer and a wiring layer on the main surface of the base material 1, and forming an electrode pad 5 on the surface of the wiring section 3 opposite the base material 1.

[0013] The substrate 1 may be, for example, a silicon substrate, a glass substrate, a stainless steel substrate, or a glass cloth, or may be a semiconductor package having a semiconductor chip and a sealing resin layer that seals the semiconductor chip.

[0014] The thickness of the substrate 1 may be, for example, 0.2 mm or more and 2.0 mm or less. A substrate having a thickness of 0.2 mm or more is likely to have good handleability. A substrate having a thickness of 2.0 mm or less is often advantageous in terms of manufacturing costs. The substrate 1 may be a wafer having a circular main surface or a panel having a rectangular main surface. For example, the substrate 1 may be a wafer having a circular main surface with a diameter of 200 mm or more and 450 mm or less, or a panel having a rectangular main surface with a width of 300 mm or more and 700 mm or less.

[0015] The wiring portion 3 can be formed by a method including forming an insulating resin layer and a wiring layer provided in the insulating resin layer by a conventional method. The wiring portion 3 may have a multilayer wiring structure including two or more wiring layers.

[0016] The electrode pad 5 may include, for example, forming a seed layer on the surface of the wiring portion 3 opposite the substrate 1; forming a resist layer 4 on the seed layer, the resist layer 4 having an opening 4a through which a portion of the seed layer is exposed; forming the electrode pad 5 including an electroplated layer filling the opening 4a; removing the resist layer 4; and removing the portion of the seed layer not covered by the electroplated layer. The seed layer may be formed by sputtering. The seed layer may be a metal layer containing a metal species such as copper or titanium. The seed layer may have a thickness of 20 nm to 200 nm, 40 nm to 200 nm, or 60 nm to 200 nm.

[0017] The electrode pad 5 may be a copper pad containing copper. The thickness of the electrode pad 5 may be 1 μm or more and 20 μm or less, 3 μm or more and 15 μm or less, or 5 μm or more and 15 μm or less.

[0018] The shape of the connection surface 5S of the electrode pad 5 or the opening 4a for forming it may be circular or elliptical. The maximum width of the electrode pad 5 (connection surface 5S) and the opening 4a may be 5 μm or more, or 20 μm or more, and may be 400 μm or less, or 300 μm or less, or 10 μm or less. The electrode pad 5 (connection surface 5S) and the opening 4a may have an area equivalent to the area of ​​a circle having a diameter of 5 μm or more and 400 μm or less, or 5 μm or more and 10 μm or less.

[0019] The connection surface 5S of the prepared wiring board 10 is processed to have an arithmetic mean roughness Ra of 0.5 μm or more and 2.0 μm or less. A large arithmetic mean roughness Ra is advantageous in terms of improving adhesion through the anchor effect, but according to the knowledge of the inventors, if the arithmetic mean roughness Ra exceeds 2.0 μm, defects such as cracks are likely to occur in the insulating resin layer (particularly the surface insulating resin layer 7 described below) that contacts the connection surface 5S. The arithmetic mean roughness Ra can be measured by a method in accordance with JIS B0601-1994.

[0020] If the connecting surface 5S before treatment has an arithmetic mean roughness Ra of less than 0.5 μm, the connecting surface 5S is roughened so that the arithmetic mean roughness Ra is 0.5 μm or more and 2.0 μm or less. If the connecting surface 5S before treatment has an arithmetic mean roughness Ra of more than 2.0 μm, the connecting surface 5S is smoothed so that the arithmetic mean roughness Ra is 0.5 μm or more and 2.0 μm or less. The roughening and smoothing treatments may include contacting the connecting surface 5S with a treatment liquid. The treatment liquid for the roughening treatment may be, for example, an acidic aqueous solution. The acidic aqueous solution may contain an organic or inorganic acid, a cupric ion source, a halide ion source, and a polymer. The organic acid may be, for example, formic acid, acetic acid, propionic acid, butyric acid, or a combination thereof. The inorganic acid may be, for example, sulfuric acid, hydrochloric acid, or a combination thereof. The halide may be, for example, hydrochloric acid, hydrobromic acid, sodium chloride, potassium chloride, calcium chloride, potassium bromide, or a combination thereof. The cupric ion source may be, for example, cupric chloride, cupric bromide, cupric hydroxide, cupric oxide, or a combination thereof. The polymer may have a polyamine chain or a cationic group (e.g., a quaternary ammonium group). The treatment solution for the smoothing treatment may be selected from, for example, a treatment solution containing an imidazole compound and a sugar alcohol; a treatment solution containing an aromatic compound having an amino group and an aromatic ring, a polybasic acid, and a halide ion or an oxidizing agent (e.g., hypochlorous acid, chlorous acid, chloric acid, perchloric acid, persulfuric acid, percarbonate, hydrogen peroxide, organic peroxide, etc.); a treatment solution containing an aromatic compound having an amino group and an aromatic ring and a thio compound; and a treatment solution containing a silane coupling agent, a metal ion, and a halide ion.

[0021] On the connection surface 5S after treatment, the number of protrusions having a height exceeding 3 μm may be 5 or less per 15 μm of in-plane length of the connection surface 5S. Relatively large protrusions having a height exceeding 3 μm may be the starting point of defects such as cracks in the surface insulating resin layer. The height of the protrusions is measured along the in-plane direction of the connection surface 5S, and is determined based on the deepest of the bottoms of the recesses on both sides of the protrusion. The number of protrusions having a height exceeding 3 μm may be 4 or less, 3 or less, 2 or less, or 1 or less per 15 μm of in-plane length of the connection surface 5S.

[0022] After processing the connection surface 5S, a surface insulating resin layer 7 is formed on the surface of the wiring portion 3 opposite the substrate 1, the surface insulating resin layer 7 having an opening 7a exposing the center of the electrode pad 5. The surface insulating resin layer 7 is formed so as to contact the peripheral edge of the connection surface 5S. The thickness of the portion of the surface insulating resin layer 7 in contact with the wiring portion 3 may be 15 μm or more and 30 μm or less.

[0023] The surface insulating resin layer 7 can be formed, for example, from a resist material typically used to form solder resist. The openings 7a can be formed, for example, by laser ablation, photolithography (exposure and development), or imprinting. The material for forming the surface insulating resin layer 7 may be a thermosetting or photocurable resist material. In the case of photolithography, a photocurable resist material is used.

[0024] The thermosetting resist material may contain a thermosetting resin that hardens by heating to form a cured product exhibiting electrical insulation. The thermosetting resin may be, for example, an epoxy resin, a phenolic resin, a triazine ring-containing resin, an unsaturated polyester resin, a bismaleimide resin, a diallyl phthalate resin, a silicone resin, a resin having a benzoxazine ring, a norbornene resin, a cyanate resin, an isocyanate resin, a urethane resin, a benzocyclobutene resin, a maleimide resin, a bismaleimide triazine resin, a polyazomethine resin, a thermosetting polyimide, or a combination thereof. Examples of epoxy resins include bisphenol type epoxy resins such as bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, bisphenol E type epoxy resin, bisphenol M type epoxy resin, bisphenol P type epoxy resin, and bisphenol Z type epoxy resin; novolac type epoxy resins such as bisphenol A novolac type epoxy resin, phenol novolac type epoxy resin, and cresol novolac epoxy resin; biphenyl type epoxy resin, biphenyl aralkyl type epoxy resin, aryl alkylene type epoxy resin, tetraphenylol ethane type epoxy resin, naphthalene type epoxy resin, anthracene type epoxy resin, phenoxy type epoxy resin, and dicyclopentadiene type epoxy resin. resins, norbornene-type epoxy resins, adamantane-type epoxy resins, fluorene-type epoxy resins, glycidyl methacrylate copolymer-based epoxy resins, copolymers of cyclohexylmaleimide and glycidyl methacrylate, epoxy-modified polybutadiene rubber derivatives, CTBN-modified epoxy resins, trimethylolpropane polyglycidyl ether, phenyl-1,3-diglycidyl ether, biphenyl-4,4′-diglycidyl ether, 1,6-hexanediol diglycidyl ether, diglycidyl ether of ethylene glycol or propylene glycol, sorbitol polyglycidyl ether, tris(2,3-epoxypropyl)isocyanurate, and triglycidyl tris(2-hydroxyethyl)isocyanurate.Examples of phenolic resins include novolac-type phenolic resins such as phenol novolac resin, cresol novolac resin, and bisphenol A novolac resin, unmodified resol phenolic resin, and resol-type phenolic resins such as oil-modified resol phenolic resins modified with tung oil, linseed oil, walnut oil, etc. Examples of triazine ring-containing resins include urea resins and melamine resins.

[0025] The photocurable resist material may include a photocurable resin that is, for example, an epoxy resin (such as an alicyclic epoxy resin), an oxetane compound, a vinyl ether compound, or a combination thereof. Examples of cycloaliphatic epoxy resins include 3,4,3′,4′-diepoxybicyclohexyl, 2,2-bis(3,4-epoxycyclohexyl)propane, 2,2-bis(3,4-epoxycyclohexyl)-1,3-hexafluoropropane, bis(3,4-epoxycyclohexyl)methane, 1-[1,1-bis(3,4-epoxycyclohexyl)]ethylbenzene, bis(3,4-epoxycyclohexyl)adipate, 3,4-epoxycyclohexylmethyl(3,4-epoxy)cyclohexanecarboxylate, (3,4-epoxy-6-methylcyclohexyl)methyl-3′,4′-epoxy-6-methylcyclohexanecarboxylate, ethylene-1,2-bis(3,4-epoxycyclohexanecarboxylic acid) ester, cyclohexene oxide, 3,4-epoxycyclohexylmethyl alcohol, and 3,4-epoxycyclohexylethyltrimethoxysilane.

[0026] The material for forming the surface insulating resin layer 7 may include a thermoplastic resin. The thermoplastic resin may be a general-purpose plastic, an engineering plastic, a thermoplastic elastomer, or a combination thereof. Examples of general-purpose plastics include acrylic resin, modified acrylic resin, low-density polyethylene, high-density polyethylene, ethylene-vinyl acetate copolymer, polyethylene terephthalate, polypropylene, modified polypropylene, polystyrene, acrylonitrile-butadiene-styrene copolymer, acrylonitrile-styrene copolymer, cellulose acetate, polyvinyl alcohol, polyvinyl chloride, polyvinylidene chloride, and polylactic acid. Examples of engineering plastics include polyamide, thermoplastic polyurethane, polyacetal, polycarbonate, ultra-high molecular weight polyethylene, polybutylene terephthalate, modified polyphenylene ether, polysulfone, polyphenylene sulfide, polyethersulfone, polyetheretherketone, polyarylate, polyetherimide, polyamideimide, liquid crystal polymer, polyamide 6T, polyamide 9T, polytetrafluoroethylene, polyvinylidene fluoride, polyesterimide, and thermoplastic polyimide. Examples of the thermoplastic elastomer include an olefin-based thermoplastic elastomer, a styrene-based thermoplastic elastomer, a polyester-based thermoplastic elastomer, a urethane-based thermoplastic elastomer, an amide-based thermoplastic elastomer, a vinyl chloride-based thermoplastic elastomer, and a hydrogenated thermoplastic elastomer.

[0027] The material for forming the surface insulating resin layer 7 may contain an inorganic filler, which can contribute to improving the reliability and rigidity of the surface insulating resin layer 7. The inorganic filler can be, for example, silica, barium sulfate, barium titanate, talc, clay, calcined kaolin, magnesium carbonate, calcium carbonate, aluminum oxide, aluminum hydroxide, mica powder, or a combination thereof.

[0028] A semiconductor device can be obtained by mounting a semiconductor chip on the wiring substrate obtained by the above method. Figure 3 is a cross-sectional view showing an example of a semiconductor device. The semiconductor device 100 shown in Figure 3 includes a wiring substrate 10, a semiconductor chip 20 mounted on the wiring substrate 10, solder bumps 25 interposed between the semiconductor chip 20 and electrode pads 5 of the wiring substrate 10 to electrically connect them, and an insulating resin layer 30 (adhesive layer) filled between the semiconductor chip 20 and the wiring substrate 10.

[0029] The occurrence of cracks in the insulating resin layer can be effectively suppressed even in a semiconductor device having fine wiring and a large number of pins. The semiconductor device may have an interposer including a fine wiring layer for mounting different types of semiconductor chips together. For example, the spacing between pins on the semiconductor chip may be 200 μm or less, or 100 μm or less, or 30 μm or more. The number of pins on the semiconductor chip may be 500 or more, or 1,000 or more, or 10,000 or less.

[0030] The present invention is not limited to the following examples.

[0031] A wiring substrate was prepared, which had a copper pad with a connection surface (width: 260 μm) having an arithmetic mean roughness Ra of 0.03 μm and a surface insulating resin layer (solder resist) with an opening through which the copper pad was exposed. The connection surface of the copper pad was roughened using a roughening treatment solution to form a surface with an arithmetic mean roughness Ra of 0.5 μm, 1.0 μm, 2.0 μm, 3.0 μm, or 5.0 μm. The arithmetic mean roughness Ra was measured using a laser microscope (Olympus Corporation, OLS4100). A semiconductor chip was mounted on the wiring substrate using a nitrogen reflow oven so as to be connected to the treated connection surface via solder bumps. The temperature of the nitrogen reflow oven was set to 260°C. After confirming that the solder bumps and semiconductor chip were connected to the wiring substrate, an insulating resin layer was filled between the semiconductor chip and wiring substrate and thermally cured. The semiconductor device thus formed was placed in a temperature cycle tester and subjected to 400 cycles of heat treatment under conditions of a high temperature of 165° C., a low temperature of −65° C., and a holding time of 15 minutes.

[0032] The cross section of the surface insulating resin layer near the copper pad of the heat-treated semiconductor device was observed to check for the presence or absence of cracks. The results are shown in Table 1. It was confirmed that forming a connection surface with an Ra of 0.5 μm or more and 2.0 μm or less effectively suppresses the occurrence of cracks in the surface insulating resin layer. When the Ra was 0.03 μm, interfacial peeling was observed between the connection surface and the surface insulating resin layer, suggesting insufficient adhesion.

[0033]

[0034] 3...wiring portion, 4a, 7a...openings, 5...electrode pads, 5S...connection surface, 7...surface insulating resin layer, 10...wiring substrate (wiring structure), 20...semiconductor chip, 25...solder bumps, 100...semiconductor device.

Claims

1. A wiring section including a wiring layer; an electrode pad provided on the wiring portion and connected to the wiring layer; a surface insulating resin layer provided on a surface of the wiring portion on the electrode pad side, the surface insulating resin layer having an opening through which the electrode pad is exposed; Equipped with the surface insulating resin layer is in contact with a part of a connection surface which is a surface of the electrode pad opposite to the wiring portion, and the connection surface including the part not in contact with the surface insulating resin layer has an arithmetic mean roughness Ra of 0.5 μm or more and 2.0 μm or less; Wiring board.

2. 2. The wiring board according to claim 1, wherein the number of protrusions having a height exceeding 3 μm on said connection surface is 5 or less per 15 μm of length in an in-plane direction of said connection surface.

3. A wiring board as described in claim 1, wherein the connection surface including the portion not in contact with the surface insulating resin layer has an arithmetic mean roughness Ra of 1.0 μm or more and 2.0 μm or less.

4. 4. The wiring board according to claim 3, wherein the surface insulating resin layer is a layer formed from a thermosetting or photosetting resist material containing an epoxy resin.

5. A wiring board according to any one of claims 1 to 4, A semiconductor chip mounted on the wiring substrate; A semiconductor device comprising:

6. Preparing a wiring structure including a wiring section including a wiring layer and an electrode pad provided on the wiring section; forming a surface insulating resin layer having an opening exposing a connection surface, which is a surface of the electrode pad opposite to the wiring portion, on a surface of the wiring portion on the electrode pad side, so as to be in contact with a part of the connection surface; treating the connection surface including a portion not in contact with the surface insulating resin layer to have an arithmetic mean roughness Ra of 0.5 μm or more and 2.0 μm or less; A method for manufacturing a wiring substrate comprising:

7. 7. The method according to claim 6, wherein the connection surface is treated to have an arithmetic mean roughness Ra of 0.5 μm or more and 2.0 μm or less, and the number of protrusions having a height exceeding 3 μm is 5 or less per 15 μm of length in an in-plane direction of the connection surface.

8. A method as described in claim 6 or 7, wherein the connection surface including the portion not in contact with the surface insulating resin layer is treated to have an arithmetic mean roughness Ra of 1.0 μm or more and 2.0 μm or less.

9. The method according to claim 8 , wherein the surface insulating resin layer is formed of a thermosetting or photosetting resist material containing an epoxy resin.