Semiconductor light emitting device

Abstract

This semiconductor light emitting device comprises a substrate, a light emitting element mounted on the substrate, a transistor, and a first capacitor module. The first capacitor module has a first main surface facing the substrate, and a first connection electrode and a second connection electrode provided on the first main surface, and is electrically connected to the light emitting element. The first capacitor module includes a silicon substrate having a first surface and a second surface facing opposite each other, a first connection electrode provided on the first surface, and a counter electrode provided on the second surface, facing the first connection electrode.

Description

Semiconductor light-emitting device

[0001] The present disclosure relates to semiconductor light emitting devices.

[0002] One type of semiconductor light-emitting device is a semiconductor laser device that includes a semiconductor light-emitting element as a laser light source (see, for example, Patent Document 1). Such semiconductor laser devices are widely used as light source devices mounted in various electronic devices.

[0003] JP 2016-29718 A

[0004] A semiconductor light emitting device includes, for example, a switching element and a capacitor for driving a semiconductor light emitting element. Therefore, parasitic inductance exists on the wiring path of the circuit including the semiconductor light emitting element. The parasitic inductance can affect the output characteristics of the semiconductor light emitting element.

[0005] A semiconductor light-emitting device that is one aspect of the present disclosure comprises a substrate, a light-emitting element mounted on the substrate, a transistor mounted on the substrate and configured to drive the light-emitting element, and a capacitor module mounted on the substrate and having a main surface facing the substrate, a first connection electrode and a second connection electrode provided on the main surface, and electrically connected to the light-emitting element, wherein the capacitor module includes a silicon substrate having a first surface and a second surface facing opposite to each other, the first connection electrode provided on the first surface, and an opposing electrode provided on the second surface and opposing the first connection electrode.

[0006] According to the semiconductor light emitting device according to one aspect of the present disclosure, the parasitic inductance can be reduced.

[0007] FIG. 1 is a perspective view schematically illustrating an exemplary semiconductor light-emitting device according to a first embodiment. FIG. 2 is a schematic cross-sectional view of the semiconductor light-emitting device of FIG. 1. FIG. 3 is a perspective view schematically illustrating a stem and a lead pin. FIG. 4 is a perspective view schematically illustrating the stem and the lead pin as viewed from the opposite side to that of FIG. 3. FIG. 5 is a perspective view schematically illustrating a semiconductor light-emitting device and a drive substrate. FIG. 6 is a plan view schematically illustrating a light-emitting module according to the first embodiment. FIG. 7 is a perspective view of the light-emitting module of FIG. 6. FIG. 8 is a plan view showing the internal wiring structure of a substrate of the light-emitting module of FIG. 6. FIG. 9 is a plan view showing the internal wiring structure of a substrate of the light-emitting module of FIG. 6. FIG. 10 is a cross-sectional view taken along line 10-10 in FIG. 6. FIG. 11 is a cross-sectional view taken along line 11-11 in FIG. 6. FIG. 12 is a circuit diagram schematically illustrating the electrical configuration of a semiconductor light-emitting device. FIG. 13 is a cross-sectional view of a light-emitting module of a comparative example. FIG. 14 is a cross-sectional view of a light-emitting module including a modified capacitor module. FIG. 15 is a cross-sectional view of a light-emitting module including a modified capacitor module. FIG. 16 is a cross-sectional view showing a light-emitting module including a capacitor module according to a modified example. FIG. 17 is a perspective view schematically showing a light-emitting module including a substrate according to a modified example. FIG. 18 is a plan view showing the internal wiring structure of the substrate of FIG. 17. FIG. 19 is a plan view showing the internal wiring structure of the substrate of FIG. 17. FIG. 20 is a plan view showing the internal wiring structure of the substrate of FIG. 17. FIG. 21 is a cross-sectional view of FIG. 17 taken along line 21-21 in FIG. 18. FIG. 22 is a perspective view schematically showing an exemplary semiconductor light-emitting device according to a second embodiment. FIG. 23 is a plan view schematically showing the semiconductor light-emitting device of FIG. 22. FIG. 24 is a plan view showing the internal wiring structure of the substrate of the light-emitting module of FIG. 22. FIG. 25 is a plan view showing the internal wiring structure of the substrate of the light-emitting module of FIG. 22. FIG. 26 is a cross-sectional view taken along line 26-26 in FIG. 23. FIG. 27 is a cross-sectional view taken along line 27-27 in FIG. 23.

[0008] Hereinafter, several embodiments of the semiconductor light emitting device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and not to rank the objects.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] First Embodiment The configuration of a semiconductor light emitting device 10A according to a first embodiment will now be described. FIG. 1 is a perspective view that schematically illustrates an exemplary semiconductor light emitting device 10A according to the first embodiment. FIG. 2 is a cross-sectional view of the semiconductor light emitting device 10A of FIG. 1. Note that, in this disclosure, for the purpose of explanation only, components may be described based on the mutually orthogonal X, Y, and Z axes shown in the drawings such as FIG. 1. Hereinafter, the +Z direction is defined as up, the −Z direction as down, the +X direction as right, and the −X direction as left.

[0011] 1 can be used in a laser system such as LiDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging), which is an example of three-dimensional distance measurement. Note that semiconductor light-emitting device 10A may also be used in a laser system for two-dimensional distance measurement.

[0012] (Package Structure) First, an overview of the package structure will be described. As shown in Figures 1 and 2, the semiconductor light emitting device 10A includes a stem 20, a light emitting module 30A mounted on the stem 20, and an enclosing member 40. The stem 20 includes a base 22 and a heat sink 24 standing on the base 22. The light emitting module 30A is mounted on the heat sink 24. The enclosing member 40 is provided on the base 22 so as to surround the light emitting module 30A and the heat sink 24. A structure in which the light emitting module 30A is packaged using the stem 20 and the enclosing member 40 is also called a CAN package structure.

[0013] The surrounding member 40 defines an accommodation space 42 that accommodates the light emitting module 30A. The surrounding member 40 is fixed to the base 22 of the stem 20, and together with the stem 20, the accommodation space 42 is airtight and hollow, forming a hollow sealed structure.

[0014] In the first embodiment, the enclosure member 40 includes a cap 44 and a light-transmitting plate 46 (see FIG. 2 ). The light-transmitting plate 46 may be omitted depending on the application of the semiconductor light-emitting device 10A. The material of the cap 44 is not particularly limited, but it may be formed of a metal material with light-blocking properties, such as iron (Fe) or an Fe alloy. In the first embodiment, the cap 44 includes a top portion 44A, a cylindrical portion 44B, and a flange portion 44C, which are integrally formed.

[0015] The tubular portion 44B is formed, for example, in a cylindrical shape. The top portion 44A is located at one end (the upper end in FIGS. 1 and 2 ) of the tubular portion 44B, and the flange portion 44C is located at the other end (the lower end in FIGS. 1 and 2 ) of the tubular portion 44B. The flange portion 44C is fixed to the surface 22A of the base 22, for example, by welding or a bonding material. The top portion 44A includes a window portion 44AW that allows light emitted from the light-emitting module 30A to pass through. The window portion 44AW is formed, for example, in a circular shape.

[0016] The light-transmitting plate 46 is fixed to the top portion 44A from the inside of the cap 44 with a bonding material or the like to close the window portion 44AW. The light-transmitting plate 46 is made of a transparent material such as glass, and transmits light passing through the window portion 44AW. The light-transmitting plate 46 also serves as a sealing member that seals the accommodation space 42 of the light-emitting module 30A surrounded by the enclosing member 40.

[0017] (Outline of Light-Emitting Module) Next, an outline of the light-emitting module 30A will be described. The light-emitting module 30A includes a substrate 50A, a light-emitting element 60, and a light-emitting element drive circuit 70. The light-emitting element 60 and the light-emitting element drive circuit 70 are mounted on the substrate 50A. The light-emitting element 60 is a laser diode (semiconductor laser element). The light-emitting element drive circuit 70 includes a transistor 80 that drives the light-emitting element 60. The transistor 80 is mounted on the substrate 50A as a vertical-structure metal-oxide-semiconductor field-effect transistor (MOSFET). In the present disclosure, a vertical-structure MOSFET is referred to as a vertical MOSFET.

[0018] In the first embodiment, the light-emitting element drive circuit 70 further includes a first capacitor module 110 and a second capacitor module 120. The first and second capacitor modules 110, 120 include silicon capacitors. The light-emitting element drive circuit 70 drives the light-emitting element 60 by supplying the charges stored in the first and second capacitor modules 110, 120 to the light-emitting element 60 as a pulse current via the transistor 80.

[0019] (Stem) Next, a description will be given of the structure of the stem 20. Fig. 3 is a perspective view that schematically shows the structure of the stem 20, and Fig. 4 is a perspective view of the stem 20 as viewed from the opposite side to that of Fig. 3.

[0020] As described above, the stem 20 includes the base 22 and the heat sink 24. In the first embodiment, the base 22 and the heat sink 24 are integrally formed. The stem 20 is made of a conductive material such as copper (Cu), a Cu alloy, Fe, or an Fe alloy. The base 22 and the heat sink 24 may be made of different metals.

[0021] The base 22 has, for example, a substantially circular shape when viewed in the thickness direction of the base 22. In the present disclosure, the thickness direction of the base 22 refers to a direction (Z-axis direction) perpendicular to the surface 22A of the base 22. The size of the base 22 is not particularly limited.

[0022] The heat sink 24 is provided integrally with the surface 22A of the base 22. The heat sink 24 has, for example, a substantially fan shape when viewed in the thickness direction of the base 22. The size of the heat sink 24 is not particularly limited.

[0023] The heat sink 24 includes a planar support surface 24A, and the light emitting module 30A shown in Figures 1 and 2 is mounted on this support surface 24A. For example, the light emitting module 30A is joined to the support surface 24A with a conductive bonding material (not shown) and is electrically connected to the heat sink 24 via this conductive bonding material. In the first embodiment, the heat sink 24 is electrically connected to the transistor 80 of the light emitting module 30A via the conductive bonding material. For example, a conductive paste such as silver (Ag) paste can be used as the conductive bonding material.

[0024] The base 22 includes a plurality of through holes, for example, three through holes 26A, 26B, and 26C in the first embodiment, that penetrate the base 22 in the thickness direction. Each of the through holes 26A, 26B, and 26C has, for example, a substantially circular shape when viewed in the thickness direction of the base 22. The size of each of the through holes 26A, 26B, and 26C is not particularly limited.

[0025] FIG. 5 is a perspective view schematically illustrating an example of mounting the semiconductor light emitting device 10A. The semiconductor light emitting device 10A is mounted on a drive substrate 910 that controls the driving of the light emitting module 30A. The semiconductor light emitting device 10A includes a plurality of lead pins that electrically connect the light emitting module 30A and the drive substrate 910. As shown in FIGS. 3 and 4, the semiconductor light emitting device 10A of the first embodiment includes four lead pins 142A, 142B, 142C, and 142D. In the first embodiment, the lead pins 142A and 142B correspond to first lead pins, the lead pin 142D corresponds to the second lead pin, and the lead pin 142C corresponds to the third lead pin.

[0026] 1, 3, and 4, the lead pins 142A, 142B, and 142C penetrate the base 22. In the first embodiment, the lead pins 142A, 142B, and 142C are inserted into the through holes 26A, 26B, and 26C of the base 22, respectively. The insides of these through holes 26A, 26B, and 26C are filled with an insulating material 144 that electrically insulates the lead pins 142A, 142B, and 142C from the base 22, respectively. The insulating material 144 is formed of, for example, glass.

[0027] The lead pins 142A, 142B, 142C include connecting portions 146A, 146B, 146C and terminal portions 148A, 148B, 148C. The connecting portions 146A, 146B, 146C are portions that protrude from the front surface 22A of the base 22, and the terminal portions 148A, 148B, 148C are portions that protrude from the back surface 22B of the base 22. The lengths of the connecting portions 146A, 146B, 146C are not particularly limited.

[0028] 2 and 4 , the lead pin 142D includes a connecting portion 146D and a terminal portion 148D. The connecting portion 146D is provided at one end of the terminal portion 148D and is joined to the rear surface 22B of the base 22. Therefore, the lead pin 142D is fixed to the base 22. The lead pin 142D is fixed at a position overlapping the heat sink 24 when viewed in the thickness direction of the base 22. This lead pin 142D is electrically connected to the transistor 80 of the light-emitting module 30A via the base 22 and the heat sink 24.

[0029] Terminal portions 148A, 148B, 148C, and 148D of lead pins 142A, 142B, 142C, and 142D are used to mount semiconductor light emitting device 10A on drive substrate 910. The lengths of terminal portions 148A, 148B, 148C, and 148D are not particularly limited.

[0030] 5 , the lengths of the terminal portions 148A, 148B, 148C, and 148D when the semiconductor light-emitting device 10A is mounted on the drive substrate 910 correspond to the distance between the rear surface 22B of the base 22 and the drive substrate 910. As this distance increases, the terminal portions 148A, 148B, 148C, and 148D become longer, and the thermal resistance generated in the lead pins 142A, 142B, 142C, and 142D increases. Because such thermal resistance can cause the temperature of the light-emitting element 60 to rise, it is desirable that the distance between the rear surface 22B of the base 22 and the drive substrate 910 be short.

[0031] As shown in FIG. 1 , connection portions 146A, 146B, and 146C of the lead pins 142A, 142B, and 142C are electrically connected to the light-emitting module 30A by wires 152A, 152B, and 152C, respectively. The wires 152A, 152B, and 152C may be made of a metal material such as gold (Au). In the first embodiment, the connection portion 146A is electrically connected to the transistor 80 of the light-emitting module 30A by, for example, two wires 152A. Note that the number of wires 152A may be one, or three or more. The connection portion 146B is electrically connected to the transistor 80 of the light-emitting module 30A by, for example, one wire 152B. The connection portion 146C is electrically connected to an external element connection pad 160 provided on the substrate 50A of the light-emitting module 30A by, for example, one wire 152C.

[0032] The external element connection pad 160 is used to connect an external element to the substrate 50A (light-emitting module 30A). In the first embodiment, the external element connected to the external element connection pad 160 is a Schottky barrier diode (SBD) 906 (see FIG. 12 ) provided on the drive substrate 910. As will be described later, the SBD 906 is connected in anti-parallel to the light-emitting element 60 and functions as a protection diode for the light-emitting element 60, thereby suppressing reverse current from flowing through the light-emitting element 60.

[0033] Fig. 6 is a plan view schematically showing a light-emitting module 30A according to the first embodiment, and Fig. 7 is a perspective view of the light-emitting module 30A. Figs. 8 and 9 are plan views showing the internal wiring structure of a substrate 50A of the light-emitting module 30A. Fig. 10 is a cross-sectional view taken along line 10-10 in Fig. 6, and Fig. 11 is a cross-sectional view taken along line 11-11 in Fig. 6.

[0034] As shown in Figure 6, the substrate 50A has a rectangular shape. The size of the substrate 50A is not particularly limited. For example, the substrate 50A has a substantially square shape having a first side surface 52A and a second side surface 52B that are parallel to each other, and a third side surface 52C and a fourth side surface 52D that are parallel to each other and connect the first side surface 52A and the second side surface 52B. Note that the term "parallel" used in this disclosure includes not only a case where two objects are completely parallel to each other, but also a case where they are not completely parallel but are substantially parallel.

[0035] A light-emitting element 60, which is a laser diode, a transistor 80 that drives the light-emitting element 60, a first capacitor module 110, and a second capacitor module 120 are mounted on a substrate 50A. The light-emitting element 60, the transistor 80, the first capacitor module 110, and the second capacitor module 120 each have a rectangular shape when viewed from above the substrate 50A. In this disclosure, a planar view of the substrate 50A refers to viewing an object in the thickness direction (Y-axis direction) of the substrate 50A.

[0036] (Light-Emitting Element) In the first embodiment, the light-emitting element 60 has a rectangular shape in a plan view of the substrate 50A, with a first side surface 62A and a second side surface 62B that are parallel to each other, and a third side surface 62C and a fourth side surface 62D that connect the first side surface 62A and the second side surface 62B and are also parallel to each other. In the light-emitting element 60, the third side surface 62C and the fourth side surface 62D are shorter than the first side surface 62A and the second side surface 62B. The light-emitting element 60 is disposed such that the third side surface 62C of the light-emitting element 60 is adjacent to and parallel to the third side surface 52C of the substrate 50A. In a plan view of the substrate 50A, the light-emitting element 60 is disposed closer to the third side surface 52C of the substrate 50A than the center of the substrate 50A.

[0037] As shown in Figure 6, the light-emitting element 60 includes a light-emitting end surface 64 at the position of the third side surface 62C of the light-emitting element 60, and laser light is emitted from the light-emitting end surface 64 in a direction approximately perpendicular to this light-emitting end surface 64 (roughly the +Z direction).

[0038] As shown in Figures 7 and 10, the light-emitting element 60 includes an anode electrode 66 provided on a front surface 60A of the light-emitting element 60 and a cathode electrode 68 provided on a back surface 60B of the light-emitting element 60, and this cathode electrode 68 is bonded to the substrate 50A.

[0039] (Transistor) As shown in FIG. 6 , in the first embodiment, the transistor 80 has a rectangular shape in a plan view of the substrate 50A, with a first side surface 82A and a second side surface 82B that are parallel to each other, and a third side surface 82C and a fourth side surface 82D that connect the first side surface 82A and the second side surface 82B and are parallel to each other. In the transistor 80, the third side surface 82C and the fourth side surface 82D are shorter than the first side surface 82A and the second side surface 82B. The transistor 80 is disposed such that the fourth side surface 82D of the transistor 80 is adjacent to and parallel with the fourth side surface 52D of the substrate 50A. Furthermore, the transistor 80 is disposed such that the third side surface 82C of the transistor 80 is adjacent to and parallel with the fourth side surface 62D of the light-emitting element 60.

[0040] 7 and 10 , a transistor 80 implemented as a vertical MOSFET includes a source electrode 84 provided on a portion of a front surface 80A of the transistor 80 and a gate electrode 86 (see FIG. 7 ) provided on another portion of the front surface 80A of the transistor 80. The source electrode 84 is formed to be larger in size than the gate electrode 86. The transistor 80 also includes a drain electrode 88 provided over almost the entire back surface 80B of the transistor 80, and this drain electrode 88 is bonded to the substrate 50A.

[0041] 6, the gate electrode 86 of the transistor 80 is electrically connected to the connection portion 146B of the lead pin 142B by a wire 152B. A control voltage for controlling the switching of the transistor 80 is supplied to the gate electrode 86 from a gate driver 908 (see FIG. 12) provided on the drive substrate 910 shown in FIG. 5 via the lead pin 142B and the wire 152B.

[0042] The source electrode 84 of the transistor 80 is electrically connected to the connection portion 146A of the lead pin 142A by a wire 152A. A ground voltage is applied to the source electrode 84 from the drive substrate 910 via the lead pin 142A and the wire 152A.

[0043] Furthermore, the source electrode 84 of the transistor 80 is electrically connected to the anode electrode 66 of the light-emitting element 60 via a plurality of wires 190, for example, four wires 190 in the first embodiment. These wires 190 form a wiring path connecting the transistor 80 and the light-emitting element 60, and when the transistor 80 is turned on, a current flows from the transistor 80 to the light-emitting element 60 via this wiring path. Therefore, by increasing the number of wires 190 and facilitating the flow of current from the transistor 80 to the light-emitting element 60, the influence of parasitic inductance can be suppressed. For example, the number of wires 190 is set to be greater than the number of wires 152A and 152B. The wires 190 may be ribbon wires. Note that in the first embodiment, the wires 152A and 152B correspond to first wires, and the wire 190 corresponds to a second wire.

[0044] (Capacitor Module) As shown in FIGS. 6, 7, and 11, the first capacitor module 110 and the second capacitor module 120 have a generally rectangular parallelepiped shape.

[0045] 6 , the first capacitor module 110 has a rectangular shape in a plan view of the substrate 50A, with a first side surface 111A and a second side surface 111B that are parallel to each other, and a third side surface 111C and a fourth side surface 111D that are parallel to each other and connect the first side surface 111A and the second side surface 111B. In the first capacitor module 110, the third side surface 111C and the fourth side surface 111D are shorter than the first side surface 111A and the second side surface 111B. The first capacitor module 110 is arranged such that the first side surface 111A of the first capacitor module 110 is adjacent to and parallel with the first side surface 52A of the substrate 50A, and the third side surface 111C of the first capacitor module 110 is adjacent to and parallel with the third side surface 52C of the substrate 50A. Furthermore, the first capacitor module 110 is arranged such that the second side surface 111B of the first capacitor module 110 is adjacent to and parallel with the first side surface 82A of the transistor 80.

[0046] As shown in FIGS. 6 and 11 , the first capacitor module 110 has a first main surface 112A and a second main surface 112B that are parallel to each other. The first capacitor module 110 is disposed so that the first main surface 112A faces the substrate 50A in the thickness direction (Y-axis direction) of the substrate 50A. The first main surface 112A corresponds to the main surface facing the substrate 50A in the thickness direction (Y-axis direction) of the substrate 50A. The first capacitor module 110 includes a first connection electrode 113 and a second connection electrode 114 provided on the first main surface 112A. The first connection electrode 113 and the second connection electrode 114 are disposed apart from each other. The first connection electrode 113 and the second connection electrode 114 are disposed side by side in the longitudinal direction (+Z direction) of the first capacitor module 110. These first and second connection electrodes 113 and 114 are bonded to the substrate 50A.

[0047] The second connection electrode 114 of the first capacitor module 110 is electrically connected to the drain electrode 88 of the transistor 80 via the internal wiring structure of the substrate 50A. The first connection electrode 113 of the first capacitor module 110 is electrically connected to the cathode electrode 68 of the light-emitting element 60 via the internal wiring structure of the substrate 50A.

[0048] The first capacitor module 110 includes a silicon capacitor 115, a connection portion 118, and a sealing resin 119. The silicon capacitor 115 includes a silicon substrate 116. As shown in FIG. 2, the silicon substrate 116 is formed in a rectangular plate shape when viewed from above the substrate 50A. As shown in FIG. 11, the silicon substrate 116 has a first surface 116A and a second surface 116B facing opposite each other. The silicon capacitor 115 includes a first connection electrode 113 provided on the first surface 116A of the silicon substrate 116 and a counter electrode 117 provided on the second surface 116B. The counter electrode 117 faces the first connection electrode 113 across the silicon substrate 116. The first connection electrode 113 is in contact with the first surface 116A of the silicon substrate 116. The counter electrode 117 is in contact with the second surface 116B of the silicon substrate 116. This silicon capacitor 115 is a capacitor having a first connection electrode 113 and an opposing electrode 117 arranged on either side of a silicon substrate 116 as two opposing electrodes, and has a capacitance value due to the coupling between the first connection electrode 113 and the opposing electrode 117.

[0049] The counter electrode 117 is electrically connected to the second connection electrode 114 by a connection portion 118. The connection portion 118 includes a first wiring 118A electrically connected to the counter electrode 117 and a second wiring 118B electrically connecting the first wiring 118A to the second connection electrode 114. The first wiring 118A extends in the longitudinal direction of the first capacitor module 110. The second wiring 118B is a via wiring formed on the sealing resin 119 and provided in an opening 119A that exposes a portion of the second connection electrode 114. As shown in FIGS. 6 and 11 , the first capacitor module 110 includes a plurality of second wirings 118B.

[0050] The first capacitor module 110 includes a sealing resin 119 that seals the silicon capacitor 115 (silicon substrate 116). The sealing resin 119 seals the silicon substrate 116 and counter electrode 117 of the silicon capacitor 115, and the connection portion 118, while exposing the lower surfaces of the first connection electrode 113 and the second connection electrode 114.

[0051] 6 , the second capacitor module 120 has a rectangular shape in a plan view of the substrate 50A, with a first side surface 121A and a second side surface 121B that are parallel to each other, and a third side surface 121C and a fourth side surface 121D that are parallel to each other and connect the first side surface 121A and the second side surface 121B. In the second capacitor module 120, the third side surface 121C and the fourth side surface 121D are shorter than the first side surface 121A and the second side surface 121B. The second capacitor module 120 is arranged such that the second side surface 121B of the second capacitor module 120 is adjacent to and parallel with the second side surface 52B of the substrate 50A, and the third side surface 121C of the second capacitor module 120 is adjacent to and parallel with the third side surface 52C of the substrate 50A. Furthermore, the second capacitor module 120 is arranged such that the first side surface 121A of the second capacitor module 120 is adjacent to and parallel with the second side surface 82B of the transistor 80.

[0052] The second capacitor module 120 has the same configuration as the first capacitor module 110, so a cross-sectional view of the second capacitor module 120 is omitted. The components constituting the second capacitor module 120 are shown in FIG.

[0053] The second capacitor module 120 has a first main surface 122A and a second main surface 122B that are parallel to each other. The second capacitor module 120 is disposed so that the first main surface 122A faces the substrate 50A in the thickness direction (Y-axis direction) of the substrate 50A. The first main surface 122A corresponds to the main surface facing the substrate 50A in the thickness direction (Y-axis direction) of the substrate 50A. The second capacitor module 120 includes a first connection electrode 123 and a second connection electrode 124 provided on the first main surface 122A. The first connection electrode 123 and the second connection electrode 124 are disposed apart from each other. The first connection electrode 123 and the second connection electrode 124 are disposed side by side in the longitudinal direction (+Z direction) of the second capacitor module 120. These first and second connection electrodes 123 and 124 are bonded to the substrate 50A.

[0054] The second connection electrode 124 of the second capacitor module 120 is electrically connected to the drain electrode 88 of the transistor 80 via the internal wiring structure of the substrate 50A. The first connection electrode 123 of the second capacitor module 120 is electrically connected to the cathode electrode 68 of the light-emitting element 60 via the internal wiring structure of the substrate 50A.

[0055] The second capacitor module 120 includes a silicon capacitor 125, a connection portion 128, and a sealing resin 129. The silicon capacitor 125 includes a silicon substrate 126. As shown in FIG. 2 , the silicon substrate 126 is formed in a rectangular plate shape when viewed from above the substrate 50A. The silicon substrate 126 has a first surface and a second surface facing opposite each other. The silicon capacitor 125 includes a first connection electrode 123 provided on the first surface of the silicon substrate 126 and a counter electrode 127 provided on the second surface. The counter electrode 127 faces the first connection electrode 123 across the silicon substrate 126. The first connection electrode 123 is in contact with the first surface of the silicon substrate 126. The counter electrode 127 is in contact with the second surface of the silicon substrate 126. This silicon capacitor 125 is a capacitor having a first connection electrode 123 and an opposing electrode 127 arranged on either side of a silicon substrate 126 as two opposing electrodes, and has a capacitance value due to the coupling between the first connection electrode 123 and the opposing electrode 127.

[0056] The counter electrode 127 is electrically connected to the second connection electrode 124 by a connection portion 128. The connection portion 128 includes a first wiring 128A electrically connected to the counter electrode 127 and a second wiring 128B electrically connecting the first wiring 128A to the second connection electrode 124. The first wiring 128A extends in the length direction of the second capacitor module 120. As shown in FIG. 6 , the second capacitor module 120 includes a plurality of second wirings 128B.

[0057] The second capacitor module 120 includes a sealing resin 129 that seals the silicon capacitor 125 (silicon substrate 126). The sealing resin 129 seals the silicon substrate 126 and counter electrode 127 of the silicon capacitor 125, as well as the connection portion 128, and is formed so as to expose the lower surfaces of the first connection electrode 123 and the second connection electrode 124.

[0058] In this manner, the first capacitor module 110 is disposed adjacent to the first side surface 82A of the transistor 80, while the second capacitor module 120 is disposed adjacent to the second side surface 82B of the transistor 80. This arrangement allows the third side surface 82C of the transistor 80 to be located between the first capacitor module 110 and the second capacitor module 120, thereby positioning the transistor 80 closer to the light-emitting element 60. This makes it possible to shorten the distance between the transistor 80 and the light-emitting element 60 on the substrate 50A. As a result, the length of the wiring path (wire 190) connecting the light-emitting element 60 and the transistor 80 can be shortened, thereby suppressing the effects of parasitic inductance.

[0059] The first and second capacitor modules 110 and 120 include silicon capacitors 115 and 125, respectively. Multilayer ceramic capacitors (MLCCs), for example, are used in many electronic devices as compact capacitors. The resulting capacitors have parasitic resistance (equivalent series resistance: ESR) and parasitic inductance (equivalent series inductance: ESL) compared to ideal capacitors. The silicon capacitors 115 and 125 have a smaller parasitic inductance (ESL) compared to multilayer ceramic capacitors. The multilayer ceramic capacitor has a parasitic resistance (ESR) of approximately 100 mΩ and a parasitic inductance (ESL) of approximately 0.3 to 0.4 nH. In contrast, the parasitic resistance (ESR) of the first and second capacitor modules 110 and 120 is preferably less than 100 mΩ. The parasitic inductance (ESL) of the first and second capacitor modules 110, 120 is preferably less than 100 pH.

[0060] Furthermore, the first capacitor module 110 and the second capacitor module 120 are disposed symmetrically on the substrate 50A with respect to the light-emitting element 60 and the transistor 80. As a result, a first wiring path through which a current flows from the first capacitor module 110 to the light-emitting element 60 via the transistor 80, and a second wiring path through which a current flows from the second capacitor module 120 to the light-emitting element 60 via the transistor 80, are disposed symmetrically with respect to the light-emitting element 60 and the transistor 80.

[0061] 10 and 11 , the first and second capacitor modules 110, 120 are formed to be thicker than the light-emitting element 60. On the other hand, the first and second capacitor modules 110, 120 are formed to be thinner than the transistor 80. The thickness of the first and second capacitor modules 110, 120 is not less than 50 μm and not more than 200 μm. The thickness of the first and second capacitor modules 110, 120 is, for example, 160 μm. The thickness of the multilayer ceramic capacitor having capacitance used in the light-emitting module 30A is, for example, about 500 μm.

[0062] The first wiring path includes a wiring path connecting the second connection electrode 114 of the first capacitor module 110 and the drain electrode 88 of the transistor 80, a wire 190 connecting the source electrode 84 of the transistor 80 and the anode electrode 66 of the light-emitting element 60, and a wiring path connecting the cathode electrode 68 of the light-emitting element 60 and the first connection electrode 113 of the first capacitor module 110. These wiring paths are formed by the internal wiring structure of the substrate 50A.

[0063] The second wiring path includes a wiring path connecting the second connection electrode 124 of the second capacitor module 120 and the drain electrode 88 of the transistor 80, a wire 190 connecting the source electrode 84 of the transistor 80 and the anode electrode 66 of the light-emitting element 60, and a wiring path connecting the cathode electrode 68 of the light-emitting element 60 and the first connection electrode 123 of the second capacitor module 120. These wiring paths are formed by the internal wiring structure of the substrate 50A.

[0064] By arranging the first wiring path and the second wiring path symmetrically in this manner, the magnetic flux generated by the current flowing through the first wiring path and the magnetic flux generated by the current flowing through the second wiring path cancel each other out, thereby reducing the parasitic inductance present in the first wiring path and the parasitic inductance present in the second wiring path.

[0065] (Substrate) Next, the structure of the substrate 50A of the light-emitting module 30A will be described. As shown in FIGS. 6 to 11 , the substrate 50A is, for example, a printed wiring board, and in the first embodiment, has a two-layer wiring structure as its internal wiring structure. That is, the substrate 50A in the first embodiment is a double-sided substrate. The substrate 50A includes an insulating base material 210, a first wiring layer 220 provided on a front surface 212A of the base material 210, and a second wiring layer 230 provided on a back surface 212B of the base material 210. The base material 210 is formed of an insulating material such as a resin base material, a silicon base material, a glass base material, or a ceramic base material. That is, the substrate 50A can be a resin substrate, a silicon substrate, a glass substrate, a ceramic substrate, or the like. In the first embodiment, a resin base material formed of glass epoxy resin is used as the base material 210. The first wiring layer 220 and the second wiring layer 230 are formed of a metal material such as Cu.

[0066] 7 to 11, the substrate 50A includes a plurality of via wirings that penetrate the base material 210 and electrically connect the first wiring layer 220 and the second wiring layer 230, and in the first embodiment, includes a first via wiring 242 and a plurality (e.g., six) of second via wirings 244 and a third via wiring 246. These first to third via wirings 242, 244, and 246 are formed of a metal material such as Cu.

[0067] The substrate 50A also includes a first insulating layer 250 provided on the surface 220A of the first wiring layer 220 to partially expose the first wiring layer 220, and a second insulating layer 260 provided on the back surface 230B of the second wiring layer 230 to partially expose the second wiring layer 230. The first insulating layer 250 and the second insulating layer 260 are formed of an insulating resin such as epoxy resin or polyimide resin. The first insulating layer 250 and the second insulating layer 260 may also contain a filler such as silica or alumina. For ease of illustration, the base material 210, the first insulating layer 250, and the second insulating layer 260 are shown in phantom lines (two-dot chain lines) in FIG. 7 .

[0068] Fig. 8 is a plan view showing the first wiring layer 220 and the base material 210. Note that the first insulating layer 250 is not shown in Fig. 8. As shown in Fig. 8, the first wiring layer 220 includes a plurality of wires provided on the surface 212A of the base material 210 and arranged spaced apart from one another, and in the first embodiment, includes first surface-side wires 310, second surface-side wires 320, and third surface-side wires 330.

[0069] The first surface-side wiring 310 is arranged along the first, second, and third side surfaces 52A, 52B, and 52C of the substrate 50A, and is formed, for example, with a size of approximately one-third the area of ​​the substrate 50A. The first surface-side wiring 310 includes first to third wiring regions 312, 314, and 316. Note that the first to third wiring regions 312, 314, and 316 are each part of the first surface-side wiring 310, and the first surface-side wiring 310 does not necessarily have physical boundaries between the first to third wiring regions 312, 314, and 316.

[0070] The first wiring region 312 is a light-emitting element mounting region where the cathode electrode 68 of the light-emitting element 60 is mounted. The second wiring region 314 is a part of the first capacitor mounting region where the first connection electrode 113 of the first capacitor module 110 is mounted. The third wiring region 316 is a part of the second capacitor mounting region where the first connection electrode 123 of the second capacitor module 120 is mounted. Therefore, the cathode electrode 68 of the light-emitting element 60 is electrically connected to the first connection electrodes 113, 123 of the first and second capacitor modules 110, 120 via the first surface-side wiring 310. The second wiring region 314 and the third wiring region 316 are arranged symmetrically with respect to the first wiring region 312.

[0071] The second surface-side wiring 320 is arranged along the first, second, and fourth side surfaces 52A, 52B, and 52D of the substrate 50A, and is arranged at a distance from the first surface-side wiring 310. The second surface-side wiring 320 is formed, for example, to have a size slightly smaller than approximately two-thirds the area of ​​the substrate 50A. The second surface-side wiring 320 includes fourth to sixth wiring regions 322, 324, and 326. Note that the fourth to sixth wiring regions 322, 324, and 326 are each part of the second surface-side wiring 320, and physical boundaries between the fourth to sixth wiring regions 322, 324, and 326 do not exist on the second surface-side wiring 320.

[0072] The fourth wiring region 322 is a transistor mounting region where the drain electrode 88 of the transistor 80 is mounted. The fifth wiring region 324 is a part of the first capacitor mounting region where the second connection electrode 114 of the first capacitor module 110 is mounted. The sixth wiring region 326 is a part of the second capacitor mounting region where the second connection electrode 124 of the second capacitor module 120 is mounted. Therefore, the drain electrode 88 of the transistor 80 is electrically connected to the second connection electrodes 114, 124 of the first and second capacitor modules 110, 120 via the second surface side wiring 320. The fifth wiring region 324 and the sixth wiring region 326 are arranged symmetrically with respect to the fourth wiring region 322.

[0073] The second surface-side wiring 320 further includes a notch 328. This notch 328 is formed at a position adjacent to a fourth wiring region 322 (transistor mounting region) and a fifth wiring region 324 (part of the first capacitor mounting region) of the second surface-side wiring 320.

[0074] The third surface-side wiring 330 is arranged along the first and fourth side surfaces 52A and 52D of the substrate 50A and is arranged spaced apart from the second surface-side wiring 320. In the first embodiment, the third surface-side wiring 330 is arranged adjacent to (but spaced apart from) the notch 328 of the second surface-side wiring 320. The total area of ​​the second surface-side wiring 320 and the third surface-side wiring 330 corresponds to approximately two-thirds of the area of ​​the substrate 50A. In other words, the second surface-side wiring 320 and the third surface-side wiring 330 are arranged spaced apart from each other so that their combined shape forms a rectangle having a size approximately two-thirds the area of ​​the substrate 50A.

[0075] The third surface-side wiring 330 includes a seventh wiring region 332. The seventh wiring region 332 is a part of the third surface-side wiring 330, and the physical boundary of the seventh wiring region 332 does not exist in the third surface-side wiring 330. The seventh wiring region 332 is an external element connection region for connecting an external element to the substrate 50A (light-emitting element drive circuit 70), and an external element connection pad 160 (see FIG. 6) is arranged in this seventh wiring region 332. In the first embodiment, the anode electrode 906A of the SBD 906 (see FIG. 12) is connected to the seventh wiring region 332 (external element connection pad 160) via a lead pin 142C and a wire 152C (see FIG. 6).

[0076] The first insulating layer 250 includes first to seventh openings 251 to 257 (see FIG. 6) that expose the first to seventh wiring regions 312, 314, 316, 322, 324, 326, and 332 of the first to third surface side wirings 310, 320, and 330, respectively.

[0077] A first metal plating material 362 (see FIGS. 6, 7, 10, and 11) is provided on the first to sixth wiring regions 312, 314, 316, 322, 324, and 326 exposed through the first to sixth openings 251 to 256 of the first insulating layer 250. The first metal plating material 362 may be, for example, a laminate containing nickel (Ni) and gold (Au) or a laminate containing Ni, palladium (Pd), and Au. As shown in FIG. 10, the cathode electrode 68 of the light-emitting element 60 is bonded to the first metal plating material 362 in the first wiring region 312 (light-emitting element mounting region) by a bonding member (not shown). The drain electrode 88 of the transistor 80 is bonded to the first metal plating material 362 in the fourth wiring region 322 (transistor mounting region) by a bonding member (not shown). As shown in FIG. 11 , the first and second connection electrodes 113, 114 of the first capacitor module 110 are bonded to the first metal plating material 362 in the fifth and second wiring regions 324, 314 (first capacitor mounting regions) by bonding materials (not shown). Although a cross-sectional view is omitted, similar to the first capacitor module 110, the first and second connection electrodes 123, 124 of the second capacitor module 120 are bonded to the first metal plating material 362 in the sixth and third wiring regions 326, 316 (second capacitor mounting regions) by bonding materials (not shown). Examples of bonding materials include silver (Ag) paste and solder paste containing tin (Su), silver (Ag), and copper (Cu). The bonding material may be changed depending on the component to be bonded to the first metal plating material 362. For example, Ag paste can be used to bond the light-emitting element 60. Furthermore, the transistor 80 and the first and second capacitor modules 110 and 120 can be joined using a solder paste material or an Ag paste material.

[0078] The external element connection pad 160 (FIGS. 6 and 11) described above is provided in the seventh wiring region 332 exposed from the seventh opening 257 of the first insulating layer 250. The external element connection pad 160 is formed of a second metal plating material. As the second metal plating material, a laminate containing Ni and Au, or a laminate containing Ni, Pd, and Au can be used.

[0079] Fig. 9 is a plan view showing the second wiring layer 230 and the second insulating layer 260. Note that the first insulating layer 250, the first wiring layer 220, and the base material 210 are not shown in Fig. 9. As shown in Fig. 9, the second wiring layer 230 includes a plurality of wires that are provided on the back surface 212B (see Fig. 7) of the base material 210 and that are spaced apart from each other, and in the first embodiment, include first back surface side wires 410 and second back surface side wires 420.

[0080] The first back surface side wiring 410 is arranged along the first, second, third, and fourth side surfaces 52A, 52B, 52C, and 52D of the substrate 50A. The first back surface side wiring 410 is formed in a generally gate shape, and an opening 410A is defined inside the first back surface side wiring 410 in a plan view. The opening 410A is formed in a position corresponding to the fourth wiring region 322 (transistor mounting region) of the second surface side wiring 320 in a plan view of the substrate 50A, and is larger in size than the fourth wiring region 322. The first back surface side wiring 410 overlaps with the first and third surface side wirings 310 and 330 and also partially overlaps with the second surface side wiring 320 in a plan view of the substrate 50A.

[0081] The second back-surface-side wiring 420 is disposed within the opening 410A inside the first back-surface-side wiring 410 along the fourth side surface 52D of the substrate 50A. The second back-surface-side wiring 420 includes an eighth wiring region 414. Note that the eighth wiring region 414 is a part of the second back-surface-side wiring 420, and the physical boundary of the eighth wiring region 414 does not exist within the second back-surface-side wiring 420. The eighth wiring region 414 is a transistor connection region for electrically connecting the drain electrode 88 of the transistor 80 to the heat sink 24 (see, for example, FIG. 1 ). The second back-surface-side wiring 420 overlaps with the second front-surface-side wiring 320 in a plan view of the substrate 50A.

[0082] The second insulating layer 260 includes an eighth opening 258 that exposes an eighth wiring region 414 (transistor connection region) of the second back-surface-side wiring 420. As shown in FIG. 10 , a third metal plating material 364 is provided in the eighth wiring region 414 exposed through the eighth opening 258. The third metal plating material 364 may be, for example, a laminate containing Ni and Au, or a laminate containing Ni, Pd, and Au. The third metal plating material 364 is bonded to the heat sink 24 by a bonding material (not shown). This bonding material may be an Ag paste or a solder paste.

[0083] The second insulating layer 260 covers the back surface 230B of the second wiring layer 230 except for the eighth wiring region 414 (transistor connection region). Therefore, the first back surface side wiring 410 is not exposed from the second insulating layer 260 and is not electrically connected to the heat sink 24.

[0084] 7 to 11 , the first wiring layer 220 and the second wiring layer 230 are electrically connected by the first to third via wirings 242, 244, and 246 that penetrate the base material 210. In the first embodiment, the via wirings 242, 244, and 246 are formed, for example, in a cylindrical shape, but the shape is not particularly limited. These via wirings 242, 244, and 246 are so-called thermal vias, and function as a conductive path between the first wiring layer 220 and the second wiring layer 230, as well as a heat dissipation path from the first wiring layer 220 to the second wiring layer 230.

[0085] The first via wiring 242 is located in the first wiring region 312 (light-emitting element mounting region) and electrically connects the first front surface side wiring 310 and the first back surface side wiring 410. Therefore, the cathode electrode 68 of the light-emitting element 60 and the first connection electrodes 113, 123 of the first and second capacitor modules 110, 120 are electrically connected to the first back surface side wiring 410 via the first front surface side wiring 310 and the first via wiring 242.

[0086] The second via wiring 244 is located in the fourth wiring region 322 (transistor mounting region) and the eighth wiring region 414 (transistor mounting region) and electrically connects the second surface side wiring 320 and the second back surface side wiring 420. Therefore, the drain electrode 88 of the transistor 80 is electrically connected to the heat sink 24 of the stem 20 via the second surface side wiring 320, the second via wiring 244, and the second back surface side wiring 420. The drain electrode 88 of the transistor 80 is also electrically connected to the second connection electrodes 114, 124 of the first and second capacitor modules 110, 120 via the second surface side wiring 320. The arrangement of the second via wiring 244 is not particularly limited. For example, the second via wiring 244 is evenly arranged within the fourth and eighth wiring regions 322, 414. In the first embodiment, the second via wiring 244 is arranged in a 2×3 array, for example.

[0087] The third via wiring 246 electrically connects the third surface-side wiring 330 and the first back-side wiring 410. Therefore, the anode electrode 906A of the SBD 906 (see FIG. 12 ) connected to the external element connection pad 160 is electrically connected to the first connection electrodes 113, 123 of the first and second capacitor modules 110, 120 via the third surface-side wiring 330, the third via wiring 246, the first back-side wiring 410, the first via wiring 242, and the first surface-side wiring 310. Furthermore, since the first connection electrodes 113, 123 of the first and second capacitor modules 110, 120 are electrically connected to the cathode electrode 68 of the light-emitting element 60, the anode electrode 906A of the SBD 906 is also electrically connected to the cathode electrode 68 of the light-emitting element 60.

[0088] (Electrical Configuration of Semiconductor Light-Emitting Device) Figure 12 is a circuit diagram that schematically illustrates the electrical configuration of the semiconductor light-emitting device 10A. The light-emitting element drive circuit 70 includes a light-emitting element 60 mounted on a substrate 50A of the light-emitting module 30A, a transistor 80 (vertical MOSFET), a first capacitor module 110, and a second capacitor module 120. Note that in Figure 12, the first capacitor module 110 and the second capacitor module 120 are shown as a single capacitor.

[0089] The drain electrode 88 of the transistor 80 is connected to the second connection electrodes 114, 124 of the first and second capacitor modules 110, 120. The drain electrode 88 of the transistor 80 and the second connection electrodes 114, 124 of the first and second capacitor modules 110, 120 are connected to a positive electrode 904A of a constant voltage source 904 via a resistor element 902. A negative electrode 904B of the constant voltage source 904 is connected to ground. In the first embodiment, the constant voltage source 904 and the resistor element 902 are provided on a drive substrate 910 (see FIG. 5 ). The voltage from the constant voltage source 904 is applied to the drain electrode 88 of the transistor 80 and the second connection electrodes 114, 124 of the first and second capacitor modules 110, 120 via the resistor element 902, the lead pin 142D (see FIGS. 1 and 2 ), the base 22 and heat sink 24 of the stem 20, and the internal wiring structure of the substrate 50A.

[0090] The source electrode 84 of the transistor 80 is connected to the anode electrode 66 of the light-emitting element 60 and is also connected to ground. In the first embodiment, a ground voltage is applied to the source electrode 84 of the transistor 80 from the drive substrate 910 via a lead pin 142A (see FIGS. 1 and 2) and a wire 152A. The source electrode 84 of the transistor 80 is also connected to the anode electrode 66 of the light-emitting element 60 via a wire 190 (see FIGS. 1 and 2).

[0091] The gate electrode 86 of the transistor 80 is connected to a gate driver 908 provided on a drive substrate 910. In the first embodiment, a control voltage is supplied from the gate driver 908 to the gate electrode 86 of the transistor 80 via a lead pin 142B (see FIGS. 1 and 6) and a wire 152B, and the on / off of the transistor 80 is controlled by this control voltage.

[0092] The cathode electrode 68 of the light-emitting element 60 is connected to the first connection electrodes 113, 123 of the first and second capacitor modules 110, 120. In the first embodiment, the cathode electrode 68 of the light-emitting element 60 is connected to the first connection electrodes 113, 123 of the first and second capacitor modules 110, 120 via the internal wiring structure of the substrate 50A.

[0093] Furthermore, the cathode electrode 68 of the light-emitting element 60 and the first connection electrodes 113, 123 of the first and second capacitor modules 110, 120 are connected to the anode electrode 906A of the SBD 906. In the first embodiment, the SBD 906 is provided on a drive substrate 910, and the anode electrode 906A of the SBD 906 is connected to an external element connection pad 160 via a lead pin 142C (see FIGS. 1 and 2 ) and a wire 152C. This external element connection pad 160 is connected to the cathode electrode 68 of the light-emitting element 60 and the first connection electrodes 113, 123 of the first and second capacitor modules 110, 120 via the internal wiring structure of the substrate 50A.

[0094] A cathode electrode 906B of the SBD 906 is connected to a negative electrode 904B of the constant voltage source 904. In the first embodiment, the cathode electrode 906B of the SBD 906 is connected to the anode electrode 66 of the light-emitting element 60 via a lead pin 142A (see FIGS. 1 and 2 ), a wire 152A, the source electrode 84 of the transistor 80, and a wire 190.

[0095] When the transistor 80 is turned off by the control voltage from the gate driver 908, a closed loop circuit is formed by the constant voltage source 904, the resistive element 902, the first and second capacitor modules 110, 120, and the SBD 906. This causes the first and second capacitor modules 110, 120 to be charged based on the voltage supplied from the constant voltage source 904.

[0096] When the transistor 80 is turned on by a control voltage from the gate driver 908, a closed loop circuit is formed by the transistor 80, the light-emitting element 60, and the first and second capacitor modules 110, 120. As a result, a current (pulse current) based on the charges stored in the first and second capacitor modules 110, 120 flows through the light-emitting element 60 via the transistor 80, causing the light-emitting element 60 to emit laser light.

[0097] (Function) Next, the function of the semiconductor light emitting device 10A of the first embodiment will be described. The semiconductor light emitting device 10A includes a substrate 50A, a light emitting element 60 mounted on the substrate 50A, a transistor 80, a first capacitor module 110, and a second capacitor module 120. The first capacitor module 110 has a first main surface 112A facing the substrate 50A, a first connection electrode 113 and a second connection electrode 114 provided on the first main surface 112A, and is electrically connected to the light emitting element 60. The second capacitor module 120 has a first main surface 122A facing the substrate 50A, and a first connection electrode 123 and a second connection electrode 124 provided on the first main surface 122A, and is electrically connected to the light emitting element 60. The first capacitor module 110 includes a silicon substrate 116 having a first surface 116A and a second surface 116B facing opposite directions, a first connection electrode 113 provided on the first surface 116A, and a counter electrode 117 provided on the second surface 116B and facing the first connection electrode 113. The second capacitor module 120 includes a silicon substrate 126 having a first surface and a second surface facing opposite directions, a first connection electrode 123 provided on the first surface, and a counter electrode 127 provided on the second surface and facing the first connection electrode 123.

[0098] The first capacitor module 110 includes a silicon capacitor 115 configured with a silicon substrate 116, a first connection electrode 113, and a counter electrode 117. The second capacitor module 120 includes a silicon capacitor 125 configured with a silicon substrate 126, a first connection electrode 123, and a counter electrode 127. The silicon capacitors 115 and 125 have a smaller parasitic inductance (ESL) than multilayer ceramic capacitors used as small capacitors. Therefore, the parasitic inductance in the first and second wiring paths for the light-emitting element 60 can be reduced.

[0099] The parasitic inductance occurring in the first and second wiring paths affects the rise and fall characteristics of the pulse current supplied to the light-emitting element 60. The larger the parasitic inductance, the gentler the rise and fall of the pulse current. Therefore, by reducing the parasitic inductance, the rise and fall of the pulse current can be made steeper. The pulse current affects the output characteristics of the light-emitting element 60, i.e., the rise and fall characteristics of the light output of the semiconductor light-emitting device 10A. Therefore, by reducing the parasitic inductance, the rise and fall of the light output can be made steeper. This allows for the acquisition of light output with a shorter pulse width.

[0100] FIG. 13 is a cross-sectional view of a light-emitting module of a comparative example, taken at a position corresponding to FIG. 11 . In FIG. 13 , only a silicon capacitor 115 is mounted on a substrate 50A. The counter electrode 117 of the silicon capacitor 115 is electrically connected to the second surface-side wiring 320 (fifth wiring region 324) by a wire 191. As described above, the silicon capacitor 115 has lower resistance and lower inductance than a multilayer ceramic capacitor. However, in this comparative example, the parasitic inductance of the wire 191 connecting the silicon capacitor 115 to the second surface-side wiring 320 is greater than the parasitic inductance of the connection portions 118, 128 of the first and second capacitor modules 110, 120 in the first embodiment. Therefore, it can be said that there are fewer benefits to using the silicon capacitor 115 in this comparative example.

[0101] The light-emitting module 30A is mounted on the heat sink 24 of the stem 20, and the surrounding member 40 is provided on the base 22 of the stem 20 so as to surround the light-emitting module 30A and the heat sink 24. The light-emitting module 30A includes a light-emitting element 60 and a light-emitting element drive circuit 70, and the light-emitting element drive circuit 70 includes a transistor 80 that drives the light-emitting element 60. The transistor 80 is implemented as a vertical MOSFET on a substrate 50A mounted on the heat sink 24.

[0102] By employing a vertical MOSFET for the transistor 80, the source electrode 84 is disposed so as to overlap the drain electrode 88 in a plan view of the substrate 50A. Therefore, by employing a vertical MOSFET, the wiring path of the transistor 80 mounted on the substrate 50A can be made shorter than when a horizontal MOSFET is employed. As a result, the size of the substrate 50A can be reduced, and the size of the light-emitting module 30A can be made smaller.

[0103] (Effects) The semiconductor light-emitting device 10A of the first embodiment has the following effects. (1-1) The semiconductor light-emitting device 10A includes a substrate 50A, a light-emitting element 60 mounted on the substrate 50A, a transistor 80, a first capacitor module 110, and a second capacitor module 120. The first capacitor module 110 has a first main surface 112A facing the substrate 50A in the thickness direction (Y-axis direction) of the substrate 50A, a first connection electrode 113 and a second connection electrode 114 provided on the first main surface 112A, and is electrically connected to the light-emitting element 60. The second capacitor module 120 has a first main surface 122A facing the substrate 50A in the thickness direction (Y-axis direction) of the substrate 50A, a first connection electrode 123 and a second connection electrode 124 provided on the first main surface 122A, and is electrically connected to the light-emitting element 60. The first capacitor module 110 includes a silicon substrate 116 having a first surface 116A and a second surface 116B facing opposite directions, a first connection electrode 113 provided on the first surface 116A, and a counter electrode 117 provided on the second surface 116B and facing the first connection electrode 113. The second capacitor module 120 includes a silicon substrate 126 having a first surface and a second surface facing opposite directions, a first connection electrode 123 provided on the first surface, and a counter electrode 127 provided on the second surface and facing the first connection electrode 123.

[0104] According to this configuration, the parasitic inductance (ESL) in the first and second capacitor modules 110, 120 can be made smaller than the parasitic inductance of, for example, a multilayer ceramic capacitor. This makes it possible to reduce the parasitic inductance occurring in the wiring path between the cathode electrode 68 of the light-emitting element 60 and the transistor 80. This makes it possible to reduce the parasitic inductance in the wiring path connecting the light-emitting element 60 and the transistor 80.

[0105] (1-2) Parasitic inductance occurring in the wiring path affects the rise and fall characteristics of the pulse current supplied to the light-emitting element 60. The larger the parasitic inductance, the more gradual the rise and fall of the pulse current. Therefore, by reducing the parasitic inductance, the rise and fall of the pulse current can be made steeper. The pulse current affects the output characteristics of the light-emitting element 60, that is, the rise and fall characteristics of the light output of the semiconductor light-emitting device 10A. Therefore, by reducing the parasitic inductance, the rise and fall of the light output can be made steeper. This allows for light output with a shorter pulse width to be obtained.

[0106] (1-3) By employing a vertical MOSFET for the transistor 80, it is possible to shorten the wiring paths through which current flows from the first and second capacitor modules 110, 120 to the light-emitting element 60 via the transistor 80, compared to when a horizontal MOSFET is employed. This makes it possible to reduce the parasitic inductance occurring in each wiring path.

[0107] (1-4) The first capacitor module 110 is mounted on the substrate 50A adjacent to the first side surface 82A of the transistor 80 in a plan view of the substrate 50A. The second capacitor module 120 is mounted on the substrate 50A adjacent to the second side surface 82B of the transistor 80 in a plan view of the substrate 50A. Therefore, the third side surface 82C of the transistor 80 is located between the first capacitor module 110 and the second capacitor module 120. The light-emitting element 60 is disposed adjacent to the third side surface 82C of the transistor 80 and is electrically connected to the transistor 80 by multiple wires 190. This configuration allows the transistor 80 to be disposed close to the light-emitting element 60. This shortens the length of the wires 190, thereby shortening the wiring path through which current flows from the transistor 80 to the light-emitting element 60, thereby reducing parasitic inductance occurring in the wiring path.

[0108] (1-5) The first capacitor module 110 and the second capacitor module 120 are arranged symmetrically with respect to the light-emitting element 60 and the transistor 80. As a result, a first wiring path through which a current flows from the first capacitor module 110 to the light-emitting element 60 via the transistor 80 and the wire 190, and a second wiring path through which a current flows from the second capacitor module 120 to the light-emitting element 60 via the transistor 80 and the wire 190, are arranged symmetrically with respect to the light-emitting element 60 and the transistor 80. In this arrangement, the magnetic flux formed by the current flowing through the first wiring path and the magnetic flux formed by the current flowing through the second wiring path cancel each other out. This makes it possible to reduce the parasitic inductance present in the first wiring path and the parasitic inductance present in the second wiring path.

[0109] (1-6) The light-emitting element drive circuit 70 supplies current to the light-emitting element 60 using the first capacitor module 110 and the second capacitor module 120. In this configuration, the current supplied to the light-emitting element 60 can be increased.

[0110] (1-7) The third side surface 82C of the transistor 80 is shorter than the first side surface 82A and the second side surface 82B of the transistor 80. Furthermore, the distance between the first capacitor module 110 and the second capacitor module 120 is greater than the length of the third side surface 82C of the transistor 80. With this configuration, the short side (third side surface 82C) of the transistor 80 is located between the first and second capacitor modules 110 and 120. This shortens the wiring paths through which current flows from the first and second capacitor modules 110 and 120 to the light-emitting element 60 via the transistor 80, thereby reducing the parasitic inductance occurring in each wiring path.

[0111] (1-8) The number of wires 190 connecting the transistor 80 and the light-emitting element 60 is greater than the number of wires 152A, 152B connecting the transistor 80 and the lead pins 142A, 142B. This makes it easier for current to flow from the transistor 80 to the light-emitting element 60, thereby reducing parasitic inductance.

[0112] (1-9) The first via wiring 242 is arranged only in the first wiring region 312 (light-emitting element mounting region) directly below the light-emitting element 60. The first via wiring 242 is part of a wiring path connecting the cathode electrode 68 of the light-emitting element 60 to the external element connection pad 160, and electrically connects the first front-surface side wiring 310 and the first back-surface side wiring 410. Here, if multiple first via wirings 242 were arranged outside the first wiring region 312, the flow of current from the cathode electrode 68 of the light-emitting element 60 to the first connection electrodes 113, 123 of the first and second capacitor modules 110, 120 via the first front-surface side wiring 310 may be obstructed. As a result, increasing the number of first via wirings 242 obstructs the flow of current from the second connection electrodes 114, 124 of the first and second capacitor modules 110, 120 to the light-emitting element 60 via the transistor 80 and the wire 190. In the first embodiment, only one first via wiring 242 is arranged in the first wiring region 312 directly below the light emitting element 60. Therefore, the first via wiring 242 is prevented from interfering with the flow of current to the light emitting element 60.

[0113] (Modifications of the First Embodiment) The above-described first embodiment can be modified, for example, as follows. The above-described embodiment and each of the following modifications can be combined with each other as long as no technical contradiction occurs. In the following modifications, parts common to the above-described embodiment will be assigned the same reference numerals as in the above-described embodiment, and their description will be omitted.

[0114] The configurations of the first and second capacitor modules 110, 120 may be modified as appropriate. Figures 14 to 16 are cross-sectional views of a light-emitting module including a modified capacitor module 110A, taken along a line corresponding to that of Figure 11 of the first embodiment.

[0115] 14 , the capacitor module 110A includes a silicon substrate 116, a first connection electrode 113, a second connection electrode 114, a counter electrode 117, and a connection portion 118. The first connection electrode 113 includes an electrode 113A provided on the first main surface 112A, a second counter electrode 113B provided on the second surface 116B of the silicon substrate 116, and a via wiring 113C connecting the electrode 113A and the second counter electrode 113B. This capacitor module 110A can reduce parasitic inductance, similar to the first embodiment.

[0116] 15 , in the capacitor module 110B, the sealing resin 119 has a first opening 119B exposing a portion of the counter electrode 117 and a plurality of second openings 119C exposing a portion of the second connection electrode 114. The first wiring 118A and the second wiring 118B of the connection portion 118 are continuously formed along the upper surface of the sealing resin 119. That is, the first wiring 118A is formed by a conductive film formed on the first surface 119D of the sealing resin 119 and the inner wall surfaces of the first openings 119B. The second wiring 118B is formed by a conductive film formed on the inner wall surfaces of the plurality of second openings 119C of the sealing resin 119. This capacitor module 110B can reduce parasitic inductance, as in the first embodiment.

[0117] 16, the capacitor module 110C includes a silicon substrate 116, a first connection electrode 113, a second connection electrode 114, and a connection portion 118. This capacitor module 110C does not include the sealing resin 119 shown in FIG.

[0118] The first connection electrode 113 and the second connection electrode 114 are disposed on a first surface 116A of the silicon substrate 116, spaced apart in the longitudinal direction of the silicon substrate 116. The connection portion 118 includes an opposing electrode 117 provided on a second surface 116B of the silicon substrate 116 and facing the first connection electrode 113. The silicon substrate 116 has a plurality of through holes 116C penetrating the silicon substrate 116 from the first surface 116A to the second surface 116B. The connection portion 118 includes a first wiring 118A formed on the second surface 116B of the silicon substrate 116 and a second wiring 118B formed in the plurality of through holes 116C and connecting the first wiring 118A and the second connection electrode 114. The second wiring 118B is a through wiring that penetrates the silicon substrate 116. This capacitor module 110C can reduce parasitic inductance, as in the first embodiment.

[0119] The configuration of the substrate 50A may be modified as appropriate. Figures 17 to 21 show a modified light-emitting module 30A1, which uses a modified substrate 50A1. Figures 18 to 20 are cross-sectional views showing the internal wiring structure of the substrate 50A1. Figure 21 is a cross-sectional view of Figure 17 taken along line 21-21 in Figure 18.

[0120] 17 to 21, the substrate 50A1 of the light-emitting module 30A1 is, for example, a printed wiring board, and in this modification, has a three-layer wiring structure as an internal wiring structure. In other words, the substrate 50A1 of this modification is a multi-layer substrate.

[0121] The substrate 50A1 includes an insulating first base material 210A, a first wiring layer 220 provided on a front surface 214A of the first base material 210A, an insulating second base material 210B, and a second wiring layer 230 provided on a back surface 216B of the second base material 210B. The substrate 50A1 also includes an intermediate wiring layer 240 provided on the back surface 214B of the first base material 210A and on the front surface 216A of the second base material 210B.

[0122] That is, in this modified example, the base material 210 of the first embodiment is divided into a first base material 210A and a second base material 210B, and the intermediate wiring layer 240 is located between the first base material 210A and the second base material 210B. Therefore, it can be said that the substrate 50A1 of this modified example has a configuration in which the intermediate wiring layer 240 is located inside the base material 210 of the first embodiment. The intermediate wiring layer 240, like the first and second wiring layers 220, 230, is formed of a metal material such as Cu.

[0123] The first substrate 210A and the second substrate 210B are formed of an insulating material such as a resin substrate, a silicon substrate, a glass substrate, a ceramic substrate, etc. In this modification, resin substrates made of glass epoxy resin are used as the first substrate 210A and the second substrate 210B.

[0124] The configurations of the first wiring layer 220 and the second wiring layer 230 are the same as those in the first embodiment. Therefore, as shown in Fig. 18 , the first wiring layer 220 includes first to third surface-side wirings 310, 320, and 330. The first surface-side wiring 310 includes first to third wiring regions 312, 314, and 316, the second surface-side wiring 320 includes fourth to sixth wiring regions 322, 324, and 326, and the third surface-side wiring 330 includes a seventh wiring region 332. Furthermore, as shown in Fig. 20 , the second wiring layer 230 includes first and second back-side wirings 410 and 420, and the second back-side wiring 420 includes an eighth wiring region 414.

[0125] 19 , the intermediate wiring layer 240 includes a first intermediate wiring 510, a second intermediate wiring 520, and a third intermediate wiring 530. The first intermediate wiring 510 is arranged along the first, second, and third side surfaces 52A, 52B, and 52C of the substrate 50A1, and is formed, for example, with a size that is approximately one-third the area of ​​the substrate 50A1. The first intermediate wiring 510 overlaps the first front-surface-side wiring 310 and the first back-surface-side wiring 410 in a plan view of the substrate 50A1.

[0126] The second intermediate wiring 520 is arranged along the first, second, and fourth side surfaces 52A, 52B, and 52D of the substrate 50A1 and is arranged at a distance from the first intermediate wiring 510. The second intermediate wiring 520 is formed, for example, to have a size slightly smaller than approximately two-thirds the area of ​​the substrate 50A1. In this modification, the second intermediate wiring 520 is formed, for example, to have the same size and shape as the first surface-side wiring 310 and includes a notch 522 at the same position as the first surface-side wiring 310 in a plan view of the substrate 50A1. The second intermediate wiring 520 overlaps with the second surface-side wiring 320 and the second back-side wiring 420 and also partially overlaps with the first back-side wiring 410 in a plan view of the substrate 50A1.

[0127] The third intermediate wiring 530 is arranged along the first and fourth side surfaces 52A and 52D of the substrate 50A1 and is spaced apart from the second intermediate wiring 520. In this modification, the third intermediate wiring 530 is formed, for example, with the same size and shape as the third surface-side wiring 330 and is arranged adjacent to (but spaced apart from) the notch 522 of the second intermediate wiring 520. The total area of ​​the second intermediate wiring 520 and the third intermediate wiring 530 corresponds to approximately two-thirds of the area of ​​the substrate 50A1. In other words, the second intermediate wiring 520 and the third intermediate wiring 530 are spaced apart from each other so that their combined shape forms a rectangle having a size approximately two-thirds the area of ​​the substrate 50A1. The third intermediate wiring 530 overlaps the third surface-side wiring 330 and the first back-surface-side wiring 410 in a plan view of the substrate 50A1.

[0128] Similar to the first embodiment, the substrate 50A1 includes a first insulating layer 250 and a second insulating layer 260. The configurations of the first insulating layer 250 and the second insulating layer 260 are similar to those of the first embodiment, and detailed description thereof will be omitted.

[0129] 17 to 21 , similar to the first embodiment, the substrate 50A1 includes first to third via wirings 242, 244, 246 that penetrate the first and second base materials 210A and 210B and electrically connect the first wiring layer 220 and the second wiring layer 230. In this modified example, the first via wiring 242 electrically connects the first surface-side wiring 310, the first intermediate wiring 510, and the first back-side wiring 410. The second via wiring 244 electrically connects the second surface-side wiring 320, the second intermediate wiring 520, and the second back-side wiring 420. The third via wiring 246 electrically connects the third surface-side wiring 330, the third intermediate wiring 530, and the first back-side wiring 410.

[0130] 17 and 19 to 21 , the substrate 50A1 further includes a plurality of (for example, four) fourth via wirings 248 that electrically connect the first intermediate wiring 510 and the first back-surface-side wiring 410. The fourth via wirings 248 are formed of a metal material such as Cu. The arrangement of the fourth via wirings 248 is not particularly limited. For example, the fourth via wirings 248 are evenly arranged within the first intermediate wiring 510 except for the positions of the first via wirings 242. In this modification, for example, the fourth via wirings 248 are arranged in a row together with the first via wirings 242.

[0131] In the substrate 50A1 of this modified example, the light emitting element 60 is small. Therefore, the area of ​​the first wiring region 312 (light emitting element mounting region) where the light emitting element 60 is mounted is small. Therefore, the number of first via wirings 242 that can be arranged within the first wiring region 312 is limited. As in the first embodiment, in this modified example, only one first via wiring 242 is arranged in the first wiring region 312 directly below the light emitting element 60. Therefore, similar to the advantage (1-9) obtained in the first embodiment described above, in this modified example, the first via wiring 242 is prevented from interfering with the flow of current to the light emitting element 60. In this modified example, the first via wiring 242 electrically connects the first front-surface side wiring 310, the first intermediate wiring 510, and the first back-surface side wiring 410. This first via wiring 242 is also used as a heat dissipation path. However, if there is only one first via wiring 242, sufficient heat dissipation using the first via wiring 242 may not be achieved. In this modified example, the substrate 50A1 of the light-emitting module 30A1 includes a plurality of (for example, four) fourth via wirings 248 that connect the first intermediate wiring 510 and the first back-surface-side wiring 410. These fourth via wirings 248 do not obstruct the flow of current to the light-emitting element 60 as described above, and can improve heat dissipation.

[0132] Second Embodiment The configuration of a semiconductor light emitting device 10B according to a second embodiment will be described below. Note that, in the semiconductor light emitting device 10B according to the second embodiment, components common to the semiconductor light emitting device 10A according to the first embodiment will be denoted by the same reference numerals.

[0133] FIG. 22 is a perspective view schematically illustrating an exemplary semiconductor light-emitting device 10B according to the second embodiment. FIG. 23 is a plan view schematically illustrating the semiconductor light-emitting device of FIG. 22. FIG. 24 is a plan view showing the internal wiring structure of the substrate of the light-emitting module of FIG. 22. FIG. 25 is a plan view showing the internal wiring structure of the substrate of the light-emitting module of FIG. 22. FIG. 26 is a cross-sectional view taken along line 26-26 in FIG. 23. FIG. 27 is a cross-sectional view taken along line 27-27 in FIG. 23. For ease of explanation, the sealing resin 90 is omitted from FIG. 23. In FIGS. 26 and 27, the sealing resin 90 is indicated by a two-dot chain line. For ease of explanation, the wires 190, 152A, and 152B are omitted from FIGS. 26 and 27.

[0134] The semiconductor light emitting device 10B of the second embodiment is a surface-mount type device. Therefore, it does not have the stem 20 and the like of the semiconductor light emitting device 10A of the first embodiment. The semiconductor light emitting device 10B of the second embodiment also differs from the semiconductor light emitting device 10A of the first embodiment in that the configuration of the substrate 50B is different and that it includes a sealing resin 90. These points will be described in detail below.

[0135] 22, the semiconductor light emitting device 10B has a generally rectangular flat plate shape. The semiconductor light emitting device 10B includes a light emitting module 30B and a sealing resin 90. The light emitting module 30B includes a substrate 50B, a light emitting element 60, and a light emitting element drive circuit 70.

[0136] 23 to 27, the substrate 50B has a rectangular shape. The size of the substrate 50B is not particularly limited. In the substrate 50B of the second embodiment, the first side surface 52A and the second side surface 52B have a rectangular shape that is longer than the third side surface 52C and the fourth side surface 52D.

[0137] As shown in FIG. 24 , the first wiring layer 220 includes a plurality of wirings provided on the surface 212A of the base material 210 and spaced apart from one another, and in the second embodiment, includes a first surface-side wiring 310, a second surface-side wiring 320, a third surface-side wiring 340, and a fourth surface-side wiring 350.

[0138] The first surface-side wiring 310 is arranged along the first, second, and third side surfaces 52A, 52B, and 52C of the substrate 50B, and is formed, for example, with a size of approximately one-third the area of ​​the substrate 50B. The first surface-side wiring 310 includes first to third wiring regions 312, 314, and 316. Note that the first to third wiring regions 312, 314, and 316 are each part of the first surface-side wiring 310, and the first surface-side wiring 310 does not necessarily have physical boundaries between the first to third wiring regions 312, 314, and 316.

[0139] The first wiring region 312 is a light-emitting element mounting region where the cathode electrode 68 of the light-emitting element 60 is mounted. The second wiring region 314 is a part of the first capacitor mounting region where the second connection electrode 114 of the first capacitor module 110 is mounted. The third wiring region 316 is a part of the second capacitor mounting region where the second connection electrode 124 of the second capacitor module 120 is mounted. Therefore, the cathode electrode 68 of the light-emitting element 60 is electrically connected to the second connection electrodes 114, 124 of the first and second capacitor modules 110, 120 via the first surface-side wiring 310. The second wiring region 314 and the third wiring region 316 are arranged symmetrically with respect to the first wiring region 312.

[0140] The second surface-side wiring 320 is disposed in the central portion of the substrate 50B, i.e., in the central portion between the third side surface 52C and the fourth side surface 52D of the substrate 50B. The second surface-side wiring 320 is disposed along the first and second side surfaces 52A and 52B of the substrate 50B and is disposed at a distance from the first surface-side wiring 310. The second surface-side wiring 320 is formed, for example, with a size slightly larger than approximately half the area of ​​the substrate 50B. The second surface-side wiring 320 includes fourth to sixth wiring regions 322, 324, and 326. Note that the fourth to sixth wiring regions 322, 324, and 326 are each part of the second surface-side wiring 320, and physical boundaries between the fourth to sixth wiring regions 322, 324, and 326 do not exist in the second surface-side wiring 320.

[0141] The fourth wiring region 322 is a transistor mounting region where the drain electrode 88 of the transistor 80 is mounted. The fifth wiring region 324 is a part of the first capacitor mounting region where the second connection electrode 114 of the first capacitor module 110 is mounted. The sixth wiring region 326 is a part of the second capacitor mounting region where the second connection electrode 124 of the second capacitor module 120 is mounted. Therefore, the drain electrode 88 of the transistor 80 is electrically connected to the second connection electrodes 114, 124 of the first and second capacitor modules 110, 120 via the second surface side wiring 320. The fifth wiring region 324 and the sixth wiring region 326 are arranged symmetrically with respect to the fourth wiring region 322.

[0142] The third surface-side wiring 340 and the fourth surface-side wiring 350 are arranged side by side and spaced apart from each other along the fourth side surface 52D of the substrate 50B. The third surface-side wiring 340 is arranged along the first and fourth side surfaces 52A and 52D of the substrate 50B and spaced apart from the second surface-side wiring 320. The third surface-side wiring 340 includes a seventh wiring region 342. Note that the seventh wiring region 342 is a part of the third surface-side wiring 340, and the physical boundary of the seventh wiring region 342 does not exist on the third surface-side wiring 340. In the seventh wiring region 342, a connection pad 162 (see FIGS. 23, 26, and 27) is arranged. Note that in the second embodiment, the gate electrode 86 of the transistor 80 is connected to the seventh wiring region 342 (connection pad 162) via a wire 152B (see FIG. 23).

[0143] The fourth surface-side wiring 350 is arranged along the second and fourth side surfaces 52B, 52D of the substrate 50B and is arranged spaced apart from the second surface-side wiring 320. The fourth surface-side wiring 350 includes an eighth wiring region 352. Note that the eighth wiring region 352 is part of the fourth surface-side wiring 350, and the physical boundary of the eighth wiring region 352 does not exist on the fourth surface-side wiring 350. A connection pad 164 (see FIG. 23 ) is arranged in the eighth wiring region 352. Note that in the second embodiment, the source electrode 84 of the transistor 80 is connected to the eighth wiring region 352 (connection pad 164) via a wire 152A (see FIG. 23 ).

[0144] The first insulating layer 250 includes first to eighth openings 251 to 258 (see FIG. 23) that expose the first to eighth wiring regions 312, 314, 316, 322, 324, 326, 342, and 352 of the first to fourth surface side wirings 310, 320, 340, and 350, respectively.

[0145] A first metal plating material 362 (see FIGS. 23, 26, and 27) is provided on the first to sixth wiring regions 312, 314, 316, 322, 324, and 326 exposed through the first to sixth openings 251 to 256 of the first insulating layer 250. The first metal plating material 362 may be, for example, a laminate containing Ni and gold (Au), or a laminate containing Ni, Pd, and Au. As shown in FIG. 26, the cathode electrode 68 of the light-emitting element 60 is bonded to the first metal plating material 362 in the first wiring region 312 (light-emitting element mounting region) by a bonding member (not shown). The drain electrode 88 of the transistor 80 is bonded to the first metal plating material 362 in the fourth wiring region 322 (transistor mounting region) by a bonding member (not shown). 27 , the first and second connection electrodes 113, 114 of the first capacitor module 110 are bonded to the first metal plated material 362 in the fifth and second wiring regions 324, 314 (first capacitor mounting regions) by bonding members (not shown). Although a cross-sectional view is omitted, similar to the first capacitor module 110, the first and second connection electrodes 123, 124 of the second capacitor module 120 are bonded to the first metal plated material 362 in the sixth and third wiring regions 326, 316 (second capacitor mounting regions) by bonding members (not shown). The bonding material may be Ag paste or a solder paste containing Su—Ag—Cu. The bonding material may be changed depending on the material to be bonded to the first metal plated material 362. For example, Ag paste may be used to bond the light-emitting element 60. Furthermore, the transistor 80 and the first and second capacitor modules 110 and 120 can be joined using a solder paste material or an Ag paste material.

[0146] The seventh and eighth wiring regions 342, 352 exposed from the seventh and eighth openings 257, 258 of the first insulating layer 250 are provided with the above-mentioned connection pads 162, 164 (FIGS. 23 and 27). These connection pads 162, 164 are formed of a second metal plating material. As the second metal plating material, a laminate containing Ni and Au, or a laminate containing Ni, Pd, and Au can be used.

[0147] Fig. 25 is a plan view showing the second wiring layer 230 and the second insulating layer 260. Note that the first insulating layer 250, the first wiring layer 220, and the base material 210 are not shown in Fig. 25.

[0148] As shown in FIG. 25 , the second wiring layer 230 includes a plurality of wirings provided on the rear surface 212B (see FIG. 23 ) of the base material 210 and arranged at a distance from each other, and in the second embodiment, includes a first rear surface side wiring 410, a second rear surface side wiring 420, a third rear surface side wiring 430, and a fourth rear surface side wiring 440.

[0149] The first back surface side wiring 410 is arranged along the first, second, and third side surfaces 52A, 52B, and 52C of the substrate 50B. The first back surface side wiring 410 is formed in a rectangular shape extending along the third side surface 52C. The first back surface side wiring 410 includes a first wiring region 412. Note that the first wiring region 412 is a part of the first back surface side wiring 410, and the physical boundary of the first wiring region 412 does not exist in the first back surface side wiring 410. The first back surface side wiring 410 overlaps with the first front surface side wiring 310 shown in FIG. 24 in a plan view of the substrate 50B.

[0150] The second back surface side wiring 420 is disposed in the central portion of the substrate 50B, i.e., in the central portion between the third side surface 52C and the fourth side surface 52D of the substrate 50B. The second back surface side wiring 420 is disposed along the first and second side surfaces 52A and 52B of the substrate 50B and is disposed at a distance from the first back surface side wiring 410. The second back surface side wiring 420 is formed to have the same size as the second surface side wiring 320 shown in FIG. 24, for example. The second back surface side wiring 420 includes a second wiring region 422. The second back surface side wiring 420 overlaps with the second surface side wiring 320 shown in FIG. 24 in a plan view of the substrate 50B.

[0151] The third back-surface-side wiring 430 and the fourth back-surface-side wiring 440 are arranged side by side along the fourth side surface 52D of the substrate 50B and are spaced apart from each other. The third back-surface-side wiring 430 is arranged along the first and fourth side surfaces 52A, 52D of the substrate 50B and is spaced apart from the second back-surface-side wiring 420. The third back-surface-side wiring 430 includes a third wiring region 432. Note that the third wiring region 432 is a part of the third back-surface-side wiring 430, and the physical boundary of the third wiring region 432 does not exist on the third back-surface-side wiring 430. The third back-surface-side wiring 430 overlaps with the third front-surface-side wiring 340 in a plan view of the substrate 50B.

[0152] The fourth back-surface-side wiring 440 is arranged along the second and fourth side surfaces 52B, 52D of the substrate 50B and is arranged spaced apart from the second back-surface-side wiring 420. The fourth back-surface-side wiring 440 includes a fourth wiring region 442. Note that the fourth wiring region 442 is a part of the fourth back-surface-side wiring 440, and the physical boundary of the fourth wiring region 442 does not exist on the fourth back-surface-side wiring 440. The fourth back-surface-side wiring 440 overlaps with the fourth front-surface-side wiring 350 in a plan view of the substrate 50B.

[0153] The second insulating layer 260 includes first to fourth openings 261 to 264 that expose first to fourth wiring regions 412, 422, 432, and 442 of the first to fourth back-surface-side wirings 410, 420, 430, and 440, respectively. As shown in FIGS. 26 and 27 , the first to third wiring regions 412, 422, and 432 exposed from the first to third openings 261 to 263 of the second insulating layer 260 are provided with a third metal plating material 364. Although not shown, the fourth wiring region 442 exposed from the fourth opening 264 shown in FIG. 25 is provided with the third metal plating material 364, similar to the third wiring region 432. The third metal plating material 364 of the first to fourth wiring regions 412, 422, 432, and 442 is bonded to pads of the drive substrate by a bonding material (not shown). Therefore, the first to fourth rear-surface-side wirings 410, 420, 430, 440 and the third metal plating material 364 constitute the mounting electrodes of the semiconductor light-emitting device 10B. A laminate containing Ni and Au, or a laminate containing Ni, Pd, and Au can be used as the third metal plating material 364. A solder paste material containing Su-Ag-Cu, for example, can be used as the bonding material.

[0154] 23 to 27 , the first wiring layer 220 and the second wiring layer 230 are electrically connected by the first to fourth via wirings 242, 244, 246, and 248 that penetrate the base material 210. In the second embodiment, the via wirings 242, 244, 246, and 248 are formed, for example, in a cylindrical shape, but the shape is not particularly limited. These via wirings 242, 244, 246, and 248 are so-called thermal vias, and function as a conductive path between the first wiring layer 220 and the second wiring layer 230, as well as a heat dissipation path from the first wiring layer 220 to the second wiring layer 230.

[0155] The first via wiring 242 is located in the first wiring region 312 (light-emitting element mounting region) and electrically connects the first front surface side wiring 310 and the first back surface side wiring 410. Therefore, the cathode electrode 68 of the light-emitting element 60 and the first connection electrodes 113, 123 of the first and second capacitor modules 110, 120 are electrically connected to the first back surface side wiring 410 via the first front surface side wiring 310 and the first via wiring 242.

[0156] The second via wiring 244 is located in the fourth wiring region 322 (transistor mounting region) and electrically connects the second surface side wiring 320 and the second back surface side wiring 420. Therefore, the drain electrode 88 of the transistor 80 is electrically connected to the second back surface side wiring 420 via the second surface side wiring 320 and the second via wiring 244. The drain electrode 88 of the transistor 80 is also electrically connected to the second connection electrodes 114, 124 of the first and second capacitor modules 110, 120 via the second surface side wiring 320. The arrangement of the second via wiring 244 is not particularly limited. For example, the second via wiring 244 is evenly arranged within the fourth and second wiring regions 322, 422. In the second embodiment, the second via wiring 244 is arranged in a 2×3 array, for example.

[0157] The third via wiring 246 electrically connects the third front-surface-side wiring 340 and the third back-surface-side wiring 430. Therefore, the gate electrode 86 of the transistor 80 is electrically connected to the third back-surface-side wiring 430 via the wire 152B, the third front-surface-side wiring 340, and the third via wiring 246 shown in FIG. 23 . The arrangement of the third via wiring 246 is not particularly limited. For example, two third via wirings 246 are arranged side by side along the fourth side surface 52D of the substrate 50B.

[0158] The fourth via wiring 248 electrically connects the fourth front surface side wiring 350 and the fourth back surface side wiring 440. Therefore, the source electrode 84 of the transistor 80 is electrically connected to the fourth back surface side wiring 440 via the wire 152A, the fourth front surface side wiring 350, and the fourth via wiring 248 shown in FIG. 23 . The arrangement of the fourth via wiring 248 is not particularly limited. For example, two fourth via wirings 248 are arranged side by side along the fourth side surface 52D of the substrate 50B.

[0159] 22, 26, and 27, the sealing resin 90 is formed to cover the surface of the substrate 50B. The sealing resin 90 seals the light-emitting element 60, the transistor 80, the first and second capacitor modules 110 and 120, and the wires 190, 152A, and 152B (see FIG. 23) mounted on the surface of the substrate 50B. The sealing resin 90 is made of a translucent resin material. This resin material may be an epoxy resin, an acrylic resin, or the like.

[0160] (Effects) According to the semiconductor light emitting device 10B of the second embodiment, the following effects can be obtained: (2-1) The effects (1-1) to (1-7) and (1-9) of the semiconductor light emitting device 10A of the first embodiment can be obtained.

[0161] (2-2) The semiconductor light emitting device 10B of the second embodiment is a surface-mounted light emitting module, and can therefore be mounted on a circuit board in the same manner as the circuit elements that make up the gate driver 908 shown in FIG.

[0162] (Modifications) The above embodiment can be modified as follows: Furthermore, the above embodiment and the following modifications can be combined with each other within the scope of technical compatibility.

[0163] The first connection electrodes 113 and 123 of the first and second capacitor modules 110 and 120 may be mounted on the substrates 50A and 50B so as to be electrically connected to the drain electrode 88 of the transistor 80 .

[0164] In the first embodiment, the number of lead pins 142D fixed to the rear surface 22B of the base 22 and electrically connected to the heat sink 24 is not limited to one. Instead of the first and second capacitor modules 110, 120, one or three or more capacitor modules may be used.

[0165] The number of second via wirings 244 is not limited to six and can be any other number. In other words, the number of second via wirings 244 can be one or more. The number of fourth via wirings 248 is not limited to four and can be any other number. In other words, the number of second via wirings 248 can be one or more.

[0166] The number of intermediate wiring layers 240 is not limited to one. Multiple intermediate wiring layers 240 may be interposed inside the base material 210. A protection diode (e.g., SBD 906) connected in anti-parallel to the light-emitting element 60 may be mounted on the light-emitting module 30A (e.g., substrate 50A). By integrating the SBD 906 provided on the drive substrate 910 into the light-emitting module 30A, the drive substrate 910 can be made smaller, thereby reducing the size of the entire system.

[0167] The gate driver 908 that controls the driving of the transistor 80 may be mounted on the light-emitting module 30A (for example, the substrate 50A). By integrating the gate driver 908 provided on the drive substrate 910 into the light-emitting module 30A, the drive substrate 910 can be made smaller, thereby reducing the size of the entire system.

[0168] As used herein, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B." The term "on" as used in this disclosure includes both the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, the expression "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be placed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be placed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0169] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0170] (Supplementary Notes) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the Supplementary Notes are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples to aid understanding, and the components described in each Supplementary Note should not be limited to the components indicated by the reference symbols.

[0171] (Supplementary Note 1) A capacitor module (110, 120) mounted on the substrate (50A, 50B) and having a main surface (112A, 122A) facing the substrate (50A, 50B) in the thickness direction (Y) of the substrate (50A, 50B), and a first connection electrode (113, 123) and a second connection electrode (114, 124) provided on the main surface (112A, 122A), the capacitor module (110, 120) being electrically connected to the light-emitting element (60), wherein the capacitor module (110, 120) comprises: a silicon substrate (116, 126) having a first surface and a second surface facing opposite to each other; A semiconductor light emitting device comprising: a first connection electrode (113, 123) provided on the first surface; and a counter electrode (117, 127) provided on the second surface and facing the first connection electrode (113, 123).

[0172] (Supplementary Note 2) The semiconductor light emitting device according to Supplementary Note 1, wherein the first connection electrodes (113, 123) and the second connection electrodes (114, 124) are arranged apart from each other in a direction parallel to the main surfaces (112A, 122A).

[0173] (Supplementary Note 3) The semiconductor light emitting device according to Supplementary Note 1 or Supplementary Note 2, wherein the capacitor module (110, 120) includes a connection portion (118, 128) that connects the counter electrode (117, 127) to the second connection electrode (114, 124).

[0174] (Appendix 4) The semiconductor light-emitting device according to Appendix 3, wherein the connection portion (118, 128) includes a first wiring (118A, 128A) connected to the counter electrode (117, 127) and a second wiring (118B, 128B) connecting the first wiring (118A, 128A) to the second connection electrode (114, 124).

[0175] (Supplementary Note 5) The semiconductor light emitting device according to Supplementary Note 4, wherein a plurality of the second wirings (118B, 128B) are provided.

[0176] (Supplementary Note 6) The semiconductor light emitting device according to Supplementary Note 4 or Supplementary Note 5, wherein the second wiring (118B, 128B) is a through wiring that penetrates the silicon substrate (116, 126).

[0177] (Supplementary Note 7) The semiconductor light emitting device according to any one of Supplementary Note 4 to Supplementary Note 6, wherein the capacitor module (110, 120) includes a sealing resin (119, 129) that seals the silicon substrate (116, 126).

[0178] (Supplementary Note 8) The semiconductor light emitting device according to Supplementary Note 7, wherein the second wiring (118B, 128B) is a via wiring provided in an opening formed in the sealing resin (119, 129).

[0179] (Supplementary Note 9) The semiconductor light emitting device according to any one of Supplementary Note 1 to Supplementary Note 8, wherein the thickness of the capacitor module (110, 120) is equal to or less than the thickness of the transistor (80).

[0180] (Supplementary Note 10) The semiconductor light emitting device according to any one of Supplementary Note 1 to Supplementary Note 9, wherein the transistor (80) is a vertical MOSEFT.

[0181] (Supplementary Note 11) The semiconductor light emitting device according to any one of Supplementary Note 1 to Supplementary Note 10, wherein two capacitor modules (110, 120) are mounted on the substrate (50A, 50B).

[0182] (Supplementary Note 12) The semiconductor light emitting device according to any one of Supplementary Note 1 to Supplementary Note 11, further comprising a protection diode mounted on the substrate (50A, 50B) and connected to the light emitting element (60).

[0183] (Supplementary Note 13) The semiconductor light-emitting device according to any one of Supplementary Note 1 to Supplementary Note 12, wherein the substrate (50A, 50B) is a resin substrate, a silicon substrate, a glass substrate, or a ceramic substrate.

[0184] (Supplementary Note 14) The semiconductor light emitting device according to any one of Supplementary Note 1 to Supplementary Note 13, wherein the substrate (50A, 50B) is a double-sided substrate or a multi-layer substrate.

[0185] (Appendix 15) A semiconductor light emitting device according to any one of appendices 1 to 14, comprising: a stem (20) including a conductive base (22) and a conductive heat sink (24) on which the substrates (50A, 50B) are mounted; and a plurality of lead pins (142A to 142D) provided on the base (22).

[0186] (Appendix 16) The semiconductor light-emitting device according to any one of appendices 1 to 15, wherein the substrate (50A, 50B) includes a mounting electrode provided on a surface opposite to a surface on which the light-emitting element (60) is mounted.

[0187] (Supplementary Note 17) The semiconductor light emitting device according to Supplementary Note 16, further comprising a light-transmitting sealing resin (90) that covers the light emitting element (60) together with the surface on which the light emitting element (60) is mounted.

[0188] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0189] 10A, 10B Semiconductor light emitting device 20 Stem 22 Base 24 Heat sink 30A, 30A1, 30B Light emitting module 40 Surrounding member 42 Storage space 50A, 50A1, 50B Substrate 60 Light emitting element 66 Anode electrode 68 Cathode electrode 70 Light emitting element drive circuit 80 Transistor 84 Source electrode 86 Gate electrode 88 Drain electrode 90 Sealing resin 110 First capacitor module 110A to 110C Capacitor module 111A First side surface 111B Second side surface 111C Third side surface 111D Fourth side surface 112A First main surface 112B Second main surface 113 First connection electrode 113A Electrode 113B Second opposing electrode 113C Via wiring 114 Second connection electrode 115 Silicon capacitor 116 Silicon substrate 116A First surface 116B Second surface 116C Through hole 117 Counter electrode 118 Connection portion 118A First wiring 118B Second wiring 119 Sealing resin 119A Opening 119B First opening 119C Second opening 119D First surface 120 Second capacitor module 121A First side surface 121B Second side surface 121C Third side surface 121D Fourth side surface 122A First main surface 122B Second main surface 123 First connection electrode 124 Second connection electrode 125 Silicon capacitor 126 Silicon substrate 127 Counter electrode 128 Connection portion 128A First wiring 128B Second wiring 129 Sealing resin 142A to 142D Lead pin 144 Insulating material 152A to 152C Wires 160 External element connection pads 162 Connection pads 164 Connection pads 190,191 Wire 210 Base material 210A First base material 210B Second base material 220 First wiring layer 230 Second wiring layer 240 Intermediate wiring layer 242 First via wiring 244 Second via wiring 246 Third via wiring 248 Fourth via wiring 250 First insulating layer 260 Second insulating layer 310 First surface side wiring 320 Second surface side wiring 330 Third surface side wiring 340 Third surface side wiring 350 Fourth surface side wiring 362 First metal plated material 364 Third metal plated material 410 First back surface side wiring 420 Second back surface side wiring 430 Third back surface side wiring 440 Fourth back surface side wiring 530 Third intermediate wiring 902 Resistive element 904 Constant voltage source 906 Schottky barrier diode (SBD) 908 Gate driver 910 Drive board

Claims

1. A substrate; A light emitting element mounted on the substrate; a transistor mounted on the substrate and configured to drive the light emitting element; a capacitor module mounted on the substrate, the capacitor module having a main surface facing the substrate in a thickness direction of the substrate, and a first connection electrode and a second connection electrode provided on the main surface, the capacitor module being electrically connected to the light-emitting element; Equipped with The capacitor module includes: a silicon substrate having a first surface and a second surface facing in opposite directions; The first connection electrode provided on the first surface; a counter electrode provided on the second surface and facing the first connection electrode; Including, Semiconductor light emitting device.

2. The semiconductor light emitting device according to claim 1 , wherein the first connection electrode and the second connection electrode are spaced apart in a direction parallel to the main surface.

3. The semiconductor light emitting device according to claim 1 , wherein the capacitor module includes a connection portion that connects the counter electrode to the second connection electrode.

4. The semiconductor light emitting device according to claim 3 , wherein the connection portion includes a first wiring connected to the counter electrode, and a second wiring connecting the first wiring to the second connection electrode.

5. The semiconductor light emitting device according to claim 4 , wherein the second wiring is provided in a plurality of parts.

6. The semiconductor light emitting device according to claim 4 , wherein the second wiring is a through wiring that penetrates the silicon substrate.

7. The capacitor module includes a sealing resin that seals the silicon substrate. The semiconductor light emitting device of claim 4 , further comprising a grease.

8. The semiconductor light emitting device according to claim 7 , wherein the second wiring is a via wiring provided in an opening formed in the sealing resin.

9. The semiconductor light emitting device according to claim 1 , wherein the thickness of the capacitor module is equal to or smaller than the thickness of the transistor.

10. 2. The semiconductor light emitting device according to claim 1, wherein the transistor is a vertical MOSFET.

11. The semiconductor light emitting device according to claim 1 , wherein two capacitor modules are mounted on the substrate.

12. The semiconductor light emitting device according to claim 1 , further comprising a protection diode mounted on the substrate and connected to the light emitting element.

13. 2. The semiconductor light emitting device according to claim 1, wherein the substrate is a resin substrate, a silicon substrate, a glass substrate, or a ceramic substrate.

14. The semiconductor light emitting device according to claim 1 , wherein the substrate is a double-sided substrate or a multi-layer substrate.

15. a stem including a conductive base and a conductive heat sink on which the substrate is mounted; A plurality of lead pins provided on the base; The semiconductor light emitting device of claim 1 .

16. The semiconductor light emitting device according to claim 1 , wherein the substrate includes a mounting electrode provided on a surface opposite to a surface on which the light emitting element is mounted.

17. The semiconductor light emitting device according to claim 16 , further comprising a light-transmitting sealing resin that covers the light emitting element together with a surface on which the light emitting element is mounted.