Electronic component

Abstract

An electronic component (101) according to the present invention is provided with: a substrate (1); an insulator layer (2) which expands along a surface of the substrate (1); a planar conductor (4) which is formed on the substrate (1) or in the insulator layer (2) and planarly expands so as to be parallel to the surface of the substrate (1); and a conductor pattern (5) for inductors, the conductor pattern (5) being formed on the insulator layer (2) or in the insulator layer (2). When viewed from a direction that is perpendicular to the surface of the substrate (1), if Ls is the length in the longitudinal direction of a region where the formation region of the conductor pattern (5) for inductors and the planar conductor (4) overlap with each other, and d is the distance between the conductor pattern (5) for inductors and the planar conductor (4), the value of Ls / d is 1 to 60.

Description

Electronic Components

[0001] The present invention relates to an electronic component having a conductor pattern that forms a capacitor or inductor on a substrate.

[0002] An electronic component having a conductor pattern that forms a capacitor or inductor on a substrate is used as, for example, an LC composite component.

[0003] Patent Document 1 discloses an LC composite component in which an electrode for a capacitor is disposed outside the air-core portion of a coil formed by a helical conductor pattern.

[0004] Patent Document 2 discloses an LC composite component in which electrodes for a capacitor are arranged so as not to overlap the central axis of a coil conductor formed by a spiral conductor pattern.

[0005] Patent Document 3 discloses an LC composite component in which a capacitor with a comb-shaped electrode is arranged on an upper or lower layer other than the central region of a coil conductor with a spiral conductor pattern, and the comb-shaped electrode is formed perpendicular to the conductor wiring for the inductor.

[0006] JP 2004-079973 A JP 2012-178717 A JP 2019-091847 A

[0007] In the LC composite elements shown in Patent Documents 1, 2, and 3, the magnetic field generated by the coil does not pass through the electrodes of the capacitance section, so the Q value of the inductor does not deteriorate. However, in the LC composite components having the structures shown in Patent Documents 1, 2, and 3, the capacitor electrodes must be positioned so as to avoid the center of the coil, which increases the planar area of ​​the LC composite component. In other words, if the capacitor electrodes are positioned so as to avoid the center of the coil, the desired capacitance cannot be ensured, and if the coil conductor is positioned so as to avoid the capacitor electrodes, the desired inductance cannot be ensured, making it impossible to miniaturize the LC composite component.

[0008] The above problem is not limited to LC composite components that combine an inductor and a capacitor, but also occurs in electronic components that include a planar conductor and a conductor pattern for an inductor.

[0009] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a miniaturized electronic component that includes an inductor conductor pattern that generates a desired inductance and a planar conductor having a desired size.

[0010] An example of an electronic component disclosed herein comprises a substrate, an insulator layer extending along a surface of the substrate, a single or multiple sheet conductors formed on or within the substrate and extending in a plane parallel to the surface of the substrate, and an inductor conductor pattern formed on or within the insulator layer, wherein, when viewed from a direction perpendicular to the surface of the substrate, Ls represents the longitudinal length of a single region where the inductor conductor pattern formation region and the sheet conductor overlap, or the combined longitudinal length in a predetermined direction of multiple regions where the inductor conductor pattern formation region and the sheet conductor overlap, and d represents the distance between the inductor conductor pattern and the sheet conductor closest to the inductor conductor pattern, and the value of Ls / d is 1 or greater and 60 or less.

[0011] According to the present invention, it is possible to obtain a miniaturized electronic component that includes an inductor conductor pattern that generates a desired inductance and a planar conductor having a desired size.

[0012] FIG. 1 is a perspective view and a front view of an electronic component 101 according to a first embodiment. FIG. 2 is a plan view and a cross-sectional view of a main portion of the electronic component 101. FIG. 3 is a perspective view showing the positional relationship between the inductor conductor pattern 5 and the sheet conductor 4. FIG. 4 is a diagram showing trends in Ls / d and Q / Q0 found from multiple combinations of Ls and d. FIGS. 5A, 5B, 5C, and 5D are diagrams showing examples of the shape of the region where the inductor conductor pattern 5 is formed and the sheet conductor 4 overlap. FIG. 6 is a plan view and a cross-sectional view of an electronic component 102 according to a second embodiment. FIG. 7 is an equivalent circuit diagram of the electronic component 102. FIG. 8 is a diagram showing the structure of each layer of the electronic component 102. FIGS. 9A, 9B, 9C, and 9D are cross-sectional views of the electronic component 102 at various manufacturing steps. FIGS. 10A, 10B, 10C, and 10D are cross-sectional views of the electronic component 102 at various manufacturing steps. FIG. 11 is a plan view and a cross-sectional view of an electronic component 103 according to a third embodiment. FIG. 12 is a diagram showing the structure of each layer of the electronic component 103. FIGS. 13(A), 13(B), 13(C), and 13(D) are cross-sectional views of the electronic component 103 at various manufacturing steps. FIGS. 14(A), 14(B), and 14(C) are cross-sectional views of the electronic component 103 at various manufacturing steps. FIG. 15 is a plan view and a cross-sectional view of an electronic component 104 according to a fourth embodiment. FIG. 16 is a plan view and a cross-sectional view of an electronic component 105 according to a fifth embodiment. FIG. 17 is an equivalent circuit diagram of the electronic component 105. FIG. 18 is a diagram showing the structure of each layer of the electronic component 105. FIGS. 19(A), 19(B), 19(C), and 19(D) are cross-sectional views of the electronic component 105 at various manufacturing steps. FIGS. 20(A), 20(B), and 20(C) are cross-sectional views of the electronic component 105 at various manufacturing steps. FIG. 21 is a cross-sectional view of an electronic component 106 according to the sixth embodiment.

[0013] Hereinafter, several specific examples will be given with reference to the drawings to illustrate multiple embodiments for carrying out the present invention. The same reference numerals are used for the same parts in each drawing. For ease of explanation and understanding of the main points, the embodiments are shown divided into multiple embodiments for convenience of explanation, but partial substitution or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, a description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0014] First Embodiment The upper part of Fig. 1 is a perspective view of an electronic component 101 according to a first embodiment. In this perspective view, the outer shape is represented by a two-dot chain line. The lower part of Fig. 1 is a front view of the electronic component 101 as viewed in the Y-axis direction.

[0015] This electronic component 101 comprises an electrically insulating substrate 1, an insulator layer 2 extending along the surface of the substrate 1, a planar conductor 4 formed on the substrate 1 or in the insulator layer 2 and extending in a plane parallel to the surface of the substrate 1, and a rectangular spiral coil type inductor conductor pattern 5 formed on the substrate 1 or in the insulator layer 2.

[0016] The upper part of Fig. 2 is a plan view of the main part of the electronic component 101, and the lower part of Fig. 2 is a cross-sectional view of the X-X portion in the plan view. Fig. 3 is a perspective view showing the positional relationship between the inductor conductor pattern 5 and the sheet conductor 4. However, for convenience of explanation, the distance between the inductor conductor pattern 5 and the sheet conductor 4 is intentionally drawn wider.

[0017] The inductor conductor pattern 5 has an opening MH for the magnetic flux φ where the magnetic flux is concentrated, and in response to this magnetic flux (high frequency magnetic flux) φ, an eddy current EC flows in the planar conductor 4. The eddy current EC increases as the magnetic flux φ increases.

[0018] 2, the width of the sheet conductor 4 is represented by W. When the distance between the inductor conductor pattern 5 and the sheet conductor 4 is represented by d, the smaller the distance d between the inductor conductor pattern 5 and the sheet conductor 4, the larger the eddy current EC. Furthermore, when the surface of the substrate 1 is viewed from the perpendicular direction, the longitudinal length of the area where the inductor conductor pattern 5 overlaps with the sheet conductor 4 is represented by Ls. When Ls is larger, the eddy current EC becomes larger. Therefore, the larger the value of Ls / d, the larger the eddy current EC becomes.

[0019] Table 1 shows the relationship between the longitudinal length Ls of the area where the inductor conductor pattern 5 is formed and the sheet conductor 4 overlap, the distance d between the inductor conductor pattern 5 and the sheet conductor 4, and the deterioration of the inductor's Q value, etc.

[0020]

[0021] In Table 1, S [μm 2 ] is the area of ​​the area where the inductor conductor pattern 5 and the sheet conductor 4 overlap when they are square. In Table 1, Q0 is the Q value of the inductor formed by the inductor conductor pattern 5 when there is no sheet conductor 4, and Q / Q0 is the area S [μm 2 ] is placed at a distance d [μm] from the inductor conductor pattern 5. L0 is the inductance of the inductor conductor pattern 5 in the absence of the inductor conductor pattern 4, and L / L0 is the ratio of the Q value to the area S [μm 2 ] is placed at a distance d [μm] from the inductor conductor pattern 5, and the ratio of L value to L0.

[0022] Figure 4 shows the trends between Ls / d and Q / Q0 found from the above-mentioned multiple combinations of Ls and d. In Figure 4, the horizontal axis represents Ls / d, and the vertical axis represents Q / Q0. As is clear from Figure 4, when the value of Ls / d (the value of √(S) / d) is in the range of 1 to 60, Q / Q0 is 0.3 or more, so the presence of the sheet conductor 4 does not reduce the Q value of the inductor much. Furthermore, when the value of Ls / d is in the range of 1 to 55, the reduction in Q / Q0 is further reduced.

[0023] The examples in Table 1 and FIG. 4 are examples where the overlapping area between the inductor conductor pattern 5 and the sheet conductor 4 is square, i.e., the worst case. Therefore, if the overlapping area between the formation area of ​​the inductor conductor pattern 5 and the sheet conductor 4 is not square, the longitudinal length of this overlapping area can be treated as Ls.

[0024] In the example shown in Figure 1, when viewed from a direction perpendicular to the surface of the substrate 1, there is only one area where the formation area of ​​the inductor conductor pattern 5 overlaps with the sheet conductor 4. However, if there are multiple such areas, the total longitudinal length in a predetermined direction of the multiple areas where the formation area of ​​the inductor conductor pattern 5 overlaps with the sheet conductor 4 can be treated as Ls.

[0025] 5(A), 5(B), 5(C), and 5(D) are diagrams showing examples of the shape of the region where the inductor conductor pattern 5 overlaps with the sheet conductor 4. As shown in Fig. 5(A), if the region of the sheet conductor 4 overlapping with the region where the inductor conductor pattern 5 is formed is L-shaped, the longitudinal dimension of that region is defined as Ls. Also, as shown in Fig. 5(B), if the region of the sheet conductor 4 overlapping with the region where the inductor conductor pattern 5 is formed is circular or elliptical, the longitudinal dimension of that region is defined as Ls. Furthermore, as shown in Fig. 5(C), if the region of the sheet conductor 4 overlapping with the region where the inductor conductor pattern 5 is formed is T-shaped, the longitudinal dimension of the width Lx height Ly of that region is defined as Ls.

[0026] 5(D), when there are multiple areas of the sheet conductor overlapping the area where the inductor conductor pattern 5 is formed, the combined longitudinal length of those overlapping areas in a predetermined direction is defined as Ls. In the example shown in Fig. 5(D), of the two sheet conductor areas overlapping the area where the inductor conductor pattern 5 is formed, one has an X-axis dimension of Lx1 and a Y-axis dimension of Ly1, while the other has an X-axis dimension of Lx2 and a Y-axis dimension of Ly2. In this example, the combined dimension of Ly1 + Ly2 is greater than the combined dimension of Lx1 + Lx2, so the value of Ly1 + Ly2 is the longitudinal length Ls.

[0027] Second Embodiment In a second embodiment, an LC composite electronic component will be illustrated. The upper part of Fig. 6 is a plan view of an electronic component 102 according to the second embodiment, and the lower part of Fig. 6 is a cross-sectional view taken along line X-X in the upper part of Fig. 6.

[0028] The electronic component 102 comprises a substrate 1, an insulator layer 2 extending along the surface of the substrate 1, an inductor formed in the insulator layer 2, sheet conductors 3 and 4 formed on the substrate 1 and extending along the substrate 1, sheet conductor connecting conductors 7A, 7B, and 7C that are electrically connected to the sheet conductor 3, and a sheet conductor connecting conductor 8 that is electrically connected to the sheet conductor 4.

[0029] Terminal electrodes 10A and 10B are formed on the surface of the insulating layer 2. The terminal electrodes 10A and 10B are electrically connected to the terminal electrodes 9A and 9B.

[0030] The inductor is a spiral coil type inductor formed by an inductor conductor pattern 5 along the surface of the substrate 1 .

[0031] The sheet conductors 3 and 4 are capacitor electrodes. That is, a capacitor is formed by the sheet conductors 3 and 4 and the dielectric layer 11 sandwiched between these sheet conductors 3 and 4. That is, the sheet conductors 3 and 4 are capacitor electrodes that form the capacitor together with the dielectric layer 11.

[0032] When viewed perpendicularly to the surface of the substrate 1, the formation area of ​​the inductor conductor pattern 5 overlaps with both the sheet conductor 3 and the sheet conductor 4. Of these sheet conductors 3 and 4, the sheet conductor 4 is closer to the inductor conductor pattern 5, so the distance between the inductor conductor pattern 5 and the sheet conductor 4 is represented by d. Furthermore, the longitudinal length of the largest area of ​​overlap between the inductor conductor pattern 5 and the sheet conductor 4 is represented by Ls.

[0033] 6, the value of Ls is 190 μm, and the distance d between the inductor conductor pattern 5 and the sheet conductor 4 is 20 μm. Therefore, Ls / d is 9.5, which is smaller than 60 and even smaller than 55. As a result of creating and simulating the structural model shown in FIG. 6, according to this embodiment, the ratio Q / Q0 of the Q value when the sheet conductor 4 is present to the Q value when the sheet conductor 4 is absent is 0.48, and although the Q value decreases, it is not an extreme decrease, and an electronic component having an inductor with an effective Q value can be obtained.

[0034] 7 is an equivalent circuit diagram of the electronic component 102. In this manner, the electronic component 102 forms a series circuit of the inductor L1 and the capacitor C1. This electronic component 102 can be used as a frequency filter or an impedance matching circuit.

[0035] Fig. 8 is a diagram showing the structure of each layer of electronic component 102. In Fig. 8, layer La is the layer of substrate 1, layer Lb is the layer where sheet conductor 3 is formed, layer Lc is the layer where dielectric layer 11 and sheet conductor connecting conductor 7A are formed, and layer Ld is the layer where sheet conductor 4 and sheet conductor connecting conductor 7B are formed. Layer Le is the layer where sheet conductor connecting conductors 7C and 8 are formed, layer Lf is the layer where inductor conductor pattern 5 and terminal electrodes 9A and 9B are formed, and layer Lg is the layer where terminal electrodes 10A and 10B are formed.

[0036] Next, an example of a method for manufacturing an electronic component 102 composed of the layers shown in Figure 8 will be described. Figure 9(A) is a cross-sectional view of a substrate. This substrate 1 can be a semiconductor substrate such as a Si substrate or a GaAs substrate, as well as a glass substrate or a ceramic substrate. Figure 9(B) is a cross-sectional view of the state after the planar conductor 3 has been formed. In this process, the substrate is formed by semiconductor processes such as evaporating an Al or Cu film on the surface of the substrate 1 and lifting it off, or depositing the Al or Cu film by sputtering or CVD, followed by lithography and etching.

[0037] 9(C) is a cross-sectional view showing the state after the dielectric layer 11 has been formed. In this process, a dielectric layer 11 such as an SiO2 film or SiN film is formed on the surface of the sheet conductor 3 by a semiconductor process such as sputtering or CVD. Then, as shown in FIG. 9(D), an opening is formed in the area where the sheet conductor connecting conductor 7A will be formed, and the sheet conductor connecting conductors 7A, 7B and the sheet conductor 4 are formed. In this process, the pattern of the sheet conductor 4 is formed by semiconductor processes such as forming an opening by lithography and etching, evaporating an Al or Cu film and lifting it off, or depositing an Al or Cu film by sputtering or CVD, lithography, and etching.

[0038] 10A is a cross-sectional view showing the state in which the insulating layer 2 has been formed and the opening AP has been formed. In this configuration, a resin (organic) film or an inorganic film such as an SiO2 film or an SiN film is formed by a method such as spin coating, CVD, or sputtering, and then the opening AP is formed in a predetermined position by lithography and etching.

[0039] 10B is a cross-sectional view of the state in which the conductors 7C and 8 for connecting planar conductors have been formed. In this process, the conductors 7C and 8 for connecting planar conductors are formed in the openings AP shown in FIG. 10A. For example, they can be formed by forming a Cu film, lithography, and plating, or by sputtering Cu, lithography, and etching, or by lithography, vapor deposition, and lift-off of a Cu film.

[0040] 10C is a cross-sectional view showing the state after the inductor conductor pattern 5 and terminal electrodes 9A and 9B have been formed. In this process, the inductor conductor pattern 5 and terminal electrodes 9A and 9B are formed on the surface of the insulator layer 2. For example, they can be formed by forming a Cu film, lithography, and plating, or by sputtering Cu, lithography, and etching, or by lithography, vapor deposition, and lift-off of a Cu film.

[0041] 10(D) is a cross-sectional view of the terminal electrodes 10A, 10B after they have been formed. In this process, the terminal electrodes 10A, 10B are electrodes for mounting, and are formed by plating the surfaces of the terminal electrodes 9A, 9B with Ni, Au, or the like. After that, a protective film is formed, and the portions corresponding to the terminal electrodes 10A, 10B are opened to expose the terminal electrodes 10A, 10B.

[0042] Third Embodiment In a third embodiment, an electronic component having a sheet conductor configuration different from the examples shown in the first and second embodiments will be illustrated.

[0043] Fig. 11 is a diagram showing the structure of an electronic component 103 according to the third embodiment. The <Plan View> in Fig. 11 is a plan view of the electronic component 103. The <Cross Section> in Fig. 11 is a cross section taken along the line X-X in the plan view of the electronic component 103.

[0044] The electronic component 103 comprises a substrate 1, an insulator layer 2 extending along the surface of the substrate 1, an inductor conductor pattern 5 formed in the insulator layer 2, a dielectric layer 11 and a sheet conductor 4 formed on the substrate 1 and extending along the substrate 1, a sheet conductor connecting conductor 8 that is electrically connected to the sheet conductor 4, and sheet conductor connecting conductors 7A, 7B, and 7C that are electrically connected to the substrate 1.

[0045] A dielectric layer 11 is formed on the surface of a substrate 1, and a sheet conductor 4 is formed on the surface of this dielectric layer 11. Furthermore, a sheet conductor connecting conductor 7A is formed at a predetermined position on the surface of the substrate 1. The substrate 1 is a semiconductor substrate with high conductivity. The other configurations are as shown in the second embodiment.

[0046] 11, the value of Ls is 210 μm, and the distance d between the inductor conductor pattern 5 and the sheet conductor 4 is 30 μm. Therefore, Ls / d is 7, which is smaller than 60 and even smaller than 55. According to this embodiment, the ratio Q / Q0 of the Q value when the sheet conductor 4 is present to the Q value when the sheet conductor 4 is absent is 0.61, and an electronic component having an inductor with an effective Q value can be obtained.

[0047] Fig. 12 is a diagram showing the structure of each layer of the electronic component 103. In Fig. 12, layer La is the layer of the substrate 1, layer Lb is the layer on which the planar conductor connecting conductor 7A and the dielectric layer 11 are formed, layer Lc is the layer on which the dielectric layer 11 and the planar conductor 4 are formed, and layer Ld is the layer on which the planar conductor connecting conductors 7C and 8 are formed. Layer Le is the layer on which the inductor conductor pattern 5 and the terminal electrodes 9A and 9B are formed. And layer Lf is the layer on which the terminal electrodes 10A and 10B are formed.

[0048] Next, a method for manufacturing the electronic component 103 composed of the layers shown in FIG. 11 will be described. FIG. 13A is a cross-sectional view of the substrate. This substrate 1 can be a semiconductor substrate such as a Si substrate or a GaAs substrate, as well as a glass substrate or a ceramic substrate. FIG. 13B is a cross-sectional view of the dielectric layer 11 after forming an aperture AP at a predetermined position. FIG. 13C is a cross-sectional view of the dielectric layer 11 after forming a conductor 7A for connecting a planar conductor in the aperture AP and forming a conductor 7B for connecting a planar conductor and a planar conductor 4 on the upper surface of the dielectric layer 11. FIG. 13D is a cross-sectional view of the insulating layer 2 after forming an aperture AP. In this configuration, a resin (organic) film or an inorganic film such as a SiO2 film or a SiN film is formed by spin coating, CVD, or sputtering, and then an aperture AP is formed at a predetermined position by lithography and etching.

[0049] 14A is a cross-sectional view of the state in which the conductors 7C and 8 for connecting planar conductors have been formed. In this process, the conductors 7C and 8 for connecting planar conductors are formed in the opening AP shown in FIG. 13D. For example, they can be formed by forming a Cu film, lithography, and plating, or by sputtering Cu, lithography, and etching, or by lithography, vapor deposition, and lift-off of a Cu film.

[0050] 14B is a cross-sectional view showing the state after the inductor conductor pattern 5 and the terminal electrodes 9A, 9B have been formed. In this process, the inductor conductor pattern 5 and the terminal electrodes 9A, 9B are formed on the surface of the insulator layer 2. For example, they can be formed by forming a Cu film, lithography, and plating, or by sputtering Cu, lithography, and etching, or by lithography, vapor deposition, and lift-off of a Cu film.

[0051] 14(C) is a cross-sectional view of the state after the terminal electrodes 10A, 10B have been formed. In this process, the terminal electrodes 10A, 10B are electrodes for mounting, and are formed by plating the surfaces of the terminal electrodes 9A, 9B with Ni, Au, or the like. After that, a protective film is formed, and the portions corresponding to the terminal electrodes 10A, 10B are opened to expose the terminal electrodes 10A, 10B.

[0052] Fourth Embodiment In the fourth embodiment, an electronic component having a planar conductor on the back surface of a substrate is illustrated. The plan view in Fig. 15 is a plan view of electronic component 104. The cross-sectional view in Fig. 15 is a cross-sectional view taken along the line X-X in the plan view of electronic component 104.

[0053] The electronic component 104 comprises a substrate 1, a dielectric layer 11 formed on the upper surface of the substrate 1, a terminal electrode 9A formed on the lower surface of the substrate 1, an insulator layer 2, an inductor conductor pattern 5 formed in the insulator layer 2, a sheet conductor 4 extending along the substrate 1, and a sheet conductor connecting conductor 8 that is electrically connected to the sheet conductor 4.

[0054] In the electronic component 104 of this embodiment, the capacitance generated between the sheet conductor 4 and the terminal electrode 9A is used as a capacitor. The terminal electrodes 9A and 9B on the top and bottom surfaces are also used.

[0055] In this embodiment, the value of Ls is 210 μm, and the value of d is 30 μm. Except for the back electrode, the electronic component 103 shown in the third embodiment is the same. Therefore, the value of Ls / d is the same as the result shown in the third embodiment.

[0056] Fifth Embodiment In a fifth embodiment, an electronic component having three terminal electrodes and an electronic component including a resistor element will be exemplified.

[0057] Fig. 16 is a diagram showing the structure of an electronic component 105 according to the fifth embodiment. The <Plan View> in Fig. 16 is a plan view of the electronic component 105. The <Cross Section> in Fig. 16 is a cross section taken along the line X-X in the plan view of the electronic component 105.

[0058] The electronic component 105 includes a substrate 1, an insulator film 20 extending along the surface of the substrate 1, an inductor conductor pattern 5 formed in an insulator layer 2, a resistor film 21 formed on the insulator film 20 and extending along the insulator film 20, a planar conductor connecting conductor 7 electrically connecting the resistor film 21 to a terminal electrode 9A, and a planar conductor connecting conductor 8 electrically connecting the resistor film 21 to a terminal electrode 9B. In this embodiment, the resistor film 21 corresponds to a planar conductor according to the present invention.

[0059] 17 is an equivalent circuit diagram of the electronic component 105. As described above, the electronic component 105 constitutes a composite component of the inductor L1 and the resistor element R1.

[0060] 18 is a diagram showing the structure of each layer of the electronic component 105. In Fig. 18, layer La is the layer where the insulator film 20 and resistor film 21 are formed, layer Lb is the layer where the planar conductor connecting conductors 7 and 8 are formed, layer Lc is the layer where the inductor conductor pattern 5 and terminal electrodes 9A, 9B, and 9C are formed, and layer Ld is the layer where the terminal electrodes 10A, 10B, and 10C are formed.

[0061] Next, a method for manufacturing an electronic component 105 composed of the layers shown in Fig. 18 will be illustrated. Fig. 19(A) is a cross-sectional view of the substrate. Fig. 19(B) is a cross-sectional view in a state where an insulator film 20 has been formed. Fig. 19(C) is a cross-sectional view in a state where a resistor film 21 has been formed on the insulator film 20. Fig. 19(D) is a cross-sectional view in a state where an insulator layer 2 has been formed and an opening AP has been formed.

[0062] The resistor film 21 is made of a material having a conductivity between that of the insulator layer and that of the conductor forming the terminal electrode or the conductor pattern for the inductor. The resistor film 21 may be made of, for example, NiCr, Si containing impurities, or a film in which an insulator and a conductor are laminated.

[0063] Fig. 20A is a cross-sectional view showing the state in which the planar conductor connecting conductors 7 and 8 have been formed. In this step, the planar conductor connecting conductors 7 and 8 are formed in the opening AP shown in Fig. 19D.

[0064] 20B is a cross-sectional view of the state after the inductor conductor pattern 5 and the terminal electrodes 9A, 9B, and 9C are formed. In this step, the inductor conductor pattern 5 and the terminal electrodes 9A, 9B, and 9C are formed on the surface of the insulator layer 2.

[0065] 20C is a cross-sectional view of the terminal electrodes 10A, 10B, and 10C for mounting after they have been formed. In this process, the surfaces of the terminal electrodes 9A, 9B, and 9C are plated with Ni, Au, or the like. After that, a protective film is formed, and openings are made in the areas corresponding to the terminal electrodes 10A, 10B, and 10C to expose the terminal electrodes 10A, 10B, and 10C.

[0066] In this embodiment, the value of Ls is 250 μm, the value of d is 30 μm, and Ls / d is approximately 8.3. In this example, Ls / d is also smaller than 55, and Q / Q0 is 0.52, resulting in an electronic component with a sufficiently large inductor Q value.

[0067] Sixth Embodiment In a sixth embodiment, an electronic component having a capacitor electrode inside a dielectric layer will be exemplified.

[0068] 21 is a cross-sectional view of an electronic component 106 according to a sixth embodiment. This electronic component 106 includes a substrate 1, a dielectric layer 11 extending along the surface of the substrate 1, sheet conductors 3 and 4 formed within the dielectric layer 11, a spiral coil-type inductor conductor pattern 5 formed on the insulator layer 2, and terminal electrodes 9A, 9B, 10A, and 10B. One end of the inductor conductor pattern 5 is electrically connected to the sheet conductor 4 and terminal electrode 9A, and the other end of the inductor conductor pattern 5 is electrically connected to the sheet conductor 3 and terminal electrode 9B. This electronic component 106 constitutes a parallel circuit of an inductor and a capacitor.

[0069] In this embodiment, too, when the longitudinal length of the area where the inductor conductor pattern 5 overlaps with the sheet conductor 4 is represented by Ls and the distance between the inductor conductor pattern and the sheet conductor is represented by d, Ls / d is a value between 1 and 60.

[0070] In each of the above-described embodiments, an example is shown in which the conductor pattern for the inductor has an opening MH for the magnetic flux φ where the magnetic flux is concentrated, and a sheet conductor is arranged in all or part of the opening MH, and an example in which the sheet conductor covers the entire opening MH for the magnetic flux φ is not necessarily explicitly stated, but the sheet conductor may cover the entire opening MH for the magnetic flux φ.

[0071] In addition, while the above-described embodiments have shown electronic components that include a capacitor or a resistor as a passive component in addition to an inductor, electronic components that include passive components that include both a capacitor and a resistor can be similarly configured. Electronic components that include passive components that include multiple capacitors or multiple inductors can also be similarly configured.

[0072] The present invention can also be applied to electronic components used as LC parallel resonant circuits, bandpass filters including a plurality of inductors and capacitors, diplexers, and the like.

[0073] Furthermore, in the present invention, the substrate is a semiconductor substrate, and the planar conductor can be similarly applied to electronic components that, together with the semiconductor substrate, constitute a semiconductor active element, such as a high-frequency power amplifier in which an active component is provided on a semiconductor substrate.

[0074] Finally, the present invention is not limited to the above-described embodiments. Those skilled in the art can make appropriate modifications and variations. The scope of the present invention is defined not by the above-described embodiments but by the claims. Furthermore, the scope of the present invention includes modifications and variations from the embodiments within the scope of the claims and their equivalents.

[0075] The configuration of the electronic component of the present invention is listed below.

[0076] <1> A substrate comprising: a substrate; an insulator layer extending along a surface of the substrate; a single or multiple sheet conductors formed on or in the substrate and extending in a plane parallel to the surface of the substrate; and an inductor conductor pattern formed on or in the insulator layer, wherein, when viewed from a direction perpendicular to the surface of the substrate, the longitudinal length of a single region where the formation region of the inductor conductor pattern and the sheet conductor overlap is represented by Ls, or the combined longitudinal length in a predetermined direction of multiple regions where the formation region of the inductor conductor pattern and the sheet conductor overlap is represented by d, and the distance between the inductor conductor pattern and the sheet conductor closest to the inductor conductor pattern is represented by d, the value of Ls / d is 1 or greater and 60 or less.

[0077] <2> The electronic component according to <1>, wherein the value of Ls / d is 1 or more and 55 or less.

[0078] <3> The electronic component according to <1> or <2>, further comprising a dielectric layer formed between the substrate and the insulator layer, wherein the planar conductor is a capacitor electrode that constitutes a capacitor together with the dielectric layer.

[0079] <4> The electronic component according to <1> or <2>, wherein the substrate is a low-resistance semiconductor substrate, and the planar conductor is a capacitor electrode that constitutes a capacitor together with the semiconductor substrate.

[0080] <5> The electronic component according to <1> or <2>, wherein the substrate is a semiconductor substrate, and the planar conductor forms a semiconductor active element together with the semiconductor substrate.

[0081] <6> The electronic component according to any one of <1> to <5>, wherein the sheet conductor is a resistive thin film.

[0082] <7> The electronic component according to any one of <1> to <6>, wherein the inductor conductor pattern has a magnetic flux opening where magnetic flux concentrates, and the sheet conductor is disposed in the opening.

[0083] <8> The electronic component according to <7>, wherein the sheet conductor covers the entire opening.

[0084] AP...opening C1...capacitor d...spacing EC...eddy current Ls...longitudinal length L1...inductor Lx...width Ly...height La, Lb, Lc, Ld, Le, Lf, Lg...layer MH...magnetic flux opening R1...resistance element φ...magnetic flux 1...substrate 2...insulating layer 3, 4...sheet conductor 5...inductor conductor pattern 7, 8...sheet conductor connecting conductor 7A, 7B, 7C, 8...sheet conductor connecting conductor 9A, 9B, 9C, 10A, 10B, 10C...terminal electrode 11...dielectric layer 20...insulating film 21...resistor film 101 to 106...electronic component

Claims

1. A substrate; an insulating layer extending along a surface of the substrate; a single or a plurality of planar conductors formed on the substrate or within the insulating layer and extending in a planar shape parallel to a surface of the substrate; a conductor pattern for an inductor formed on or in the insulating layer, When viewed from a direction perpendicular to the surface of the substrate, the longitudinal length of a single region where the region where the inductor conductor pattern is formed and the sheet conductor overlap, or the combined longitudinal length in a predetermined direction of a plurality of regions where the region where the inductor conductor pattern is formed and the sheet conductor overlap, is represented by Ls, and the distance between the inductor conductor pattern and the sheet conductor closest to the inductor conductor pattern is represented by d, a value of Ls / d is 1 or more and 60 or less. Electronic components.

2. The value of Ls / d is 1 or more and 55 or less; The electronic component according to claim 1 .

3. a dielectric layer formed between the substrate and the insulator layer; The planar conductor is a capacitor electrode that constitutes a capacitor together with the dielectric layer. The electronic component according to claim 1 or 2.

4. the substrate is a low resistance semiconductor substrate, the planar conductor is a capacitor electrode that constitutes a capacitor together with the semiconductor substrate; The electronic component according to claim 1 or 2.

5. the substrate is a semiconductor substrate; the planar conductor constitutes a semiconductor active element together with the semiconductor substrate; The electronic component according to claim 1 or 2.

6. The planar conductor is a resistive thin film. The electronic component according to claim 1 or 2.

7. the inductor conductor pattern has an opening for magnetic flux concentration, and the sheet conductor is disposed in the opening. The electronic component according to claim 1 or 2.

8. The sheet conductor covers the entire opening, The electronic component according to claim 7.