Semiconductor device and power conversion device

Abstract

This semiconductor device includes: a gate voltage control circuit that applies on-bias and off-bias to a gate terminal of a power semiconductor element in accordance with a first drive signal; and an off-bias voltage control circuit that changes a voltage level of the off-bias in accordance with the first drive signal and a second drive signal and controls an application period of the changed off-bias.

Description

Semiconductor device and power conversion device

[0001] The present disclosure relates to a semiconductor device, and to driving a power semiconductor element.

[0002] One of the problems related to the reliability of power semiconductor devices is false gate firing. When false gate firing occurs, a short circuit occurs between the high-voltage power supply on the upper arm of a power inverter and the low-voltage power supply on the lower arm of the phase where the false gate firing occurred. This causes a large short-circuit current to flow between the power supplies, increasing losses in the inverter device and, in the worst case, leading to thermal runaway.

[0003] A widely known method for preventing gate misfire is to apply a negative bias between the gate and source of a power semiconductor device. Gate misfire is caused by a displacement current generated by the turn-on operation of the power semiconductor device on the opposing arm. This displacement current is proportional to the voltage change rate of the power conversion device on the opposing arm, so the faster the switching speed, the greater the displacement current, making misfire of the switching device more likely to occur. If a negative bias is applied at the time of the misfire, a short circuit between the upper and lower arm devices can be avoided without exceeding the gate threshold voltage, and the greater the negative bias, the greater the effect of preventing misfire.

[0004] On the other hand, when applying a negative bias between the gate and source, conventionally, the gate is driven so that a negative bias is always applied while the power semiconductor element is in off-state. If the negative bias is applied for a long period of time, stress is placed on the gate oxide film of the power semiconductor element. Reports on metal-oxide-semiconductor field-effect transistors (SiC-MOSFETs) made from silicon nitride have shown that increased stress on the gate oxide film can cause degradation of the characteristics and failure of the power semiconductor element. This can also lead to a decrease in the reliability of the entire power inverter system.

[0005] JP 2013-219874 A

[0006] Andreas Marz, and 3 others, “Comparison of SiC MOSFET gate-drive concepts to suppress parasitic turn-on in low inductance power modules”, EPE, 2017.

[0007] In Patent Document 1, two voltages are applied to the gate terminal of a power semiconductor device: a first voltage and a second voltage, which is lower than the first voltage. The power semiconductor device is turned off using the first voltage, but the first voltage is generally not higher than the negative bias applied to the gate terminal. This means that the switching loss of the power semiconductor device increases compared to when the second voltage is used. On the other hand, increasing the first voltage improves the switching loss by speeding up the turn-on operation, but requires that a negative bias (e.g., the second voltage) higher than the first voltage be continuously applied to the gate until the turn-on operation of the power semiconductor device on the opposing arm is completed, including the dead time after the turn-off operation. This creates a trade-off between the aforementioned problem of gate oxide stress and the overall reliability of the power converter.

[0008] In the case of Non-Patent Document 1, a negative bias is applied to the gate terminal of the power semiconductor element in the arm from the start of the turn-off operation of the power semiconductor element in the opposing arm to the end of the turn-on operation of the power semiconductor element in the opposing arm. In other words, a negative bias continues to be applied to the gate terminal of the arm element in the arm during the dead time and switching period. Therefore, there is a concern that the effect of reducing stress on the gate oxide film may be insufficient in systems with a long dead time setting.

[0009] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device and a power conversion device that can improve the reliability of power semiconductor elements.

[0010] A semiconductor device according to one embodiment includes a gate voltage control circuit that applies an on-bias and an off-bias to a gate terminal of a power semiconductor element in accordance with a first drive signal, and an off-bias voltage control circuit that changes the voltage level of the off-bias in accordance with the first drive signal and a second drive signal and controls the application period of the changed off-bias.

[0011] A power conversion apparatus according to one embodiment includes a first power semiconductor device, a second power semiconductor device provided on an opposing arm connected in series with the first power semiconductor device, and first and second gate drive circuits provided corresponding to the first and second power semiconductor devices, respectively, and driving the corresponding power semiconductor device in accordance with first and second drive signals. Each gate drive circuit includes a gate voltage control circuit that applies an on-bias and an off-bias to a gate terminal of the power semiconductor device in accordance with the corresponding drive signal, and an off-bias voltage control circuit that changes the voltage level of the off-bias in accordance with the first and second drive signals and controls the application period of the changed off-bias.

[0012] The semiconductor device and power conversion device according to the present disclosure can improve the reliability of power semiconductor elements.

[0013] FIG. 10 is a block diagram for explaining the function of a gate drive circuit 100 of a power semiconductor device according to a first embodiment. FIG. 11 is a diagram for explaining specific configurations of a first control circuit 21 and a second control circuit 31 according to the first embodiment. FIG. 12 is a diagram for explaining a timing chart when a gate drive circuit 100 according to the first embodiment controls a gate of a power semiconductor element 10. FIG. 13 is a diagram for explaining a gate drive circuit 101 according to a second embodiment. FIG. 14 is a diagram for explaining a timing chart when a gate drive circuit 101 according to the second embodiment controls a gate of a power semiconductor element. FIG. 15 is a block diagram for explaining the function of a gate drive circuit 100# of a power semiconductor device according to a third embodiment. FIG. 16 is a diagram for explaining specific configurations of a first control circuit 21# and a second control circuit 31# according to the third embodiment. FIG. 17 is a diagram for explaining a waveform of a gate voltage Vgs of a SiC-MOSFET to which a gate drive circuit 100 of the present disclosure is applied. FIG. 18 is a diagram for explaining a timing chart when a gate drive circuit 101 according to a fifth embodiment controls a gate of a power semiconductor element. FIG. 19 is a block diagram for explaining the function of an integrated drive circuit 102 according to a sixth embodiment. FIG. 19 is a block diagram showing the configuration of a power conversion system according to a seventh embodiment.

[0014] First Embodiment A gate drive circuit for a power semiconductor device, which is an example of the present disclosure, will be described below.

[0015] FIG. 1 is a block diagram for illustrating the function of a gate drive circuit 100 according to the first embodiment.

[0016] 1, a gate drive circuit 100 controls the gate of a power semiconductor device 10 connected between DC high-voltage power supplies in accordance with input of external drive signals IN1 and IN2. Specifically, the gate drive circuit 100 controls the so-called switching operation of switching on and off the power semiconductor device 10.

[0017] The power semiconductor device 10 corresponds to a switching element in the main circuit of an inverter circuit of a power conversion device. For example, it is one element of a 2-in-1 half-bridge circuit, a 4-in-1 full-bridge circuit, or a 6-in-1 three-phase inverter. These circuit configurations generate inverter output voltage using PWM control, so a high voltage of several hundred volts or more is applied between the drain and source of the device when it is in off operation. Furthermore, a large current corresponding to the system of the power conversion device flows through the device when it is in on operation. These operating states are controlled by the gate voltage that turns the power semiconductor device 10 on and off in accordance with an external drive signal IN1.

[0018] The gate drive circuit 100 includes a gate voltage control circuit 20 and an off-bias voltage control circuit 30 .

[0019] The gate voltage control circuit 20 controls the on-bias and off-bias of the gate of the power semiconductor device 10 .

[0020] The gate voltage control circuit 20 includes a first control circuit 21 and a first switching circuit 22. The first control circuit 21 controls the gate control signal in response to the input external drive signal IN1 so that the power semiconductor element 10 performs the desired switching operation. Specifically, the first control circuit 21 sets the gate control signal to "1" during the period when the power semiconductor element 10 should be on, and sets the gate control signal to "0" during the period when the power semiconductor element 10 should be off. These binary voltage signals can be configured by generating pulse waveforms using a communication signal source of a 5V system, 3.3V system, etc., of a logic circuit.

[0021] The first switching circuit 22 is disposed between the gate of the power semiconductor device 10 and the first control circuit 21. The high side of the first switching circuit 22 is connected to the positive voltage source Vdd, and the low side is connected to the second switching circuit 32.

[0022] The first switching circuit 22 includes an NPN transistor 22A, a PNP transistor 22B, and a resistor element 22C.

[0023] The NPN transistor 22A and the PNP transistor 22B are connected in series. The NPN transistor 22A is connected to a positive voltage source Vdd and to an output node.

[0024] The PNP transistor 22B is connected to the output node and the output node of the second switching circuit 32 .

[0025] The gates of the NPN transistor 22A and the PNP transistor 22B are connected to the first control circuit 21 via the resistive element 22C.

[0026] The first switching circuit 22 can switch the current path in response to the gate control signal output from the first control circuit 21. This changes the path through which the gate current of the power semiconductor element 10 flows, which is equivalent to switching between charging and discharging of the gate. Therefore, the first switching circuit 22 functions to switch the gate voltage applied to the gate of the power semiconductor element 10 and control the on / off operation of the power semiconductor element 10.

[0027] In accordance with external drive signals IN1 and IN2, off-bias voltage control circuit 30 controls the level of the off-bias applied to the gate during the off operation of power semiconductor element 10. Specifically, off-bias voltage control circuit 30 sets the voltage level during the off operation of power semiconductor element 10 so that it is always 0 V or less, since a positive value may exceed the gate threshold voltage of power semiconductor element 10.

[0028] In addition, the number of switching off-bias levels is assumed to be two, for example. In this embodiment, external drive signals IN1 and IN2 are used to switch between the two off-bias levels. External drive signal IN1 is the same as the input signal to first control circuit 21. External drive signal IN2 is required to provide timing information for false gate firing (also called self-turn-on phenomenon) of power semiconductor device 10, which will be described later, to gate drive circuit 100. External drive signal IN2 is provided as a means separate from external drive signal IN1.

[0029] The off-bias voltage control circuit 30 includes a second control circuit 31 and a second switching circuit 32. The second control circuit 31 outputs an off-bias voltage control signal that can arbitrarily adjust the voltage level and application period of the off-bias applied to the gate of the power semiconductor element 10 based on the input of the external drive signal IN1 and the external drive signal IN2. The specific method will be described later.

[0030] The second switching circuit 32 is connected to the second control circuit 31 , the first switching circuit 22 , and the source electrode of the power semiconductor element 10 .

[0031] The high side of the second switching circuit 32 is connected to the source electrode of the power semiconductor device 10, and the low side is connected to the negative voltage source Vneg.

[0032] The second switching circuit 32 includes an NPN transistor 32A, a PNP transistor 32B, and a resistor element 32C.

[0033] The NPN transistor 32A and the PNP transistor 32B are connected in series. The NPN transistor 32A is connected to the source electrode of the power semiconductor device 10 and to the output node. The output node is connected to the first switching circuit 22.

[0034] The PNP transistor 32B is connected to the output node and the negative voltage source Vneg. The gates of the NPN transistor 32A and the PNP transistor 32B are connected to the second control circuit 31 via the resistive element 32C.

[0035] The second switching circuit 32 switches the off-bias level of the gate in response to the off-bias voltage control signal generated by the second control circuit 31. Specifically, it switches between a reference potential Vs based on the source potential of the power semiconductor element 10 and a negative voltage source Vneg. That is, the off-bias level applied to the gate of the power semiconductor element 10 is switched by switching the source potential of the power semiconductor element 10.

[0036] Hereinafter, the state of connection to the reference potential Vs will also be referred to as "shallow off-bias" and the state of connection to the negative voltage source Vneg as "deep off-bias" as necessary.

[0037] However, the shallow off-bias and deep off-bias applied to the gate of the power semiconductor element 10 are premised on the off operation of the power semiconductor element 10. Therefore, the shallow off-bias and deep off-bias applied to the gate of the power semiconductor element 10 are not uniquely determined solely by the operation of the second switching circuit 32, but the first switching circuit 22 switches between the shallow off-bias and deep off-bias applied to the gate of the power semiconductor element 10 only during the off operation of the power semiconductor element 10. In other words, the off-bias level applied to the gate of the power semiconductor element 10 is controlled based on the states of the gate voltage control circuit 20 and the off-bias voltage control circuit 30.

[0038] The first control circuit 21 and the second control circuit 31, which are not shown in the figure, may be composed of passive elements such as resistors, capacitors, and diodes, as well as RC filters. They may also be equipped with a Schmitt trigger element to adjust the transmission signal. The first control circuit 21 includes a delay line (which can be implemented using a delay IC or a buffer circuit) that delays the transmission signal by a fixed time, and the second control circuit 31 includes a logic operation circuit that performs logical operations such as logical sum (OR) and logical product (AND) of the transmission signal.

[0039] Furthermore, the first switching circuit 22 and the second switching circuit 32, which are not shown in the figures, may have a totem-pole circuit structure in which switching elements are arranged in upper and lower arms, and may control the output in two stages in accordance with the input gate control signal. Specifically, they may be configured as a push-pull circuit in which the high-side element is an NPN transistor and the low-side element is a PNP transistor, as described above, or other configurations may be adopted.

[0040] FIG. 2 is a diagram illustrating a specific configuration of first control circuit 21 and second control circuit 31 according to the first embodiment.

[0041] 2, the first control circuit 21 includes a control unit 21A and a delay circuit 21B. The control unit 21A receives the external drive signal IN1 as an input signal and generates a conditioned signal. This can be realized, for example, by a capacitor for maintaining voltage, a diode element for preventing reverse conduction, and a Schmitt trigger element for conditioned transmission signals.

[0042] The delay circuit 21B receives the output signal of the control unit 21A, delays the output signal by a certain amount of time, and generates a delayed signal. For example, it may be a delay line that delays the transmission signal by a certain amount of time, and the delay line may be composed of a logic IC or a buffer element.

[0043] By configuring the first control circuit 21 in this manner, the gate control signal input to the first switching circuit 22 shown in FIG. 1 is delayed by a certain amount of time relative to the external drive signal IN1. The operation of the first switching circuit 22 can also be delayed by the same amount of time depending on the delay amount of the gate control signal. Therefore, the timing of the switching operation of the power semiconductor element 10 is also delayed by the same amount of time overall. Furthermore, the gate delay amount of the power semiconductor element 10 can be variably set by providing multiple terminals per element for the logic IC and buffer element that make up the delay line, setting separate delay amounts for the logic IC and buffer element, or even switching the circuit connection destination using a jumper pin.

[0044] The second control circuit 31 includes delay circuits 31A and 31B, inverters IV0 and IV1, AND circuits AD0 and AD1, and a NOR circuit NR.

[0045] The AND circuit AD0 receives the external drive signal IN1 via the delay circuit 31A and the external drive signal IN1 via the inverter IV0, and outputs the result of the AND logic operation to the NOR circuit NR.

[0046] The AND circuit AD1 receives the external drive signal IN2 via the delay circuit 31B and the inverter IV1, and outputs the result of an AND logic operation to the NOR circuit NR.

[0047] The NOR circuit NR receives the inputs of the AND circuits AD0 and AD1 and outputs the result of a NOR logic operation.

[0048] The delay circuits 31A and 31B are delay circuits that generate delay signals. For example, they may be configured with an RC filter, which is a general delay time adjustment circuit, or, even better, with a Schmitt trigger element that adjusts the transmission signal. The delay amounts of the delay circuits 31A and 31B can be adjusted to different values.

[0049] The NOR circuit NR normally outputs an off-bias voltage control signal ("1"), which turns on the NPN transistor 32A of the second switching circuit 32.

[0050] On the other hand, in response to the change of the external drive signal IN1 from "1" to "0," the AND circuit AD0 outputs a one-shot pulse signal proportional to the delay amount of the delay circuit 31 A. In response to this, the NOR circuit NR turns on the PNP transistor 32B of the second switching circuit 32 in response to the period of the one-shot pulse signal.

[0051] Furthermore, in response to the external drive signal IN2 changing from "0" to "1," the AND circuit AD1 outputs a one-shot pulse signal proportional to the delay amount of the delay circuit 31B. In response to this, the NOR circuit NR turns on the PNP transistor 32B of the second switching circuit 32 in response to the period of the one-shot pulse signal.

[0052] The second control circuit 31 is a logic operation circuit that receives two external drive signals IN1 and IN2, performs logical operations such as logical sum (OR) or logical product (AND) on the two signals, and generates one off-bias voltage control signal from the two output signals. For example, it may be configured with a discrete IC element containing only one element, or it may be configured with a 2-in-1 logic IC having two logic functions. It may also be configured with at least one AND element and one OR element that perform logical operations.

[0053] By providing delay circuits 31A and 31B, it is possible to generate an off-bias voltage control signal according to external drive signal IN1 and external drive signal IN2 and adjust the time of this signal.

[0054] Specifically, it is possible to determine the application timing and application duration of the deep off-bias Vneg to be applied to the gate of the power semiconductor element 10 according to the delay amount of the delay circuits 31A and 31B. Furthermore, the resistors and capacitors of the RC filters of the delay circuits 31A and 31B may be configured with variable resistors or variable capacitors. With such a configuration, it becomes possible to variably set the application timing and application duration of the deep off-bias Vneg to the power semiconductor element 10.

[0055] According to the first embodiment, the first control circuit 21 included in the gate voltage control circuit 20 is provided with the control unit 21A and the delay circuit 21B, and the second control circuit 31 included in the off-bias voltage control circuit 30 is provided with the delay circuits 31A and 31B, thereby making it possible to generate an appropriate off-bias level control signal and determine the application timing and application time of the deep off-bias Vneg of the power semiconductor element 10. As a result, the reliability of the power semiconductor element 10 is improved.

[0056] Next, a description will be given of a specific operation of gate drive circuit 100 according to the first embodiment. Fig. 3 is a timing chart illustrating the operation of gate drive circuit 100 according to the first embodiment when controlling the gate of power semiconductor device 10.

[0057] 3 shows differences in operation between gate drive circuit 100 according to the first embodiment and a comparative example. The horizontal axis represents time, and the vertical axis represents external drive signal IN1, external drive signal IN2, and gate voltage Vgs of power semiconductor device 10, respectively.

[0058] At time t0, in response to the change of the external drive signal IN1 from "1" to "0", the gate drive circuit 100 begins discharging the gate of the power semiconductor device 10. That is, the power semiconductor device 10 performs a turn-off operation. Since the gate charge that was charged during the turn-on operation is extracted, the gate voltage Vgs of the power semiconductor device begins to drop.

[0059] First, the gate voltage Vgs drops sharply from the on-bias voltage Vdd. Next, the drain-source voltage Vds (not shown) of the power semiconductor device 10 starts to rise, and at the same time, the gate voltage Vgs maintains a certain voltage value. This period is called the mirror period, and continues until the change in the gate-drain parasitic capacitance dependent on the drain-source voltage Vds disappears (generally, for SiC-MOSFETs, the mirror period is very short). After the mirror period ends, the gate voltage Vgs starts to drop again, and when it reaches the deep off-bias Vneg, the turn-off operation ends. Here, there is a significant difference between the gate drive circuit according to the first embodiment and the comparative example (here, the configuration according to Patent Document 1).

[0060] The biggest difference is the presence or absence of a deep off-bias Vneg. The gate drive circuit 100 according to the first embodiment has the function of applying a deep off-bias Vneg to the gate, and therefore the turn-off speed of the power semiconductor device 10 is faster than that of the comparative example, which does not have the deep off-bias application function. In the sections from time t0 to the start of the mirror period and from the end of the mirror period to the end of the turn-off operation, the absolute value of the rate of change dVgs / dt of the gate voltage Vgs is larger in the configuration according to the first embodiment than in the configuration of the comparative example.

[0061] This effect makes it possible to improve the turn-off loss of the power semiconductor device 10, and provides the advantages of suppressing heat generation in the power conversion device and reducing the size of the cooler.

[0062] On the other hand, in the configuration according to the comparative example, the turn-off operation is performed with a shallow off-bias Vs, and there is a concern that the turn-off loss of the power semiconductor device 10 may not be sufficiently reduced. Furthermore, there are differences in the behavior of the gate voltage Vgs after the turn-off operation is completed.

[0063] Since the configuration according to the first embodiment has a deep off-bias Vneg, the gate voltage Vgs drops from the shallow off-bias Vs to the deep off-bias Vneg.

[0064] In the gate drive circuit 100 according to the first embodiment, the turn-off operation of the power semiconductor device 10 is completed at time t1 when the gate voltage Vgs reaches the deep off-bias Vneg.

[0065] According to the configuration of gate drive circuit 100 according to the first embodiment, a deep off-bias Vneg is applied to the gate of power semiconductor device 10 from time t1, which may cause the aforementioned stress on the gate oxide film to deteriorate characteristics or cause a malfunction. However, the period from time t1 to time t2, when the deep off-bias Vneg begins to return to the shallow off-bias Vs, is sufficiently shorter than the dead time Td (when both the upper arm and the lower arm are turned off) set in the inverter circuit of the power conversion device. In other words, the actual stress on the gate oxide film is very small. Therefore, high reliability of power semiconductor device 10 can be ensured.

[0066] In this example, during the period from time t0 to time t2, a deep off-bias Vneg is applied to the gate of the power semiconductor device 10. This period is defined as a first period. Next, the period after time t2 will be described.

[0067] During the dead time period Td, the gate voltage Vgs of the power semiconductor device 10 is set to a shallow off-bias Vs, and the external drive signals IN1 and IN2 are set to "0".

[0068] Here, the external drive signal IN2 has a function of informing the timing of the gate misfiring of the power semiconductor element 10, that is, the timing of turning on the opposing arm element.

[0069] Therefore, the external drive signal IN2 changes from "0" to "1" at the end of the dead time period Td.

[0070] The gate drive circuit 100 determines that it is time to turn on the opposing arm element of the power semiconductor element 10 in accordance with a change in the external drive signal IN2, and again changes the gate voltage Vgs of the power semiconductor element 10 from the shallow off-bias Vs to the deep off-bias Vneg. Then, as the opposing arm element turns on, the gate voltage Vgs of the power semiconductor element 10 rises from the deep off-bias Vneg. By setting the value of the deep off-bias Vneg to be greater than the voltage value of the rise of the gate voltage Vgs, the gate voltage Vgs does not exceed 0 V. In other words, there is sufficient margin for the gate threshold voltage of the power semiconductor element 10.

[0071] Here, the period t on from time t3 until the opposing arm element of the power semiconductor element 10 actually starts turning on corresponds to the delay amount of the gate control signal to the opposing arm element. Since it takes time for the deep off-bias Vneg applied to the gate voltage Vgs of the power semiconductor element 10 to be established, a delay is inserted in the gate control signal to the opposing arm element. In this way, it is possible to completely prevent erroneous gate firing of the power semiconductor element 10.

[0072] At time t4 after the opposing arm element of power semiconductor element 10 has finished turning on, the gate voltage Vgs of power semiconductor element 10 begins to return from the deep off-bias Vneg to the shallow off-bias Vs again. In other words, the stress on the gate oxide film of power semiconductor element 10 is very small. That is, the deep off-bias Vneg is applied to the gate of power semiconductor element 10 during the period from time t3 to time t4. Here, the period from the end of dead time period Td to the time when the shallow off-bias is applied to the gate of power semiconductor element 10 is defined as the second period. In other words, the period from time t3 to time t4 is included in the second period.

[0073] The gate drive circuit 100 according to the first embodiment improves switching loss by applying a deep off-bias to the power semiconductor element 10, while limiting the application time of the deep off-bias to the limited sections of the first period and the second period, thereby improving the reliability of the power semiconductor element 10. This leads to a longer life of the power semiconductor element, and makes it possible to realize an economical power converter system.

[0074] Second Embodiment In a second embodiment, the operation of a gate drive circuit 101 including a gate resistance control circuit 40 between the power semiconductor element 10 and the first switching circuit 22 will be described.

[0075] 4 is a diagram illustrating a gate drive circuit 101 according to the second embodiment. Referring to Fig. 4, gate drive circuit 101 differs from gate drive circuit 100 according to the first embodiment in that a gate resistance control circuit 40 is provided between power semiconductor element 10 and first switching circuit 22. Since the other configurations are similar, detailed description thereof will not be repeated.

[0076] The gate resistance control circuit 40 includes a gate resistance 41 and a bypass switching element 42 connected in parallel across the gate resistance 41 .

[0077] The gate resistor 41 adjusts the switching speed of the power semiconductor device 10, more specifically, the turn-on speed and the turn-off speed.

[0078] When the resistance value of the gate resistor 41 is large, the surge voltage of the drain-source voltage Vds and electromagnetic noise during switching can be reduced, but the switching loss increases. Conversely, when the resistance value of the gate resistor 41 is small, the relationship between the surge voltage of the drain-source voltage Vds, electromagnetic noise, and switching loss is the opposite of when the resistance value is large.

[0079] The bypass switching element 42 performs a turn-on operation and a turn-off operation in response to an ON / OFF command of a gate control signal. The bypass switching element 42 is connected in parallel to the gate resistor 41. After the bypass switching element 42 turns on, the gate current flows through the bypass switching element 42, and after the bypass switching element 42 turns off, the gate current flows through the gate resistor 41.

[0080] The timing when bypass switching element 42 according to the second embodiment is turned on to bypass gate resistor 41 is when the gate off-bias level is switched between deep off-bias Vneg and shallow off-bias Vs.

[0081] Specifically, in the first period, the bypass switching element 42 maintains its off operation until the turn-off operation of the power semiconductor element 10 is completed, and then, from the point when the turn-off operation of the power semiconductor element 10 is completed and the deep off-bias Vneg is established, the bypass switching element 42 is turned on until it is switched to the shallow off-bias Vs.

[0082] As an example, the bypass switching element 42 is turned on during the period from time Tb1 to time Tb2.

[0083] Similarly, the timing for turning off the bypass switching element 42 according to the second embodiment and switching to the path via the gate resistor 41 is from the point at which the dead time period Td ends and the shallow off-bias Vs is switched to the deep off-bias Vneg in preparation for the turn-on operation of the opposing arm element, until the start of the turn-on operation of the opposing arm element.

[0084] Specifically, in the second period, from the shallow off-bias Vs to the establishment of the deep off-bias Vneg, the bypass switching element 42 maintains its on operation, and before the opposing arm element turns on, the bypass switching element 42 is turned off.

[0085] As an example, the bypass switching element 42 is turned on during the period from time T3 to time Tb3.

[0086] By operating the bypass switching element 42 as described above, a bypass path that does not go through the gate resistor 41 is utilized only for switching between the deep off-bias Vneg and the shallow off-bias Vs applied to the gate of the power semiconductor element 10.

[0087] As described above, in the first embodiment, the second switching circuit 32 operates in conjunction with the first switching circuit 22. In other words, the switching speed between the deep off-bias Vneg and the shallow off-bias Vs depends on the circuit constant of the discharge path of the power semiconductor element 10. In other words, if the value of the gate resistor 41 is large, the switching speed between the deep off-bias Vneg and the shallow off-bias Vs will be slower accordingly. In the second embodiment, by providing a bypass path that does not pass through the gate resistor 41, it is possible to increase the switching speed between the deep off-bias Vneg and the shallow off-bias Vs. In other words, it is possible to suitably control the level and timing of the off-bias applied to the gate of the power semiconductor element 10.

[0088] Furthermore, the gate resistor 41 is effective against false gate firing. If the gate resistor 41 has a small value (for example, 0 ohms), oscillations due to the stray inductance component of the gate wiring of the power semiconductor device 10 may occur, which may cause false gate firing. Furthermore, the device may be more susceptible to electromagnetic noise, which may also trigger false gate firing. To prevent these phenomena, the bypass switching device 42 is turned off, and a path via the gate resistor 41 is set, during false gate firing, i.e., during the turn-on operation of the opposing arm device.

[0089] Next, a description will be given of a specific operation of gate drive circuit 101 according to embodiment 2. Fig. 5 is a diagram illustrating a timing chart when gate drive circuit 101 according to embodiment 2 controls the gate of a power semiconductor element.

[0090] Referring to FIG. 5, the basic operations of gate drive circuit 101 according to the second embodiment and gate drive circuit 100 according to the first embodiment are similar, and therefore detailed description thereof will not be repeated.

[0091] At time t0, the turn-off operation of the power semiconductor device 10 begins. As shown in the figure, the gate voltage of the power semiconductor device 10 is lowered to the deep off-bias Vneg, and the deep off-bias Vneg is established at time t1. Thereafter, at time t2, the deep off-bias Vneg is switched to the shallow off-bias Vs in order to shorten the application time of the deep off-bias Vneg.

[0092] Here, the difference from the gate drive circuit 100 according to the first embodiment is that the bypass switching element 42 is turned on at time tb1 within the interval between time t1 and time t2 included in the first period. By adding the operation of this embodiment at time tb1, the gate voltage of the power semiconductor element 10 changes at time t2. Specifically, the switching speed from the deep off-bias Vneg to the shallow off-bias Vs is increased, and a quick return to the shallow off-bias Vs is possible, as shown in the figure. Because the return to the shallow off-bias Vs is quick, the application time of the deep off-bias Vneg can be reliably shortened compared to the first embodiment. At time tb2, the bypass switching element 42 is turned off.

[0093] After the dead time period Td has elapsed, the external drive signal IN2 indicating the timing of the turn-on operation of the opposing arm element changes from "0" to "1." That is, the dead time period Td ends at time t3.

[0094] At time t3, the gate voltage of the power semiconductor device 10 switches again from the shallow off-bias Vs to the negative bias Vneg.

[0095] At time t3, the bypass switching element 42 is turned on. As a result, the speed of switching from the shallow off-bias Vs to the deep off-bias Vneg is faster than in the first embodiment because the gate resistor 41 is bypassed, and as shown in the figure, it is possible to quickly apply the deep off-bias Vneg to the gate of the power semiconductor element 10.

[0096] Then, at time tb3, the bypass switching element 42 is turned off.

[0097] At a subsequent time t on , the opposing arm element turns on, causing erroneous firing of the gate of the power semiconductor element 10. Here, at a time tb3 within the section between the time t3 and the time t on included in the second period, the bypass switching element 42 turns off.

[0098] In this way, by adding the operation of the gate resistance control circuit 40 according to the second embodiment at time tb3, it is possible to prevent the erroneous gate firing of the power semiconductor element 10 due to the influence of the stray inductance and electromagnetic noise described above. Specifically, by turning off the bypass switching element 42 and providing the gate resistor 41, it is possible to obtain the same erroneous gate firing tolerance as in the first embodiment, as shown in the figure.

[0099] During the period after time tb2 of the dead time period Td, i.e., during the off-bias period of the power semiconductor device 10, the gate resistance control circuit 40 turns off the bypass switching device 42 to connect the gate resistor 41. By keeping the gate resistor 41 connected in this manner even during the off-bias period of the power semiconductor device 10, it is possible to damp gate vibrations caused by external factors. As a result, it is possible to prevent erroneous gate firing of the power semiconductor device 10.

[0100] The on-operation period (tb1-tb2, t3-tb3) of the bypass switching element 42 can be set using the components described in embodiment 1. Specifically, this can be achieved by combining an RC filter that delays the period from time t0 to tb1 and the logical operation circuit described in embodiment 1 that creates a one-shot pulse using external drive signals IN1 and IN2. Furthermore, the on-operation period (bypass period) of the bypass switching element 42 can also be set arbitrarily, and it is also possible to switch between on and off operations at multiple locations.

[0101] The gate resistor 41 is composed of circuit elements such as general lead resistors and chip resistors, and may have circuit constants and power capacities that conform to the switching operation conditions of the power semiconductor element 10. The number of circuit elements constituting the gate resistor 41 may be single or multiple, and may be configured in series or parallel. An inexpensive discrete circuit element is sufficient for the bypass switching element 42 as long as it can accommodate the gate capacitance of the power semiconductor element 10. The faster the response speed of the bypass switching element 42, the more desirable it is. A higher gate threshold voltage reduces the risk of malfunction but decreases the fast response speed, while a lower gate threshold voltage improves the fast response speed but increases the risk of malfunction.

[0102] The gate drive circuit 101 according to the second embodiment includes the gate resistance control circuit 40 between the power semiconductor element 10 and the first switching circuit 22, thereby making it possible to further shorten the period of time during which the deep off-bias Vneg is applied to the gate of the power semiconductor element 10. Furthermore, by speeding up the switching from the shallow off-bias Vs to the deep off-bias Vneg, the reliability of the power semiconductor element 10 is further improved.

[0103] Therefore, the life of the power semiconductor device 10 can be further extended, and the use of economical power converter systems can be promoted.

[0104] Third Embodiment In a third embodiment, a configuration of a switching circuit different from that in the first embodiment will be described.

[0105] FIG. 6 is a block diagram for illustrating the function of gate drive circuit 100# of a power semiconductor device according to the third embodiment.

[0106] Referring to FIG. 6, gate drive circuit 100# differs from gate drive circuit 100 in that gate voltage control circuit 20 is replaced with gate voltage control circuit 20# and off-bias voltage control circuit 30 is replaced with off-bias voltage control circuit 30#.

[0107] The other configuration is similar to that of gate drive circuit 100 according to the first embodiment, and therefore detailed description thereof will not be repeated.

[0108] Gate voltage control circuit 20# differs from gate voltage control circuit 20 in that first control circuit 21 is replaced with a first control circuit 21# and first switching circuit 22 is replaced with a first switching circuit 22#.

[0109] Off-bias voltage control circuit 30# differs from off-bias voltage control circuit 30 in that second control circuit 31 is replaced with second control circuit 31# and second switching circuit 32 is replaced with second switching circuit 32#.

[0110] The first switching circuit 22# includes a PMOSFET 22P on the high side and an NMOSFET 22N on the low side.

[0111] The PMOSFET 22P and the NMOSFET 22N are connected in series. The PMOSFET 22P is connected to a positive voltage source Vdd and to an output node.

[0112] The NMOSFET 22N is connected to the output node and the output node of the second switching circuit 32.

[0113] The second switching circuit 32# includes a PMOSFET 32P on the high side and an NMOSFET 32N on the low side.

[0114] The PMOSFET 32P and the NMOSFET 32N are connected in series. The PMOSFET 32P is connected to the source electrode of the power semiconductor device 10 and to the output node. The output node is connected to the first switching circuit 22#.

[0115] The NMOSFET 32N is connected to the output node and the negative voltage supply Vneg. The switching circuit according to the third embodiment is particularly effective for a power conversion device that uses, for example, a wide bandgap semiconductor and is used for high-frequency drive applications.

[0116] A CMOS circuit according to the third embodiment, which is configured by a PMOSFET 22P and an NMOSFET 22N, and a PMOSFET 32P and an NMOSFET 32N, will be described.

[0117] Because both the upper and lower arm elements are composed of MOSFETs, power consumption is lower than when they are composed of bipolar transistors. Also, as the switching frequency of the power inverter increases, the number of switching times of the gate drive circuit also increases accordingly. In other words, this is extremely useful for the high-frequency drive applications mentioned above.

[0118] The output lines of the PMOSFET 22P and NMOSFET 22N swing between the power supply voltage Vdd applied to the high side of the PMOSFET 22P and the low side potential (shallow off-bias Vs or deep off-bias Vneg). Furthermore, a constant driving capability is obtained regardless of the difference between the input voltage from the power supply voltage and the output voltage of the output line. This type of drive output makes it possible to realize a gate drive circuit 100# that has high driving capability and high stability.

[0119] On the other hand, in a typical push-pull circuit, the swing range of the output line is narrowed by the gate threshold voltage of the upper and lower arm transistor elements. In other words, when the output voltage is outside the swing range, the output of the push-pull circuit becomes floating, resulting in unstable operation.

[0120] Gate drive circuit 100# according to the third embodiment can achieve high drive capability and stable operation by implementing a switching circuit using a CMOS circuit. These effects are expected to improve the characteristics of power semiconductor device 10 and also lead to suppression of oscillation caused by fluctuations in the gate potential.

[0121] Although the advantages of CMOS circuits have been described above, they also have disadvantages. When the upper and lower arm elements are switched, a through current may flow between the high-side power supply voltage and the low-side reference potential. This through current may increase the power consumption of the gate drive circuit 100. The increased power consumption means that the circuit is unsuitable for high-frequency drive operation, which contradicts the advantages mentioned above.

[0122] Therefore, a dead time period between the upper and lower arms may be generated in the upstream stages of the PMOSFET 22P, NMOSFET 22N and the PMOSFET 32P, NMOSFET 32N. By providing an appropriate dead time period, it is possible to reduce the through current flowing into the CMOS circuit. For example, the signals applied to the gates of the PMOSFET 22P, NMOSFET 22N and the PMOSFET 32P, NMOSFET 32N may be controlled independently.

[0123] 7 is a diagram illustrating the specific configuration of first control circuit 21# and second control circuit 31# according to embodiment 3. The basic element configurations are similar to those of first control circuit 21 and second control circuit 31 shown in FIG. 2, so repeated description will be omitted.

[0124] Referring to FIG. 7, first control circuit 21# includes a control unit 21A# and a delay circuit 21B#.

[0125] Second control circuit 31# includes delay circuits 31A# and 31B#, an inverter IV, an AND circuit AD, and an OR circuit OR.

[0126] AND circuit AD receives external drive signal IN2 that has passed through delay circuit 31B# and inverter IV, and external drive signal IN2 that has not passed through any elements or additional circuits, and outputs the result of an AND logic operation to OR circuit OR.

[0127] OR circuit OR receives external drive signal IN1 via delay circuit 31A# and the input of AND circuit AD, and outputs the OR logic operation result.

[0128] Delay circuits 31A# and 31B# are delay circuits that generate delay signals. For example, they may be configured with an RC filter, which is a general delay time adjustment circuit, or, even better, with a Schmitt trigger element that adjusts the transmission signal. The delay amounts of delay circuits 31A# and 31B# can be adjusted to different values.

[0129] The OR circuit OR outputs an off-bias voltage control signal ("1") when the power semiconductor element 10 is in a steady on state with no switching operation, and outputs an off-bias voltage control signal ("0") when the power semiconductor element 10 is in a steady off state with no switching operation.

[0130] As a result, PMOSFET 32P of second switching circuit 32# repeatedly turns on and off at regular intervals.

[0131] On the other hand, during the transitional timing of the switching operation, the output of the off-bias voltage control signal changes in a complex manner. As the external drive signal IN1 changes from "1" to "0," the OR circuit OR maintains the output of "1" for a period proportional to the delay amount of the delay circuit 31A#. In response to this, the OR circuit OR turns on the NMOSFET 32N of the second switching circuit 32# in response to the period during which the output of "1" is maintained.

[0132] Furthermore, in response to the change of external drive signal IN2 from "0" to "1," AND circuit AD outputs a one-shot pulse signal proportional to the delay amount of delay circuit 31B#, and in response to this, OR circuit OR turns on NMOSFET 32N of second switching circuit 32# in response to the period of the one-shot pulse signal.

[0133] According to this embodiment, a PMOSFET 22P and an NMOSFET 22N are provided inside a first control circuit 21 included in a gate voltage control circuit 20, and a PMOSFET 32P and an NMOSFET 32N are provided inside a second control circuit 31 included in an off-bias voltage control circuit 30. This makes it possible to bring out the high characteristics of the power semiconductor device 10 while suppressing gate oscillation and other problems that are an issue in high-frequency applications.

[0134] It is also possible to further apply the configuration of the gate resistance control circuit 40 according to the second embodiment.

[0135] Fourth Embodiment In a fourth embodiment, another mode for controlling the off-bias level applied to the gate of the power semiconductor element 10 will be described.

[0136] FIG. 8 is a diagram illustrating the waveform of the gate voltage Vgs of a SiC-MOSFET to which the gate drive circuit 100 of the present disclosure is applied.

[0137] 8 shows the case where the period during which the deep off-bias is applied is adjusted. Here, the gate on-bias is set to +20 V, the shallow off-bias Vs is set to 0 V, and the deep off-bias Vneg is set to -5 V. All driving conditions were the same except for the period of the deep off-bias Vneg.

[0138] The waveform LA shows a case where the off-bias application period is shorter than that of the waveform LB, that is, these waveforms differ in the period of the deep off-bias Vneg.

[0139] The period of the deep off-bias Vneg is adjusted by adjusting the time constant of the RC filter that constitutes the delay circuit included in the off-bias voltage control circuit 30.

[0140] Specifically, the amount of delay of the delay circuit is adjusted by adjusting the capacitance of the capacitor, thereby adjusting the application period of the off bias.

[0141] Specifically, when two types of capacitance, 470 pF and 680 pF, are provided as the capacitor capacitance of the delay circuit, by setting the capacitance of the capacitor to "470 pF", it is possible to shorten the period of the deep off-bias Vneg, which makes it possible to further reduce the stress on the gate oxide film.

[0142] For example, by using a variable capacitance element as the capacitor, it is possible to set the optimum capacitance of the capacitor and adjust the period of the off-bias Vneg to an optimum period.

[0143] Fifth Embodiment In a fifth embodiment, another mode of operation of the gate drive circuit 100 including the gate resistance control circuit 40 according to the second embodiment will be described.

[0144] FIG. 9 is a timing chart illustrating the gate drive circuit 101 according to the fifth embodiment controlling the gate of the power semiconductor element.

[0145] Referring to FIG. 9, the basic operations of gate drive circuit 101 according to the fifth embodiment and gate drive circuit 100 according to the second embodiment are similar, and therefore detailed description thereof will not be repeated.

[0146] Compared with the timing chart of FIG. 5, during the period between times tb4 and tb5 located between times ton and t4, the bypass switching element 42 included in the gate resistance control circuit 40 described in FIG. 3 is turned on.

[0147] 9, the gate voltage Vgs of the power semiconductor element 10 is quickly switched from the deep off-bias Vneg to the shallow off-bias Vs, thereby reliably shortening the application time of the deep off-bias Vneg to the gate of the power semiconductor element 10.

[0148] The time tb4 at which the bypass switching element 42 turns on is set to occur between the time when the turn-on operation of the opposing arm element of the power semiconductor element 10 ends and time t4. This setting suppresses oscillation of the gate of the power semiconductor element 10 during the turn-on period of the opposing arm element, making it possible to avoid the risk of false firing. This also makes it possible to obtain the effect of shortening the application time of the deep off-bias Vneg of the power semiconductor element 10.

[0149] This embodiment can be realized by adding an additional element to the configuration shown in Fig. 4. The additional element controls the gate resistance control circuit 40 so that the value of the gate resistance 41 decreases, and provides a function to determine the time tb3 that is the timing for turning on the bypass switching element 42.

[0150] Specifically, time tb4 is determined by utilizing timing information about time ton, which is the timing of the turn-on operation of the opposing arm element of power semiconductor element 10.

[0151] For example, timing information about time t on can be obtained by providing an overvoltage detection circuit or a voltage change rate dVds / dt detection circuit between the drain electrode and source electrode of the power semiconductor element 10. Alternatively, a gate current detection circuit may be connected in series adjacent to the gate resistance control circuit 40. By synchronizing the detection information of these detection circuits with the signal of the second control circuit 31 included in the off-bias voltage control circuit 30, it is possible to adjust the appropriate timing of time tb3.

[0152] Alternatively, a state timer with a time set in advance may be provided in the second control circuit 31 included in the off-bias voltage control circuit 30. Time tb4 may be set by measuring the time required for the opposing arm element of the power semiconductor element 10 to turn on, for example, through a preliminary experiment.

[0153] In the fifth embodiment, the timing at which the bypass switching element 42 included in the gate resistance control circuit 40 performs the turn-on operation is further added to the configuration according to the second embodiment. This makes it possible to more suitably achieve a reduction in the application time of the deep off-bias Vneg applied to the gate of the power semiconductor element 10.

[0154] Sixth Embodiment In a sixth embodiment, the configuration of the integrated driving circuit 102 will be described.

[0155] FIG. 10 is a block diagram for explaining the function of the integrated driving circuit 102 according to the sixth embodiment.

[0156] Referring to FIG. 10 , the integrated drive circuit 102 according to the sixth embodiment is different from the gate drive circuit 100 in that it includes two drive circuits, a gate drive circuit 100P and a gate drive circuit 100N, and is an integrated circuit that incorporates these two gate drive circuits.

[0157] The integrated type means, for example, that upper and lower arms are integrated in which power semiconductor elements are connected in series, and as shown in FIG. 10, it is possible to apply it to the configuration of a half-bridge circuit often seen in power modules in which power semiconductor elements are packaged in a 2-in-1 configuration.

[0158] The power semiconductor elements 10P and 10N are connected in series to each other, and a single drive circuit called an integrated drive circuit 102 drives the power semiconductor elements of the upper and lower arms.

[0159] The input signals are external drive signals IN1 and IN2. As explained in the first embodiment, the external drive signal IN may be a logic pulse signal in which the external drive signal IN is set to "1" during the period when the corresponding power semiconductor element should be turned on, and the external drive signal IN is set to "0" during the period when the corresponding power semiconductor element should be turned off.

[0160] Here, external drive signal IN1 controls the gate of power semiconductor element 10P, which is the upper arm element, and is input to gate voltage control circuit 20P. External drive signal IN2 controls the gate of power semiconductor element 10N, which is the lower arm element, and is input to gate voltage control circuit 20N.

[0161] As explained in the first embodiment, an external drive signal IN2 is input to the off-bias voltage control circuit 30P to notify the timing of the turn-on operation of the power semiconductor element 10N of the lower arm element, which is the opposing arm element. An external drive signal IN1 is input to the off-bias voltage control circuit 30N to notify the timing of the turn-on operation of the power semiconductor element 10P of the upper arm element, which is the opposing arm element.

[0162] With this configuration, the same operation as that of the gate drive circuit 100 described in the first embodiment is executed.

[0163] The gate drive circuits 100P and 100N included in the integrated drive circuit 102 basically have the same circuit configuration, but if there is variation in the element characteristics between the power semiconductor elements 10P and 10N of the upper and lower arm elements, fine adjustments may be made internally in the off-bias voltage control circuits 30P and 30N. For example, by adjusting the timing of the deep off-bias Vneg and the shallow off-bias Vs for the off-bias voltage control circuits 30P and 30N, more suitable operation of the power semiconductor elements can be achieved.

[0164] In the sixth embodiment, external drive signals IN1 and IN2 are provided with insulating elements such as photocouplers or insulating transformers, or isolation elements with sufficient dielectric strength are provided inside gate voltage control circuits 20P and 20N and off-bias voltage control circuits 30P and 30N. The isolation elements may be multi-input, multi-output isolator ICs, and in such a configuration, the insulating process for gate voltage control circuit 20P and off-bias voltage control circuit 30P can be shared.

[0165] The positive voltage source Vdd_P supplied to the gate drive circuit 100P is always configured as an isolated power source, and the potential of the positive voltage source Vdd_P is a floating potential with respect to the ground potential. The deep off-bias Vneg_P and shallow off-bias Vs_P provided inside the gate drive circuit 100P are also floating potentials with respect to the ground potential. Because the positive voltage source Vdd_P is a floating power source, any potential may be created using, for example, a three-terminal regulator, and an appropriate deep off-bias Vneg_P and shallow off-bias Vs_P may be generated.

[0166] By satisfying this configuration, the power semiconductor element 10P, which corresponds to the upper arm in the half-bridge circuit, can be operated electrically safely by the gate drive circuit 100P included in the integrated drive circuit 102.

[0167] In this example, the configuration of a half-bridge circuit will be described, but the method according to the fifth embodiment can also be applied to a power module for a three-phase inverter in which power semiconductor elements are packaged in a 6-in-1 configuration.

[0168] The configuration according to the sixth embodiment includes an integrated drive circuit 102 that integrates the drive circuits for the upper and lower arms to drive the upper and lower arm elements in the half-bridge circuit of the power conversion device. As a result, it is possible to drive the upper arm element power semiconductor element 10P and the lower arm element power semiconductor element 10N with a simple circuit configuration, without the need for additional external drive signals or complex measures.

[0169] Seventh Embodiment In a seventh embodiment, the power conversion device according to the above-described embodiment is applied to a power conversion system. Although the present disclosure is not limited to a specific power conversion device, the following describes a case in which the present disclosure is applied to a three-phase inverter as the seventh embodiment.

[0170] FIG. 11 is a block diagram showing a configuration of a power conversion system according to a seventh embodiment. Referring to FIG. 11 , the power conversion system according to the seventh embodiment includes a power supply 1000, a power conversion device 1001, and a load 1004. The power supply 1000 is a DC power supply and supplies DC power to the power conversion device 1001. The power supply 1000 can be configured from various elements, such as a DC system, a solar cell, or a storage battery, or it may be configured from a rectifier circuit connected to an AC system or an AC / DC converter. Furthermore, the power supply 1000 may be configured from a DC / DC converter that converts DC power output from the DC system into predetermined power.

[0171] The power conversion device 1001 is a three-phase inverter connected between the power supply 1000 and the load 1004, and converts DC power supplied from the power supply 1000 into AC power and supplies the AC power to the load 1004. The power conversion device 1001 includes a main conversion circuit 1002 that converts DC power into AC power and outputs it, and a control circuit 1003 that outputs a control signal to the main conversion circuit 1002 to control the main conversion circuit 1002.

[0172] The load 1004 is a three-phase motor driven by AC power supplied from the power conversion device 1001. The load 1004 is not limited to a specific application, but is a motor mounted on various electrical devices, and is used as, for example, a motor for a hybrid vehicle, an electric vehicle, a railcar, an elevator, or an air conditioning device.

[0173] The following describes the details of the power conversion device 1001. The main conversion circuit 1002 includes power semiconductor elements and freewheeling diodes (not shown), and by switching the power semiconductor elements, converts DC power supplied from the power source 1000 into AC power, which is supplied to the load 1004.

[0174] Although there are various specific circuit configurations for the main conversion circuit 1002, the main conversion circuit 1002 according to the embodiment is a two-level, three-phase full-bridge circuit that can be configured with six power semiconductor elements and six freewheeling diodes connected in anti-parallel to each power semiconductor element. Two of the six power semiconductor elements are connected in series to form upper and lower arms, each of which constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 1002, are connected to a load 1004.

[0175] The main conversion circuit 1002 can be configured to use the gate drive circuits described in the first to sixth embodiments for driving the respective power semiconductor elements.

[0176] The gate drive circuit generates gate control signals that drive the power semiconductor elements of main conversion circuit 1002 and supplies them to the control electrodes of the power semiconductor elements of main conversion circuit 1002. Specifically, control circuit 1003 outputs to the control electrodes of each power semiconductor element an external drive signal that turns the power semiconductor element on and an external drive signal that turns the power semiconductor element off. When maintaining a switching element in the on state, the external drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the power semiconductor element, and when maintaining a switching element in the off state, the external drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the power semiconductor element.

[0177] The control circuit 1003 controls the power semiconductor elements of the main conversion circuit 1002 so that the desired power is supplied to the load 1004. Specifically, it calculates the time (on time) that each power semiconductor element of the main conversion circuit 1002 should be in the on state based on the power to be supplied to the load 1004. For example, the main conversion circuit 1002 can be controlled by PWM control, which modulates the on time of the power semiconductor elements according to the voltage to be output. Then, it outputs a control command (external drive signal) to the gate drive circuit provided in the main conversion circuit 1002 so that an on signal is output to the power semiconductor elements that should be in the on state at each point in time, and an off signal is output to the power semiconductor elements that should be in the off state.

[0178] In the power conversion device according to the embodiment, the above-described gate drive circuit constituting main conversion circuit 1002 is applied, and therefore reliability can be improved.

[0179] In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used. In addition, when supplying power to a single-phase load, the present disclosure may also be applied to a single-phase inverter. Furthermore, when supplying power to a DC load, etc., the present disclosure may also be applied to a DC / DC converter or an AC / DC converter.

[0180] Furthermore, the power conversion device to which the present disclosure is applied is not limited to cases in which the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0181] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. Furthermore, it goes without saying that there is no problem in suitably combining a plurality of embodiments, and it is desirable to enhance the effects of each embodiment to make efficient and economical use of the power conversion device.

[0182] The scope of the present disclosure is defined by the claims, rather than the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0183] 10, 10N, 10P Power semiconductor element, 20, 20N, 20P Gate voltage control circuit, 21 First control circuit, 22 First switching circuit, 30, 30N, 30P Off bias voltage control circuit, 31 Second control circuit, 32 Second switching circuit, 40 Gate resistance control circuit, 41 Gate resistor, 42 Bypass switching element, 100, 100N, 100P, 101 Gate drive circuit, 102 Integrated drive circuit, 1000 Power supply, 1001 Power conversion device, 1002 Main conversion circuit, 1003 Control circuit, 1004 Load.

Claims

1. a gate voltage control circuit that applies an on-bias and an off-bias to a gate terminal of the power semiconductor element in accordance with a first drive signal; an off-bias voltage control circuit that changes a voltage level of an off-bias in accordance with the first drive signal and the second drive signal, and controls an application period of the changed off-bias.

2. The off-bias voltage control circuit includes: changing a voltage level of the off-bias during a first period in accordance with the first drive signal during which the off-bias is applied; 2. The semiconductor device according to claim 1, wherein a voltage level of said off-bias is changed during a second period in accordance with said second drive signal during which said off-bias is applied.

3. the second drive signal is a control signal for applying an on-bias and an off-bias to a gate terminal of a power semiconductor element on an opposing arm connected in series with the power semiconductor element, 3. The semiconductor device according to claim 2, wherein said second period includes a period of time following a dead time period until a turn-on operation of said power semiconductor element on said opposing arm is completed.

4. 2. The semiconductor device according to claim 1, wherein said off-bias voltage control circuit sets a first off-bias to a second off-bias lower than said first off-bias in accordance with said first and second drive signals.

5. 2. The semiconductor device according to claim 1, further comprising a gate resistance control circuit provided between said power semiconductor element and said gate voltage control circuit, said gate resistance control circuit controlling said power semiconductor element.

6. 6. The semiconductor device according to claim 5, wherein said gate resistance control circuit controls said gate resistance when changing a voltage level of said off-bias.

7. 7. The semiconductor device according to claim 6, wherein said gate resistance control circuit sets said gate resistance large before changing a voltage level of said off-bias, and sets said gate resistance small when changing a voltage level of said off-bias.

8. The gate resistance control circuit includes: a resistor element provided between the power semiconductor device and the gate voltage control circuit; 6. The semiconductor device according to claim 5, further comprising a bypass circuit which bypasses said resistance element.

9. The off-bias voltage control circuit includes: a first delay circuit that delays the first drive signal; a second delay circuit that delays the second drive signal; a logic circuit that generates a switching signal based on a combination of the delay signal of the first delay circuit and the delay signal of the second delay circuit; 9. The semiconductor device according to claim 1, further comprising a switching circuit that changes a voltage level of an off-bias based on the switching signal.

10. A first power semiconductor device; a second power semiconductor device provided on an opposing arm side connected in series with the first power semiconductor device; first and second gate drive circuits provided corresponding to the first and second power semiconductor elements, respectively, for driving the corresponding power semiconductor elements in accordance with first and second drive signals; Each of the gate drive circuits includes: a gate voltage control circuit that applies an on-bias and an off-bias to a gate terminal of the power semiconductor element in accordance with a corresponding drive signal; an off-bias voltage control circuit that changes a voltage level of an off-bias in accordance with the first and second drive signals and controls an application period of the changed off-bias.