Low-voltage differential signal equipment and driver thereof

Abstract

An output circuit of the low-voltage differential signal equipment comprises a first current source and a differential push-pull output circuit, the first current source is connected between a power supply end and the differential push-pull output circuit, and the differential push-pull output circuit is connected with a differential output end of the driver. A first output voltage and a second output voltage are generated according to the first input signal and the second input signal; a turn-off circuit is connected with a differential output end of a driver and is used for turning off a first current source by using a short-circuited power supply on the differential output end when the driver is in a leakage protection state; a first end of a substrate clamping circuit of the low-voltage differential signal driver is connected with a power supply end, a second end of the substrate clamping circuit provides a substrate potential for an MOS tube in a first current source, and when the driver is in a leakage protection state, the substrate clamping circuit is in a turn-off state in the direction from the second end to the first end, so that when the low-voltage differential signal driver is in a power-off state, the substrate clamping circuit is in a turn-off state. And effective leakage protection can be carried out on the low-voltage differential signal driver.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low voltage differential signal device and a driver thereof. Background Art

[0002] LVDS (Low Voltage Differential Signaling) is a point-to-point high-speed differential electrical interface designed for applications requiring ultra-low power consumption, low noise, and high data rates.

[0003] Under normal circumstances, the LVDS interface circuit needs to meet the TIA / EIA-644-A standard issued by the United States Electronic Industry and Communications Industry Association. While stipulating the electrical and switching characteristics that the LVDS interface circuit needs to meet, this standard also stipulates the self-protection function required by the LVDS device, including that the LVDS device needs to have a small leakage current (in some cases, less than 20uA) in the case of an open circuit or short circuit that may exist at the output node. LVDS devices usually include an LVDS driver and a receiver. In the prior art LVDS driver, when the output node is short-circuited to the power supply terminal in the power-off state, a large leakage current will flow into the LVDS device, thereby failing to meet the self-protection requirements of the TIA / EIA-644-A standard.

[0004] Therefore, a new low voltage differential signal device and its driver are yet to be proposed to solve the above problems. Summary of the invention

[0005] In view of the above problems, an object of the present invention is to provide a low voltage differential signal device and a driver thereof, so that when the low voltage differential signal driver is in a power-off state, the low voltage differential signal driver can also be effectively protected from leakage.

[0006] According to one aspect of the present invention, there is provided a low-voltage differential signal driver, comprising an output circuit, including a first current source and a differential push-pull output circuit, wherein the first current source is connected between a power supply terminal and the differential push-pull output circuit, the differential push-pull output circuit is connected to a differential output terminal of the driver and is used to generate a first output voltage and a second output voltage according to a first input signal and a second input signal; a shutdown circuit, which is connected to the differential output terminal of the driver and is used to shut down the first current source by using a short-circuited power supply on the differential output terminal when the driver is in a leakage protection state; and a substrate clamping circuit, wherein a first end of the substrate clamping circuit is connected to the power supply terminal and a second end of the substrate clamping circuit provides a substrate potential for a MOS tube in the first current source, and when the driver is in a leakage protection state, the substrate clamping circuit is in a shutdown state in a direction from the second end to the first end.

[0007] Optionally, the differential push-pull output circuit includes a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, the first current source includes a third PMOS tube and a fourth PMOS tube connected sequentially between the power supply terminal and the first ends of the first PMOS tube and the second PMOS tube, the substrates of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all connected to the first voltage terminal, and the substrates of the first NMOS tube and the second NMOS tube are all connected to the second voltage terminal.

[0008] Optionally, the second end of the substrate clamping circuit is connected to the first voltage end; the shutdown circuit is connected to the control end of the fourth PMOS tube, and is used to shut down the fourth PMOS tube by using the short-circuited power supply on the differential output end to shut down the first current source when the driver is in a leakage protection state.

[0009] Optionally, the output circuit also includes a second current source, the first current source, the differential push-pull output circuit and the second current source are connected between the power supply terminal and the ground terminal in sequence, the second current source includes a third NMOS tube, the first end of the third NMOS tube is connected to the second ends of the first NMOS tube and the second NMOS tube, and the substrate of the third NMOS tube is connected to the second voltage terminal.

[0010] Optionally, the driver further includes an open circuit protection circuit, which is used to pull the power supply terminal down to the ground terminal when the power supply terminal is open circuit.

[0011] Optionally, the substrate clamping circuit includes a first transistor connected between the power supply terminal and the first voltage terminal, a control terminal of which is connected to the power supply terminal, and a substrate of which is connected to the second voltage terminal, and the second voltage terminal is a ground terminal.

[0012] Optionally, the shutdown circuit includes a second transistor connected between the control end and the positive differential output end of the fourth PMOS tube, whose control end is connected to the power supply end, and whose substrate is connected to the first voltage end; a third transistor connected between the control end and the negative differential output end of the fourth PMOS tube, whose control end is connected to the control end of the second transistor, and whose substrate is connected to the first voltage end.

[0013] Optionally, the substrate clamping circuit further includes a first resistor connected between the power supply terminal and the control terminal of the first transistor; and a second resistor connected between the second terminal of the first transistor and the first voltage terminal.

[0014] Optionally, the shutdown circuit also includes a third resistor connected between the power supply terminal and the control terminal of the second transistor; a fourth resistor connected between the second terminal of the second transistor and the positive differential output terminal; and a fifth resistor connected between the second terminal of the third transistor and the negative differential output terminal.

[0015] According to another aspect of the present invention, a low voltage differential signal device is provided, comprising the low voltage differential signal driver as described above; and a low voltage differential signal receiving end connected to the low voltage differential signal driver via a differential signal line.

[0016] The present invention provides a low voltage differential signal device and a driver thereof. The LVDS driver comprises an output circuit, a shutdown circuit and a substrate clamping circuit. The shutdown circuit is connected to the differential output end of the LVDS driver. The first end of the substrate clamping circuit is connected to the power supply end, and the second end provides a substrate potential for a MOS tube in a first current source. When the LVDS driver is in a leakage protection state, the shutdown circuit uses the short-circuited power supply on the differential output end to shut down the first current source, and the substrate clamping circuit is in a shutdown state in the direction from the second end to the first end, so that the LVDS driver can meet the self-protection requirements of the TIA / EIA-644-A standard. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0018] Figure 1 A circuit diagram of a low voltage differential signal driver is shown;

[0019] Figure 2 Shows Figure 1 The schematic diagram of leakage test of the low voltage differential signal driver shown is that the differential output terminal is short-circuited to the second power supply terminal when the low voltage differential signal driver is in the power-off state;

[0020] Figure 3 Shows Figure 1 The low voltage differential signal driver shown is in a power-off state, and the differential output terminal is short-circuited to the leakage schematic diagram of the second power supply terminal;

[0021] Figure 4 A circuit diagram of a low voltage differential signal driver according to an embodiment of the present invention is shown;

[0022] Figure 5 Shows Figure 4 The diagram shows leakage of a low voltage differential signal driver in which the differential output terminal is short-circuited to the second power supply terminal when the low voltage differential signal driver is in a power-off state. DETAILED DESCRIPTION

[0023] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements or modules are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0024] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0025] At the same time, certain words are used in this patent specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.

[0026] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0027] Figure 1 A circuit diagram of a low voltage differential signal driver is shown.

[0028] See also Figure 1, the LVDS driver 100 includes an output circuit and a common-mode feedback circuit. The output circuit includes transistors M1, M2, M4, M5 and M3 connected in sequence between a first power supply terminal and a ground terminal, and transistors M6 and M7 connected in sequence between an intermediate node of transistors M2 and M4 and an intermediate node of transistors M5 and M3. Transistors M1-M2, transistors M4 and M6 are PMOS transistors, whose substrates are all connected to the first power supply terminal, transistors M3, M5 and M7 are NMOS transistors, whose substrates are all connected to the ground terminal, control terminals of transistors M4-M5 receive input signals Vin1, control terminals of transistors M6-M7 receive input signals Vin2, control terminals of transistor M1 receive bias voltage Vbias1, control terminals of transistor M2 receive bias voltage Vbias2, intermediate nodes of transistors M6 and M7 provide output voltage Vout+ as a first output node, and intermediate nodes of transistors M4 and M5 provide output voltage Vout- as a second output node. The input signals Vin1 and Vin2 are inverted signals, and the ground terminal provides a ground voltage GND. The first power terminal is a chip power terminal, which provides a power supply voltage VDD. The first output node is connected to the positive differential output terminal of the LVDS driver 100, and the second output node is connected to the negative differential output terminal of the LVDS driver 100.

[0029] The common-mode feedback circuit includes an error amplifier 110 and resistors R1 and R2 connected in sequence between the positive differential output terminal and the negative differential output terminal of the LVDS driver 100. The positive input terminal of the error amplifier 110 is connected to the middle node of the resistors R1 and R2, the negative input terminal receives the reference voltage Vref, and the output terminal is connected to the control terminal of the transistor M3.

[0030] Furthermore, the positive differential output terminal and the negative differential output terminal of the LVDS driver 100 are also connected to the LVDS receiving terminal. The LVDS receiving terminal includes a terminal resistor Rt, capacitors CL1 and CL2, the terminal resistor Rt is connected between the positive differential output terminal and the negative differential output terminal, the capacitor CL1 is connected between the positive differential output terminal and the ground terminal, the capacitor CL2 is connected between the negative differential output terminal and the ground terminal, and the current flowing through the terminal resistor Rt is the driving current Iout.

[0031] The LVDS driver 100 uses the drain terminals of the PMOS tube M6 and the NMOS tube M7 to provide the output voltage Vout+, and the drain terminals of the PMOS tube M4 and the NMOS tube M5 to provide the output voltage Vout-, which can meet the requirements of large output drive current Iout and fast flipping of the output voltages Vout+ and Vout-. When the LVDS driver 100 is in a normal working state, the PMOS tube and the NMOS tube on the opposite side are alternately turned on (that is, when M4 and M7 are turned on, M5 and M6 are turned off, and when M5 and M6 are turned on, M4 and M7 are turned off), and the output current Is provided by the current source composed of the transistors M1 and M2 flows through the terminal resistor Rt through the transistors M4-M7, thereby obtaining the differential output voltages Vout+ and Vout-, and the positive and negative of the differential output voltages Vout+ and Vout- are related to the turning on and off of the transistors M4-M7.

[0032] Figure 2 Shows Figure 1 The schematic diagram of leakage test of the low voltage differential signal driver shown is that the differential output terminal is short-circuited to the second power supply terminal when the low voltage differential signal driver is in the power-off state; Figure 3 Shows Figure 1 The diagram shows leakage of a low voltage differential signal driver in which the differential output terminal is short-circuited to the second power supply terminal when the low voltage differential signal driver is in a power-off state.

[0033] See also Figure 2 and Figure 3 When the LVDS driver 100 is in a power-off state, if the differential output terminal (positive differential output terminal and / or negative differential output terminal) is short-circuited to the second power supply terminal, the LVDS driver 100 will have leakage. Take the case where the positive differential output terminal is short-circuited to the second power supply terminal when the LVDS driver 100 is in a power-off state as an example. At this time, the potential of the positive differential output terminal of the LVDS driver 100 is raised to the power supply voltage VDD1 of the second power supply terminal, and the first power supply terminal is in a suspended (open circuit) state or a short circuit state, resulting in a leakage current flowing from the positive differential output terminal to the first power supply terminal. The leakage path of the leakage current is positive differential output terminal-M6-M2-M1-first power supply terminal. In addition, at this time, the body diode between the drain and substrate of transistors M6 and M2 is forward biased, which will also generate leakage current, which will be injected into the substrate of transistors M1 and M2 and the source terminal of transistor M1, that is, the first power supply terminal. Therefore, the LVDS driver 100 cannot meet the self-protection requirements of the TIA / EIA-644-A standard, which affects the reliability of the entire LVDS device.

[0034] Figure 4 A circuit diagram of a low voltage differential signal driver according to an embodiment of the present invention is shown; Figure 5 Shows Figure 4The diagram shows leakage of a low voltage differential signal driver in which the differential output terminal is short-circuited to the second power supply terminal when the low voltage differential signal driver is in a power-off state.

[0035] See also Figure 4 and Figure 5 The LVDS driver 200 includes an output circuit 210 , a common-mode feedback circuit 220 , a substrate clamp circuit 230 , a shutdown circuit 240 , and an open-circuit protection circuit 250 .

[0036] The output circuit 210 is used to generate output voltages Vout+ and Vout- according to input signals Vin1 and Vin2. The output circuit 210 includes a first current source, a differential push-pull output circuit, and a second current source, which are sequentially connected between a first power supply terminal and a ground terminal, and the differential push-pull output circuit is connected to the differential output terminal of the LVDS driver 200. Among them, the first power supply terminal refers to the chip power supply terminal.

[0037] The first end of the substrate clamp circuit 230 is connected to the first power supply terminal, and the second end provides a substrate potential for the MOS tube in the first current source, and when the LVDS driver 200 is in the leakage protection state, the substrate clamp circuit 230 is in the off state in the direction from the second end to the first end. The second end of the substrate clamp circuit 230 is connected to the first voltage terminal A. The leakage protection state refers to the state in which the LVDS driver 200 is in the power-off state, and the differential output terminal (positive differential output terminal and / or negative differential output terminal) is short-circuited to the second power supply terminal.

[0038] The shut-down circuit 240 is connected to the differential output terminal of the LVDS driver 200 and is used to shut down the first current source by using the short-circuited power supply on the differential output terminal when the LVDS driver 200 is in the leakage protection state.

[0039] The differential push-pull output circuit includes a first PMOS tube M4, a second PMOS tube M6, a first NMOS tube M5, and a second NMOS tube M7, the first current source includes a third PMOS tube M1 and a fourth PMOS tube M2, and the second current source includes a third NMOS tube M3. The third PMOS tube M1, the fourth PMOS tube M2, the first PMOS tube M4, the first NMOS tube M5, and the third NMOS tube M3 are sequentially connected between the first power supply terminal and the ground terminal, the second PMOS tube M6 and the second NMOS tube M7 are sequentially connected between the middle node of the fourth PMOS tube M2 and the first PMOS tube M4 and the middle node of the first NMOS tube M5 and the third NMOS tube M3, the substrates of the first to fourth PMOS tubes are connected to the first voltage terminal A, and the substrates of the first to third NMOS tubes are connected to the second voltage terminal, and the second voltage terminal is, for example, the ground terminal. The control ends of the first PMOS tube M4 and the first NMOS tube M5 receive the input signal Vin1, the control ends of the second PMOS tube M6 and the second NMOS tube M7 receive the input signal Vin2, the middle node of the second PMOS tube M6 and the second NMOS tube M7 is used as the first output node to provide the output voltage Vout+, and the middle node of the first PMOS tube M4 and the first NMOS tube M5 is used as the second output node to provide the output voltage Vout-. Among them, the input signals Vin1 and Vin2 are inverted signals, the first power supply end provides the power supply voltage VDD, and the ground end provides the ground voltage GND. The first output node is connected to the positive differential output end of the LVDS driver 200, and the second output node is connected to the negative differential output end of the LVDS driver 200.

[0040] The shutdown circuit 230 is also connected to the control end of the fourth PMOS transistor M2 and is used to shut down the fourth PMOS transistor M2 by using the short-circuited power supply on the differential output end to shut down the first current source when the LVDS driver 200 is in the leakage protection state.

[0041] The common-mode feedback circuit 220 is used to compare the common-mode feedback voltage of the output voltages Vout+ and Vout- with the reference voltage Vref, and generate a control voltage Vc according to the comparison result, so as to adjust the output voltages Vout+ and Vout- through the control voltage Vc, so that the common-mode feedback voltage of the output voltages Vout+ and Vout- is stabilized near the reference voltage Vref.

[0042] The open circuit protection circuit 250 is used to pull the first power supply terminal down to the ground terminal when the LVDS driver 200 is in the power-off state and the first power supply terminal is in the open circuit state, so that the shutdown circuit 240 works normally. It can be understood that the open circuit protection circuit 250 can be implemented by any existing circuit that can pull the first power supply terminal down to the ground terminal when the LVDS driver 200 is in the power-off state and the first power supply terminal is in the open circuit state. For example, the open circuit protection circuit 250 is implemented by a resistor R1 connected between the first power supply terminal and the ground terminal.

[0043] The common mode feedback circuit 220 includes an error amplifier 221, and resistors R7 and R8 connected in sequence between the positive differential output terminal and the negative differential output terminal. The positive input terminal of the error amplifier 221 is connected to the middle node of the resistors R7 and R8, the negative input terminal receives the reference voltage Vref, and the output terminal is connected to the control terminal of the transistor M3 to provide the control voltage Vc to the control terminal of the transistor M3.

[0044] The substrate clamp circuit 230 includes a transistor M11 . The transistor M11 is connected between the first power supply terminal and the first voltage terminal A. The substrate of the transistor M11 is connected to the ground terminal. The control terminal of the transistor M11 is connected to the first power supply terminal.

[0045] The substrate clamp circuit 230 further includes a resistor R6 connected between the control terminal of the transistor M11 and the first power terminal, and a resistor R5 connected between the second terminal of the transistor M11 and the first voltage terminal A. The resistors R5 and R6 are used to implement electrostatic discharge (ESD) protection.

[0046] The shutdown circuit 240 includes transistors M12 and M13, the control ends of the transistors M12 and M13 are connected to the first power supply end, the first end of the transistor M12 and the first end of the transistor M13 are connected to the control end of the fourth PMOS transistor M2, the substrate of the transistor M12 and the substrate of the transistor M13 are connected to the first voltage end A, the second end of the transistor M12 is connected to the first output node, and the second end of the transistor M13 is connected to the second output node.

[0047] The shutdown circuit 240 further includes resistors R2-R4, wherein the resistor R2 is connected between the first power supply terminal and the control terminal of the transistor M12, the resistor R3 is connected between the second terminal of the transistor M12 and the first output node, and the resistor R4 is connected between the second terminal of the transistor M13 and the second output node. The resistors R2-R4 are used to implement electrostatic discharge (ESD) protection.

[0048] Optionally, transistors M12-M13 are also P-channel Metal-Oxide-Semiconductor (PMOS), and transistor M11 is also N-channel Metal-Oxide-Semiconductor (NMOS). The first end of the PMOS is the source, the second end is the drain, and the control end is the gate. The first end of the NMOS is the drain, the second end is the source, and the control end is the gate.

[0049] The working principle of the LVDS driver 200 is that when it is in a normal working state, the substrate of the PMOS tube is connected to the power supply voltage VDD through the transistor M11. At this time, the transistor M11 is used as a forward-conducting diode to provide a substrate potential slightly lower than the power supply voltage VDD for the first voltage terminal A, so that the normal operation of the LVDS driver 200 is not affected. The gate voltage Vb of the transistors M12 and M13 is pulled up to the power supply voltage VDD, and the transistors M12 and M13 are turned off. At the same time, the gate voltage of the fourth PMOS tube M2 depends on the bias voltage Vbias2, so that the fourth PMOS tube M2 works normally, and the current flowing through the resistor R1 is equivalent to a constant static working current, which does not affect the normal operation of the LVDS driver 200.

[0050] When the LVDS driver 200 is in the leakage protection state, if the first power supply terminal is short-circuited to the ground voltage GND, the gate voltage Vb of the transistors M12 and M13 is pulled to the ground voltage GND, the transistors M12 and M13 are turned on, and the gate voltage Va of the fourth PMOS tube M2 is pulled up by the high voltage of the differential output terminal, so that the fourth PMOS tube M2 is in the off state, and therefore, the leakage path leading to the source end of the fourth PMOS tube M2 is cut off. In addition, at this time, the leakage current introduced by the forward conduction of the drain-substrate diodes of the PMOS tubes M2, M4, M6 and M12-M13 flows to the source end of the transistor M11 through the resistor R5, and the gate voltage of the transistor M11 is pulled down by the first power supply terminal, so that the transistor M11 is in the off state, and the parasitic diode between the source end and the substrate of the transistor M11 is in the reverse bias state, so there is no leakage current flowing into the first power supply terminal through the transistor M11. Therefore, when the first power supply terminal is short-circuited to the ground terminal, the LVDS driver 200 has no leakage path leading to the first power supply terminal, forcing the leakage current to be in a very small state; if the first power supply terminal is open, since the gate voltage Vb of the transistors M12 and M13 is in an uncertain state at this time, the transistors M12 and M13 may not be turned on, and the leakage current flows into the first power supply terminal through the source terminal of the transistor M2, thereby causing a large leakage current. Therefore, at this time, it is necessary to set the resistor R1 to pull the first power supply terminal down to the ground terminal, thereby turning on the transistors M12 and M13, so that the shutdown circuit 240 can work normally.

[0051] When the LVDS driver 200 provided by the embodiment of the present invention is in the leakage protection state, the shutdown circuit 240 uses the short-circuited power supply on the differential output end to shut down the first current source, and the substrate clamp circuit is in the shutdown state in the direction from the second end to the first end, so that the LVDS driver 200 can meet the self-protection requirements of the TIA / EIA-644-A standard.

[0052] It is understandable that the present invention also provides an LVDS device, the LVDS device includes an LVDS driver 200 and an LVDS receiving end, and the LVDS driver 200 and the LVDS receiving end are connected via a differential data line. Figure 1 The LVDS receiver is shown.

[0053] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.

Claims

1. A low voltage differential signal driver, comprising: An output circuit, comprising a first current source and a differential push-pull output circuit, wherein the first current source is connected between a power supply terminal and the differential push-pull output circuit, the differential push-pull output circuit is connected to a differential output terminal of the driver, and is used to generate a first output voltage and a second output voltage according to a first input signal and a second input signal; A shut-down circuit connected to the differential output terminal of the driver, and configured to shut down the first current source by using the short-circuited power supply on the differential output terminal when the driver is in a leakage protection state; A substrate clamp circuit, wherein a first end is connected to the power supply end, and a second end provides a substrate potential for the MOS tube in the first current source, and when the driver is in a leakage protection state, the substrate clamp circuit is in an off state in the direction from the second end to the first end.

2. The driver according to claim 1, wherein: The differential push-pull output circuit includes a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, the first current source includes a third PMOS tube and a fourth PMOS tube which are sequentially connected between the power supply terminal and the first ends of the first PMOS tube and the second PMOS tube, the substrates of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all connected to the first voltage terminal, and the substrates of the first NMOS tube and the second NMOS tube are all connected to the second voltage terminal.

3. The driver according to claim 2, wherein: The second end of the substrate clamp circuit is connected to the first voltage end; The shutdown circuit is connected to the control end of the fourth PMOS tube and is used to shut down the fourth PMOS tube by using the short-circuited power supply on the differential output end to shut down the first current source when the driver is in a leakage protection state.

4. The driver according to claim 2, wherein: The output circuit further includes: a second current source, wherein the first current source, the differential push-pull output circuit and the second current source are sequentially connected between the power supply terminal and the ground terminal, The second current source includes a third NMOS tube, a first end of the third NMOS tube is connected to the second ends of the first NMOS tube and the second NMOS tube, and a substrate of the third NMOS tube is connected to the second voltage end.

5. The driver according to claim 1, further comprising: The open circuit protection circuit is used to pull the power supply terminal down to the ground terminal when the power supply terminal is open circuited.

6. The driver according to claim 3, wherein: The substrate clamping circuit comprises: The first transistor is connected between the power supply terminal and the first voltage terminal, a control terminal of the first transistor is connected to the power supply terminal, and a substrate of the first transistor is connected to the second voltage terminal, and the second voltage terminal is a ground terminal.

7. The driver according to claim 4, wherein: The shutdown circuit comprises: A second transistor is connected between the control terminal and the positive differential output terminal of the fourth PMOS transistor, the control terminal of which is connected to the power supply terminal, and the substrate of which is connected to the first voltage terminal; The third transistor is connected between the control terminal of the fourth PMOS tube and the negative differential output terminal, the control terminal of the third transistor is connected to the control terminal of the second transistor, and the substrate of the third transistor is connected to the first voltage terminal.

8. The driver according to claim 6, wherein: The substrate clamping circuit further comprises: A first resistor connected between the power supply terminal and the control terminal of the first transistor; The second resistor is connected between the second end of the first transistor and the first voltage end.

9. The driver according to claim 7, wherein: The shutdown circuit further comprises: a third resistor connected between the power supply terminal and the control terminal of the second transistor; a fourth resistor, connected between the second end of the second transistor and the positive differential output end; A fifth resistor is connected between the second terminal of the third transistor and the negative differential output terminal.

10. A low voltage differential signal device, comprising: The low voltage differential signal driver according to any one of claims 1 to 9; as well as The low voltage differential signal receiving end is connected to the low voltage differential signal driver through a differential signal line.

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