Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor that can suppress the occurrence of peeling between internal electrode layers at the ends of a laminated body, even if a dielectric layer etc. is made thin.　A multilayer ceramic capacitor according to the present invention comprises: a laminated body that has a plurality of dielectric layers which are laminated and a plurality of internal electrode layers which are laminated on the dielectric layers, and that has a first main surface and second main surface which are opposite from each other in the lamination direction, a first end surface and a second end surface which are opposite from each other in the length direction orthogonal to the lamination direction, and a first side surface and a second side surface which are opposite from each other in the width direction orthogonal to the lamination direction and the length direction; a first external electrode that is disposed on the first end surface; and a second external electrode that is disposed on the second end surface. The plurality of internal electrode layers have a plurality of first internal electrode layers and a plurality of second internal electrode layers which are disposed alternatingly on different dielectric layers. The plurality of first internal electrode layers have a plurality of first counter electrode parts that are opposite from the second internal electrode layers and a plurality of first lead-out parts that respectively extend from the plurality of first counter electrode parts and that lead out to the first end surface. The second internal electrode layers have a plurality of second counter electrode parts that are opposite from the first internal electrode layers and a plurality of second lead-out parts that respectively extend from the plurality of second counter electrode parts and that lead out to the first side surface. The first lead-out parts have first connection parts connected so as to span to at least two first lead-out parts in the lamination direction, between first lead-out parts positioned on differing dielectric layers of at least the first main surface side or at least the second main surface side. The second lead-out parts have second connection parts connected so as to span to at least two second lead-out parts in the lamination direction, between second lead-out parts positioned on differing dielectric layers of at least the first main surface side or at least the second main surface side.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors have been known as multilayer ceramic electronic components. Generally, multilayer ceramic capacitors include a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes are provided on both end surfaces of the laminate. For example, Patent Document 1 discloses a multilayer ceramic capacitor having the above-described structure and including a base electrode layer on which external electrodes are formed by baking (see Patent Document 1).

[0003] In recent years, the trend toward lower impedance in electronic circuit lines, particularly in mobile device products, has accelerated, and there is a demand for higher capacitance multilayer ceramic capacitors for decoupling applications, such as those described in Patent Document 1. A common method for increasing the capacitance of a multilayer ceramic capacitor is to increase the number of laminated internal electrode layers by thinning the dielectric layers and internal electrode layers.

[0004] Japanese Patent Application Laid-Open No. 2003-243249

[0005] However, when the number of stacked internal electrode layers is increased by thinning the dielectric layers and internal electrode layers, in the inner layer portion formed by stacking multiple internal electrode layers and the outer layer portion formed by stacking only multiple dielectric layers, if a balling phenomenon occurs in which the internal electrode layers aggregate in the lengthwise and widthwise directions due to the heat generated during firing of the laminate and expand in the height direction (stacking direction) to increase in thickness, the tensile stress in the height direction increases at the end face portion and outer layer portion, which are structural singular points of the inner layer portion, and peeling may become more likely to occur between the internal electrode layers.

[0006] The present invention has been made in view of such problems, and aims to provide a multilayer ceramic capacitor that can suppress the occurrence of peeling between internal electrode layers at the ends of the laminate, even when the dielectric layers and the like are thinned.

[0007] A multilayer ceramic capacitor according to the present invention comprises a laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the laminate having first and second main faces opposing each other in the lamination direction, first end faces and second end faces opposing each other in a length direction perpendicular to the lamination direction, and first and second side faces opposing each other in a width direction perpendicular to the lamination direction and the length direction, a first external electrode arranged on the first end face, and a second external electrode arranged on the second end face, wherein the plurality of internal electrode layers have a plurality of first internal electrode layers and a plurality of second internal electrode layers alternately arranged on different dielectric layers, and the plurality of first internal electrode layers have a plurality of first opposing electrode portions opposing the second internal electrode layers, and each of the plurality of first opposing electrode portions the second internal electrode layer has a plurality of second opposing electrode portions facing the first internal electrode layer and a plurality of second opposing electrode portions extending from each of the plurality of second opposing electrode portions and being drawn to the first side surface, the first leading portions have first connection portions connected to straddle at least two or more first leading portions in the stacking direction between the first leading portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side, and the second leading portions have second connection portions connected to straddle at least two or more second leading portions in the stacking direction between the second leading portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side.

[0008] According to the multilayer ceramic capacitor of the present invention, the first lead portions of the first internal electrode layers have first connection portions that are connected to straddle at least two or more first lead portions in the stacking direction between first lead portions that are arranged on different dielectric layers located on at least one of the first main surface side and the second main surface (12b) side, and the second lead portions of the second internal electrode layers have second connection portions that are connected to straddle at least two or more second lead portions in the stacking direction between second lead portions that are arranged on different dielectric layers located on at least one of the first main surface side and the second main surface (12b) side. Therefore, it is possible to improve the adhesion strength between the internal electrode layers between the first lead portions located on different dielectric layers and between the second lead portions located on different dielectric layers in the first lead portions of the first internal electrode layers and the second lead portions located on different dielectric layers in the first lead portions of the first internal electrode layers and the second lead portions of the second internal electrode layers that are located on both main surface sides where peeling of the multilayer ceramic capacitor is likely to occur. As a result, even if the heat generated during firing of the laminate causes the internal electrode layers to aggregate laterally and expand vertically, increasing their thickness, resulting in a balling phenomenon, the internal electrode layers are firmly connected to each other in the portions of the laminate's end faces and on both main surfaces where peeling is likely to occur, thereby preventing peeling between the internal electrode layers.

[0009] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can suppress the occurrence of peeling between internal electrode layers at the ends of the laminate even when the dielectric layers and the like are thinned.

[0010] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0011] 1 is an external perspective view showing an example of a two-terminal multilayer ceramic capacitor according to a first embodiment of the present invention. 2 is a front view showing an example of a two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention. 3 is a cross-sectional view taken along line III-III in FIG. 1. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. 5 is a cross-sectional view taken along line V-V in FIG. 3. 6 is an enlarged view showing a configuration of a connection portion of the two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention in region R1 in FIG. 3. 7 is an external perspective view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. 8 is a top view showing an example of a three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. 9 is a front view showing an example of a three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. 10 is a cross-sectional view taken along line X-X in FIG. 7. 11 is a cross-sectional view taken along line XI-XI in FIG. 11. 12 is a cross-sectional view taken along line XII-XII in FIG. 11.

[0012] A. First Embodiment 1. Two-Terminal Multilayer Ceramic Capacitor A two-terminal multilayer ceramic capacitor 10 will be described as a multilayer ceramic capacitor according to a first embodiment of the present invention with reference to FIGS. 1 to 5. FIG.

[0013] Fig. 1 is an external perspective view showing an example of a two-terminal multilayer ceramic capacitor according to a first embodiment of the present invention. Fig. 2 is a front view showing an example of a two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 1. Fig. 5 is a cross-sectional view taken along line VV in Fig. 3. Fig. 6 is an enlarged view showing the configuration of a connection portion of the two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention in region R1 in Fig. 3.

[0014] As shown in FIGS. 1 to 4, a two-terminal multilayer ceramic capacitor 10 includes a laminate 12 and external electrodes 30 disposed on the surfaces of the laminate 12 .

[0015] As shown in FIGS. 1 to 4, a two-terminal multilayer ceramic capacitor 10 includes a rectangular parallelepiped laminate 12 and external electrodes 30 disposed on both ends of the laminate 12 .

[0016] The laminate 12 includes a plurality of dielectric layers 14 stacked together and a plurality of internal electrode layers 16 stacked on the dielectric layers 14. The laminate 12 further includes a first main surface 12a and a second main surface 12b facing in a stacking direction x, a first side surface 12c and a second side surface 12d facing in a width direction y perpendicular to the stacking direction x, and a first end surface 12e and a second end surface 12f facing in a length direction z perpendicular to the stacking direction x and the width direction y. The corners and ridges of the laminate 12 are rounded. The corners refer to the intersections of three adjacent surfaces of the laminate, and the ridges refer to the intersections of two adjacent surfaces of the laminate. Furthermore, unevenness may be formed on some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f. The dielectric layers 14 and the internal electrode layers 16 are stacked in the height direction.

[0017] The laminate 12 has an internal layer portion 18 composed of one or more dielectric layers 14 and multiple internal electrode layers 16 disposed thereon. The internal electrode layers 16 have first internal electrode layers 16a extending to the first end face 12e and second internal electrode layers 16b extending to the second end face 12f, and in the internal layer portion 18, the multiple first internal electrode layers 16a and second internal electrode layers 16b face each other with the dielectric layer 14 interposed therebetween.

[0018] The laminate 12 has a first main surface side outer layer portion 20a located on the first main surface 12a side and formed of a plurality of dielectric layers 14 located between the first main surface 12a and the outermost surface of the inner layer portion 18 on the first main surface 12a side and a line aligned with that outermost surface. Similarly, the laminate 12 has a second main surface side outer layer portion 20b located on the second main surface 12b side and formed of a plurality of dielectric layers 14 located between the second main surface 12b and the outermost surface of the inner layer portion 18 on the second main surface 12b side and a line aligned with that outermost surface.

[0019] The laminate 12 has a first side surface side outer layer portion 22a located on the first side surface 12c side and formed from a plurality of dielectric layers 14 located between the first side surface 12c and the outermost surface of the inner layer portion 18 on the first side surface 12c side. Similarly, the laminate 12 has a second side surface side outer layer portion 22b located on the second side surface 12d side and formed from a plurality of dielectric layers 14 located between the second side surface 12d and the outermost surface of the inner layer portion 18 on the second side surface 12d side. The first side surface side outer layer portion 22a and the second side surface side outer layer portion 22b are also referred to as W gaps or side gaps.

[0020] The laminate 12 has a first end face side outer layer portion 24a located on the first end face 12e side and formed from a plurality of dielectric layers 14 located between the first end face 12e and the outermost surface of the inner layer portion 18 on the first end face 12e side. Similarly, the laminate 12 has a second end face side outer layer portion 24b located on the second end face 12f side and formed from a plurality of dielectric layers 14 located between the second end face 12f and the outermost surface of the inner layer portion 18 on the second end face 12f side. The first end face side outer layer portion 24a and the second end face side outer layer portion 24b are also referred to as L gaps or end gaps.

[0021] The first main surface side outer layer portion 20a is located on the first main surface 12a side of the laminate 12, and is an assembly of multiple dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a. The dielectric layers 14 used in the first main surface side outer layer portion 20a may be the same as the dielectric layers 14 used in the internal layer portion 18. The second main surface side outer layer portion 20b is located on the second main surface 12b side of the laminate 12, and is an assembly of multiple dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b.

[0022] The dielectric layer 14 can be formed of, for example, a ceramic dielectric material. Examples of such dielectric materials include dielectric ceramics containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When the dielectric material is a primary component, it may contain a secondary component, such as a manganese compound, an iron compound, a chromium compound, a cobalt compound, or a nickel compound, in a smaller amount than the primary component, depending on the desired properties of the laminate 12.

[0023] The dimensions of the laminate 12 are not particularly limited.

[0024] The dielectric layer 14 can be formed of, for example, a ceramic dielectric material. Examples of such dielectric materials include dielectric ceramics containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When the dielectric material is a primary component, it may contain a secondary component, such as a manganese compound, an iron compound, a chromium compound, a cobalt compound, or a nickel compound, in a smaller amount than the primary component, depending on the desired properties of the laminate 12.

[0025] The thickness of the dielectric layer 14 in the laminate 12 after firing is preferably about 0.5 μm or more and 10.0 μm or less.

[0026] The number of dielectric layers 14 to be laminated is preferably 15 to 700. However, this number of dielectric layers 14 is the total number of the dielectric layers 14 constituting the inner layer portion 18 and the dielectric layers of the first and second outer layer portions 20 a and 20 b.

[0027] The laminate 12 has a plurality of first internal electrode layers 16a and a plurality of second internal electrode layers 16b as the plurality of internal electrode layers 16. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are substantially parallel to the first main surface 12a and the second main surface 12b, and are embedded so as to be alternately arranged with the dielectric layer 14 sandwiched between them along the lamination direction x of the laminate 12.

[0028] The first internal electrode layer 16a is disposed on the plurality of dielectric layers 14 and is located inside the laminate 12. The first internal electrode layer 16a has a first opposing electrode portion 26a that faces the second internal electrode layer 16b, and a first lead portion 28a that is located on one end side of the first internal electrode layer 16a and extends from the first opposing electrode portion 26a to the first end face 12e of the laminate 12. Therefore, the ends of the plurality of first lead portions 28a are led out to the surface of the first end face 12e and are exposed from the laminate 12.

[0029] The shape of the first opposing electrode portion 26a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first opposing electrode portion 26a may be tapered in plan view, with a slope increasing in either direction.

[0030] The shape of the first lead portion 28a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first lead portion 28a may be tapered in plan view, with a slope increasing in either direction.

[0031] The width of the first opposing electrode portion 26a of the first internal electrode layer 16a and the width of the first lead-out portion 28a of the first internal electrode layer 16a may be formed to be the same width, or one of the widths may be formed to be narrower.

[0032] The second internal electrode layer 16b is disposed on the plurality of dielectric layers 14 and is located inside the laminate 12. The second internal electrode layer 16b has a second opposing electrode portion 26b that faces the first internal electrode layer 16a, and a second lead portion 28b that is located on one end side of the second internal electrode layer 16b and extends from the second opposing electrode portion 26b to the second end face 12f of the laminate 12. Therefore, the ends of the plurality of second lead portions 28b are led to the surface of the second end face 12f and are exposed from the laminate 12.

[0033] The shape of the second opposing electrode portion 26b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second opposing electrode portion 26b may be tapered in plan view, with a slope increasing in either direction.

[0034] The shape of the second lead portion 28b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second lead portion 28b may be tapered in plan view, with a slope increasing in either direction.

[0035] The width of the second opposing electrode portion 26b of the second internal electrode layer 16b and the width of the second lead-out portion 28b of the second internal electrode layer 16b may be formed to be the same width, or one of the widths may be formed to be narrower.

[0036] FIG. 6 shows the configuration of the connection portion of the two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention in the region R1 of FIG.

[0037] The first lead portion 28a has a first connection portion 29a that is connected and arranged so as to span at least two or more first lead portions 28a in the stacking direction between first lead portions 28a that are arranged on different dielectric layers 14 located on at least one of the first main surface 12a side and the second main surface 12b side.

[0038] The second lead portion 28b has a second connection portion 29b that is connected and arranged so as to span at least two or more second lead portions 28b in the stacking direction between second lead portions 28b that are arranged on different dielectric layers 14 located on at least one of the first main surface 12a side and the second main surface 12b side.

[0039] The first connection portion 29a is preferably located closer to the first end face 12e than half the dimension of the first end face side outer layer portion 24a in the length direction z. The second connection portion 29b is preferably located closer to the second end face 12f than half the dimension of the second end face side outer layer portion 24b in the length direction z. This directly improves the adhesion strength between the internal electrode layers 16 at a location where stress concentration due to a balling phenomenon, in which the internal electrode layers 16 aggregate laterally and expand in the height direction to increase in thickness due to heat during firing of the laminate 12, is most likely to occur.

[0040] It is preferable that a plurality of first connection portions 29 a and a plurality of second connection portions 29 b are present. This directly improves the adhesive strength between the internal electrode layers 16 at locations where stress concentration due to a balling phenomenon, in which the internal electrode layers 16 aggregate laterally and expand in the height direction to increase in thickness due to heat during firing of the laminate 12, is most likely to occur.

[0041] The first connecting portion 29a is preferably located on the first main surface 12a side excluding the center portion in the stacking direction of the inner layer portion 18, and on the second main surface 12b side excluding the center portion in the stacking direction of the inner layer portion 18. The second connecting portion 29b is preferably located on the first main surface 12a side excluding the center portion in the stacking direction x of the inner layer portion 18, and on the second main surface 12b side excluding the center portion in the stacking direction of the inner layer portion 18. This makes it possible to maintain the ceramic strength of the laminate 12 in the central portion in the stacking direction of the inner layer portion 18, where the lead portions of the internal electrode layers 16 are present, while suppressing the occurrence of peeling between the internal electrode layers 16. Therefore, it is possible to suppress the occurrence of cracks, chips, or the like in the laminate 12 of the two-terminal multilayer ceramic capacitor 10 when an external impact is applied to the two-terminal multilayer ceramic capacitor 10, while suppressing the occurrence of peeling between the internal electrode layers 16.

[0042] In this case, the dimension t2 in the stacking direction of the center of the inner layer portion 18 in the stacking direction x, which is an area where the first connecting portion 29a is not arranged, is preferably 25% to 75% of the dimension t1 in the stacking direction of the inner layer portion 18. Furthermore, the dimension t2 in the stacking direction of the center of the inner layer portion 18 in the stacking direction, which is an area where the second connecting portion 29b is not arranged, is preferably 25% to 75% of the dimension t1 in the stacking direction of the inner layer portion 18.

[0043] Here, if the dimension t2 in the stacking direction of the center of the stacking direction of the inner layer portion 18 in the region where the first connecting portion 29a and the second connecting portion 29b are not arranged becomes smaller than 25% of the dimension t1 in the stacking direction of the inner layer portion 18, there is a concern that when an external impact is applied to the two-terminal multilayer ceramic capacitor 10, cracks, chips, or the like will occur in the laminate 12 of the two-terminal multilayer ceramic capacitor 10. Furthermore, when the dimension t2 in the stacking direction of the center in the stacking direction of the inner layer portion 18 in the region where the first connecting portion 29 a and the second connecting portion 29 b are not arranged becomes larger than 75% of the dimension t1 in the stacking direction of the inner layer portion 18, it may not be possible to ensure sufficient adhesion strength between the internal electrode layers 16 between the first leading portions 28 a located on different dielectric layers 14 and between the second leading portions 28 b located on different dielectric layers 14 in the leading portions of the internal electrode layers 16 of the inner layer portion 18 located on the main surface-side outer layer portions 20 a, 20 b sides where peeling of the two-terminal multilayer ceramic capacitor 10 is likely to occur.

[0044] The dimension of the first connection portion 29a in the length direction z connecting the first end face 12e and the second end face 12f is preferably 3% to 97% of the thickness of the first lead portion 28a of the first internal electrode layer 16a. The dimension of the second connection portion 29b in the length direction z connecting the first end face 12e and the second end face 12f is preferably 3% to 97% of the thickness of the second lead portion 28b of the second internal electrode layer 16b. This makes the electrical resistance higher than that of the internal electrode layer 16 and makes it difficult for current to flow, thereby preventing changes in electrical characteristics due to the presence of the first connection portion 29a and the second connection portion 29b and suppressing peeling between the internal electrode layers 16.

[0045] The first connecting portion 29 a and the second connecting portion 29 b may be arranged continuously in the width direction y within the region where the first internal electrode layer 16 a and the second internal electrode layer 16 b of the two-terminal multilayer ceramic capacitor 10 are arranged, as shown in FIG. 5 , or may be arranged discontinuously, although not shown.

[0046] The first connecting portions 29a and the second connecting portions 29b are preferably concentrated in the center in the width direction y of the two-terminal multilayer ceramic capacitor 10. This makes it possible to further ensure the adhesive strength between the internal electrode layers 16 at the center in the width direction y of the two-terminal multilayer ceramic capacitor 10.

[0047] The first connecting portion 29 a and the second connecting portion 29 b are confirmed by the following method. That is, the two-terminal multilayer ceramic capacitor 10 is polished to a position ½W of the dimension in the width direction y of the two-terminal multilayer ceramic capacitor 10 so as to be parallel to the first side surface 12 c or the second side surface 12 d, thereby exposing the LT cross section. The exposed LT cross section is then observed, and the first connecting portion 29 a and the second connecting portion 29 b are confirmed using an electron microscope.

[0048] The measurement method for the length direction z of the first connecting portion 29a and the second connecting portion 29b, which connects the first end face 12e and the second end face 12f, is as follows. Specifically, to measure the length direction z of the first connecting portion 29a and the second connecting portion 29b, first, the two-terminal multilayer ceramic capacitor 10 is polished to a position ½W of the width direction y of the two-terminal multilayer ceramic capacitor 10 so that the two-terminal multilayer ceramic capacitor 10 is parallel to the first side face 12c or the second side face 12d, thereby exposing the LT cross section. The exposed LT cross section is then observed, and the first connecting portion 29a and the second connecting portion 29b are observed using an electron microscope, and the length direction z of the first connecting portion 29a and the second connecting portion 29b is measured. Specifically, in the internal electrode layer 16 located on the first main surface 12a side, the dimensions in the longitudinal direction z connecting the first end face 12e and the second end face 12f of the first connection portion 29a and the second connection portion 29b existing in the first tenth layer from the first main surface 12a toward the second main surface 12b, or the dimensions in the longitudinal direction z connecting the first end face 12e and the second end face 12f of the first connection portion 19a and the second connection portion 29b existing in the internal electrode layer 16 located on the second main surface 12b side from the second main surface 12b toward the first main surface 12a, are measured, and the average value is used as the dimension in the longitudinal direction z of the first connection portion 29a and the second connection portion 29b.

[0049] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0050] The thickness of each of the first internal electrode layer 16a and the second internal electrode layer 16b is not particularly limited, but is preferably, for example, about 0.4 μm or more and 0.8 μm or less.

[0051] The number of each of the first internal electrode layers 16a and the second internal electrode layers 16b is not particularly limited, but is preferably 2 or more and 1000 or less in total.

[0052] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0053] Next, external electrodes 30 are provided on the first side surface 12c, the second side surface 12d, the first end surface 12e side, and the second end surface 12f side of the laminate 12, as shown in FIGS.

[0054] The external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0055] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed on at least the surface of the first end face 12e. The first external electrode 30a also extends from the first end face 12e of the laminate 12 and is disposed on a portion of the first principal surface 12a, a portion of the second principal surface 12b, and a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first lead portion 28a of the first internal electrode layer 16a.

[0056] The second external electrode 30b is connected to the second internal electrode layer 16b and is disposed on at least the surface of the second end face 12f. The second external electrode 30b also extends from the second end face 12f and is disposed on a part of the first main face 12a, a part of the second main face 12b, a part of the first side face 12c, and a part of the second side face 12d. In this case, the second external electrode 30b is electrically connected to the second lead portion 28b of the second internal electrode layer 16b.

[0057] Within the laminate 12, capacitance is formed by the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b opposing each other via the dielectric layer 14. Therefore, capacitance can be obtained between the first external electrode 30a connected to the first internal electrode layer 16a and the second external electrode 30b connected to the second internal electrode layer 16b, and the characteristics of a capacitor are exhibited.

[0058] The external electrode 30 includes a base electrode layer 32 containing a metal component and a glass component, and a plating layer 34 formed on the surface of the base electrode layer 32. The first external electrode 30a preferably has a first base electrode layer 32a disposed on the surface of the first end face 12e, and a first plating layer 34a disposed on the surface of the first base electrode layer 32a. The second external electrode 30b preferably has a second base electrode layer 32b disposed on the surface of the second end face 12f, and a second plating layer 34b disposed on the surface of the second base electrode layer 32b.

[0059] The base electrode layer 32 includes a first base electrode layer 32a and a second base electrode layer 32b.

[0060] The first base electrode layer 32a is disposed on the surface of the first end face 12e of the laminate 12, and is formed so as to extend from the first end face 12e to cover a portion of each of the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d.

[0061] The second base electrode layer 32b is disposed on the surface of the second end face 12f of the laminate 12, and is formed so as to extend from the second end face 12f to cover a portion of each of the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d.

[0062] The first base electrode layer 32a may be arranged only on the surface of the first end face 12e of the laminate 12, and the second base electrode layer 32b may be arranged only on the surface of the second end face 12f of the laminate 12.

[0063] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, etc. Hereinafter, each configuration when the base electrode layer 32 is the baked layer, the conductive resin layer, or the thin film layer will be described.

[0064] The baking layer contains a glass component and a metal component. The glass component of the baking layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baking layer contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baking layer is formed by applying a conductive paste containing a glass component and a metal component to the laminate 12 and baking it. The baking layer may be formed by simultaneously baking a laminated chip having an internal electrode layer 16 and a dielectric layer 14 with a conductive paste applied to the laminated chip, or by baking a laminated chip having an internal electrode layer 16 and a dielectric layer 14 to obtain a laminate and then baking the conductive paste onto the laminate.

[0065] In addition, when a laminated chip having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the laminated chip are fired simultaneously, it is preferable to form the firing layer by firing a material to which a dielectric material has been added instead of a glass component.

[0066] The baking layer may be a multi-layer.

[0067] When the first base electrode layer 32a is formed as a baked layer, the thickness of the first base electrode layer 32a at the center in the stacking direction x located on the first end face 12e is preferably, for example, about 3 μm to 100 μm. When the second base electrode layer 32b is formed as a baked layer, the thickness of the second base electrode layer 32b at the center in the stacking direction x located on the second end face 12f is preferably, for example, about 3 μm to 100 μm.

[0068] Furthermore, when the base electrode layer 32 is provided on the first main surface 12a and the second main surface 12b using a baked layer, the thickness of the first base electrode layer 32a located on the first main surface 12a and the second main surface 12b at the center in the longitudinal direction z in the direction connecting the first main surface 12a and the second main surface 12b is preferably, for example, approximately 3 μm or more and 70 μm or less, and the thickness of the second base electrode layer 32b located on the first main surface 12a and the second main surface 12b at the center in the longitudinal direction z in the direction connecting the first main surface 12a and the second main surface 12b is preferably, for example, approximately 3 μm or more and 70 μm or less.

[0069] Furthermore, when the base electrode layer 32 is provided on the first side surface 12c and the second side surface 12d using a baked layer, it is preferable that the thickness of the first base electrode layer 32a located on the first side surface 12c and the second side surface 12d at the center in the longitudinal direction z in the direction connecting the first side surface 12c and the second side surface 12d is, for example, about 10 μm or more and 100 μm or less, and it is preferable that the thickness of the second base electrode layer 32b located on the first side surface 12c and the second side surface 12d at the center in the longitudinal direction z in the direction connecting the first side surface 12c and the second side surface 12d is, for example, about 10 μm or more and 100 μm or less.

[0070] When a conductive resin layer is provided as the base electrode layer 32, the conductive resin layer may be disposed on the baked layer so as to cover the baked layer, or may be disposed directly on the laminate 12. However, the conductive resin layer may be disposed only on the base electrode layer 32 located on both end faces 12e, 12f. The conductive resin layer contains a metal and a thermosetting resin. The conductive resin layer may completely cover the base electrode layer, or may cover only a portion of the base electrode layer.

[0071] Since the conductive resin layer contains a thermosetting resin, it is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even if the two-terminal multilayer ceramic capacitor 10 is subjected to a physical shock or a shock due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the two-terminal multilayer ceramic capacitor 10.

[0072] The metal contained in the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these. It is also possible to use a metal powder whose surface is coated with Ag. When using a metal powder whose surface is coated with Ag, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder. It is also possible to use Cu or Ni that has been subjected to an oxidation prevention treatment. The reason for using Ag conductive metal powder as the conductive metal is that it is possible to use an inexpensive base metal while maintaining the above-mentioned properties of Ag.

[0073] The metal contained in the conductive resin layer is preferably contained in an amount of 35 vol% to 75 vol% of the total volume of the conductive resin. The average particle size of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, approximately 0.3 μm to 10 μm.

[0074] The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, when the conductive fillers come into contact with each other, a conductive path is formed inside the conductive resin layer.

[0075] The metal contained in the conductive resin layer may be spherical or flat, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0076] The resin for the conductive resin layer may be any of various known thermosetting resins, such as epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins, as it has excellent heat resistance, moisture resistance, adhesion, etc.

[0077] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used as the curing agent for the epoxy resin.

[0078] The conductive resin layer may be a multi-layered layer.

[0079] The thickness of the conductive resin layer located at the center of the stacking direction x of the laminate 12 located at the first end face 12e and the second end face 12f is preferably, for example, about 10 μm or more and 150 μm or less.

[0080] The thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0081] The plating layer 34 includes a first plating layer 34a and a second plating layer 34b.

[0082] The first plating layer 34a is disposed so as to cover the surface of the first base electrode layer 32a, and the second plating layer 34b is disposed so as to cover the surface of the second base electrode layer 32b.

[0083] The plating layer 34 may contain at least one metal selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0084] The plating layer 34 may be formed as a single layer or as multiple layers. When formed as multiple layers, it preferably has a two-layer structure of, for example, Ni plating and Sn plating. By using a plating layer made of Ni plating as the layer in direct contact with the base electrode layer, particularly when the base electrode layer is a conductive resin layer, it is possible to prevent the base electrode layer from being eroded by the solder used for mounting when the multilayer ceramic capacitor is mounted.

[0085] Furthermore, by using a Sn plating layer as the upper layer of the Ni plating layer, the wettability of the solder used for mounting the two-terminal multilayer ceramic capacitor 10 on a mounting substrate is improved, making it easier to mount.

[0086] The thickness of each of the plating layers 34 is preferably 1.0 μm or more and 15.0 μm or less.

[0087] The external electrodes 30 may be formed only with plating layers without providing the base electrode layer 32. Although not shown, a structure in which plating layers are provided without providing the base electrode layer 32 will be described below.

[0088] Each of the first external electrode 30a and the second external electrode 30b may not be provided with a base electrode layer, and a plating layer may be formed directly on the surface of the laminate 12. That is, the two-terminal multilayer ceramic capacitor 10 may have a structure including a plating layer electrically connected to the first internal electrode layer 16a or the second internal electrode layer 16b. In such a case, a catalyst may be disposed on the surface of the laminate 12 as a pretreatment, and then the plating layer may be formed.

[0089] In addition, when a plating layer is formed directly on the laminate without providing a base electrode layer, the amount of reduction in the thickness of the base electrode layer can be converted into a lower profile, i.e., a thinner laminate, or into the thickness of the laminate, i.e., the thickness of the effective layer portion, thereby improving the design freedom of the thickness of the laminate 12.

[0090] The plating layer preferably includes a lower-layer plating electrode formed on the surface of the laminate 12 and an upper-layer plating electrode formed on the surface of the lower-layer plating electrode. The lower-layer plating electrode and the upper-layer plating electrode each preferably include at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal. Furthermore, the lower-layer plating electrode is preferably formed using Ni, which has solder barrier properties, and the upper-layer plating electrode is preferably formed using Sn or Au, which have good solder wettability.

[0091] Furthermore, for example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the lower-layer plated electrode be formed using Cu, which has good bonding properties with Ni. Note that the upper-layer plated electrode may be formed as needed, and the first external electrode 30a and the second external electrode 30b may each be composed of only the lower-layer plated electrode. The upper-layer plated electrode may be the outermost layer of the plated layer, or another plated electrode may be formed on the surface of the upper-layer plated electrode.

[0092] When the external electrode 30 is formed only with the plating layer without providing the base electrode layer 32, the thickness of each plating layer disposed without providing the base electrode layer 32 is preferably 1.0 μm or more and 15.0 μm or less. Furthermore, it is preferable that the plating layer does not contain glass. The metal ratio per unit volume of the plating layer is preferably 99% by volume or more.

[0093] The dimension in the length direction z of the two-terminal multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension L, the dimension in the stacking direction x of the two-terminal multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension T, and the dimension in the width direction y of the two-terminal multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension W. The dimensions of the two-terminal multilayer ceramic capacitor 10 are as follows: L in the length direction z is 0.2 mm to 11.0 mm, W in the width direction y is 0.1 mm to 11.0 mm, and T in the stacking direction x is 0.1 mm to 11.0 mm. The dimensions of the two-terminal multilayer ceramic capacitor 10 can be measured using a microscope.

[0094] In the two-terminal multilayer ceramic capacitor 10 shown in FIG. 1, the first lead portions 28a of the first internal electrode layers 16a have first connection portions 29a that are connected to straddle at least two or more of the first lead portions 28a in the stacking direction between the first lead portions 28a that are arranged on different dielectric layers 14 that are located on at least one of the first main surface 12a side and the second main surface 12b side, and the second lead portions 28b of the second internal electrode layers 16b have second connection portions 29b that are connected to straddle at least two or more of the second lead portions 28b in the stacking direction between the second lead portions 28b that are arranged on different dielectric layers 14 that are located on at least one of the first main surface 12a side and the second main surface 12b side. Therefore, it is possible to improve the adhesion strength between the internal electrode layers 16 between the first lead portions 28a located on different dielectric layers 14 and between the second lead portions 28b located on different dielectric layers 14 in the first lead portions 28a of the first internal electrode layers 16a and the second lead portions 28b of the second internal electrode layers 16b located on the main surface-side outer layer portions 20a, 20b sides where peeling is likely to occur in the two-terminal multilayer ceramic capacitor 10. As a result, even if a balling phenomenon occurs in which the internal electrode layers 16 aggregate laterally due to heat during firing of the laminate 12 and expand in the stacking direction x to increase in thickness, the internal electrode layers 16 are firmly connected to each other in the portions of the laminate 12 at both end faces 12e, 12f and the internal electrode layers 16 located on the main surface-side outer layer portions 20a, 20b sides where peeling is likely to occur, so that peeling between the internal electrode layers 16 can be suppressed.

[0095] 2. Method for Manufacturing a Two-Terminal Multilayer Ceramic Capacitor Next, a method for manufacturing a two-terminal multilayer ceramic capacitor will be described.

[0096] First, a dielectric sheet for the dielectric layers and a conductive paste for the internal electrode layers are prepared. The dielectric sheet and the conductive paste for the internal electrode layers contain a binder and a solvent. The binder and the solvent may be known.

[0097] When forming the dielectric sheet, a paste containing a dielectric is printed by inkjet printing to create the dielectric sheet. At this time, the dielectric sheet on which the pattern of the internal electrode layer is not printed is printed continuously. On the other hand, for the dielectric sheet on which the pattern for the first internal electrode layer and the pattern for the second internal electrode layer are printed, the patterns are printed discontinuously at the locations where the first connecting portion and the second connecting portion are to be formed. When a conductive paste for the internal electrodes is printed thereon by inkjet printing or screen printing, the conductive paste for the internal electrodes is allowed to fill the discontinuous portions, thereby forming the first connecting portion and the second connecting portion. At this time, by controlling the width of the discontinuous portions by inkjet printing, the longitudinal dimension connecting the first end face and the second end face of the first connecting portion and the second connecting portion can be controlled.

[0098] Furthermore, with regard to the dielectric sheets, outer layer dielectric sheets on which no internal electrode layer patterns are printed are also prepared.

[0099] Next, a predetermined number of dielectric sheets for outer layers, on which the pattern of the internal electrode layer is not printed, are laminated to form a portion that will become the second main surface side outer layer portion on the second main surface side. Then, a dielectric sheet on which the pattern of the first internal electrode layer is printed and a dielectric sheet on which the pattern of the second internal electrode layer is printed are sequentially laminated on the portion that will become the second main surface side outer layer portion so as to form the structure of the present invention, to form a portion that will become the internal layer portion. After that, a predetermined number of dielectric sheets for outer layers, on which the pattern of the internal electrode layer is not printed, are further laminated on the portion that will become the internal layer portion, to form a portion that will become the first main surface side outer layer portion on the first main surface side. In this way, a laminated sheet is produced.

[0100] Next, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0101] The laminated block is then cut to a predetermined size to obtain laminated chips, which may have rounded corners and ridges by barrel polishing or the like.

[0102] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the materials of the dielectric layers and internal electrode layers, but is preferably 900° C. or higher and 1400° C. or lower.

[0103] (Formation of External Electrodes) (a) In the Case of Baked Layer In the following description, the base electrode layer is formed as a baked layer. When forming a baked layer, a conductive paste containing a glass component and a metal is prepared, applied, and then baked to form the base electrode layer.

[0104] A first base electrode layer 32a of the first external electrode 30a and a second base electrode layer 32b of the second external electrode 30b are formed on the first end face 12e and the second end face 12f of the laminate 12 obtained by firing.

[0105] When forming a baked layer as the base electrode layer 32, a conductive paste containing a glass component and a metal component is applied by a method such as dipping, and then a baking process is performed to form a baked layer as the base electrode layer 32. The temperature of the baking process at this time is preferably 700°C or higher and 900°C or lower.

[0106] When the base electrode layer 32 is formed as a baked layer, the baked layer may contain a ceramic component. In this case, the ceramic component may be contained instead of the glass component, or both may be contained.

[0107] The ceramic component is preferably, for example, the same type of ceramic material as that of the laminate 12. When the baked layer contains a ceramic component, it is preferable to apply a conductive paste to the laminated chip before firing, and then simultaneously bake (fire) the laminated chip before firing and the conductive paste applied to the laminated chip before firing to form the laminate 12 on which the baked layer is formed. The temperature (firing temperature) of the baking process at this time is preferably 900°C or higher and 1400°C or lower.

[0108] (b) In the case of a conductive resin layer When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed on the surface of a baked layer, or the conductive resin layer may be formed alone directly on the laminate 12 without forming a baked layer.

[0109] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate 12, and then performing a heat treatment at a temperature of 250°C to 550°C to thermally cure the resin. The heat treatment is preferably performed in an N2 atmosphere. In addition, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration below 100 ppm.

[0110] The conductive resin paste can be applied using a method similar to the method of forming the base electrode layer 32 as a baked layer, for example, a method of applying the conductive resin paste by extruding it through a slit or a roller transfer method.

[0111] (c) In the case of a thin film layer When the base electrode layer 32 is formed as a thin film layer, the areas other than the desired areas where the external electrodes 30 are to be formed are covered by masking or the like, and the exposed desired areas are subjected to a thin film formation method such as sputtering or vapor deposition to form the base electrode layer. The base electrode layer formed as a thin film layer is a layer of deposited metal particles having a thickness of 1 μm or less.

[0112] (Plating Electrode) Furthermore, an external electrode may be formed as a plating electrode using only a plating layer without providing the base electrode layer 32. In this case, it can be formed by the following method.

[0113] Either or both of the first external electrode 30a and the second external electrode 30b may have a plating layer formed directly on the surface of the laminate 12 without providing a base electrode layer 32. That is, the two-terminal multilayer ceramic capacitor 10 may have a structure including plating layers directly and electrically connected to the first internal electrode layer 16a and the second internal electrode layer 16b. While electrolytic plating or electroless plating may be used for plating, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, complicating the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferably used as the plating method. Furthermore, if necessary, an upper-layer plated electrode may be formed on the surface of the lower-layer plated electrode in the same manner.

[0114] (Preparation of Plating Layer) Subsequently, as necessary, a plating layer is formed on the surface of the base electrode layer 32, the surface of the conductive resin layer or the surface of the lower-layer plating electrode, and the surface of the upper-layer plating electrode. More specifically, in this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layer 34 on the base electrode layer 32, which is a baked layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred.

[0115] In the manner described above, the two-terminal multilayer ceramic capacitor 10 of the first embodiment is manufactured.

[0116] B. Second Embodiment 1. Three-Terminal Multilayer Ceramic Capacitor A three-terminal multilayer ceramic capacitor 110 will be described as a multilayer ceramic capacitor according to a second embodiment of the present invention with reference to FIGS. 7 to 12. FIG.

[0117] Fig. 7 is an external perspective view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Fig. 8 is a top view showing an example of a three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. Fig. 9 is a front view showing an example of a three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. Fig. 10 is a cross-sectional view taken along line X-X in Fig. 7. Fig. 11 is a cross-sectional view taken along line XI-XI in Fig. 7. Fig. 12 is a cross-sectional view taken along line XI-XI in Fig. 11. Fig. 13 is a cross-sectional view taken along line XII-XII in Fig. 11.

[0118] The laminate 12 has a plurality of dielectric layers 14 stacked one on top of the other, and a plurality of internal electrode layers 116 stacked on the dielectric layers 14. The dielectric layers 14 and the internal electrode layers 116 are stacked in a stacking direction x.

[0119] The laminate 12 has a first main surface 12a and a second main surface 12b that face in the stacking direction x, a first side surface 12c and a second side surface 12d that face in the width direction y that is perpendicular to the stacking direction x, and a first end surface 12e and a second end surface 12f that face in the length direction z that is perpendicular to the stacking direction x and the width direction y. The corners and ridges of the laminate 12 are rounded. Note that a corner refers to a portion where three adjacent surfaces of the laminate intersect, and a ridge refers to a portion where two adjacent surfaces of the laminate intersect. Furthermore, unevenness may be formed on some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0120] The laminate 12 has an internal layer portion 18 composed of one or more dielectric layers 14 and multiple internal electrode layers 116 disposed thereon. The internal electrode layers 116 have first internal electrode layers 116a extending to the first end face 12e and the second end face 12f and second internal electrode layers 116b extending to the first side face 12c and the second side face 12d, and in the internal layer portion 18, the multiple first internal electrode layers 116a and second internal electrode layers 116b face each other with the dielectric layer 14 interposed therebetween.

[0121] The laminate 12 has a first main surface side outer layer portion 20a located on the first main surface 12a side and formed of a plurality of dielectric layers 14 located between the first main surface 12a and the outermost surface of the inner layer portion 18 on the first main surface 12a side and a line aligned with that outermost surface. Similarly, the laminate 12 has a second main surface side outer layer portion 20b located on the second main surface 12b side and formed of a plurality of dielectric layers 14 located between the second main surface 12b and the outermost surface of the inner layer portion 18 on the second main surface 12b side and a line aligned with that outermost surface.

[0122] The laminate 12 also has a first side surface side outer layer portion 22a located on the first side surface 12c side and formed from a plurality of dielectric layers 14 located between the first side surface 12c and the outermost surface of the inner layer portion 18 on the first side surface 12c side. Similarly, the laminate 12 has a second side surface side outer layer portion 22b located on the second side surface 12d side and formed from a plurality of dielectric layers 14 located between the second side surface 12d and the outermost surface of the inner layer portion 18 on the second side surface 12d side.

[0123] Furthermore, the laminate 12 has a first end face side outer layer portion 24a located on the first end face 12e side and formed from a plurality of dielectric layers 14 located between the first end face 12e and the outermost surface of the inner layer portion 18 on the first end face 12e side. Similarly, the laminate 12 has a second end face side outer layer portion 24b located on the second end face 12f side and formed from a plurality of dielectric layers 14 located between the second end face 12f and the outermost surface of the inner layer portion 18 on the second end face 12f side.

[0124] The first main surface side outer layer portion 20a is located on the first main surface 12a side. The first main surface side outer layer portion 20a is an assembly of multiple dielectric layers 14 located between the first main surface 12a and the internal electrode layer 116 closest to the first main surface 12a. The second main surface side outer layer portion 20b is located on the second main surface 12b side. The second main surface side outer layer portion 20b is an assembly of multiple dielectric layers 14 located between the second main surface 12b and the internal electrode layer 116 closest to the second main surface 12b.

[0125] The dimensions of the laminate 12 are not particularly limited.

[0126] The material of the dielectric layers 14 is the same as that of the two-terminal multilayer ceramic capacitor 10, and therefore a description thereof will be omitted. Furthermore, the average thickness of the dielectric layers 14 in the lamination direction x after firing is also the same as that of the two-terminal multilayer ceramic capacitor 10, and therefore a description thereof will be omitted.

[0127] The laminate 12 has a plurality of first internal electrode layers 116a and a plurality of second internal electrode layers 116b as the plurality of internal electrode layers 116. The plurality of first internal electrode layers 116a and the plurality of second internal electrode layers 116b are embedded so as to be alternately arranged at equal intervals along the stacking direction x of the laminate 12.

[0128] 16 , the first internal electrode layer 116a includes a first opposing electrode portion 126a facing the second internal electrode layer 116b, a first lead portion 128a extending from the first opposing electrode portion 126a to the surface of the first end face 12e of the laminate 12, and a second lead portion 128b extending from the first opposing electrode portion 126a to the surface of the second end face 12f of the laminate 12. Thus, the ends of the multiple first lead portions 128a are extended to the surface of the first end face 12e and exposed from the laminate 12, and the ends of the multiple second lead portions 128b are extended to the surface of the second end face 12f and exposed from the laminate 12. Therefore, the first internal electrode layer 116a is not exposed on the surfaces of the first side face 12c and the second side face 12d of the laminate 12.

[0129] 17 , the second internal electrode layer 116b has a generally cross shape and includes a second opposing electrode portion 126b facing the first internal electrode layer 116a, a third lead portion 128c extending from the second opposing electrode portion 126b to the surface of the first side face 12c of the laminate 12, and a fourth lead portion 128d extending from the second opposing electrode portion 126b to the surface of the second side face 12d of the laminate 12. Therefore, the third lead portion 128c has an end portion extending to the surface of the first side face 12c and exposed from the laminate 12, and the fourth lead portion 128d has an end portion extending to the surface of the second side face 12d and exposed from the laminate 12. Therefore, the second internal electrode layer 116b is not exposed on the surface of the first end face 12e or the surface of the second end face 12f of the laminate 12.

[0130] The four corners of the second opposing electrode portion 126b of the second internal electrode layer 116b are not chamfered, but may be chamfered. This makes it possible to prevent overlap with the corners of the first opposing electrode portion 126a of the first internal electrode layer 116a, thereby suppressing electric field concentration. As a result, it is possible to suppress dielectric breakdown of the ceramic capacitor that may occur due to electric field concentration.

[0131] The first lead portion 128a has a first connection portion 129a that is connected and arranged so as to span at least two or more first lead portions 128a in the stacking direction between first lead portions 128a that are arranged on different dielectric layers 14 located on at least one of the first main surface 12a side and the second main surface 12b side.

[0132] The second lead portion 128b has a second connection portion 129b that is connected and arranged so as to span at least two or more second lead portions 128b in the stacking direction between second lead portions 128b that are arranged on different dielectric layers 14 located on at least one of the first main surface 12a side and the second main surface 12b side.

[0133] The third lead portion 128c has a third connection portion 129c that is connected and arranged so as to span at least two or more third lead portions 128c in the stacking direction between the third lead portions 128c that are arranged on different dielectric layers 14 located on at least one of the first main surface 12a side and the second main surface 12b side.

[0134] The fourth lead-out portion 128d has a fourth connection portion 129d that is connected and arranged so as to span at least two or more fourth lead-out portions 128d in the stacking direction between fourth lead-out portions 128d that are arranged on different dielectric layers 14 located on at least one of the first main surface 12a side and the second main surface 12b side.

[0135] The first connecting portion 129a is preferably located closer to the first end face 12e than half the dimension of the first end face side outer layer portion 24a in the length direction z. The second connecting portion 129b is preferably located closer to the second end face 12f than half the dimension of the second end face side outer layer portion 24b in the length direction z. The third connecting portion 129c is preferably located closer to the first end face 12e than half the dimension of the first side face side outer layer portion 22a in the length direction z. The fourth connecting portion 129d is preferably located closer to the second end face 12f than half the dimension of the second side face side outer layer portion 22b in the length direction z. This directly improves the adhesion strength between the internal electrode layers 116 in locations where stress concentration is most likely to occur due to the balling phenomenon, in which the internal electrode layers 116 aggregate laterally due to heat during firing of the laminate 12 and expand in the stacking direction x to increase their thickness.

[0136] It is preferable that there are a plurality of first connecting portions 129a. It is preferable that there are a plurality of second connecting portions 129b. It is preferable that there are a plurality of third connecting portions 129c. It is preferable that there are a plurality of fourth connecting portions 129d. This directly improves the adhesion strength between the internal electrode layers 116 at locations where stress concentration due to the balling phenomenon, in which the internal electrode layers 116 aggregate laterally due to heat during firing of the laminate 12 and expand in the stacking direction x to increase their thickness, is most likely to occur.

[0137] The first connecting portion 129a is preferably located on the first main surface 12a side excluding the center portion in the stacking direction of the inner layer portion 18 and on the second main surface 12b side excluding the center portion in the stacking direction of the inner layer portion 18. The second connecting portion 129b is preferably located on the first main surface 12a side excluding the center portion in the stacking direction of the inner layer portion 18 and on the second main surface 12b side excluding the center portion in the stacking direction of the inner layer portion 18. The third connecting portion 129c is preferably located on the first main surface 12a side excluding the center portion in the stacking direction of the inner layer portion 18 and on the second main surface 12b side excluding the center portion in the stacking direction of the inner layer portion 18. The fourth connecting portion 129d is preferably located on the first main surface 12a side excluding the center portion in the stacking direction of the inner layer portion 18 and on the second main surface 12b side excluding the center portion in the stacking direction of the inner layer portion 18. This makes it possible to suppress the occurrence of peeling between the internal electrode layers 116, while maintaining the ceramic strength of the laminate 12 in the central portion in the lamination direction of the inner layer portion 18, in the portion where the lead portions of the internal electrode layers 116 are present. Therefore, while suppressing the occurrence of peeling between the internal electrode layers 116, it is also possible to suppress the occurrence of breakage, chipping, cracks, etc. in the laminate 12 of the three-terminal multilayer ceramic capacitor 110 when an external impact is applied to the three-terminal multilayer ceramic capacitor 110.

[0138] In this case, the dimension t2 in the stacking direction of the central portion of the inner layer portion 18, which is an area where the first connecting portion 129a is not arranged, is preferably 25% to 75% of the dimension t1 in the stacking direction of the inner layer portion 18. The dimension t2 in the stacking direction of the central portion of the inner layer portion 18, which is an area where the second connecting portion 129b is not arranged, is preferably 25% to 75% of the dimension t1 in the stacking direction of the inner layer portion 18. The dimension t3 in the stacking direction of the central portion of the inner layer portion 18, which is an area where the third connecting portion 129c is not arranged, is preferably 25% to 75% of the dimension t1 in the stacking direction of the inner layer portion 18. The dimension t3 in the stacking direction of the central portion of the inner layer portion 18, which is an area where the fourth connecting portion 129d is not arranged, is preferably 25% to 75% of the dimension t1 in the stacking direction of the inner layer portion 18.

[0139] Here, if the dimension t2 in the stacking direction of the center of the stacking direction of the inner layer portion 18 in the area where the first connecting portion 129a and the second connecting portion 129b are not arranged becomes smaller than 25% of the dimension t1 in the stacking direction of the inner layer portion 18, there is a concern that when an external impact is applied to the three-terminal multilayer ceramic capacitor 110, cracks, chips, or the like will occur in the laminate 12 of the three-terminal multilayer ceramic capacitor 110. Furthermore, if the dimension t2 in the stacking direction of the center in the stacking direction of the inner layer portion 18 in the region where the first connecting portion 129a and the second connecting portion 129b are not arranged becomes larger than 75% of the dimension t1 in the stacking direction of the inner layer portion 18, it may not be possible to ensure sufficient adhesion strength between the internal electrode layers 116 between the first leading portions 128a located on different dielectric layers 14 and between the second leading portions 128b located on different dielectric layers 14 at the leading portions of the internal electrode layers 116 of the inner layer portion 18 located on the main surface-side outer layer portions 20a, 20b side where peeling of the three-terminal multilayer ceramic capacitor 110 is likely to occur.

[0140] Furthermore, if the dimension t3 in the stacking direction of the center of the stacking direction of the inner layer portion 18 in the area where the third connecting portion 129c and the fourth connecting portion 129d are not arranged becomes smaller than 25% of the dimension t1 in the stacking direction of the inner layer portion 18, there is a concern that cracks, chips, or the like may occur in the laminate 12 of the three-terminal multilayer ceramic capacitor 110 when an external impact is applied to the three-terminal multilayer ceramic capacitor 110. Furthermore, if the dimension t3 in the stacking direction of the center in the stacking direction of the inner layer portion 18 in the region where the third connecting portion 129c and the fourth connecting portion 129d are not arranged becomes larger than 75% of the dimension t1 in the stacking direction of the inner layer portion 18, it may not be possible to ensure sufficient adhesion strength between the internal electrode layers 116 between the first leading portions 128a located on different dielectric layers 14 and between the second leading portions 128b located on different dielectric layers 14 at the leading portions of the internal electrode layers 116 of the inner layer portion 18 located on the side outer layer portions 22a, 22b where peeling of the three-terminal multilayer ceramic capacitor 110 is likely to occur.

[0141] The dimension of the first connection portion 129a in the length direction z connecting the first end face 12e and the second end face 12f is preferably 3% to 97% of the thickness of the first lead portion 128a of the first internal electrode layer 116a. The dimension of the second connection portion 129b in the length direction z connecting the first end face 12e and the second end face 12f is preferably 3% to 97% of the thickness of the second lead portion 128b of the first internal electrode layer 116a. The dimension of the third connection portion 129c in the length direction z connecting the first side face 12c and the second side face 12d is preferably 3% to 97% of the thickness of the third lead portion 128c of the second internal electrode layer 116b. The dimension of the fourth connection portion 129d in the longitudinal direction z connecting the first side surface 12c and the second side surface 12d is preferably 3% to 97% of the thickness of the fourth lead portion 128d of the second internal electrode layer 116b. This makes the electrical resistance higher than that of the internal electrode layer 16 and makes it difficult for current to flow, thereby preventing changes in electrical characteristics due to the presence of the first connection portion 129a to the fourth connection portion 129d and suppressing peeling between the internal electrode layers 116.

[0142] The first connecting portion 129a and the second connecting portion 129b are preferably concentrated in the center in the width direction y of the three-terminal multilayer ceramic capacitor 110. The third connecting portion 129c and the fourth connecting portion 129d are preferably concentrated in the center in the width direction y of the three-terminal multilayer ceramic capacitor 110. This makes it possible to further ensure the adhesion strength between the internal electrode layers 16 at the center in the width direction y of the three-terminal multilayer ceramic capacitor 110.

[0143] The material compositions of the first internal electrode layers 116a and the second internal electrode layers 116b and the compositions within the layers in the stacking direction x are similar to those of the first internal electrode layers 16a and the second internal electrode layers 16b of the two-terminal multilayer ceramic capacitor 10 of the first embodiment.

[0144] The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0145] The first external electrode 30a is connected to the first internal electrode layer 116a and is disposed on the surface of the first end face 12e. The first external electrode 30a also extends from the first end face 12e of the laminate 12 and is disposed on a portion of the first principal surface 12a, a portion of the second principal surface 12b, and a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first lead portion 128a of the first internal electrode layer 116a.

[0146] The second external electrode 30b is connected to the first internal electrode layer 116a and is disposed on the surface of the second end face 12f. The second external electrode 30b also extends from the second end face 12f of the laminate 12 and is disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, and a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second lead portion 128b of the first internal electrode layer 116a.

[0147] The third external electrode 30c is connected to the second internal electrode layer 116b and is disposed on the surface of the first side surface 12c. The third external electrode 30c also extends from the first side surface 12c of the laminate 12 and is disposed on a part of the first main surface 12a and a part of the second main surface 12b. In this case, the third external electrode 30c is electrically connected to the third lead portion 128c of the second internal electrode layer 116b.

[0148] The fourth external electrode 30d is connected to the second internal electrode layer 116b and is disposed on the surface of the second side surface 12d. The fourth external electrode 30d also extends from the second side surface 12d of the laminate 12 and is disposed on a part of the first main surface 12a and a part of the second main surface 12b. In this case, the fourth external electrode 30d is electrically connected to the fourth lead portion 128d of the second internal electrode layer 116b.

[0149] Within the laminate 12, capacitance is formed by the first opposing electrode portion 126a of the first internal electrode layer 116a and the second opposing electrode portion 126b of the second internal electrode layer 116b opposing each other via the dielectric layer 14. Therefore, capacitance can be obtained between the first external electrode 30a and the second external electrode 30b to which the first internal electrode layer 116a is connected and the third external electrode 30c and the fourth external electrode 30d to which the second internal electrode layer 116b is connected, and capacitor characteristics are exhibited.

[0150] The base electrode layer 32 includes a first base electrode layer 32a, a second base electrode layer 32b, a third base electrode layer 32c, and a fourth base electrode layer 32d.

[0151] The first base electrode layer 32a is connected to the first internal electrode layer 116a and is disposed on the surface of the first end face 12e. The first base electrode layer 32a also extends from the first end face 12e and is disposed on parts of the first and second main faces 12a and 12b, as well as parts of the first and second side faces 12c and 12d. In this case, the first base electrode layer 32a is electrically connected to the first lead portion 128a of the first internal electrode layer 116a. The second base electrode layer 32b is connected to the first internal electrode layer 116a and is disposed on the surface of the second end face 12f. The second base electrode layer 32b also extends from the second end face 12f and is disposed on parts of the first and second main faces 12a and 12b, as well as parts of the first and second side faces 12c and 12d. In this case, the second base electrode layer 32b is electrically connected to the second lead portion 128b of the first internal electrode layer 116a.

[0152] The third base electrode layer 32c is connected to the second internal electrode layer 116b and is disposed on the surface of the first side surface 12c. The third base electrode layer 32c also extends from the first side surface 12c and is disposed on a portion of the first main surface 12a and a portion of the second main surface 12b. In this case, the third base electrode layer 32c is electrically connected to the third lead portion 128c of the second internal electrode layer 116b. The fourth base electrode layer 32d is connected to the second internal electrode layer 116b and is disposed on the surface of the second side surface 12d. The fourth base electrode layer 32d also extends from the second side surface 12d and is disposed on a portion of the first main surface 12a and a portion of the second main surface 12b. In this case, the fourth base electrode layer 32d is electrically connected to the fourth lead portion 128d of the second internal electrode layer 116b.

[0153] The plating layer 34 includes a first plating layer 34a, a second plating layer 34b, a third plating layer 34c, and a fourth plating layer 34d.

[0154] The first plating layer 34a is disposed so as to cover the surface of the first base electrode layer 32a. The second plating layer 34b is disposed so as to cover the surface of the second base electrode layer 32b. The third plating layer 34c is disposed so as to cover the surface of the third base electrode layer 32c. The fourth plating layer 34d is disposed so as to cover the surface of the fourth base electrode layer 32d.

[0155] The material compositions and intra-layer configurations of the first external electrode 30 a, the second external electrode 30 b, the third external electrode 30 c, and the fourth external electrode 30 d of the external electrodes 30 of the three-terminal multilayer ceramic capacitor 110 are similar to those of the first external electrode 30 a and the second external electrode 30 b of the external electrodes 30 of the two-terminal multilayer ceramic capacitor 10 of the first embodiment.

[0156] The dimension in the length direction z of the three-terminal multilayer ceramic capacitor 110 including the laminate 12 and the first external electrodes 30a to 30d is defined as dimension L, the dimension in the stacking direction x of the three-terminal multilayer ceramic capacitor 110 including the laminate 12 and the first external electrodes 30a to 30d is defined as dimension T, and the dimension in the width direction y of the three-terminal multilayer ceramic capacitor 110 including the laminate 12 and the first external electrodes 30a to 30d is defined as dimension W. The dimensions of the three-terminal multilayer ceramic capacitor 110 are not particularly limited, but are preferably such that the dimension L in the length direction z is 0.2 mm to 11.0 mm, the dimension W in the width direction y is 0.1 mm to 11.0 mm, and the dimension T in the stacking direction x is 0.1 mm to 11.0 mm. The dimensions of the three-terminal multilayer ceramic capacitor 110 can be measured using a microscope.

[0157] As a result, the three-terminal multilayer ceramic capacitor 110 shown in FIG. 6 can have various configurations similar to those that can be adopted by the two-terminal multilayer ceramic capacitor 10 shown in FIG. 1, and can achieve various effects according to the various configurations.

[0158] 2. Method for Manufacturing a Three-Terminal Multilayer Ceramic Capacitor Next, a method for manufacturing a three-terminal multilayer ceramic capacitor will be described.

[0159] First, a dielectric sheet for the dielectric layers and a conductive paste for the internal electrode layers are prepared. The dielectric sheet and the conductive paste for the internal electrode layers contain a binder and a solvent. The binder and the solvent may be known.

[0160] When forming the dielectric sheet, a paste containing a dielectric is printed by inkjet printing to create the dielectric sheet. At this time, the dielectric sheet on which the pattern of the internal electrode layer is not printed is printed continuously. On the other hand, for the dielectric sheet on which the pattern for the first internal electrode layer and the pattern for the second internal electrode layer are printed, the patterns are printed discontinuously at the locations where the first connecting portion and the second connecting portion are to be formed. When a conductive paste for the internal electrodes is printed thereon by inkjet printing or screen printing, the conductive paste for the internal electrodes is allowed to fill the discontinuous portions, thereby forming the first connecting portion and the second connecting portion. At this time, by controlling the width of the discontinuous portions by inkjet printing, the longitudinal dimension connecting the first end face and the second end face of the first connecting portion and the second connecting portion can be controlled.

[0161] Furthermore, with regard to the dielectric sheets, outer layer dielectric sheets on which no internal electrode layer patterns are printed are also prepared.

[0162] Next, a predetermined number of dielectric sheets for outer layers, on which the pattern of the internal electrode layer is not printed, are laminated to form a portion that will become the second main surface side outer layer portion on the second main surface side. Then, a dielectric sheet on which the pattern of the first internal electrode layer is printed and a dielectric sheet on which the pattern of the second internal electrode layer is printed are sequentially laminated on the portion that will become the second main surface side outer layer portion so as to form the structure of the present invention, to form a portion that will become the internal layer portion. After that, a predetermined number of dielectric sheets for outer layers, on which the pattern of the internal electrode layer is not printed, are further laminated on the portion that will become the internal layer portion, to form a portion that will become the first main surface side outer layer portion on the first main surface side. In this way, a laminated sheet is produced.

[0163] Next, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0164] The laminated block is then cut to a predetermined size to obtain laminated chips, which may have rounded corners and ridges by barrel polishing or the like.

[0165] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the materials of the dielectric layers and internal electrode layers, but is preferably 900° C. or higher and 1400° C. or lower.

[0166] (Formation of External Electrodes) (a) In the Case of Baked Layer In the following description, the base electrode layer is formed as a baked layer. When forming a baked layer, a conductive paste containing a glass component and a metal is prepared, applied, and then baked to form the base electrode layer.

[0167] A third base electrode layer 32c of the third external electrode 30c is formed on the first side surface 12c of the laminate 12 obtained by firing, and a fourth base electrode layer 32d of the fourth external electrode 30d is formed on the second side surface 12d of the laminate 12.

[0168] When forming a baked layer as the base electrode layer 32, a conductive paste containing a glass component and a metal component is applied, and then a baking process is performed to form a baked layer as the base electrode layer 32. The temperature of the baking process at this time is preferably 700°C or higher and 900°C or lower.

[0169] Various methods can be used to form the baked layer. For example, a method of applying a conductive paste by extruding it through a slit can be used. With this method, by increasing the amount of conductive paste extruded, the base electrode layer 32 can be formed not only on the first side surface 12c and the second side surface 12d but also on portions of the first principal surface 12a and the second principal surface 12b. The baked layer can also be formed using a roller transfer method. With the roller transfer method, when the base electrode layer 32 is formed not only on the first side surface 12c and the second side surface 12d but also on portions of the first principal surface 12a and the second principal surface 12b, the base electrode layer 32 can be formed on portions of the first principal surface 12a and the second principal surface 12b by increasing the pressing pressure during roller transfer.

[0170] Next, a first base electrode layer 32a of the first external electrode 30a is formed on a first end face 12e of the laminate 12 obtained by firing, and a second base electrode layer 32b of the second external electrode 30b is formed on a second end face 12f of the laminate 12. As in the formation of the base electrode layers 32 of the third external electrode 30c and the fourth external electrode 30d, when a baked layer is formed as the base electrode layer 32, a conductive paste containing a glass component and a metal component is applied, and then a baking process is performed to form a baked layer as the base electrode layer 32. The temperature of the baking process at this time is preferably 700°C or higher and 900°C or lower.

[0171] In addition, as a method for forming the baked layer as the base electrode layer 32 of the first external electrode 30a and the second external electrode 30b, a conductive paste for the base electrode layer is applied by a dipping method so that it extends not only to the first end face 12e and the second end face 12f, but also to part of the first main surface 12a, part of the second main surface 12b, part of the first side surface 12c, and part of the second side surface 12d.

[0172] Regarding the baking process, the third base electrode layer 32c of the third external electrode 30c, the fourth base electrode layer 32d of the fourth external electrode 30d, the first base electrode layer 32a of the first external electrode 30a, and the second base electrode layer 32b of the second external electrode 30b may be baked simultaneously, or the third base electrode layer 32c of the third external electrode 30c and the fourth base electrode layer 32d of the fourth external electrode 30d, and the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b may be baked separately.

[0173] (b) In the case of a conductive resin layer When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed on the surface of a baked layer, or the conductive resin layer may be formed alone directly on the laminate 12 without forming a baked layer.

[0174] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate 12, and then performing a heat treatment at a temperature of 250°C to 550°C to thermally cure the resin. The heat treatment is preferably performed in an N2 atmosphere. In addition, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration at 100 ppm or less.

[0175] The conductive resin paste can be applied using a method similar to the method of forming the base electrode layer 32 as a baked layer, for example, a method of applying the conductive resin paste by extruding it through a slit or a roller transfer method.

[0176] (c) In the case of a thin film layer When the base electrode layer 32 is formed as a thin film layer, the areas other than the desired areas where the external electrodes 30 are to be formed are covered by masking or the like, and the exposed desired areas are subjected to a thin film formation method such as sputtering or vapor deposition to form the base electrode layer. The base electrode layer formed as a thin film layer is a layer of 1 μm or less in thickness where metal particles are deposited.

[0177] (Plating Electrode) Furthermore, an external electrode may be formed as a plating electrode using only a plating layer without providing the base electrode layer 32. In this case, it can be formed by the following method.

[0178] For any one or each of the first external electrode 30a to the fourth external electrode 30d, a plating layer may be formed directly on the surface of the laminate 12 without providing a base electrode layer 32. That is, the three-terminal multilayer ceramic capacitor 110 may have a structure including plating layers directly and electrically connected to the first internal electrode layer 116a and the second internal electrode layer 116b. While electrolytic plating or electroless plating may be used for plating, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, complicating the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferred as the plating method. Furthermore, if necessary, an upper-layer plating electrode may be formed on the surface of the lower-layer plating electrode in the same manner.

[0179] (Preparation of Plating Layer) Subsequently, as necessary, a plating layer is formed on the surface of the base electrode layer 32, the surface of the conductive resin layer or the surface of the lower-layer plating electrode, and the surface of the upper-layer plating electrode. More specifically, in this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layer 34 on the base electrode layer 32, which is a baked layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred.

[0180] In the manner described above, the three-terminal multilayer ceramic capacitor 110 according to the second embodiment is manufactured.

[0181] The present invention, including those described above, allows various modifications to be made to the above-described embodiments in terms of configuration, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such modifications are included in the present invention.

[0182] <1> A multilayer ceramic capacitor comprising: a laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the laminate having first and second main surfaces opposing each other in a lamination direction, a first end face and a second end face opposing each other in a length direction perpendicular to the lamination direction, and a first side face and a second side face opposing each other in a width direction perpendicular to the lamination direction and the length direction; a first external electrode arranged on the first end face; and a second external electrode arranged on the second end face, wherein the plurality of internal electrode layers have a plurality of first internal electrode layers and a plurality of second internal electrode layers alternately arranged on different dielectric layers, and the plurality of first internal electrode layers have a plurality of first opposing electrode portions opposing the second internal electrode layers, and a plurality of first lead portions extending from each of the plurality of first opposing electrode portions and led to the first end face, the second internal electrode layer has a plurality of second opposing electrode portions facing the first internal electrode layer, and a plurality of second lead portions extending from each of the plurality of second opposing electrode portions and led to the first side surface, the first lead portions have first connection portions connected to straddle at least two or more of the first lead portions in the stacking direction between the first lead portions located on the different dielectric layers at least on the first main surface side or at least on the second main surface side, and the second lead portions have second connection portions connected to straddle at least two or more of the second lead portions in the stacking direction between the second lead portions located on the different dielectric layers at least on the first main surface side or at least on the second main surface side.

[0183] <2> The multilayer ceramic capacitor according to <1>, wherein the laminate includes: an inner layer portion between which the plurality of internal electrode layers face; a first end face side outer layer portion located on the first end face side and formed from the plurality of dielectric layers located between the first end face and an outermost surface of the inner layer portion on the first end face side; and a second end face side outer layer portion located on the second end face side and formed from the plurality of dielectric layers located between the second end face and an outermost surface of the inner layer portion on the second end face side, wherein the first connection portion is located closer to the first end face than half of the lengthwise dimension of the first end face side outer layer portion, and the second connection portion is located closer to the second end face than half of the lengthwise dimension of the second end face side outer layer portion.

[0184] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein a plurality of the first connection portions and a plurality of the second connection portions are present.

[0185] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the first connection portion and the second connection portion are located on at least one of the first main surface side excluding a central portion in the stacking direction of the inner layer portion and the second main surface side excluding the central portion in the stacking direction of the inner layer portion.

[0186] <5> A multilayer ceramic capacitor comprising: a laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the laminate having first and second main surfaces opposing each other in a lamination direction, a first end face and a second end face opposing each other in a length direction perpendicular to the lamination direction, and a first side face and a second side face opposing each other in a width direction perpendicular to the lamination direction and the length direction; a plurality of first internal electrode layers arranged on the plurality of dielectric layers and extended to the first end face and the second end face; a plurality of second internal electrode layers arranged on the plurality of dielectric layers and extended to the first side face and the second side face; a first external electrode arranged on the first end face and connected to the first internal electrode layer; a second external electrode arranged on the second end face and connected to the first internal electrode layer; a third external electrode arranged on the first side face and connected to the second internal electrode layer; and a fourth external electrode arranged on the second side face and connected to the second internal electrode layer, the plurality of first internal electrode layers have a plurality of first opposing electrode portions facing the second internal electrode layers via the dielectric layer, a plurality of first lead portions extending from each of the plurality of first opposing electrode portions and drawn to the first end face, and a plurality of second lead portions extending from each of the plurality of first opposing electrode portions and drawn to the second end face; the plurality of second internal electrode layers have a plurality of second opposing electrode portions facing the first internal electrode layers via the dielectric layer, a plurality of third lead portions extending from each of the plurality of second opposing electrode portions and drawn to the first side face, and a plurality of fourth lead portions extending from each of the plurality of second opposing electrode portions and drawn to the second side face; the first lead portions have first connection portions connected to straddle at least two or more of the first lead portions in the stacking direction between the first lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side,the second lead portion has a second connection portion connected to straddle at least two or more of the second lead portions in the stacking direction between the second lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side; the third lead portion has a third connection portion connected to straddle at least two or more of the third lead portions in the stacking direction between the third lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side; and the fourth lead portion has a fourth connection portion connected to straddle at least two or more of the fourth lead portions in the stacking direction between the fourth lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side.

[0187] <6> The laminate has: an inner layer portion between which the plurality of internal electrode layers face each other; a first side surface side outer layer portion located on the first side surface side and formed from the plurality of dielectric layers located between the first side surface and an outermost surface of the inner layer portion on the first side surface side; a second side surface side outer layer portion located on the second side surface side and formed from the plurality of dielectric layers located between the second side surface and an outermost surface of the inner layer portion on the second side surface side; a first end surface side outer layer portion located on the first end surface side and formed from the plurality of dielectric layers located between the first end surface and the outermost surface of the inner layer portion on the first end surface side; and a second end surface side outer layer portion located on the second end surface side and formed from the plurality of dielectric layers located between the second end surface and an outermost surface of the inner layer portion on the second end surface side, wherein the first connection portion is located closer to the first end surface than half of a dimension of the first end surface side outer layer portion in the length direction, The multilayer ceramic capacitor according to <5>, wherein the second connection portion is located closer to the second end face than half of the lengthwise dimension of the second end face side outer layer portion, the third connection portion is located closer to the first side face than half of the widthwise dimension of the first side face side outer layer portion, and the fourth connection portion is located closer to the second side face than half of the widthwise dimension of the second side face side outer layer portion.

[0188] <7> The multilayer ceramic capacitor according to <5> or <6>, wherein a plurality of the first connection portions, a plurality of the second connection portions, a plurality of the third connection portions, and a plurality of the fourth connection portions are present.

[0189] <8> The multilayer ceramic capacitor according to any one of <5> to <7>, wherein the first connecting portion and the second connecting portion, and the third connecting portion and the fourth connecting portion are located on at least one of the first main surface side excluding a central portion in the stacking direction of the inner layer portion and the second main surface side excluding the central portion in the stacking direction of the inner layer portion.

[0190] REFERENCE SIGNS LIST 10 Two-terminal multilayer ceramic capacitor 110 Three-terminal multilayer ceramic capacitor 12 Laminate 12a First main surface 12b Second main surface 12c First side surface 12d Second side surface 12e First end surface 12f Second end surface 14 Dielectric layer 16, 116 Internal electrode layer 16a, 116a First internal electrode layer 16b, 116b Second internal electrode layer 18 Internal layer portion 20a First main surface side outer layer portion 20b Second main surface side outer layer portion 22c First side surface side outer layer portion 22d Second side surface side outer layer portion 24e First end surface side outer layer portion 24f Second end surface side outer layer portion 26a, 126a First opposing electrode portion 26b, 126b Second opposing electrode portion 28a, 128a First lead portion 28b, 128b Second lead portion 128c Third lead portion 128d Fourth lead portion 30 External electrode 30a First external electrode 30b Second external electrode 30c Third external electrode 30d Fourth external electrode 32 Base electrode 32a First base electrode layer 32b Second base electrode layer 32c Third base electrode layer 32d Fourth base electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 34c Third plating layer 34d Fourth plating layer x Stacking direction y Width direction z Length direction

Claims

1. a laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the laminate having a first main surface and a second main surface opposing each other in a lamination direction, a first end face and a second end face opposing each other in a length direction perpendicular to the lamination direction, and a first side face and a second side face opposing each other in a width direction perpendicular to the lamination direction and the length direction; a first external electrode disposed on the first end surface; a second external electrode disposed on the second end surface; A multilayer ceramic capacitor having the plurality of internal electrode layers include a plurality of first internal electrode layers and a plurality of second internal electrode layers alternately arranged on different dielectric layers, the plurality of first internal electrode layers have a plurality of first opposing electrode portions opposed to the second internal electrode layer, and a plurality of first lead-out portions extending from the respective first opposing electrode portions and led to the first end face, the second internal electrode layer has a plurality of second opposing electrode portions opposed to the first internal electrode layer, and a plurality of second lead-out portions extending from each of the plurality of second opposing electrode portions and led out to the first side surface, the first lead portion has a first connection portion that is connected so as to straddle at least two or more of the first lead portions in the stacking direction between the first lead portions located on at least the first main surface side or at least the second main surface side of the different dielectric layers, the second lead portion has a second connection portion that is connected so as to span at least two or more of the second lead portions in the stacking direction between the second lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side.

2. The laminate includes an inner layer portion in which the plurality of internal electrode layers face each other, a first end face side outer layer portion located on the first end face side and formed of the plurality of dielectric layers located between the first end face and an outermost surface of the inner layer portion on the first end face side; a second end face side outer layer portion located on the second end face side and formed of the plurality of dielectric layers located between the second end face and an outermost surface of the inner layer portion on the second end face side; having the first connection portion is located closer to the first end face than half of the dimension of the first end face side outer layer portion in the longitudinal direction, 2 . The multilayer ceramic capacitor according to claim 1 , wherein the second connection portion is located closer to the second end face than half of the length of the second end face side outer layer portion.

3. 3. The multilayer ceramic capacitor according to claim 1, wherein a plurality of the first connecting portions and a plurality of the second connecting portions are provided.

4. 3. The multilayer ceramic capacitor according to claim 2, wherein the first connection portion and the second connection portion are located on at least one of the first main surface side excluding a central portion in the stacking direction of the inner layer portion and the second main surface side excluding the central portion in the stacking direction of the inner layer portion.

5. a laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the laminate having a first main surface and a second main surface opposed to each other in a lamination direction, a first end face and a second end face opposed to each other in a length direction perpendicular to the lamination direction, and a first side face and a second side face opposed to each other in a width direction perpendicular to the lamination direction and the length direction; a plurality of first internal electrode layers disposed on the plurality of dielectric layers and extending to the first end surface and the second end surface; a plurality of second internal electrode layers disposed on the plurality of dielectric layers and extending to the first side surface and the second side surface; a first external electrode disposed on the first end face and connected to the first internal electrode layer; a second external electrode disposed on the second end face and connected to the first internal electrode layer; a third external electrode disposed on the first side surface and connected to the second internal electrode layer; a fourth external electrode disposed on the second side surface and connected to the second internal electrode layer; A multilayer ceramic capacitor having the first internal electrode layers include a plurality of first opposing electrode portions opposed to the second internal electrode layer via the dielectric layer, and a plurality of first lead-out portions extending from each of the first opposing electrode portions and led to the first end face; a plurality of second lead portions extending from the plurality of first opposing electrode portions and led to the second end surface; the second internal electrode layers include a plurality of second opposing electrode portions opposed to the first internal electrode layer via the dielectric layer, and a plurality of third lead portions extending from each of the second opposing electrode portions and led to the first side surface; a plurality of fourth lead portions extending from the plurality of second opposing electrode portions and led to the second side surface; the first lead portion has a first connection portion that is connected so as to straddle at least two or more of the first lead portions in the stacking direction between the first lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side; the second lead portion has a second connection portion connected to straddle at least two or more of the second lead portions in the stacking direction between the second lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side, the third lead portion has a third connection portion connected to straddle at least two or more of the third lead portions in the stacking direction between the third lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side, the fourth lead portion has a fourth connection portion that is connected so as to span at least two or more of the fourth lead portions in the stacking direction between the fourth lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side.

6. The laminate includes an inner layer portion in which the plurality of internal electrode layers face each other, a first side surface outer layer portion located on the first side surface side and formed of the plurality of dielectric layers located between the first side surface and an outermost surface of the inner layer portion on the first side surface side; a second side surface outer layer portion located on the second side surface side and formed of the plurality of dielectric layers located between the second side surface and an outermost surface of the inner layer portion on the second side surface side; a first end face side outer layer portion located on the first end face side and formed of the plurality of dielectric layers located between the first end face and an outermost surface of the inner layer portion on the first end face side; a second end face side outer layer portion located on the second end face side and formed of the plurality of dielectric layers located between the second end face and an outermost surface of the inner layer portion on the second end face side, the first connection portion is located closer to the first end face than half of the dimension of the first end face side outer layer portion in the longitudinal direction, the second connection portion is located closer to the second end face than half of the dimension of the second end face side outer layer portion in the longitudinal direction, the third connection portion is located closer to the first side surface than half of the width direction of the first side surface outer layer portion, 6. The multilayer ceramic capacitor according to claim 5, wherein the fourth connection portion is located closer to the second side surface than half the dimension of the second side surface outer layer portion in the width direction.

7. 7. The multilayer ceramic capacitor according to claim 5, wherein a plurality of the first connecting portions, a plurality of the second connecting portions, a plurality of the third connecting portions, and a plurality of the fourth connecting portions are provided.

8. 7. The multilayer ceramic capacitor according to claim 6, wherein the first connecting portion and the second connecting portion, as well as the third connecting portion and the fourth connecting portion, are located on at least one of the first main surface side excluding the center portion in the height direction of the inner layer portion and the second main surface side excluding the center portion in the height direction of the inner layer portion.