Multilayer ceramic electronic component

Abstract

Provided is a multilayer ceramic electronic component that has high reliability and improved adhesion force of external electrodes to a laminate.　This multilayer ceramic capacitor 1 comprises a laminate 10, and a first external electrode 40A and a second external electrode 40B on both ends of the laminate 10 in a length direction L, wherein: a first end face LS1 of the laminate 10 has a first protrusion 27A that partially protrudes in the length direction L in a region extending from a first step layer 25A to a dielectric layer 20 adjacent to at least one side of the first step layer 25A in a lamination direction T; and a second end face LS2 has a second protrusion 27B that partially protrudes in the length direction L in a region extending from a second step layer 25B to the dielectric layer 20 adjacent to at least one side of second first step layer 25B in the lamination direction T.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] Multilayer ceramic capacitors have been known as multilayer ceramic electronic components. Generally, multilayer ceramic capacitors have a structure including a laminate, which is a fired body in which dielectric layers and internal electrode layers, each made of ceramic layers, are alternately stacked, and external electrodes provided on both end surfaces of the laminate. The capacitor has a desired capacitance according to the number of layers and the thickness of the dielectric layers. Patent Document 1 discloses a multilayer ceramic capacitor in which lead portions, which serve as connection portions to the external electrodes of the multiple internal electrode layers, are alternately arranged on one end surface and the other end surface in the stacking direction, and the end opposite the lead portions does not extend to the end surface, so that no internal electrode layers are arranged.

[0003] Japanese Patent Application Laid-Open No. 2006-73623

[0004] In the multilayer ceramic capacitor structure disclosed in Patent Document 1, because there are portions where the internal electrode layers are not disposed, the longitudinal ends of the multiple internal electrode layers bend inward in the lamination direction, reducing the thickness of both longitudinal ends of the laminate. This can lead to short circuits between the internal electrode layers and reduced high-temperature load reliability. In particular, the thinner the dielectric layers are and the greater the number of laminated internal electrode layers and dielectric layers, the more likely short circuits occur among the internal electrode layers, leading to reduced reliability. Therefore, multilayer ceramic capacitors are manufactured by disposing step layers made of ceramic material in spatial regions where the internal electrode layers may not be disposed during the manufacturing process, thereby preventing bending of the internal electrode layers. However, the step layers are exposed at the end faces of the laminate where the external electrodes are disposed. However, due to their weak adhesion to the external electrodes, the external electrodes may peel off, reducing moisture resistance reliability, leaving room for improvement.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a highly reliable multilayer ceramic electronic component in which the adhesive strength of the external electrodes to the laminate is improved.

[0006] a first end face and a second end face that face each other in a length direction that is perpendicular to the stacking direction; first internal electrode layers that are alternately stacked with the plurality of ceramic layers and exposed at the first end faces; second internal electrode layers that are alternately stacked with the plurality of ceramic layers and exposed at the second end faces; a first step layer that is disposed in a first step region between a pair of the ceramic layers that face each other via the second internal electrode layer, where the second internal electrode layer is not disposed, and exposed at the first end faces; and a second step layer that is disposed in a second step region between the pair of the ceramic layers that face each other via the first internal electrode layer, where the first internal electrode layer is not disposed, and exposed at the second end faces. a first external electrode arranged on the first end face and extending from the first end face to the first main surface, the second main surface, the first side surface, and the second side surface, the first external electrode being connected to the first internal electrode layer; and a second external electrode arranged on the second end face and extending from the second end face to the first main surface, the second main surface, the first side surface, and the second side surface, the second internal electrode layer being connected to the second internal electrode layer, wherein the first end face has a first convex portion that partially protrudes in the length direction from the first step layer in a region spanning to the ceramic layer adjacent to at least one side of the first step layer in the stacking direction, and the second end face has a second convex portion that partially protrudes in the length direction from the second step layer in a region spanning to the ceramic layer adjacent to at least one side of the second step layer in the stacking direction.

[0007] According to the present invention, it is possible to provide a highly reliable multilayer ceramic electronic component in which the adhesive strength of the external electrodes to the laminate is improved.

[0008] 1 is a perspective view of the appearance of a multilayer ceramic capacitor according to an embodiment. FIG. 1 is a cross-sectional view taken along line II-II of FIG. 1. FIG. 2 is a cross-sectional view taken along line III-III of FIG. 2. FIG. 3 is a cross-sectional view taken along line IVA-IVA of FIG. 2. FIG. 4 is a cross-sectional view taken along line IVB-IVB of FIG. 2. FIG. 5 is a schematic enlarged view of a portion indicated by VA in FIG. 2. FIG. 5A is a cross-sectional view taken along line VB-VB of FIG. 5A, showing a state in which the first external electrode 40A has been removed. FIG. 6A is a cross-sectional view taken along line VIB-VIB of FIG. 6A, showing a state in which the second external electrode 40B has been removed. FIG. 7A is a cross-sectional view showing a schematic example of printing a dielectric paste for step layers on a ceramic sheet, covering the ends of the conductive paste for internal electrode layers. FIG. 7B is a cross-sectional view showing the state of the first end face side of a multilayer ceramic capacitor obtained by stacking the ceramic sheets shown in FIG.

[0009] Hereinafter, a multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to an embodiment of the present disclosure will be described with reference to the drawings. Fig. 1 is an external perspective view of the multilayer ceramic capacitor 1 according to the embodiment. Fig. 2 is a cross-sectional view taken along II-II in Fig. 1. Fig. 3 is a cross-sectional view taken along III-III in Fig. 2. Fig. 4A is a cross-sectional view taken along IVA-IVA in Fig. 2. Fig. 4B is a cross-sectional view taken along IVB-IVB in Fig. 2.

[0010] 1, the multilayer ceramic capacitor 1 according to the embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 10 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at both ends of the laminate 10 while being spaced apart from each other.

[0011] (Laminate) In Fig. 1, an arrow T indicates the stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10. This stacking direction T also corresponds to the thickness direction and height direction of the multilayer ceramic capacitor 1 and the laminate 10. In Fig. 1, an arrow W indicates the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T. In Fig. 1, an arrow L indicates the length direction L of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T and the width direction W. A pair of external electrodes 40 are respectively arranged at one end and the other end of the length direction L of the laminate 10.

[0012] 1 to 4B show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as an LT cross section. The cross section shown in FIG. 3 is also referred to as a WT cross section. The cross sections shown in FIGS. 4A and 4B are also referred to as LW cross sections.

[0013] As shown in Figures 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face each other in a stacking direction T, a first side surface WS1 and a second side surface WS2 that face each other in a width direction W that is perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 that face each other in a length direction L that is perpendicular to the stacking direction T and the width direction W.

[0014] As shown in FIG. 1 , the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Incidentally, unevenness may be formed on part or all of the surfaces constituting the laminate 10.

[0015] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, the L dimension is preferably 0.2 mm or more and 6 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, the T dimension is preferably 0.05 mm or more and 5 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, the W dimension is preferably 0.1 mm or more and 5 mm or less.

[0016] As shown in Figures 2 and 3, the laminate 10 has an effective layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged to sandwich the effective layer portion 11 in the stacking direction T.

[0017] The effective layer portion 11 has a plurality of dielectric layers 20 as a plurality of ceramic layers alternately stacked in the stacking direction T, a plurality of internal electrode layers 30, and a plurality of step layers 25. The effective layer portion 11 includes, in the stacking direction T, the internal electrode layer 30 located closest to the first main surface TS1 to the internal electrode layer 30 located closest to the second main surface TS2. In the effective layer portion 11, the multiple internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The effective layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0018] (Dielectric Layer) The plurality of dielectric layers 20 are made of a dielectric material. The dielectric material is, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ Dielectric ceramics containing BaTiO as a main component can be used. Dielectric materials containing these main components and additional components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds can also be used. Dielectric materials containing BaTiO as a main component can be used. ３ The perovskite-type compound may have a plurality of crystal grains containing the perovskite-type compound having the basic structure.

[0019] The smaller the thickness of the dielectric layer 20, the greater the capacitance of the capacitor. As the thickness of the dielectric layer 20 decreases, the crystal grains inside it become smaller, but if the crystal grains become too small, the dielectric constant decreases due to the size effect. Therefore, the size of the crystal grains is appropriately designed depending on the thickness of the dielectric layer 20. For example, the crystal grain size in the dielectric layer 20 is preferably 1 μm or less.

[0020] The thickness of the dielectric layer 20 is preferably, for example, 10 μm or less. The number of laminated dielectric layers 20 is preferably 10 to 2000. Note that this number of dielectric layers 20 is the total number of the dielectric layers 20 in the effective layer portion 11 and the dielectric layers 20 in each of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0021] 2 and 3 , the first main surface side outer layer portion 12 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface side outer layer portion 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The region sandwiched between the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 is the effective layer portion 11. The dielectric layers 20 used in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 may be the same as the dielectric layer 20 used in the effective layer portion 11 .

[0022] (Internal electrode layers) The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the stacking direction T with the dielectric layer 20 sandwiched therebetween. The first internal electrode layers 31 are extended to the first end face LS1. The second internal electrode layers 32 are extended to the second end face LS2. In the following, when it is not necessary to distinguish between the first internal electrode layers 31 and the second internal electrode layers 32, the first internal electrode layers 31 and the second internal electrode layers 32 may be collectively referred to as the internal electrode layers 30.

[0023] 4A , the first internal electrode layer 31 has a first opposing portion 31A and a first lead portion 31B. The first opposing portion 31A is a region facing the second internal electrode layer 32 with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The first lead portion 31B is a portion that extends from the first opposing portion 31A to the first end face LS1 and is exposed at the first end face LS1.

[0024] 4B , the second internal electrode layer 32 has a second opposing portion 32A and a second lead portion 32B. The second opposing portion 32A is a region facing the first internal electrode layer 31 with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The second lead portion 32B is a portion that extends from the second opposing portion 32A to the second end face LS2 and is exposed at the second end face LS2.

[0025] In this embodiment, the first opposing portion 31A and the second opposing portion 32A face each other with the dielectric layer 20 interposed therebetween, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0026] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shapes of the first draw-out portion 31B and the second draw-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.

[0027] The dimension in the width direction W of the first opposing portion 31A and the dimension in the width direction W of the first lead portion 31B may be the same dimension, or one of the dimensions may be smaller. The dimension in the width direction W of the second opposing portion 32A and the dimension in the width direction W of the second lead portion 32B may be the same dimension, or one of the dimensions may be smaller.

[0028] Both end edges of the first lead portion 31B in the width direction W may extend while curving toward the center in the width direction W of the first end surface LS1 of the laminate 10. End edges of the second lead portion 32B in the width direction W may extend while curving toward the center in the width direction W of the second end surface LS2 of the laminate 10. Of the end faces (exposed faces) of the multiple first lead portions 31B extended to the first end face LS1, the distance in the stacking direction T between the end face closest to the first main surface TS1 and the end face closest to the second main surface TS2 may be shorter than the distance in the stacking direction T between the first opposing portion 31A or the second opposing portion 32A closest to the first main surface TS1 and the first opposing portion 31A or the second opposing portion 32A closest to the second main surface TS2. Of the end faces (exposed faces) of the multiple second draw-out portions 32B drawn out to the second end face LS2, the distance in the stacking direction T between the end face closest to the first main surface TS1 and the end face closest to the second main surface TS2 may be shorter than the distance in the stacking direction T between the first opposing portion 31A or the second opposing portion 32A closest to the first main surface TS1 and the first opposing portion 31A or the second opposing portion 32A closest to the second main surface TS2.

[0029] The first internal electrode layer 31 and the second internal electrode layer 32 can be made of an appropriate conductive material such as, but not limited to, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0030] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 10 or more and 2000 or less.

[0031] In order to increase the capacitance of the capacitor, the area of ​​the internal electrode layer 30 must be increased, so the coverage (coverage rate) of the internal electrode layer 30 in the LW cross section is preferably 90% or more. The coverage here is defined as the ratio of the area of ​​the internal electrode layer 30 in the LW cross section of the internal electrode layer 30 minus the area of ​​voids or holes present in the internal electrode layer 30. The higher the coverage in the LW cross section of the internal electrode layer 30, the higher the capacitance of the capacitor. However, even if the coverage is low, the dielectric layers 20 are bonded to each other via voids, resulting in high interlayer bonding strength and less likelihood of delamination. The internal electrode layer 30 preferably has a uniform thickness, but the thickness at the edge in the width direction W may be thicker than the thickness at the center in the width direction W.

[0032] (Step Layers) The multiple step layers 25 include multiple first step layers 25A and multiple second step layers 25B. As shown in FIG. 2 , each of the multiple first step layers 25A is disposed in a first step region 26A, which is a space between a pair of dielectric layers 20 facing each other in the stacking direction T via a second internal electrode layer 32, and is not disposed in the first step region 26A, so as to fill the first step region 26A. Each of the multiple first step layers 25A overlaps with a pair of dielectric layers 20 on both sides in the stacking direction T. Each of the multiple first step layers 25A is disposed in the same position as the second internal electrode layer 32 in the stacking direction T and is joined to an end of the second opposing portion 32A of the second internal electrode layer 32 on the first end face LS1 side. Each of the multiple first step layers 25A is exposed at the first end face LS1.

[0033] Each of the multiple second step layers 25B is arranged in the second step region 26B, which is a space between a pair of dielectric layers 20 facing each other in the stacking direction T with the first internal electrode layer 31 interposed therebetween, so as to fill the second step region 26B, where the first internal electrode layer 31 is not arranged. Each of the multiple second step layers 25B overlaps, in the stacking direction T, with the pair of dielectric layers 20 on both sides in the stacking direction T. Each of the multiple second step layers 25B is arranged in the same position as the first internal electrode layer 31 in the stacking direction T, and is joined to an end of the first opposing portion 31A of the first internal electrode layer 31 on the second end face LS2 side. Each of the multiple second step layers 25B is exposed at the second end face LS2.

[0034] The first step layer 25A and the second step layer 25B may be formed of the same ceramic dielectric material as the dielectric layer 20. The first step layer 25A and the second step layer 25B may be formed of a material different from that of the dielectric layer 20. The first step layer 25A and the second step layer 25B have characteristics of the present disclosure, which will be described in detail later. Hereinafter, when it is not necessary to distinguish between the first step layer 25A and the second step layer 25B, the first step layer 25A and the second step layer 25B may be collectively referred to as the step layer 25. The step layer 25 preferably has the same thickness as the internal electrode layer 30 located at the same position in the stacking direction T.

[0035] As shown in Figures 2 to 4B, the laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is a portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as a part of the effective layer portion 11. Figures 4A and 4B show the range of the counter electrode portion 11E in the width direction W and length direction L. The counter electrode portion 11E is also referred to as the effective portion of the capacitor.

[0036] The laminate 10 has a side surface side outer layer portion. As shown in FIGS. 3 to 4B , the side surface side outer layer portion has a first side surface side outer layer portion WG1 and a second side surface side outer layer portion WG2. The first side surface side outer layer portion WG1 is a portion including a dielectric layer 20 located between the effective layer portion 11, the first main surface side outer layer portion 12, the second main surface side outer layer portion 13, and the first side surface WS1. The second side surface side outer layer portion WG2 is a portion including a dielectric layer 20 located between the effective layer portion 11, the first main surface side outer layer portion 12, the second main surface side outer layer portion 13, and the second side surface WS2.

[0037] 3 to 4B show the range of the first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2 in the width direction W. The side surface side outer layer portions are also called W gaps or side gaps.

[0038] An insulating layer may be disposed on each of the first side surface WS1 and the second side surface WS2 of the laminate 10. In this case, the interface between the dielectric layer 20 and the internal electrode layer 30 is covered by the insulating layer, thereby preventing moisture from penetrating. The insulating layer is preferably formed of the same material as the dielectric layer 20, but is not limited to this. Such an insulating layer may be disposed so as to be joined to the internal electrode layer 30.

[0039] The laminate 10 has an end surface side outer layer portion. As shown in Figures 2, 4A, and 4B, the end surface side outer layer portion has a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2.

[0040] The first end face side outer layer portion LG1 is a portion located between the counter electrode portion 11E and the first end face LS1, and includes the plurality of dielectric layers 20, the plurality of first lead portions 31B, and the plurality of first step layers 25A. That is, the first end face side outer layer portion LG1 is an aggregate of the portions of the plurality of dielectric layers 20 on the first end face LS1 side, the plurality of first lead portions 31B, and the plurality of first step layers 25A.

[0041] The second end face side outer layer portion LG2 is a portion located between the counter electrode portion 11E and the second end face LS2 and includes the plurality of dielectric layers 20, the plurality of second lead portions 32B, and the plurality of second step layers 25B. That is, the second end face side outer layer portion LG2 is an aggregate of the portions of the plurality of dielectric layers 20 on the second end face LS2 side, the plurality of second lead portions 32B, and the plurality of second step layers 25B.

[0042] 2, 4A, and 4B show the range of the length direction L of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2. The end surface side outer layer portions are also referred to as L gaps or end gaps. The first step layer 25A and the second step layer 25B described above are disposed in the L gaps.

[0043] (External electrode) As shown in Figures 1 and 2, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0044] The first external electrode 40A and the second external electrode 40B have the same basic configuration. The first external electrode 40A and the second external electrode 40B have shapes that are approximately plane-symmetric with respect to a WT cross section at the center in the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40.

[0045] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is in contact with the first lead portions 31B of each of the first internal electrode layers 31 exposed at the first end face LS1. This electrically connects the first external electrode 40A to the first internal electrode layers 31. In this embodiment, the first external electrode 40A is preferably disposed on a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. That is, the first external electrode 40A is preferably provided so as to extend from the first end face LS1 around the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2.

[0046] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is in contact with the second lead portions 32B of the second internal electrode layers 32 exposed at the second end face LS2. This electrically connects the second external electrode 40B to the second internal electrode layers 32. In the embodiment, the second external electrode 40B is preferably disposed on a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2. That is, the second external electrode 40B is preferably provided so as to extend from the second end face LS2 around the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2.

[0047] As described above, in the laminate 10, capacitance is formed by the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 facing each other via the dielectric layer 20. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0048] 2, 4A, and 4B, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0049] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first lead portions 31B of each of the first internal electrode layers 31 exposed at the first end face LS1. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0050] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is in contact with the second lead portions 32B of each of the second internal electrode layers 32 exposed at the second end face LS2. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0051] The first underlying electrode layer 50A and the second underlying electrode layer 50B of the embodiment include at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0052] When the first base electrode layer 50A and the second base electrode layer 50B are baked layers, the baked layers preferably contain a glass component and a metal component. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, Li, etc. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, etc.

[0053] The baked layer is formed by applying and baking, for example, a conductive paste containing glass and metal to the laminate 10. The baked layer can be formed by co-firing (co-firing) a pre-fired laminated chip, which is the material for the laminate 10 having multiple internal electrodes and dielectric layers, with a conductive paste applied to the laminated chip. Alternatively, the baked layer can be formed by firing the laminated chip to obtain the laminate 10, and then applying and baking a conductive paste to the laminate 10 (post-firing). The baked layer may be multiple layers.

[0054] The thickness of the first base electrode layer 50A and the second base electrode layer 50B formed by baking layers in the length direction L is preferably, for example, 0.1 μm or more and 200 μm or less at the center in the stacking direction T. Furthermore, when the first base electrode layer 50A and the second base electrode layer 50B formed by baking layers are provided up to parts of the first main surface TS1 and the second main surface TS2, the thickness of the first base electrode layer 50A and the second base electrode layer 50B formed by baking layers in the length direction T is preferably, for example, 0.1 μm or more and 200 μm or less at the center in the length direction L. Furthermore, when the first base electrode layer 50A and the second base electrode layer 50B are provided up to parts of the first side surface WS1 and the second side surface WS2, the thickness of the first base electrode layer 50A and the second base electrode layer 50B formed by baking layers in the width direction W is preferably, for example, 0.1 μm or more and 200 μm or less at the center in the length direction L.

[0055] When the first underlying electrode layer 50A and the second underlying electrode layer 50B are conductive resin layers, the conductive resin layers may contain a thermosetting resin and a metal.

[0056] The conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to a physical shock or a shock due to a thermal cycle, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0057] The metal contained in the conductive resin layer can be Ag, Cu, or an alloy thereof. Alternatively, a metal powder with Ag coating on its surface can be used. When using a metal powder with Ag coating on its surface, it is preferable to use Cu or Ni as the metal powder. Cu that has been treated to prevent oxidation can also be used. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity of all metals, making it suitable as an electrode material, and Ag is a noble metal, so it does not oxidize and has high resistance. The reason for using Ag-coated metal is that it allows for the base metal to be made inexpensively while maintaining the above-mentioned properties of Ag.

[0058] The metal contained in the conductive resin layer is preferably contained in a proportion of 35 vol% or more and 75 vol% or less with respect to the volume of the entire conductive resin. The shape of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the metal powder contained in the conductive resin layer may be, for example, approximately 0.3 μm or more and 10 μm or less. The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, contact between conductive fillers, which are metal powders, forms an electrical path within the conductive resin layer. The metal powder contained in the conductive resin layer may be spherical, flat, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0059] The resin for the conductive resin layer can be, for example, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. The resin contained in the conductive resin layer is preferably contained in a proportion of 25 vol% to 65 vol% of the total volume of the conductive resin. Furthermore, the conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, and imidazole-based compounds can be used as the curing agent.

[0060] The conductive resin layer may be a multi-layer structure. The conductive resin layer is disposed so as to cover the baked layer. The conductive resin layer may be disposed directly on the laminate. When the conductive resin layer is disposed so as to cover the baked layer, the conductive resin layer is disposed between the baked layer and the plating layer (first plating layer 60A, second plating layer 60B).

[0061] The thickness of the first and second base electrode layers 50A, 50B made of conductive resin layers in the length direction L is preferably, for example, 10 μm or more and 200 μm or less at the center in the stacking direction T. Furthermore, when the first and second base electrode layers 50A, 50B made of conductive resin layers are provided up to a portion of the first main surface TS1 and a portion of the second main surface TS2, the thickness of the first and second base electrode layers 50A, 50B made of conductive resin layers in the length direction T is preferably, for example, 5 μm or more and 50 μm or less at the center in the length direction L. Furthermore, when the first and second base electrode layers 50A, 50B made of baked layers are provided up to a portion of the first and second side surfaces WS1, WS2, the thickness of the first and second base electrode layers 50A, 50B made of baked layers in the width direction W is preferably, for example, 5 μm or more and 50 μm or less at the center in the length direction L.

[0062] When the first and second base electrode layers 50A and 50B are thin film layers, the thin film layers can be formed by a thin film formation method such as sputtering, vapor deposition, etc. In the embodiment, the thin film layer is preferably a layer of 1 μm or less in thickness on which metal particles are deposited.

[0063] The first plating layer 60A of the first external electrode 40A is disposed so as to cover the first base electrode layer 50A.

[0064] The second plating layer 60B of the second external electrode 40B is disposed so as to cover the second base electrode layer 50B.

[0065] The first plating layer 60A and the second plating layer 60B preferably contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of multiple layers. The first plating layer 60A and the second plating layer 60B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0066] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A. The first plating layer 60A of the embodiment has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0067] The second plating layer 60B is disposed so as to cover the second base electrode layer 50B. The second plating layer 60B of the embodiment includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0068] The Ni plating layer prevents the first and second base electrode layers 50A and 50B from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 1 μm or more and 15 μm or less.

[0069] The external electrode 40 may be formed only with a plating layer without providing a base electrode layer on the first end face LS1 and the second end face LS2. In this case, it is preferable to form the plating layer after disposing a catalyst on the surface of the region where the plating layer is to be formed as a pretreatment.

[0070] In this case, the plating layer preferably includes a lower-layer plating electrode formed on the surface of the laminate 10 and an upper-layer plating electrode formed on the surface of the lower-layer plating electrode. The lower-layer plating electrode and the upper-layer plating electrode each preferably include at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal. The lower-layer plating electrode is preferably formed using Ni, which has solder barrier properties. The upper-layer plating electrode is preferably formed using Sn or Au, which have good solder wettability.

[0071] Furthermore, for example, when the first internal electrode layer 31 and the second internal electrode layer 32 are formed using Ni, the lower layer plating electrode is preferably formed using Cu, which has good bonding properties with Ni. Note that the upper layer plating electrode may be formed as needed, and the external electrode 40 may be composed of only the lower layer plating electrode.

[0072] Furthermore, the plating layer may have an upper-layer plating electrode as the outermost layer, or another plating electrode may be formed on the surface of the upper-layer plating electrode. The thickness of each plating layer disposed without a base electrode layer is preferably 1 μm or more and 15 μm or less. Furthermore, the plating layer preferably does not contain glass. The metal ratio per unit volume of the plating layer is preferably 99% by volume or more.

[0073] The above is the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the dimension in the length direction L of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as the L dimension, then the L dimension is preferably 0.2 mm or more and 6.5 mm or less. If the dimension in the stacking direction T of the multilayer ceramic capacitor 1 is defined as the T dimension, then the T dimension is preferably 0.1 mm or more and 6.5 mm or less. If the dimension in the width direction W of the multilayer ceramic capacitor 1 is defined as the W dimension, then the W dimension is preferably 0.1 mm or more and 5.5 mm or less.

[0074] (Step Layer and Convex Portion) Next, the step layer 25, which is a feature of the present disclosure, and the convex portions of the first end face LS1 and the second end face LS2 will be described in detail.

[0075] Fig. 5A is an enlarged schematic view of the portion indicated by VA in Fig. 2. Fig. 5B is a VB-VB cross-sectional view of Fig. 5A with the first external electrode 40A removed. Fig. 6A is an enlarged schematic view of the portion indicated by VIA in Fig. 2. Fig. 6B is a VIB-VIB cross-sectional view of Fig. 6A with the second external electrode 40B removed.

[0076] 5A and 5B, the first end surface LS1 has a plurality of first protrusions 27A protruding in the length direction L. Furthermore, as shown in Figures 6A and 6B, the second end surface LS2 has a plurality of second protrusions 27B protruding in the length direction L.

[0077] 5A and 5B , each of the multiple first protrusions 27A is formed in a region of the first end surface LS1 that includes a location corresponding to each first step layer 25A. The first protrusions 27A are formed by a portion of the ceramic material forming the first step layer 25A protruding from the first step layer 25A in the length direction L of the laminate 10. The first protrusions 27A partially protrude from the first step layer 25A in a region that extends to the dielectric layer 20 adjacent to the first step layer 25A.

[0078] The first protrusion 27A according to the embodiment hangs down from the first step layer 25A to the end face 20a of the adjacent dielectric layer 20 on one side in the stacking direction T (the lower side in FIG. 5A ), covering at least a portion of the end face 20a. Therefore, the interface 29a at the first end face LS1 between the first step layer 25A and the adjacent dielectric layer 20 on the lower side of the first step layer 25A in FIG. 5A is covered and blocked by the first protrusion 27A. As shown in FIG. 5B , the first protrusion 27A extends in the width direction W of the laminate 10, and the entire length of the interface 29a extending in the width direction W is covered by the first protrusion 27A.

[0079] The first protrusion 27A may protrude from the entire area of ​​the first step layer 25A on the first end surface LS1, or may protrude from only a part of the area. The area that the first protrusion 27A covers on the end surface 20a of the dielectric layer 20 is not limited, but it is preferable that the first protrusion 27A be formed on an area that is at least 3% or more of the dimension of the end surface 20a in the stacking direction T. This ensures that the interface 29a is covered by the first protrusion 27A.

[0080] As shown in FIG. 5A, in the first convex portion 27A, it is preferable that the protrusion amount G1 protruding in the length direction L from the end face 20 a of the dielectric layer 20 constituting the first end face LS1 is 98% or less of the thickness H2, which is the dimension in the stacking direction T of the second internal electrode layer 32.

[0081] The second protrusions 27B have a configuration similar to that of the first protrusions 27A. That is, as shown in Figures 6A and 6B, each of the multiple second protrusions 27B is formed in a region of the second end surface LS2 that includes a location corresponding to each second step layer 25B. The second protrusions 27B are formed by a portion of the ceramic material forming the second step layer 25B protruding from the second step layer 25B in the length direction L of the laminate 10. The second protrusions 27B partially protrude from the second step layer 25B in a region spanning the dielectric layer 20 adjacent to the second step layer 25B.

[0082] The second protrusion 27B according to the embodiment is formed so as to hang down from the second step layer 25B to the end face 20b of the dielectric layer 20 adjacent to one side in the stacking direction T (the lower side in FIG. 6A ) and cover the end face 20b. Therefore, at the second end face LS2, the interface 29b between the second step layer 25B and the dielectric layer 20 adjacent to the lower side of the second step layer 25B in FIG. 6A is covered and blocked by the second protrusion 27B. As shown in FIG. 6B , the second protrusion 27B extends in the width direction W of the laminate 10, and the entire length of the interface 29b extending in the width direction W is covered by the second protrusion 27B.

[0083] The second protrusion 27B may protrude from the entire area of ​​the second step layer 25B on the second end surface LS2, or may protrude from only a portion of the area. The area that the second protrusion 27B covers on the end surface 20b of the dielectric layer 20 is not limited, but it is preferable that the second protrusion 27B be formed on at least an area that is 3% or more of the dimension of the end surface 20b in the stacking direction T. This ensures that the interface 29b is covered by the second protrusion 27B.

[0084] As will be described later, the first protrusions 27A and the second protrusions 27B may become integrated with the dielectric layer 20 when the laminate 10 is fired during the manufacturing process. Therefore, with regard to the first protrusions 27A, the state in which the first protrusions 27A cover the end faces 20a and the interface 29a as described above is a state in which the laminate 10 is still a molded body before firing and the material of the first protrusions 27A can be distinguished from the material of the dielectric layer 20. Similarly, with regard to the second protrusions 27B, the state in which the second protrusions 27B cover the end faces 20b and the interface 29b as described above is a state in which the laminate 10 is still a molded body before firing and the material of the second protrusions 27B can be distinguished from the material of the dielectric layer 20. In the following description, the expressions that the first convex portion 27A and the second convex portion 27B respectively cover the end face 20a and the end face 20b, or the interface 29a and the interface 29b, are based on the concept that, even if the first convex portion 27A and the second convex portion 27B respectively are integrated with the dielectric layer 20, the laminate 10 is in the form of a molded body before firing, as described above.

[0085] In the second convex portion 27B, it is preferable that the protrusion amount G2 protruding in the length direction L from the end face 20b of the dielectric layer 20 constituting the second end face LS2 is 98% or less of the thickness H1, which is the dimension in the stacking direction T of the first internal electrode layer 31.

[0086] The ratios of the protrusion amounts G1 and G2 of the first protrusion 27A and the second protrusion 27B to the thickness of the internal electrode layer 30 (the above-mentioned 98% or less) can be measured and confirmed, for example, as follows. That is, the first side surface WS1 or the second side surface WS2 is polished to, for example, about half the width dimension of the multilayer ceramic capacitor 1 to expose the LT cross section. Next, the protrusion amounts G1 and G2 are measured at any position on the polished surface. Thereafter, the thicknesses H1 and H2 of the internal electrode layer 30 are measured, and calculated from G1 / H1 and G2 / H2. The thicknesses of each portion can be measured using a scanning electron microscope (SEM). The ratios of the areas of the first protrusion 27A and the second protrusion 27B covering the end faces 20a and 20b of the dielectric layer 20 in the stacking direction (the above-mentioned 3% or more) can also be measured and calculated in a similar manner.

[0087] (Manufacturing Method) The above is the configuration of the multilayer ceramic capacitor 1 according to the embodiment. Next, a method for manufacturing this multilayer ceramic capacitor 1 will be described. Note that the multilayer ceramic capacitor 1 according to the embodiment can be manufactured by any method as long as it satisfies the above-mentioned requirements. However, a preferred manufacturing method includes the following steps.

[0088] A dielectric sheet for the dielectric layer 20, a conductive paste for the internal electrode layer 30, and a dielectric paste for the step layer 25 are prepared. The dielectric sheet, conductive paste, and dielectric paste all contain a binder and a solvent. Known binders and solvents can be used. The dielectric paste for the step layer 25 can be one in which the amounts of binder and solvent are different from those of the dielectric sheet. The conductive paste is, for example, a metal powder to which an organic binder and an organic solvent have been added.

[0089] A conductive paste for the plurality of internal electrode layers 30 is printed in a predetermined pattern on a dielectric sheet by, for example, screen printing or gravure printing. As a result, a dielectric sheet on which a pattern of a plurality of first internal electrode layers 31 is formed and a dielectric sheet on which a pattern of a plurality of second internal electrode layers 32 is formed are prepared. Next, a dielectric paste for the step layer 25 is printed by, for example, screen printing in regions on the dielectric sheet on which the patterns of the internal electrode layers 30 are printed where the patterns of the internal electrode layers 30 are not formed, i.e., in the plurality of first step regions 26A and the plurality of second step regions 26B, to form a pattern of the plurality of step layers 25.

[0090] Alternatively, a pattern of a plurality of step layers 25 may be formed first using a dielectric paste, and then a pattern of a plurality of internal electrode layers 30 may be formed using a conductive paste.

[0091] Next, a predetermined number of dielectric sheets not printed with the patterns of the internal electrode layers 30 are stacked to form portions that will become the first main surface-side outer layer portions 12 on the first main surface TS1 side. On top of this, dielectric sheets printed with patterns of the first internal electrode layers 31 and the second step layers 25B and dielectric sheets printed with patterns of the second internal electrode layers 32 and the first step layers 25A are alternately stacked in sequence to form portions that will become the effective layer portions 11. On top of these portions that will become the effective layer portions 11, a predetermined number of dielectric sheets not printed with the patterns of the internal electrode layers 30 are stacked to form portions that will become the second main surface-side outer layer portions 13 on the second main surface TS2 side. This results in a laminate sheet including portions that can become the multiple laminates 10.

[0092] Next, this laminated sheet is pressed in the lamination direction T by means of a hydrostatic press or the like to produce a laminated block.

[0093] Next, the laminated block is cut into pieces of a predetermined size to obtain a plurality of laminated chips that are the raw material for a plurality of laminated bodies 10. Thereafter, the plurality of laminated chips may be polished by barrel polishing or the like to round the corners and ridges.

[0094] Next, the resulting plurality of laminated chips are subjected to a heat treatment at a temperature of approximately 100°C to 200°C. During this treatment, as the binder and solvent components in the dielectric paste for the step layer 25 volatilize and are removed, a portion of the first step layer 25A flows and protrudes toward the first end face LS1, and the protruding portion further flows toward the end face 20a of the dielectric layer 20, forming a first protrusion 27A. Meanwhile, a portion of the second step layer 25B flows and protrudes toward the second end face LS2, and the protruding portion further flows toward the end face 20b of the dielectric layer 20, forming a second protrusion 27B. By changing the temperature and time of this heat treatment, the amount and thickness of the first protrusion 27A and the second protrusion 27B flowing toward the end face of the dielectric layer 20 can be adjusted, thereby forming the first protrusion 27A and the second protrusion 27B having the desired shape and dimensions.

[0095] Note that a portion of the first step layer 25A may flow from the first end surface LS1 to become the first convex portion 27A, thereby reducing the thickness of the first step layer 25A. Also, a portion of the second step layer 25B may flow from the second end surface LS2 to become the second convex portion 27B, thereby reducing the thickness of the second step layer 25B. However, such thickness variations are slight, and the presence of the first step layer 25A and the second step layer 25B makes it unlikely that the thickness of the entire stack 10 at both ends in the length direction L will be reduced.

[0096] The laminated chip is then fired to obtain the laminate 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably 900°C or higher and 1400°C or lower. For example, if the first step layer 25A and the second step layer 25B are formed from the same ceramic material as the dielectric layer 20, the first protrusion 27A and the second protrusion 27B may be integrated with the dielectric layer 20 after firing. In this case, it may be difficult to distinguish between the first protrusion 27A and the end face 20a of the dielectric layer 20 when looking at the first end face LS1, and it may be difficult to distinguish between the second protrusion 27B and the end face 20b of the dielectric layer 20 when looking at the second end face LS2.

[0097] Next, the external electrodes 40 are formed on both ends of the laminate 10 in the length direction L in the following manner: First, a first base electrode layer 50A and a second base electrode layer 50B, which are base electrode layers, are formed.

[0098] When the base electrode layer is formed as a baked layer, a conductive paste that will become the base electrode layer is applied to each of the first end surface LS1 and the second end surface LS2 of the laminate 10 to form the first base electrode layer 50A and the second base electrode layer 50B. When forming the baked layer, a conductive paste containing a glass component and a metal is applied by a method such as dipping, and then a baking process is performed to form the base electrode layer. The baking temperature at this time is preferably 700°C or higher and approximately 900°C.

[0099] When the base electrode layer is a layer containing a conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied onto the baking layer or onto the laminate 10, and heat treatment is carried out at a temperature of about 250° C. to 550° C. to thermally cure the resin, thereby forming a conductive resin layer. The atmosphere during the heat treatment is N ２ In order to prevent the resin from scattering and the various metal components from being oxidized, it is preferable to carry out the heat treatment in an atmosphere in which the oxygen concentration is kept to 100 ppm or less.

[0100] When the base electrode layer is formed as a thin film layer, a thin film forming method such as sputtering or vapor deposition is used to form the thin film layer that will become the base electrode layer on the laminate 10. The base electrode layer formed as a thin film layer is preferably a layer of 1 μm or less in which metal particles are deposited.

[0101] After the base electrode layer is formed as described above, the first plating layer 60A and the second plating layer 60B are successively formed on the base electrode layer by, for example, barrel plating.

[0102] In addition, when the external electrode 40 is formed only with a plating layer without forming a base electrode layer, a plating process is performed on the first end face LS1 and the second end face LS2 of the laminate 10 to form a base plating film on the exposed surface of the internal electrode layer 30. Either electrolytic plating or electroless plating may be used for the plating process, but electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferably used as the plating method. Furthermore, if necessary, an upper layer plating electrode may be formed on the surface of the lower layer plating electrode in the same manner.

[0103] Through the above manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0104] In the above-described manufacturing method, when printing the pattern of the first step layer 25A on the dielectric sheet in producing the laminated chip, as shown in Fig. 7A , in the first step region 26A, the dielectric paste for the first step layer 25A may cover the end 32a on the first end face side of the second internal electrode layer 32 in the lamination direction T. Furthermore, in this case, the end face 32b on the first end face side of the second internal electrode layer 32 may be formed in a tapered shape so as to protrude toward the first step region 26A as it approaches the dielectric sheet for the dielectric layer 20 below in Fig. 7A .

[0105] In the multilayer ceramic capacitor 1 obtained when the pattern of the first step layer 25A is formed as shown in FIG. 7A , as shown in FIG. 7B , the excess portion 25c covering the second internal electrode layer 32, which is part of the first step layer 25A, covers the end portion 32a of the second internal electrode layer 32 in the stacking direction T. As a result, the interface 32c between the first step layer 25A and the end portion 32a of the second internal electrode layer 32 is covered and blocked by the first step layer 25A. Therefore, the first step layer 25A suppresses moisture penetration into the interface, improving moisture resistance reliability. Furthermore, because the first step layer 25A is sufficiently filled in the first step region 26A, the thickness of the end portion on the first end face LS1 side is unlikely to decrease even after pressing. Furthermore, since a sufficient amount of the first step layer 25A is present, the first protrusion 27A is easily formed. Although not shown, it goes without saying that the same procedure may be used when forming the pattern of the second step layer 25B in the second step region 26B.

[0106] Contrary to the above-described embodiment, the end of the internal electrode layer 30 may be disposed so as to cover a part of the step layer 25 .

[0107] The multilayer ceramic capacitor 1 according to the embodiment described above provides the following advantages.

[0108] The multilayer ceramic capacitor 1 according to the embodiment includes dielectric layers 20 as a plurality of ceramic layers stacked in a stacking direction T, a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the stacking direction T, a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the stacking direction T and the width direction W, and a first internal electrode layer 31 stacked alternately with the plurality of dielectric layers 20 and exposed at the first end surface LS1. and a second step layer 25A exposed at the first end face LS1, which is alternately laminated with the plurality of dielectric layers 20, and which is disposed in a first step region 26A between a pair of dielectric layers 20 opposed to each other via the second internal electrode layer 32 and in which the second internal electrode layer 32 is not disposed, and which is disposed in a second step region 26B between a pair of dielectric layers 20 opposed to each other via the first internal electrode layer 31 and in which the first internal electrode layer 31 is not disposed, and which is exposed at the second end face LS2. a first external electrode 40A disposed on the first end face LS1 and extending from the first end face LS1 to the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2, and connected to the first internal electrode layer 31; and a second external electrode 40A disposed on the second end face LS2 and extending from the second end face LS2 to the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2, and connected to the second internal electrode layer 31. 32, and a second external electrode 40B connected to the first end face LS1, wherein the first end face LS1 has a first convex portion 27A that partially protrudes in the length direction L in a region spanning from the first step layer 25A to the dielectric layer 20 adjacent to at least one side of the first step layer 25A in the stacking direction T, and the second end face LS2 has a second convex portion 27B that partially protrudes in the length direction L in a region spanning from the second step layer 25B to the dielectric layer 20 adjacent to at least one side of the second step layer 25B in the stacking direction T.

[0109] The first protrusions 27A corresponding to the first step layers 25A are partially embedded in the first external electrode 40A, which is disposed over the first end face LS1. Therefore, the inner surface of the first external electrode 40A, which is in close contact with the first end face LS1, has multiple recesses, to which the first protrusions 27A are transferred. As shown in FIG. 5A , the recesses extend to the dielectric layer 20. The embedded first protrusions 27A in the first external electrode 40A create an anchor effect, preventing the first external electrode 40A from being caught by the first protrusions 27A and peeling off. Similarly, the second protrusions 27B corresponding to the second step layers 25B are partially embedded in the second external electrode 40B, which is disposed over the second end face LS2. Therefore, a plurality of recesses onto which the plurality of second protrusions 27B are transferred are formed on the inner surface of the second external electrode 40B that is in close contact with the second end surface LS2. As shown in FIG. 6A , the recesses reach the area of ​​the dielectric layer 20. The plurality of second protrusions 27B are embedded within the second external electrode 40B, creating an anchor effect in which the second external electrode 40B is hooked onto the second protrusions 27B and is less likely to peel off. This improves the adhesive strength of the first external electrode 40A and the second external electrode 40B to the laminate 10. As a result, the reliability of the multilayer ceramic capacitor 1 is improved.

[0110] Furthermore, the first protrusion 27A covers and blocks the interface 29a between the first step layer 25A and the dielectric layer 20 at the first end face LS1, and covers and blocks the interface 29b between the second step layer 25B and the dielectric layer 20 at the second end face LS2. Therefore, the first protrusion 27A and the second protrusion 27B prevent moisture from penetrating the interfaces 29a and 29b from the outside, improving moisture-resistant reliability. Furthermore, the first protrusion 27A and the second protrusion 27B lengthen and form a complex shape the path from the outside to the interfaces 29a and 29b, which also prevents moisture from penetrating and improves moisture-resistant reliability.

[0111] In the multilayer ceramic capacitor 1 according to the embodiment, it is preferable that each of the first convex portion 27A and the second convex portion 27B is formed in an area that is 3% or more of the dimension in the stacking direction T on the end face 20a and the end face 20b of the dielectric layer 20.

[0112] As a result, the interfaces 29a and 29b are reliably covered by the first convex portion 27A and the second convex portion 27B, respectively, thereby improving the moisture resistance reliability.

[0113] In the multilayer ceramic capacitor 1 according to the embodiment, it is preferable that the protrusion amount G1 of the first convex portion 27A in the length direction L from the end face 20 a of the dielectric layer 20 constituting the first end face LS1 is 98% or less of the dimension H2 of the second internal electrode layer 32 in the stacking direction T, and the protrusion amount G2 of the second convex portion 27B in the length direction L from the end face 20 b of the dielectric layer 20 constituting the second end face LS2 is 98% or less of the dimension H1 of the first internal electrode layer 31 in the stacking direction T.

[0114] This makes it possible to provide a sufficient protrusion amount G1 of the first protrusion 27A protruding in the length direction L from the end face 20a of the dielectric layer 20, and a sufficient protrusion amount G2 of the second protrusion 27B protruding in the length direction L from the end face 20b of the dielectric layer 20. Therefore, the anchor effect of the first protrusion 27A and the second protrusion 27B is enhanced, and the fixing strength of the first external electrode 40A and the second external electrode 40B to the laminate 10 is improved.

[0115] In the multilayer ceramic capacitor 1 according to the embodiment, it is preferable that the first step layer 25A covers the end of the second internal electrode layer 32 on the first end face LS1 side in the stacking direction T, and the second step layer 25B covers at least the end of the first internal electrode layer 31 on the second end face LS2 side in the stacking direction T.

[0116] As a result, the first step layer 25A is sufficiently filled in the first step region 26A, and the second step layer 25B is sufficiently filled in the second step region 26B. Therefore, the thickness of both ends of the laminate 10 in the longitudinal direction L is less likely to decrease, and the first convex portion 27A and the second convex portion 27B having a sufficient protrusion amount are reliably formed. Furthermore, penetration of moisture into the interface between the step layer 25 and the internal electrode layer 30, which are joined to each other, is suppressed, improving moisture resistance reliability.

[0117] The present invention is not limited to the configurations of the above-described embodiments, and can be applied by making appropriate modifications within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0118] For example, in the above-described embodiment, the first convex portion 27A and the second convex portion 27B are formed from each step layer so as to cover the dielectric layer 20 on one side in the stacking direction T (the lower side in FIGS. 5A and 6A ), but they may also be formed on the opposite side. That is, they may protrude so as to also cover the dielectric layer 20 on the other side in the stacking direction T (the upper side in FIGS. 5A and 6A ).

[0119] In the above-described embodiment, the laminate 10 has convex portions protruding from the step layer at both end faces (first end face LS1, second end face LS2) in the length direction L. However, if a step layer is present on the side face (first side face WS1, second side face WS2) of the laminate 10, such convex portions may protrude from the step layer on that side face. That is, the laminate 10 may have a third step region in which either the first internal electrode layer 31 or the second internal electrode layer 32 is not disposed between the dielectric layers 20 at the end on the first side face WS1 side and the end on the second side face WS2 side, and a third step layer may be disposed in this third step region. In that case, the first side face WS1 and the second side face WS2 may have a third convex portion protruding partially in the width direction W in a region extending from the third step layer to the dielectric layer 20 adjacent to at least one side of the third step layer in the stacking direction. In this configuration in which the convex portions protrude from the step layer on the side surface side, the convex portions catch on the portions of the external electrodes 40 that wrap around the first side surface WS1 and the second side surface WS2, creating an anchor effect that makes the electrodes less likely to peel off, improving the adhesive strength of the external electrodes 40. In addition, the intrusion of moisture from the first side surface WS1 and the second side surface WS2 is suppressed, improving moisture resistance reliability.

[0120] In the above-described embodiment, a multilayer ceramic capacitor is exemplified as the multilayer ceramic electronic component. However, the multilayer ceramic electronic component of the present disclosure is not limited thereto. For example, when a piezoelectric ceramic is used in the laminate, the multilayer ceramic electronic component functions as a ceramic piezoelectric element. Specific examples of piezoelectric ceramic materials include PZT (lead zirconate titanate)-based ceramic materials. Furthermore, when a semiconductor ceramic is used in the laminate, the multilayer ceramic electronic component functions as a thermistor element. Specific examples of semiconductor ceramic materials include spinel-based ceramic materials. Furthermore, when a magnetic ceramic is used in the laminate, the multilayer ceramic electronic component functions as an inductor element. Furthermore, when functioning as an inductor element, the internal electrode layers become coil-shaped conductors. Specific examples of magnetic ceramic materials include ferrite ceramic materials.

[0121] (1) A laminate including: a plurality of ceramic layers stacked in a stacking direction; first and second main surfaces opposing each other in the stacking direction; first and second side surfaces opposing each other in a width direction perpendicular to the stacking direction; first end surfaces and second end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; first internal electrode layers stacked alternately with the plurality of ceramic layers and exposed at the first end surfaces; second internal electrode layers stacked alternately with the plurality of ceramic layers and exposed at the second end surfaces; a first step layer disposed in a first step region between a pair of the ceramic layers opposed to each other via the second internal electrode layer, where the second internal electrode layer is not disposed, and exposed at the first end surfaces; and a second step layer disposed in a second step region between the pair of the ceramic layers opposed to each other via the first internal electrode layer, where the first internal electrode layer is not disposed, and exposed at the second end surfaces. a first external electrode disposed on the first end face and extending from the first end face to the first main surface, the second main surface, the first side surface, and the second side surface, the first external electrode being connected to the first internal electrode layer; and a second external electrode disposed on the second end face and extending from the second end face to the first main surface, the second main surface, the first side surface, and the second side surface, the second external electrode being connected to the second internal electrode layer, wherein the first end face has a first convex portion that partially protrudes in the length direction from the first step layer in a region spanning to the ceramic layer that is adjacent to at least one side of the first step layer in the stacking direction, and the second end face has a second convex portion that partially protrudes in the length direction from the second step layer in a region spanning to the ceramic layer that is adjacent to at least one side of the second step layer in the stacking direction.

[0122] (2) The multilayer ceramic electronic component according to (1), wherein the first protrusions and the second protrusions are each formed in an area of ​​3% or more of the dimension of the end faces of the ceramic layers in the stacking direction.

[0123] (3) The multilayer ceramic electronic component according to (1) or (2), wherein the amount of protrusion of the first convex portion in the length direction from the end face of the ceramic layer constituting the first end face is 98% or less of the dimension of the second internal electrode layer in the stacking direction, and the amount of protrusion of the second convex portion in the length direction from the end face of the ceramic layer constituting the second end face is 98% or less of the dimension of the first internal electrode layer in the stacking direction.

[0124] (4) The multilayer ceramic electronic component according to any one of (1) to (3), wherein the first step layer covers an end portion of the second internal electrode layer on the side of the first end face in the stacking direction, and the second step layer covers at least an end portion of the first internal electrode layer on the side of the second end face in the stacking direction.

[0125] (5) The laminate has a third step region between the ceramic layers at the end on the first side surface side and the end on the second side surface side, in which either the first internal electrode layer or the second internal electrode layer is not arranged, and a third step layer is arranged in the third step region, and the first side surface and the second side surface have a third convex portion that partially protrudes in the width direction in a region spanning from the third step layer to the ceramic layer adjacent to at least one side of the third step layer in the stacking direction.

[0126] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor (multilayer ceramic electronic component) 10 Laminate 20 Dielectric layer (ceramic layer) 25A First step layer 25B Second step layer 26A First step region 26B Second step region 27A First convex portion 27B Second convex portion 30 Internal electrode layer 31 First internal electrode layer 32 Second internal electrode layer 40 External electrode 40A First external electrode 40B Second external electrode L Length direction T Stacking direction W Width direction LS1 First end face LS2 Second end face TS1 First main surface TS2 Second main surface WS1 First side surface WS2 Second side surface

Claims

1. A plurality of ceramic layers stacked in a stacking direction; a first main surface and a second main surface opposed to each other in the stacking direction; a first side surface and a second side surface facing each other in a width direction perpendicular to the stacking direction; a first end surface and a second end surface facing each other in a length direction perpendicular to the stacking direction and the width direction; a first internal electrode layer that is laminated alternately with the plurality of ceramic layers and is exposed on the first end surface; a second internal electrode layer that is laminated alternately with the plurality of ceramic layers and is exposed on the second end surface; a first step layer that is disposed in a first step region between a pair of the ceramic layers facing each other with the second internal electrode layer interposed therebetween, in which the second internal electrode layer is not disposed, and that is exposed to the first end surface; a second step layer disposed in a second step region between a pair of the ceramic layers opposed to each other via the first internal electrode layer, in which the first internal electrode layer is not disposed, and exposed to the second end surface; A laminate comprising: a first external electrode disposed on the first end face and extending from the first end face to the first main face, the second main face, the first side face, and the second side face, and connected to the first internal electrode layer; a second external electrode disposed on the second end surface, extending from the second end surface to the first main surface, the second main surface, the first side surface, and the second side surface, and connected to the second internal electrode layer; Equipped with the first end face has a first protrusion that protrudes partially in the length direction in a region extending from the first step layer to the ceramic layer adjacent to at least one side of the first step layer in the stacking direction, the second end face has a second convex portion that protrudes partially in the length direction in a region extending from the second step layer to the ceramic layer adjacent to at least one side of the second step layer in the stacking direction.

2. 2. The multilayer ceramic electronic component according to claim 1, wherein each of the first and second protrusions is formed in an area of ​​at least 3% of a dimension of the end face of the ceramic layer in the stacking direction.

3. a protruding amount of the first protrusion in the length direction from an end face of the ceramic layer constituting the first end face is 98% or less of a dimension of the second internal electrode layer in a lamination direction, 3. The multilayer ceramic electronic component according to claim 1, wherein a protruding amount of the second convex portion in the length direction from an end face of the ceramic layer constituting the second end face is 98% or less of a dimension of the first internal electrode layer in the stacking direction.

4. the first step layer covers an end portion of the second internal electrode layer on the first end face side in the stacking direction, 3. The multilayer ceramic electronic component according to claim 1, wherein the second step layer covers at least an end portion of the first internal electrode layer on the second end face side in the stacking direction.

5. the laminate has a third step region in which either the first internal electrode layer or the second internal electrode layer is not disposed between the ceramic layers at the end on the first side surface side and the end on the second side surface side, and a third step layer is disposed in the third step region; 3. The multilayer ceramic electronic component according to claim 1, wherein the first side surface and the second side surface have a third convex portion that partially protrudes in the width direction in a region extending from the third step layer to the ceramic layer adjacent to at least one side of the third step layer in the stacking direction.