Semiconductor device

Abstract

This semiconductor device comprises a first conductive portion in which a plurality of first semiconductor elements are mounted, the first conductive portion including a first wiring portion and a second wiring portion that are spaced apart from each other in a first direction. A second conductive portion in which a plurality of second semiconductor elements are mounted includes a third wiring portion and a fourth wiring portion that are disposed between the first wiring portion and the second wiring portion in the first direction, and that are spaced apart from each other in the first direction. The plurality of first semiconductor elements disposed in the first wiring portion and the plurality of second semiconductor elements disposed in the third wiring portion are staggered from each other in a second direction. The plurality of first semiconductor elements disposed in the third wiring portion and the plurality of second semiconductor elements disposed in the fourth wiring portion are staggered from each other in the second direction.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Conventionally, semiconductor devices equipped with switching elements such as MOSFETs and IGBTs have been widely known. Patent Document 1 discloses an example of a semiconductor device equipped with multiple switching elements such as MOSFETs. In this semiconductor device, a metal layer made of a thin metal film such as copper foil is disposed on an insulating substrate made of an electrically insulating material. Multiple switching elements are conductively joined to the metal layer via a conductive bonding layer such as solder. In recent years, there has been an increasing demand for semiconductor devices capable of passing large currents. This semiconductor device can easily accommodate large currents by increasing the number of switching elements, for example.

[0003] In the semiconductor device disclosed in Patent Document 1, as shown in FIG. 3 of the same document, multiple switching elements are arranged side by side in a direction (second direction x2) perpendicular to the thickness direction of the insulating substrate. Furthermore, the multiple switching elements are arranged in two rows spaced apart in a first direction x1 perpendicular to the second direction x2 in a plan view. The multiple switching elements in each row are arranged at relatively narrow intervals in the second direction x2. Furthermore, the multiple switching elements in the first row and the multiple switching elements in the second row are aligned in the second direction x2, and the switching elements in the first row and the switching elements in the second row almost entirely overlap when viewed in the first direction x1.

[0004] When the semiconductor device is in use, heat is generated from the multiple switching elements. Increasing the number of switching elements allows a large current to flow, but this also increases the amount of heat generated by the multiple switching elements. Furthermore, with multiple switching elements arranged as described above, interference between the heat generated by the multiple switching elements is likely to cause a temperature rise. This hinders the flow of a large current through the semiconductor device.

[0005] JP 2018-182330 A

[0006] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that efficiently dissipates heat generated by multiple semiconductor elements and is suitable for passing a large current.

[0007] A first aspect of the present disclosure provides a semiconductor device comprising: an insulating substrate having a main surface facing one side in a thickness direction; first and second conductive portions arranged on the main surface; a plurality of first semiconductor elements mounted on the first conductive portion and each having a switching function; a plurality of second semiconductor elements mounted on the second conductive portion and each having a switching function; and a first main terminal, a second main terminal, and a third main terminal. The first main terminal is electrically connected to the first conductive portion and electrically connected to the plurality of first semiconductor elements via the first conductive portion. The second main terminal is electrically connected to the plurality of second semiconductor elements. The third main terminal is electrically connected to the second conductive portion and electrically connected to both the plurality of first semiconductor elements and the plurality of second semiconductor elements via the second conductive portion. The first conductive portion has a first wiring portion and a second wiring portion arranged at a distance on one side and the other side in a first direction perpendicular to the thickness direction. The second conductive portion has a third wiring portion and a fourth wiring portion that are arranged between the first wiring portion and the second wiring portion in the first direction and are spaced apart on one side and the other side in the first direction. The plurality of first semiconductor elements are arranged in groups of two in the first wiring portion and the second wiring portion, respectively, along a second direction that is orthogonal to both the thickness direction and the first direction. The plurality of second semiconductor elements are arranged in groups of two in the third wiring portion and the fourth wiring portion, respectively, along the second direction. The plurality of first semiconductor elements arranged in the first wiring portion and the plurality of second semiconductor elements arranged in the third wiring portion are arranged alternately in the second direction. The plurality of first semiconductor elements arranged in the second wiring portion and the plurality of second semiconductor elements arranged in the fourth wiring portion are arranged alternately in the second direction.

[0008] According to the above configuration, the semiconductor device can efficiently dissipate heat generated in the plurality of semiconductor elements.

[0009] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0010] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 3 is a view in which a lid and a sealing portion are omitted from the plan view of FIG. 2. FIG. 4 is a view in which a case is omitted from the plan view of FIG. 3. FIG. 5 is an enlarged view in which a heat sink and first to third main terminals are omitted from the plan view of FIG. 4. FIG. 6 is a front view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 7 is a rear view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 8 is a right side view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 9 is a left side view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 10 is a bottom view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 3. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 3. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 3. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 3. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 3. FIG. 16 is a plan view similar to FIG. 4, showing a semiconductor device according to a first modified example of the first embodiment. FIG. 17 is an enlarged view in which the heat sink and the first to third main terminals are omitted from the plan view of FIG. 16. FIG. 18 is a perspective view showing a semiconductor device according to a second embodiment of the present disclosure. FIG. 19 is a plan view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 20 is a view in which the lid and sealing portion are omitted from the plan view of FIG. 19. FIG. 21 is a view in which the case is omitted from the plan view of FIG. 20. FIG. 22 is a front view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 23 is a rear view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 24 is a right side view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 25 is a left side view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 26 is a bottom view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 27 is a plan view similar to FIG. 20, showing a semiconductor device according to a first modified example of the second embodiment of the present disclosure. This is a plan view of FIG. 27 with the case omitted.

[0011] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0012] The terms "first," "second," "third," etc. in this disclosure are used merely for identification purposes and are not intended to necessarily assign any order to their objects.

[0013] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0014] 1 to 15 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes a plurality of first semiconductor elements 10A, a plurality of second semiconductor elements 10B, a support substrate 3, a first main terminal 41, a second main terminal 42, a third main terminal 43, a plurality of control terminals 45, and a plurality of wires 51, 52, 53, 54, 551, 552, 561, and 562. The semiconductor device A1 further includes a case 6, a heat sink 7, a sealing portion 81, and a lid 82.

[0015] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a plan view showing the semiconductor device A1. FIG. 3 is a plan view showing the semiconductor device A1, with the lid 82 and sealing portion 81 omitted for ease of understanding. FIG. 4 is a plan view showing the semiconductor device A1, with the case 6 omitted from the plan view of FIG. 3. FIG. 5 is an enlarged view showing the heat sink 7 and the first main terminal 41, second main terminal 42, and third main terminal 43 omitted from the plan view of FIG. 4. FIG. 6 is a front view showing the semiconductor device A1. FIG. 7 is a rear view showing the semiconductor device A1. FIG. 8 is a right side view showing the semiconductor device A1. FIG. 9 is a left side view showing the semiconductor device A1. FIG. 10 is a bottom view showing the semiconductor device A1. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 3. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 3. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 3. Fig. 14 is a cross-sectional view taken along line XIV-XIV in Fig. 3. Fig. 15 is a cross-sectional view taken along line XV-XV in Fig. 3.

[0016] In the description of the semiconductor device A1, the thickness direction of the support substrate 3 is an example of a "thickness direction" and is referred to as the "thickness direction z." A direction perpendicular to the thickness direction z is an example of a "first direction" and is referred to as the "first direction x." A direction perpendicular to both the thickness direction z and the first direction x is an example of a "second direction" and is referred to as the "second direction y."

[0017] The multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are electronic components that are central to the functionality of the semiconductor device A1. The constituent material of each of the first semiconductor elements 10A and each of the second semiconductor elements 10B is a semiconductor material primarily composed of, for example, silicon carbide (SiC). This semiconductor material is not limited to SiC and may be silicon (Si), gallium nitride (GaN), diamond (C), or the like. Each of the first semiconductor elements 10A and each of the second semiconductor elements 10B is, for example, a power semiconductor chip with switching function, such as a metal oxide semiconductor field effect transistor (MOSFET). In this embodiment, the first semiconductor elements 10A and the second semiconductor elements 10B are MOSFETs, but are not limited thereto and may be other transistors such as insulated gate bipolar transistors (IGBTs). Each of the first semiconductor elements 10A and each of the second semiconductor elements 10B is the same element. Each of the first semiconductor elements 10A and each of the second semiconductor elements 10B is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET.

[0018] 11 to 13, the first semiconductor element 10A and the second semiconductor element 10B each have an element main surface 101 and an element back surface 102. In each of the first semiconductor elements 10A and the second semiconductor elements 10B, the element main surface 101 and the element back surface 102 are spaced apart in the thickness direction z. The element main surface 101 faces the z1 side in the thickness direction z, and the element back surface 102 faces the z2 side in the thickness direction z.

[0019] In this embodiment, the semiconductor device A1 includes six first semiconductor elements 10A and six second semiconductor elements 10B. However, the number of first semiconductor elements 10A and the number of second semiconductor elements 10B are not limited to this configuration and may be changed as appropriate depending on the performance required of the semiconductor device A1. In the example shown in FIGS. 3 to 5, six first semiconductor elements 10A and six second semiconductor elements 10B are arranged. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B may be four, five, or seven or more. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B may be equal to or different from each other. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B is determined by the current capacity handled by the semiconductor device A1.

[0020] The semiconductor device A1 is configured, for example, as a half-bridge switching circuit. In this case, a plurality of first semiconductor elements 10A form an upper arm circuit of the semiconductor device A1, and a plurality of second semiconductor elements 10B form a lower arm circuit. In the upper arm circuit, the plurality of first semiconductor elements 10A are connected in parallel to each other. In the lower arm circuit, the first semiconductor elements 10A are connected in parallel to each other. In the lower arm circuit, the plurality of second semiconductor elements 10B are connected in parallel to each other. Each first semiconductor element 10A and each second semiconductor element 10B are connected in series to form a bridge layer.

[0021] As shown in FIGS. 3 to 5 and 11 , each of the multiple first semiconductor elements 10A is mounted on a first conductive portion 32A of a support substrate 3, which will be described later. Each first semiconductor element 10A is conductively bonded to the first conductive portion 32A via a conductive bonding material 19. When each first semiconductor element 10A is bonded to the first conductive portion 32A, the element back surface 102 faces the first conductive portion 32A. Unlike the present embodiment, the multiple first semiconductor elements 10A may be mounted on a metal member that is not part of the DBC substrate or the like. In this case, the metal member corresponds to the "first conductive portion." This metal member may be supported by, for example, the DBC substrate or the like.

[0022] As shown in FIGS. 3 to 5, 11, and 12, each of the multiple second semiconductor elements 10B is mounted on a second conductive portion 32B of the support substrate 3, which will be described later. Each second semiconductor element 10B is conductively bonded to the second conductive portion 32B via a conductive bonding material 19. When each second semiconductor element 10B is bonded to the second conductive portion 32B, the element back surface 102 faces the second conductive portion 32B. Note that, unlike the present embodiment, the multiple second semiconductor elements 10B may be mounted on a metal member that is not part of the DBC substrate or the like. In this case, the metal member corresponds to the "second conductive portion." This metal member may be supported by, for example, the DBC substrate or the like.

[0023] The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B each have a first principal surface electrode 11, a second principal surface electrode 12, a third principal surface electrode 13, and a back surface electrode 15. The configurations of the first principal surface electrode 11, the second principal surface electrode 12, the third principal surface electrode 13, and the back surface electrode 15 described below are common to each of the first semiconductor elements 10A and each of the second semiconductor elements 10B. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 are provided on the element main surface 101. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 are insulated by an insulating film (not shown). The back surface electrode 15 is provided on the element back surface 102.

[0024] The first principal surface electrode 11 is, for example, a gate electrode, to which a drive signal (for example, a gate voltage) for driving the first semiconductor element 10A (second semiconductor element 10B) is input. In the first semiconductor element 10A (second semiconductor element 10B), the second principal surface electrode 12 is, for example, a source electrode, through which a source current flows. The third principal surface electrode 13 is, for example, a source sense electrode, through which a source current flows. In this embodiment, the third principal surface electrode 13 is composed of two separated regions when viewed in the thickness direction z. The back surface electrode 15 is, for example, a drain electrode, through which a drain current flows. The back surface electrode 15 covers the entire area (or substantially the entire area) of the element back surface 102. The back surface electrode 15 is, for example, composed of Ag (silver) plating.

[0025] When a drive signal (gate voltage) is input to the first principal surface electrode 11 (gate electrode), each first semiconductor element 10A (each second semiconductor element 10B) switches between a conductive state and a cut-off state in response to the drive signal. In the conductive state, current flows from the back surface electrode 15 (drain electrode) to the second principal surface electrode 12 (source electrode), and in the cut-off state, this current does not flow. In other words, each first semiconductor element 10A (each second semiconductor element 10B) performs a switching operation. The semiconductor device A1 converts a DC voltage input between the first main terminal 41 and the second main terminal 42 into, for example, an AC voltage using the switching functions of the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B, and outputs the AC voltage from the third main terminal 43.

[0026] 3 to 5, the semiconductor device A1 includes a thermistor 17. The thermistor 17 is used as a temperature detection sensor. Note that the semiconductor device A1 may include, for example, a temperature-sensitive diode in addition to the thermistor 17, or may not include the thermistor 17.

[0027] The support substrate 3 supports a plurality of first semiconductor elements 10A and a plurality of second semiconductor elements 10B. The specific configuration of the support substrate 3 is not limited in any way, and may be, for example, a DBC (Direct Bonded Copper) substrate or an AMB (Active Metal Brazing) substrate. The support substrate 3 includes an insulating substrate 31, a support conductor 32, and a back surface metal layer 33. The dimension of the support substrate 3 in the z direction is, for example, not less than 0.4 mm and not more than 3.0 mm.

[0028] The insulating substrate 31 is made of, for example, ceramics with excellent thermal conductivity. Examples of such ceramics include SiN (silicon nitride). The insulating substrate 31 is not limited to ceramics and may be an insulating resin sheet or the like. The insulating substrate 31 is, for example, rectangular in plan view. As shown in FIGS. 11 to 15 , the insulating substrate 31 has a main surface 311 and a back surface 312. The main surface 311 and the back surface 312 are spaced apart in the thickness direction z. The main surface 311 faces the z1 side in the thickness direction z, and the back surface 312 faces the z2 side in the thickness direction z. The dimension of the insulating substrate 31 in the thickness direction z is not particularly limited and is, for example, 0.05 mm or more and 1.0 mm or less.

[0029] As shown in FIGS. 3 to 5 , the support conductor 32 includes a first conductive portion 32A, a second conductive portion 32B, and a third conductive portion 32C. In this embodiment, the support conductor 32 further includes a first gate portion 326A, a second gate portion 326B, a first detection portion 327A, a second detection portion 327B, and a thermistor mounting portion 328. Each portion of the support conductor 32 is disposed on the main surface 311 of the insulating substrate 31. The constituent material of the support conductor 32 includes, for example, Cu (copper). The constituent material may include, for example, Al (aluminum) other than Cu (copper). The dimension of the thickness direction z of the support conductor 32 is not particularly limited and is, for example, 0.1 mm or more and 1.5 mm or less.

[0030] The first conductive portion 32A supports a plurality of first semiconductor elements 10A. As shown in FIG. 11 , the first conductive portion 32A has a support surface 320A. The support surface 320A is a flat surface facing the z1 side in the thickness direction z. The plurality of first semiconductor elements 10A are each bonded to the support surface 320A of the first conductive portion 32A via a conductive bonding material 19. The constituent material of the conductive bonding material 19 is not particularly limited and may be, for example, solder, a metal paste material, or a sintered metal.

[0031] 4 and 5 , the first conductive portion 32A has a first wiring portion 321, a second wiring portion 322, and a first connecting portion 325A. The first wiring portion 321 and the second wiring portion 322 are spaced apart from each other on the x1 side in the first direction x and the x2 side in the first direction x, and each extends in the second direction y. In this embodiment, the first wiring portion 321 is located at the end on the x1 side in the first direction x on the insulating substrate 31, and the second wiring portion 322 is located at the end on the x2 side in the first direction x on the insulating substrate 31.

[0032] The plurality of first semiconductor elements 10A are arranged in the first wiring portion 321 and the second wiring portion 322, with multiple elements arranged in each. In the illustrated example, three first semiconductor elements 10A are arranged in each of the first wiring portion 321 and the second wiring portion 322. The three first semiconductor elements 10A arranged in the first wiring portion 321 are spaced apart in the second direction y. The distance between adjacent first semiconductor elements 10A in the second direction y on the first wiring portion 321 is greater than the length of the first semiconductor elements 10A in the second direction y. The three first semiconductor elements 10A arranged in the second wiring portion 322 are similarly spaced apart in the second direction y. The distance between adjacent first semiconductor elements 10A in the second direction y on the second wiring portion 322 is greater than the length of the first semiconductor elements 10A in the second direction y.

[0033] The first wiring portion 321 has a first end portion 321a. The first end portion 321a is located on the y2 side of the first wiring portion 321 in the second direction y. The second wiring portion 322 has a second end portion 322a. The second end portion 322a is located on the y2 side of the second wiring portion 322 in the second direction y. The first connecting portion 325A is connected to both the first end portion 321a and the second end portion 322a. The first connecting portion 325A is located closer to the y2 side in the second direction y on the insulating substrate 31. In the example shown, the first connecting portion 325A is roughly U-shaped.

[0034] The second conductive portion 32B supports a plurality of second semiconductor elements 10B. As shown in Figures 12 and 13, the second conductive portion 32B has a support surface 320B. The support surface 320B is a flat surface facing the z1 side in the thickness direction z. The plurality of second semiconductor elements 10B are respectively bonded to the support surface 320B of the second conductive portion 32B via conductive bonding material 19.

[0035] 4 and 5 , the second conductive portion 32B has a third wiring portion 323, a fourth wiring portion 324, and a second connecting portion 325B. The third wiring portion 323 and the fourth wiring portion 324 are spaced apart from each other on the x1 side and the x2 side in the first direction x, and each extend in the second direction y. The third wiring portion 323 and the fourth wiring portion 324 are disposed between the first wiring portion 321 and the second wiring portion 322 in the first direction x.

[0036] The plurality of second semiconductor elements 10B are arranged in pairs on each of the third wiring portion 323 and the fourth wiring portion 324. In the illustrated example, three second semiconductor elements 10B are arranged on each of the third wiring portion 323 and the second wiring portion 322. The three second semiconductor elements 10B arranged on the third wiring portion 323 are spaced apart in the second direction y. The distance between adjacent second semiconductor elements 10B on the third wiring portion 323 in the second direction y is greater than the length of the second semiconductor elements 10B in the second direction y. The three second semiconductor elements 10B arranged on the fourth wiring portion 324 are similarly spaced apart in the second direction y. The distance between adjacent second semiconductor elements 10B on the fourth wiring portion 324 in the second direction y is greater than the length of the second semiconductor elements 10B in the second direction y.

[0037] The third wiring portion 323 has a third end portion 323a. The third end portion 323a is located on the y2 side of the third wiring portion 323 in the second direction y. The fourth wiring portion 324 has a fourth end portion 324a. The fourth end portion 324a is located on the y2 side of the fourth wiring portion 324 in the second direction y. The second connecting portion 325B is connected to both the third end portion 323a and the fourth end portion 324a. The second connecting portion 325B is located on the insulating substrate 31 closer to the y2 side in the second direction y.

[0038] In this embodiment, the multiple (three) first semiconductor elements 10A arranged on the first wiring portion 321 and the multiple (three) second semiconductor elements 10B arranged on the third wiring portion 323 are arranged alternately in the second direction y. In this disclosure, "alternately arranged" means that the multiple first semiconductor elements 10A on the first wiring portion 321 and the multiple second semiconductor elements 10B on the third wiring portion 323 are arranged with a shift in position in the second direction y without intentionally aligning them, and this also applies to the following description. Here, the first semiconductor elements 10A on the first wiring portion 321 and the second semiconductor elements 10B on the third wiring portion 323 may partially overlap when viewed in the first direction x. In the illustrated example, of the multiple first semiconductor elements 10A arranged in the first wiring portion 321 and the multiple second semiconductor elements 10B arranged in the third wiring portion 323, one first semiconductor element 10A and one second semiconductor element 10B partially overlap when viewed in the first direction x.

[0039] The plurality (three) of first semiconductor elements 10A arranged on the second wiring portion 322 and the plurality (three) of second semiconductor elements 10B arranged on the fourth wiring portion 324 are arranged alternately in the second direction y. The first semiconductor elements 10A on the second wiring portion 322 and the second semiconductor elements 10B on the fourth wiring portion 324 may partially overlap when viewed in the first direction x. In the illustrated example, the plurality of first semiconductor elements 10A arranged on the second wiring portion 322 and the plurality of second semiconductor elements 10B arranged on the fourth wiring portion 324 do not overlap when viewed in the first direction x.

[0040] In the semiconductor device A1, the multiple (three) first semiconductor elements 10A arranged on the first wiring portion 321 and the multiple (three) first semiconductor elements 10A arranged on the second wiring portion 322 are arranged alternately in the second direction y. The first semiconductor elements 10A on the first wiring portion 321 and the first semiconductor elements 10A on the second wiring portion 322 may partially overlap when viewed in the first direction x. In the illustrated example, of the multiple first semiconductor elements 10A arranged on the first wiring portion 321 and the multiple first semiconductor elements 10A arranged on the second wiring portion 322, one first semiconductor element 10A on the first wiring portion 321 and one first semiconductor element 10A on the second wiring portion 322 partially overlap when viewed in the first direction x.

[0041] 4 and 5 , at least a portion of third conductive portion 32C is disposed between third wiring portion 323 and fourth wiring portion 324 in first direction x. Third conductive portion 32C extends in second direction y. The above-described first conductive portion 32A, second conductive portion 32B, and third conductive portion 32C, together with multiple wires 51, 52, 53, and 54, form a path of a main circuit current switched by multiple first semiconductor elements 10A and multiple second semiconductor elements 10B.

[0042] 5 , the first gate portion 326A is electrically connected to the first main surface electrodes 11 of the plurality of first semiconductor elements 10A. The first gate portion 326A is arranged in a plurality of regions. In the example shown, the first gate portion 326A is arranged between the first wiring portion 321 and the third wiring portion 323, between the second wiring portion 322 and the fourth wiring portion 324, and between the third conductive portion 32C and the second connection portion 325B.

[0043] The first detection portion 327A is electrically connected to the third main surface electrodes 13 of the multiple first semiconductor elements 10A. The first detection portion 327A is arranged in multiple regions. In the example shown, the first detection portion 327A is arranged between the first wiring portion 321 and the third wiring portion 323, between the second wiring portion 322 and the fourth wiring portion 324, and between the third conductive portion 32C and the second connection portion 325B.

[0044] The second gate portion 326B is electrically connected to the first main surface electrodes 11 of the plurality of second semiconductor elements 10B. In the example shown, the second gate portion 326B is disposed between the third conductive portion 32C and the fourth wiring portion 324, and extends in the second direction y.

[0045] The second detection portion 327B is electrically connected to the third principal surface electrodes 13 of the plurality of second semiconductor elements 10B. In the example shown, the second detection portion 327B is disposed between the third conductive portion 32C and the fourth wiring portion 324, and extends in the second direction y.

[0046] 5, the thermistor mounting portions 328 are provided in pairs. The pair of thermistor mounting portions 328 are spaced apart from each other in the second direction y and mount the thermistor 17. The pair of thermistor mounting portions 328 are located near the corners of the insulating substrate 31.

[0047] The back surface metal layer 33 is formed on the back surface 312 of the insulating substrate 31. The constituent material of the back surface metal layer 33 is the same as the constituent material of the support conductors 32. The back surface metal layer 33 has a bottom surface 332. The bottom surface 332 is a flat surface facing the z2 side in the thickness direction z. A heat sink 7, which will be described later, is attached to the bottom surface 332.

[0048] As shown in Figures 1 to 4, the first main terminal 41, the second main terminal 42, and the third main terminal 43 are external connection terminals provided on the semiconductor device A1. The first main terminal 41, the second main terminal 42, and the third main terminal 43 are each made of a plate-shaped metal plate. This metal plate contains, for example, Cu (copper) or a Cu (copper) alloy. The thickness of the metal plate is not particularly limited and is, for example, about 1.0 mm.

[0049] The first main terminal 41 and the second main terminal 42 are connected to a DC power supply located outside the semiconductor device A1. A DC voltage to be converted into power is input to the first main terminal 41 and the second main terminal 42. The first main terminal 41 is a positive terminal (P terminal), and the second main terminal 42 is a negative terminal (N terminal). The first main terminal 41 and the second main terminal 42 are located on the y1 side of the support conductor 32 (the first conductive portion 32A and the second conductive portion 32B) in the second direction y. The first main terminal 41 and the second main terminal 42 are supported by the case 6.

[0050] As shown in FIGS. 3 , 4 , 11 , and 13 , the first main terminal 41 has an external connection portion 411, an internal connection portion 412, and an intermediate portion 413. The external connection portion 411 is exposed from the semiconductor device A1 and has a flat plate shape perpendicular to the thickness direction z. A DC power cable or the like is connected to the external connection portion 411. The external connection portion 411 is supported by the case 6. The external connection portion 411 has a connection hole 411a penetrating in the thickness direction z. A fastening member such as a bolt is inserted into the connection hole 411a. A nut 419 is fixed to the z2 side of the external connection portion 411 in the thickness direction z. The nut 419 is positioned corresponding to the connection hole 411a, and a fastening member such as a bolt inserted into the connection hole 411a fits into the nut 419. Note that the surface of the external connection portion 411 may be nickel (Ni) plated.

[0051] The internal connection portion 412 is electrically connected to the first conductive portion 32A. In the illustrated example, the internal connection portion 412 has a comb-like shape that is electrically connected to the first wiring portion 321 and the second wiring portion 322 of the first conductive portion 32A. In the semiconductor device A1, the internal connection portion 412 has four teeth. The teeth are bent in the thickness direction z. Therefore, the teeth are hook-shaped when viewed in the first direction x. Two teeth of the internal connection portion 412 are electrically connected to the end of the first wiring portion 321 on the y1 side in the second direction y, and the other two teeth of the internal connection portion 412 are electrically connected to the end of the second wiring portion 322 on the y1 side in the second direction y. The method of electrically connecting the internal connection portion 412 is not limited, and methods such as ultrasonic bonding, laser bonding, welding, or methods using solder, metal paste, silver sintered body, etc. may be used as appropriate. The intermediate portion 413 interconnects the external connection portion 411 and the internal connection portion 412. The intermediate portion 413 has an L-shaped cross section in the first direction x.

[0052] The first main terminal 41 is electrically connected to the first conductive portion 32A, and is electrically connected to the back surface electrode 15 (drain electrode) of each first semiconductor element 10A via the first conductive portion 32A.

[0053] As shown in FIGS. 3 , 4 , 11 , and 12 , the second main terminal 42 has an external connection portion 421, an internal connection portion 422, and an intermediate portion 423. The external connection portion 421 is exposed from the semiconductor device A1 and has a flat plate shape perpendicular to the thickness direction z. A DC power cable or the like is connected to the external connection portion 421. The external connection portion 421 is supported by the case 6. The external connection portion 421 is disposed on the x1 side in the first direction x relative to the external connection portion 411 of the first main terminal 41. The external connection portion 421 has a connection hole 421a penetrating in the thickness direction z. A fastening member such as a bolt is inserted into the external connection portion 421. A nut 429 is fixed to the z2 side of the external connection portion 421 in the thickness direction z. The nut 429 is disposed corresponding to the connection hole 421a, and a fastening member such as a bolt inserted into the connection hole 421a fits into the nut 429. The surface of the external connection portion 421 may be nickel plated.

[0054] The internal connection portion 422 is electrically connected to the third conductive portion 32C. In the illustrated example, the internal connection portion 422 has a comb-like shape that is electrically connected to the third conductive portion 32C. In the semiconductor device A1, the internal connection portion 422 has four teeth, which are arranged along the first direction x. The teeth are bent in the thickness direction z. As a result, the teeth are hook-shaped when viewed in the first direction x. The teeth of the internal connection portion 412 are electrically connected to the end of the third conductive portion 32C on the y1 side in the second direction y. The method of electrically connecting the internal connection portion 422 is not limited, and methods such as ultrasonic bonding, laser bonding, welding, or methods using solder, metal paste, silver sintered body, etc. may be appropriately adopted. The intermediate portion 423 interconnects the external connection portion 421 and the internal connection portion 422. The cross section of the intermediate portion 423 in the first direction x is L-shaped.

[0055] 5, the third conductive portion 32C and the second main surface electrode 12 of each second semiconductor element 10B are electrically connected via a wire 53 (described later). The second main terminal 42 is electrically connected to the third conductive portion 32C, and is also electrically connected to the second main surface electrode 12 (source electrode) of each second semiconductor element 10B via the third conductive portion 32C.

[0056] The third main terminal 43 is connected to a power supply target arranged outside the semiconductor device A1. The third main terminal 43 outputs an AC voltage converted by the first semiconductor element 10A and the second semiconductor element 10B. The third main terminal 43 is arranged on the y2 side in the second direction y with respect to the support conductor 32 (the first conductive portion 32A and the second conductive portion 32B). The third main terminal 43 is supported by the case 6.

[0057] As shown in Figures 3, 4, 12, and 13, the third main terminal 43 has an external connection portion 431, an internal connection portion 432, and an intermediate portion 433. The external connection portion 431 is exposed from the semiconductor device A1 and has a flat plate shape perpendicular to the thickness direction z. A cable or the like that is electrically connected to a power supply target is connected to the external connection portion 431. The external connection portion 431 has a connection hole 431a that penetrates in the thickness direction z. A fastening member such as a bolt is inserted into the connection hole 431a. The surface of the external connection portion 431 may be nickel-plated.

[0058] The internal connection portion 432 is electrically connected to the second conductive portion 32B. In the illustrated example, the internal connection portion 432 has a comb-like shape that is electrically connected to the second connecting portion 325B of the second conductive portion 32B. In the semiconductor device A1, the internal connection portion 432 has four teeth, which are arranged along the first direction x. The teeth are bent in the thickness direction z. Therefore, the teeth are hook-shaped when viewed in the first direction x. The teeth of the internal connection portion 432 are electrically connected to the second connecting portion 325B of the second conductive portion 32B. The method of electrically connecting the internal connection portion 432 is not limited, and methods such as ultrasonic bonding, laser bonding, welding, or methods using solder, metal paste, silver sintered body, etc. may be used as appropriate. The intermediate portion 433 interconnects the external connection portion 431 and the internal connection portion 432. The intermediate portion 433 is connected to the external connection portion 431 and extends continuously, and has a flat plate shape that is perpendicular to the thickness direction z. The intermediate portion 433 is supported by the case 6.

[0059] The third main terminal 43 is electrically connected to the second conductive portion 32B, and is electrically connected to the back surface electrode 15 (drain electrode) of each second semiconductor element 10B via the second conductive portion 32B.

[0060] Each of the plurality of control terminals 45 is a pin-shaped terminal for controlling the driving of each of the first semiconductor elements 10A and each of the second semiconductor elements 10B. Each of the plurality of control terminals 45 is, for example, a press-fit terminal. Each of the plurality of control terminals 45 is disposed on the main surface 311 of the insulating substrate 31 and extends toward the z1 side in the thickness direction z. The plurality of control terminals 45 includes a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47C. The plurality of first control terminals 46A to 46E are used for controlling each of the first semiconductor elements 10A, etc. The plurality of second control terminals 47A to 47C are used for controlling each of the second semiconductor elements 10B, etc.

[0061] The first control terminals 46A to 46E are supported by the support substrate 3 (support conductors 32). The first control terminals 46A to 46E are arranged on the support substrate 3 toward the y2 side in the second direction y.

[0062] The first control terminal 46A is a terminal (gate terminal) for inputting a drive signal to the plurality of first semiconductor elements 10A. A drive signal for driving the plurality of first semiconductor elements 10A is input to the first control terminal 46A (for example, a gate voltage is applied). The first control terminal 46A is supported by the first gate portion 326A.

[0063] The first control terminal 46B is a terminal (source sense terminal) for detecting source signals of the multiple first semiconductor elements 10A. The first control terminal 46B detects the voltage (voltage corresponding to the source current) applied to each second principal surface electrode 12 (source electrode) of the multiple first semiconductor elements 10A. The first control terminal 46B is supported by the first detection portion 327A.

[0064] The first control terminal 46C is a terminal (drain sense terminal) for detecting the drain voltages of the multiple first semiconductor elements 10A. The first control terminal 46C detects the voltage (voltage corresponding to the drain current) applied to each back surface electrode 15 (drain electrode) of the multiple first semiconductor elements 10A. The first control terminal 46C is supported by the first conductive portion 32A (the first end 321a of the first wiring portion 321).

[0065] The first control terminal 46D and the first control terminal 46E are terminals that are electrically connected to the thermistor 17. The first control terminal 46D and the first control terminal 46E are supported by the thermistor mounting portion 328, respectively.

[0066] The second control terminals 47A to 47C are supported by the support substrate 3 (support conductors 32). The second control terminals 47A to 47C are arranged on the support substrate 3 toward the y1 side in the second direction y.

[0067] The second control terminal 47A is a terminal (gate terminal) for inputting a drive signal for the plurality of second semiconductor elements 10B. A drive signal for driving the plurality of second semiconductor elements 10B is input to the second control terminal 47A (for example, a gate voltage is applied). The second control terminal 47A is supported by the second gate portion 326B.

[0068] The second control terminal 47B is a terminal (source sense terminal) for detecting source signals of the multiple second semiconductor elements 10B. The second control terminal 47B detects the voltage (voltage corresponding to the source current) applied to each second main surface electrode 12 (source electrode) of the multiple second semiconductor elements 10B. The second control terminal 47B is supported by the second detection portion 327B.

[0069] The second control terminal 47C is a terminal (drain sense terminal) for detecting the drain voltages of the second semiconductor elements 10B. The second control terminal 47C detects the voltage (voltage corresponding to the drain current) applied to each back electrode 15 (drain electrode) of the second semiconductor elements 10B. The second control terminal 47C is supported by the second conductive portion 32B (fourth wiring portion 324).

[0070] Each of the plurality of control terminals 45 (the plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47C) includes a holder 451 and a metal pin 452.

[0071] The holder 451 is made of a conductive material and is joined to each part of the supporting conductor 32 (the first gate part 326A, the first detection part 327A, the first conductive part 32A, etc.) via a conductive bonding material 459, as shown in FIGS.

[0072] The multiple wires 51, 52, 53, and 54 shown in Figures 4 and 5, together with the first conductive portion 32A, the second conductive portion 32B, and the third conductive portion 32C, form a path for the main circuit current switched by the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B.

[0073] The multiple wires 51 are conductive members that electrically connect the multiple first semiconductor elements 10A to the third wiring portion 323. Each of the multiple wires 51 is connected to the second main surface electrode 12 (source electrode) of the first semiconductor element 10A arranged on the first wiring portion 321 and the third wiring portion 323, thereby electrically connecting the second main surface electrode 12 of the first semiconductor element 10A to the third wiring portion 323. In the illustrated example, multiple (four) wires 51 are connected to one first semiconductor element 10A. Each wire 51 has a first portion 511 and a second portion 512.

[0074] The first portion 511 is a bonding end portion bonded to the second principal surface electrode 12 of the first semiconductor element 10A. The second portion 512 is a bonding end portion bonded to the third wiring portion 323. As shown in FIG. 5 , at least one of the second portions 512 of the multiple wires 51 is disposed on the third wiring portion 323 between adjacent second semiconductor elements 10B in the second direction y. The wires 51 are made of, for example, aluminum (Al) or copper (Cu). Note that the constituent material, diameter, and number of the wires 51 are not limited. The multiple wires 51 are an example of a "first conductive member." Note that the wires 51 are conductive members connected between the second principal surface electrode 12 (source electrode) of the first semiconductor element 10A and the third wiring portion 323. However, such conductive members may be formed, for example, from a metal plate instead of the wires 51.

[0075] The multiple wires 52 are conductive members that electrically connect the multiple first semiconductor elements 10A to the fourth wiring portion 324. Each of the multiple wires 52 is connected to the second main surface electrode 12 (source electrode) of the first semiconductor element 10A arranged on the second wiring portion 322 and the fourth wiring portion 324, thereby electrically connecting the second main surface electrode 12 of the first semiconductor element 10A to the fourth wiring portion 324. In the illustrated example, multiple (four) wires 52 are connected to one first semiconductor element 10A. Each wire 52 has a third portion 521 and a fourth portion 522.

[0076] The third portion 521 is a bonding end portion bonded to the second principal surface electrode 12 of the first semiconductor element 10A. The fourth portion 522 is a bonding end portion bonded to the fourth wiring portion 324. As shown in FIG. 5 , at least one of the fourth portions 522 of the multiple wires 52 is disposed on the fourth wiring portion 324 between adjacent second semiconductor elements 10B in the second direction y. The wires 52 are made of, for example, aluminum (Al) or copper (Cu). Note that the constituent material, diameter, and number of the wires 52 are not limited. The multiple wires 52 are an example of a "second conductive member." Note that the wires 52 are conductive members connected between the second principal surface electrode 12 (source electrode) of the first semiconductor element 10A and the fourth wiring portion 324. However, such conductive members may be formed, for example, from a metal plate instead of the wires 52.

[0077] The multiple wires 53 are conductive members that electrically connect the multiple second semiconductor elements 10B and the third conductive portion 32C. Each of the multiple wires 53 is connected to the second principal surface electrode 12 (source electrode) of the second semiconductor element 10B arranged on the third wiring portion 323 and the third conductive portion 32C, thereby electrically connecting the second principal surface electrode 12 of the second semiconductor element 10B and the third conductive portion 32C. In the illustrated example, multiple (four) wires 53 are connected to one second semiconductor element 10B. The wires 53 are made of, for example, aluminum (Al) or copper (Cu). The material, diameter, and number of the wires 53 are not limited. The wires 53 are conductive members that connect the second principal surface electrode 12 (source electrode) of the second semiconductor element 10B and the third conductive portion 32C. However, such conductive members may be formed, for example, from a metal plate instead of the wires 53.

[0078] The multiple wires 54 are conductive members that connect the multiple second semiconductor elements 10B to the third conductive portion 32C. Each of the multiple wires 54 is connected to the second principal surface electrode 12 (source electrode) of the second semiconductor element 10B arranged on the fourth wiring portion 324 and the third conductive portion 32C, thereby connecting the second principal surface electrode 12 of the second semiconductor element 10B to the third conductive portion 32C. In the illustrated example, multiple (four) wires 54 are connected to one second semiconductor element 10B. The wires 54 are made of, for example, aluminum (Al) or copper (Cu). The material, diameter, and number of the wires 54 are not limited. The wires 54 are conductive members that connect the second principal surface electrode 12 (source electrode) of the second semiconductor element 10B to the third conductive portion 32C. However, such conductive members may be formed, for example, from a metal plate instead of the wires 54.

[0079] The plurality of wires 551 are conductive members that electrically connect the first control terminal 46A (gate terminal) and the first main surface electrodes 11 (gate electrodes) of the plurality of first semiconductor elements 10A. The plurality of wires 551 include wires that are connected to the first main surface electrode 11 of the first semiconductor element 10A and the first gate portion 326A, and wires that are connected to first gate portions 326A that are spaced apart from each other. The material of the wires 551 is not particularly limited and may be, for example, aluminum.

[0080] The plurality of wires 552 are conductive members that electrically connect the first control terminal 46B (source sense terminal) and the third main surface electrodes 13 (source sense electrodes) of the plurality of first semiconductor elements 10A. The plurality of wires 552 include wires that are connected between the third main surface electrode 13 of the first semiconductor element 10A and the first detection unit 327A, wires that are connected between the second main surface electrode 12 (source electrode) of the first semiconductor element 10A and the first detection unit 327A, and wires that are connected between the first detection units 327A that are spaced apart from each other. The material of the wires 552 is not particularly limited and may be, for example, aluminum.

[0081] The plurality of wires 561 are conductive members that electrically connect the second control terminal 47A (gate terminal) and the first main surface electrodes 11 (gate electrodes) of the plurality of second semiconductor elements 10B. Each of the plurality of wires 561 is connected to the first main surface electrode 11 of the second semiconductor element 10B and the second gate portion 326B. The material of the wires 561 is not particularly limited and may be, for example, aluminum.

[0082] The plurality of wires 562 are conductive members that electrically connect the second control terminal 47B (source sense terminal) and the plurality of third main surface electrodes 13 (source sense electrodes) of the second semiconductor elements 10B. Each of the plurality of wires 562 is connected to the third main surface electrode 13 of the second semiconductor element 10B and the second detection unit 327B. The material of the wires 562 is not particularly limited and may be, for example, aluminum.

[0083] 3, 6 to 9, and 11 to 15, the case 6 is an electrically insulating member that surrounds the support substrate 3 when viewed in the thickness direction z. The material of the case 6 is not particularly limited, and is a synthetic resin with excellent heat resistance, such as PPS (polyphenylene sulfide). The case 6 has a pair of first side walls 611, a pair of second side walls 612, a plurality of mounting portions 62, and terminal support portions 63, 64.

[0084] 3, 14, and 15, the pair of first side walls 611 are spaced apart from each other in the first direction x. The pair of first side walls 611 are arranged along both the second direction y and the thickness direction z.

[0085] 3 and 11 to 13, the pair of second side walls 612 are spaced apart from each other in the second direction y. The pair of second side walls 612 are arranged along both the first direction x and the thickness direction z. Both ends of the pair of second side walls 612 in the first direction x are connected to the pair of first side walls 611.

[0086] 2 and 3 , the multiple mounting portions 62 are portions provided at the four corners of the case 6 when viewed in the thickness direction z. Each of the multiple mounting portions 62 has a through hole formed therethrough in the thickness direction z, and a mounting member 621 is fitted into each of the through holes. Each mounting member 621 has a mounting hole 621a formed therethrough in the thickness direction z. The semiconductor device A10 can be attached to an external device (not shown), for example, by fitting a fastening member (not shown) into the mounting hole 621a.

[0087] 3 , 8 , and 11 , the terminal support portion 63 protrudes outward in the second direction y (toward the y1 side in the second direction y) from the second side wall 612 on the y1 side in the second direction y. The first main terminal 41 and the second main terminal 42 are supported by the terminal support portion 63. The terminal support portion 64 protrudes outward in the second direction y (toward the y2 side in the second direction y) from the second side wall 612 on the y2 side in the second direction y. The terminal support portion 64 supports the third main terminal 43.

[0088] As shown in Figures 6 to 15, the heat sink 7 has a plate portion 71 and multiple fins 72. The plate portion 71 is a flat metal plate and has a generally rectangular shape when viewed in the thickness direction z. The multiple fins 72 extend from the surface of the plate portion 71 on the z2 side in the thickness direction z toward the z2 side in the thickness direction z. The multiple fins 72 are arranged at appropriate intervals in the first direction x and the second direction y. The constituent material of the heat sink 7 is not particularly limited, and may be, for example, a metal material containing aluminum (Al) or copper (Cu).

[0089] As shown in FIGS. 11 to 15 , the bottom surface 332 of the support substrate 3 (rear surface metal layer 33) is bonded to the surface of the plate portion 71 facing the z1 side in the thickness direction z via a bonding material 39. This allows the support substrate 3 to be supported by the heat sink 7. The bonding material 39 may be any material capable of bonding the rear surface metal layer 33 to the plate portion 71 (heat sink 7). To efficiently transfer heat from the rear surface metal layer 33 to the heat sink 7, the bonding material 39 is preferably one with higher thermal conductivity, such as silver paste, copper paste, or solder. However, the bonding material 39 may also be an insulating material such as an epoxy resin or a silicone resin. As can be seen from FIG. 10 and other figures, the case 6 is attached to the plate portion 71 with bolts 73 inserted through through-holes formed at appropriate locations.

[0090] 11 to 15, the sealing portion 81 is housed in an area surrounded by the case 6 and the heat sink 7. The plate portion 71 covers the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B. The constituent material of the sealing portion 81 is not particularly limited, and may be, for example, silicone gel.

[0091] The lid 82 is a member that closes the area housing the sealing portion 81 from the z1 side in the thickness direction z. The lid 82 is made of, for example, an electrically insulating synthetic resin. In the illustrated example, a metal plate 821 made of, for example, copper (Cu) is embedded inside the lid 82. As shown in FIGS. 14 and 15 , a plurality of openings 822 are formed in appropriate positions in the lid 82. The openings 822 penetrate the lid 82 in the thickness direction z, and the control terminals 45 extend through the openings 822, protruding beyond the lid 82 toward the z2 side in the thickness direction z. In the illustrated example, locking claws 611a are provided in appropriate positions on the first side wall 611 of the case 6, and the locking claws 611a lock the lid 82 when the lid 82 is attached.

[0092] Next, the operation of this embodiment will be described.

[0093] The semiconductor device A1 includes an insulating substrate 31, a first conductive portion 32A, a second conductive portion 32B, a plurality of first semiconductor elements 10A, a plurality of second semiconductor elements 10B, a first main terminal 41, a second main terminal 42, and a third main terminal 43. The first conductive portion 32A has a first wiring portion 321 and a second wiring portion 322 spaced apart on the x1 side and the x2 side of the first direction x. The second conductive portion 32B has a third wiring portion 323 and a fourth wiring portion 324 spaced apart on the x1 side and the x2 side of the first direction x. The plurality of first semiconductor elements 10A are arranged in multiples (three pieces) along the second direction y in each of the first wiring portion 321 and the second wiring portion 322. The plurality of second semiconductor elements 10B are arranged in multiples (three pieces) along the second direction y in each of the third wiring portion 323 and the fourth wiring portion 324. The plurality (three) of first semiconductor elements 10A arranged in the first wiring portion 321 and the plurality (three) of second semiconductor elements 10B arranged in the third wiring portion 323 are arranged alternately in the second direction y. Furthermore, the plurality (three) of first semiconductor elements 10A arranged in the second wiring portion 322 and the plurality (three) of second semiconductor elements 10B arranged in the fourth wiring portion 324 are arranged alternately in the second direction y.

[0094] According to this configuration, the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are distributed in four columns on the first wiring portion 321 to the fourth wiring portion 324. The plurality (three) of first semiconductor elements 10A and the plurality (three) of second semiconductor elements 10B on the first wiring portion 321 and the third wiring portion 323, which are adjacent in the first direction x, are arranged alternately in the second direction y, thereby suppressing interference of heat generated by the plurality (three) of first semiconductor elements 10A and the plurality (three) of second semiconductor elements 10B. Furthermore, the plurality (three) of first semiconductor elements 10A and the plurality (three) of second semiconductor elements 10B on the second wiring portion 322 and the fourth wiring portion 324, which are adjacent in the first direction x, are arranged alternately in the second direction y, thereby suppressing interference of heat generated by the plurality (three) of first semiconductor elements 10A and the plurality (three) of second semiconductor elements 10B. This allows the semiconductor device A1 to efficiently dissipate heat generated in the plurality of first semiconductor elements 10 A and the plurality of second semiconductor elements 10 B. The semiconductor device A1 is suitable for passing a large current.

[0095] In the semiconductor device A1, the plurality (three) of first semiconductor elements 10A arranged in the second wiring portion 322 and the plurality (three) of second semiconductor elements 10B arranged in the fourth wiring portion 324 do not overlap with each other when viewed in the first direction x. This configuration is preferable for efficiently dissipating heat generated in the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B.

[0096] The first main terminal 41 and the second main terminal 42 are disposed on the y1 side in the second direction y relative to the first conductive portion 32A and the second conductive portion 32B. The third main terminal 43 is disposed on the y2 side in the second direction y relative to the first conductive portion 32A and the second conductive portion 32B. A first end 321a of the first wiring portion 321 on the y2 side in the second direction y and a second end 322a of the second wiring portion 322 on the y2 side in the second direction y are electrically connected via a first connecting portion 325A. With this configuration, the potentials of the first wiring portion 321 and the second wiring portion 322, in which the multiple first semiconductor elements 10A are dispersedly disposed, can be made uniform, thereby achieving electrical stability when the multiple first semiconductor elements 10A are driven.

[0097] The first conductive portion 32A has a first connection portion 325A that is connected to both the first end 321a of the first wiring portion 321 and the second end 322a of the second wiring portion 322. With this configuration, it is possible to easily realize a configuration in which the first end 321a and the second end 322a are electrically connected.

[0098] A third end 323a on the y2 side in the second direction y of the third wiring portion 323 and a fourth end 324a on the y2 side in the second direction y of the fourth wiring portion 324 are electrically connected via the second connecting portion 325B. With this configuration, the potentials of the third wiring portion 323 and the fourth wiring portion 324, in which the plurality of second semiconductor elements 10B are dispersedly arranged, can be made uniform, and electrical stability is achieved when the plurality of second semiconductor elements 10B are driven.

[0099] The second conductive portion 32B has a second connection portion 325B that is connected to both the third end 323a of the third wiring portion 323 and the fourth end 324a of the fourth wiring portion 324. With this configuration, it is possible to easily realize a configuration in which the third end 323a and the fourth end 324a are electrically connected.

[0100] The plurality of wires 51 electrically connect the plurality of first semiconductor elements 10A arranged on the first wiring portion 321 to the third wiring portion 323. Of the plurality of wires 51, at least one of the second portions 512 joined to the third wiring portion 323 is arranged on the third wiring portion 323 between the second semiconductor elements 10B adjacent to each other in the second direction y. With this configuration, the plurality of first semiconductor elements 10A on the first wiring portion 321 and the plurality of second semiconductor elements 10B on the third wiring portion 323 can be arranged alternately, and the plurality of wires 51 can be arranged efficiently and in a space-saving manner.

[0101] The plurality of wires 52 electrically connect the plurality of first semiconductor elements 10A arranged on the second wiring portion 322 to the fourth wiring portion 324. Of the plurality of wires 51, at least one of the fourth portions 522 joined to the fourth wiring portion 324 is arranged on the fourth wiring portion 324 between the second semiconductor elements 10B adjacent to each other in the second direction y. With this configuration, the plurality of first semiconductor elements 10A on the second wiring portion 322 and the plurality of second semiconductor elements 10B on the fourth wiring portion 324 can be arranged alternately, and the plurality of wires 52 can be arranged efficiently in a space-saving manner.

[0102] First Modification of First Embodiment: Figures 16 and 17 show a semiconductor device according to a first modification of the first embodiment. Figure 16 is a plan view similar to Figure 4 of the above embodiment, showing a semiconductor device A11 of this modification. Figure 17 is an enlarged view in which the heat sink 7 and the first main terminal 41, second main terminal 42, and third main terminal 43 are omitted from the plan view of Figure 16. Note that in Figures 16 and subsequent figures, elements that are identical or similar to those of the semiconductor device A1 of the above embodiment are given the same reference numerals as in the above embodiment, and descriptions thereof will be omitted as appropriate. Furthermore, the configurations of the various parts in each of the modifications and embodiments shown in Figure 16 and subsequent figures can be combined with each other as appropriate to the extent that no technical contradictions arise.

[0103] In the semiconductor device A11 of this modified example, the arrangement of each part of the support conductor 32 (first conductive portion 32A, second conductive portion 32B, third conductive portion 32C, etc.) and the arrangement of the multiple first semiconductor elements 10A and multiple second semiconductor elements 10B differ from those of the semiconductor device A1 of the above embodiment.

[0104] In this modification, the multiple (three) first semiconductor elements 10A arranged in the first wiring portion 321 and the multiple (three) second semiconductor elements 10B arranged in the third wiring portion 323 are arranged alternately in the second direction y. The multiple first semiconductor elements 10A arranged in the first wiring portion 321 and the multiple second semiconductor elements 10B arranged in the third wiring portion 323 do not overlap in the first direction x. Furthermore, the multiple (three) first semiconductor elements 10A arranged in the second wiring portion 322 and the multiple (three) second semiconductor elements 10B arranged in the fourth wiring portion 324 are arranged alternately in the second direction y. The multiple first semiconductor elements 10A arranged in the second wiring portion 322 and the multiple second semiconductor elements 10B arranged in the fourth wiring portion 324 do not overlap in the first direction x. On the other hand, in the semiconductor device A11 of this modification, the positions of the multiple (three) first semiconductor elements 10A arranged in the first wiring portion 321 and the multiple (three) first semiconductor elements 10A arranged in the second wiring portion 322 are aligned in the second direction y. The multiple first semiconductor elements 10A arranged in the first wiring portion 321 and the multiple first semiconductor elements 10A arranged in the second wiring portion 322 completely overlap when viewed in the first direction x.

[0105] In this modification, the support conductor 32 (first conductive portion 32A) does not have a first connecting portion 325A, but instead has a first relay portion 329. The first relay portion 329 is located on the insulating substrate 31 closer to the y2 side in the second direction y. In the illustrated example, the first relay portion 329 is roughly U-shaped. The semiconductor device A11 includes a plurality of wires 57. One of the plurality of wires 57 is connected to the first end portion 321 a of the first wiring portion 321 and the first relay portion 329. One of the plurality of wires 57 is connected to the second end portion 322 a of the second wiring portion 322 and the first relay portion 329. As a result, the first end portion 321 a of the first wiring portion 321 and the second end portion 322 a of the second wiring portion 322 are electrically connected via the first relay portion 329 and the plurality of wires 57.

[0106] The semiconductor device A11 includes a plurality of wires 581 and a plurality of wires 582. The plurality of wires 581 are connected to the third wiring portion 323 and the fourth wiring portion 324 of the second conductive portion 32B. The plurality of wires 581 are connected to intermediate portions in the second direction y of the third wiring portion 323 and the fourth wiring portion 324. In the semiconductor device A11, the third conductive portion 32C has two portions extending in the second direction y, and is generally U-shaped with the ends of the two portions extending in the second direction y on the y2 side in the second direction y connected to each other. The plurality of wires 582 are connected to intermediate portions in the second direction y of the two portions of the third conductive portion 32C extending in the second direction y.

[0107] In the semiconductor device A11 of this modification, the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are distributed in four columns on the first wiring portion 321 to the fourth wiring portion 324. The multiple (three) first semiconductor elements 10A and the multiple (three) second semiconductor elements 10B on the first wiring portion 321 and the third wiring portion 323, which are adjacent in the first direction x, are arranged alternately in the second direction y, thereby suppressing interference between heat generated by the multiple (three) first semiconductor elements 10A and the multiple (three) second semiconductor elements 10B. Furthermore, the multiple (three) first semiconductor elements 10A and the multiple (three) second semiconductor elements 10B on the second wiring portion 322 and the fourth wiring portion 324, which are adjacent in the first direction x, are arranged alternately in the second direction y, thereby suppressing interference between heat generated by the multiple (three) first semiconductor elements 10A and the multiple (three) second semiconductor elements 10B. This allows the semiconductor device A11 to efficiently dissipate heat generated in the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B. The semiconductor device A11 is suitable for passing a large current.

[0108] In the semiconductor device A11, the plurality of first semiconductor elements 10A arranged in the first wiring portion 321 and the plurality of second semiconductor elements 10B arranged in the third wiring portion 323 do not overlap in the first direction x. Furthermore, the plurality (three) of first semiconductor elements 10A arranged in the second wiring portion 322 and the plurality (three) of second semiconductor elements 10B arranged in the fourth wiring portion 324 do not overlap in the first direction x. This configuration is more preferable for efficiently dissipating heat generated in the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B.

[0109] The first main terminal 41 and the second main terminal 42 are disposed on the y1 side in the second direction y with respect to the first conductive portion 32A and the second conductive portion 32B. The third main terminal 43 is disposed on the y2 side in the second direction y with respect to the first conductive portion 32A and the second conductive portion 32B. A first end 321a of the first wiring portion 321 on the y2 side in the second direction y and a second end 322a of the second wiring portion 322 on the y2 side in the second direction y are electrically connected via the first relay portion 329 and the plurality of wires 57. With this configuration, the potentials of the first wiring portion 321 and the second wiring portion 322, in which the plurality of first semiconductor elements 10A are dispersedly disposed, can be made uniform, thereby achieving electrical stability when the plurality of first semiconductor elements 10A are driven.

[0110] A third end 323a on the y2 side in the second direction y of the third wiring portion 323 and a fourth end 324a on the y2 side in the second direction y of the fourth wiring portion 324 are electrically connected via the second connecting portion 325B. With this configuration, the potentials of the third wiring portion 323 and the fourth wiring portion 324, in which the plurality of second semiconductor elements 10B are dispersedly arranged, can be made uniform, and electrical stability is achieved when the plurality of second semiconductor elements 10B are driven.

[0111] In this modification, a plurality of wires 581 are provided, and the plurality of wires 581 are connected to intermediate portions in the second direction y of the third wiring portion 323 and the fourth wiring portion 324. With this configuration, the potentials of the third wiring portion 323 and the fourth wiring portion 324 can be made more uniform, and the plurality of second semiconductor elements 10B mounted on the third wiring portion 323 and the fourth wiring portion 324 are more electrically stable when driven. In addition, within the same range of configuration as the semiconductor device A1 of the above embodiment, the same effects as those of the above embodiment are achieved.

[0112] Second Embodiment: Figures 18 to 26 show a semiconductor device A2 according to a second embodiment of the present disclosure. Figure 18 is a perspective view showing the semiconductor device A2. Figure 19 is a plan view showing the semiconductor device A2. Figure 20 is a plan view showing the semiconductor device A1, with the lid 82 and sealing portion 81 omitted for ease of understanding. Figure 21 is a view in which the case 6 is omitted from the plan view of Figure 20. Figure 22 is a front view showing the semiconductor device A2. Figure 23 is a rear view showing the semiconductor device A2. Figure 24 is a right side view showing the semiconductor device A2. Figure 25 is a left side view showing the semiconductor device A2. Figure 26 is a bottom view showing the semiconductor device A2.

[0113] The semiconductor device A2 of this embodiment includes a plurality of units U1, each unit U1 consisting of the support substrate 3, the plurality of first semiconductor elements 10A, the plurality of second semiconductor elements 10B, the first main terminal 41, the second main terminal 42, the third main terminal 43, the plurality of control terminals 45, and the plurality of wires of the semiconductor device A1 of the above embodiment. The plurality of units U1 are arranged adjacent to each other in the first direction x. In the illustrated example, three units U1 are arranged in the first direction x. The case 6 and the heat sink 7 have larger dimensions in the first direction x than those of the semiconductor device A1 described above and are appropriately modified. The plurality of units U1 are supported by the heat sink 7. Positioning pins 65 are provided at appropriate positions on the plurality of cases 6. The pins 65 are inserted into through holes formed in the plate portion 71 of the heat sink 7. The semiconductor device A2 is used, for example, in an inverter for driving a three-phase AC motor.

[0114] Next, the operation of this embodiment will be described.

[0115] In the semiconductor device A2 of this embodiment, the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are distributed in four columns on the first wiring portion 321 to the fourth wiring portion 324. The multiple (three) first semiconductor elements 10A and the multiple (three) second semiconductor elements 10B on the first wiring portion 321 and the third wiring portion 323, which are adjacent in the first direction x, are arranged alternately in the second direction y, thereby suppressing interference of heat generated by the multiple (three) first semiconductor elements 10A and the multiple (three) second semiconductor elements 10B. Furthermore, the multiple (three) first semiconductor elements 10A and the multiple (three) second semiconductor elements 10B on the second wiring portion 322 and the fourth wiring portion 324, which are adjacent in the first direction x, are arranged alternately in the second direction y, thereby suppressing interference of heat generated by the multiple (three) first semiconductor elements 10A and the multiple (three) second semiconductor elements 10B. This allows the semiconductor device A2 to efficiently dissipate heat generated in the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B. The semiconductor device A2 is suitable for passing a large current.

[0116] The semiconductor device A2 includes a plurality (three) of units U1, each of which includes a support substrate 3 (insulating substrate 31), a first conductive portion 32A, a second conductive portion 32B, a plurality of first semiconductor elements 10A, a plurality of second semiconductor elements 10B, a first main terminal 41, a second main terminal 42, and a third main terminal 43. The units U1 are arranged adjacent to each other in the first direction x. The semiconductor device A2 including the plurality (three) of units U1 can be suitably used, for example, as an inverter module for driving a three-phase AC motor. Even in the semiconductor device A2 configured as such an inverter module, heat generated by the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B can be efficiently dissipated, providing a preferable structure for passing large currents.

[0117] In the semiconductor device A2, the multiple (three) first semiconductor elements 10A arranged on the first wiring portion 321 and the multiple (three) first semiconductor elements 10A arranged on the second wiring portion 322 are arranged alternately in the second direction y. With this configuration, in two units U1 adjacent in the first direction x, the multiple (three) first semiconductor elements 10A on the first wiring portion 321 and the multiple (three) first semiconductor elements 10A on the second wiring portion 322 adjacent in the first direction x are arranged alternately in the second direction y. This makes it possible to suppress interference of heat generated by these multiple first semiconductor elements 10A. A semiconductor device A2 configured in this manner is more preferable in terms of improving heat dissipation.

[0118] In addition, within the scope of the same configuration as the semiconductor device A1 of the first embodiment, the same effects as those of the above embodiment are achieved.

[0119] First Modification of Second Embodiment: Figures 27 and 28 show a semiconductor device according to a first modification of the second embodiment. Figure 27 is a plan view similar to Figure 20 of the above embodiment, showing a semiconductor device A21 of this modification. Figure 28 is a view in which the case 6 is omitted from the plan view of Figure 27.

[0120] The semiconductor device A21 of this modification includes a plurality of units U2, each of which includes the support substrate 3, the plurality of first semiconductor elements 10A, the plurality of second semiconductor elements 10B, the first main terminal 41, the second main terminal 42, the third main terminal 43, the plurality of control terminals 45, and the plurality of wires in the semiconductor device A11 according to the first modification of the first embodiment. The plurality of units U2 are arranged adjacent to each other in the first direction x. In the illustrated example, three units U2 are arranged in the first direction x. The case 6 and the heat sink 7 have larger dimensions in the first direction x than those of the semiconductor device A1 described above and are appropriately modified. The plurality of units U2 are supported by the heat sink 7. The semiconductor device A21 is used, for example, in an inverter for driving a three-phase AC motor.

[0121] In the semiconductor device A21 of this embodiment, the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are distributed in four columns on the first wiring portion 321 to the fourth wiring portion 324. The multiple (three) first semiconductor elements 10A and the multiple (three) second semiconductor elements 10B on the first wiring portion 321 and the third wiring portion 323, which are adjacent in the first direction x, are arranged alternately in the second direction y, thereby suppressing interference between heat generated by the multiple (three) first semiconductor elements 10A and the multiple (three) second semiconductor elements 10B. Furthermore, the multiple (three) first semiconductor elements 10A and the multiple (three) second semiconductor elements 10B on the second wiring portion 322 and the fourth wiring portion 324, which are adjacent in the first direction x, are arranged alternately in the second direction y, thereby suppressing interference between heat generated by the multiple (three) first semiconductor elements 10A and the multiple (three) second semiconductor elements 10B. This allows the semiconductor device A21 to efficiently dissipate heat generated in the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B. The semiconductor device A21 is suitable for passing a large current.

[0122] The semiconductor device A21 includes a plurality (three) of units U2, each of which includes a support substrate 3 (insulating substrate 31), a first conductive portion 32A, a second conductive portion 32B, a plurality of first semiconductor elements 10A, a plurality of second semiconductor elements 10B, a first main terminal 41, a second main terminal 42, and a third main terminal 43. The units U2 are arranged adjacent to each other in the first direction x. The semiconductor device A21 including the plurality (three) of units U2 can be suitably used, for example, in an inverter module for driving a three-phase AC motor. The semiconductor device A21 configured as such an inverter module can also efficiently dissipate heat generated by the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B, providing a preferable structure for passing large currents. Additionally, within the same configuration as the semiconductor device A1 of the first embodiment and the semiconductor device A11 of the first variation of the first embodiment, the semiconductor device A21 achieves the same effects as the first embodiment and the first variation.

[0123] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways.

[0124] The present disclosure includes the embodiments described in the following appendices.

[0125] Supplementary Note 1. An insulating substrate having a main surface facing one side in a thickness direction; a first conductive portion and a second conductive portion arranged on the main surface; a plurality of first semiconductor elements mounted on the first conductive portion, each having a switching function; a plurality of second semiconductor elements mounted on the second conductive portion, each having a switching function; a first main terminal, a second main terminal, and a third main terminal, wherein the first main terminal is conductive to the first conductive portion and is electrically connected to the plurality of first semiconductor elements via the first conductive portion, the second main terminal is electrically connected to the plurality of second semiconductor elements, the third main terminal is conductive to the second conductive portion and is electrically connected to both the plurality of first semiconductor elements and the plurality of second semiconductor elements via the second conductive portion, and the first conductive portion has a first wiring portion and a second wiring portion arranged at a distance on one side and the other side in a first direction perpendicular to the thickness direction, the second conductive portion is disposed between the first wiring portion and the second wiring portion in the first direction and has a third wiring portion and a fourth wiring portion spaced apart on one side and the other side in the first direction, the plurality of first semiconductor elements are disposed in groups of two in the first wiring portion and the second wiring portion, along a second direction orthogonal to both the thickness direction and the first direction, the plurality of second semiconductor elements are disposed in groups of two in the third wiring portion and the fourth wiring portion, along the second direction, the plurality of first semiconductor elements disposed in the first wiring portion and the plurality of second semiconductor elements disposed in the third wiring portion are disposed alternately in the second direction, and the plurality of first semiconductor elements disposed in the second wiring portion and the plurality of second semiconductor elements disposed in the fourth wiring portion are disposed alternately in the second direction. Supplementary Note 2. The semiconductor device according to Supplementary Note 1, wherein the plurality of first semiconductor elements disposed in the first wiring portion and the plurality of second semiconductor elements disposed in the third wiring portion do not overlap when viewed in the first direction. Supplementary Note 3. 3. The semiconductor device according to claim 1, wherein the plurality of first semiconductor elements arranged in the second wiring portion and the plurality of second semiconductor elements arranged in the fourth wiring portion do not overlap when viewed in the first direction.Supplementary Note 4. The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the plurality of first semiconductor elements arranged in the first wiring portion and the plurality of first semiconductor elements arranged in the second wiring portion are arranged alternately in the second direction. Supplementary Note 5. The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the first main terminal and the second main terminal are arranged on one side in the second direction with respect to the first conductive portion and the second conductive portion, and the third main terminal is arranged on the other side in the second direction with respect to the first conductive portion and the second conductive portion. Supplementary Note 6. The semiconductor device according to Supplementary Note 5, wherein the first wiring portion has a first end portion located on the other side in the second direction, the second wiring portion has a second end portion located on the other side in the second direction, and the first end portion and the second end portion are electrically connected. Supplementary Note 7. The semiconductor device according to Supplementary Note 6, wherein the first conductive portion has a first connection portion connected to both the first end portion and the second end portion. Supplementary Note 8. The semiconductor device according to any one of Supplementary Notes 5 to 7, wherein the third wiring portion has a third end portion located on the other side in the second direction, and the fourth wiring portion has a fourth end portion located on the other side in the second direction, and the third end portion and the fourth end portion are electrically connected.Supplementary Note 9. The semiconductor device according to Supplementary Note 8, wherein the second conductive portion has a second connecting portion connected to both the third end portion and the fourth end portion.Supplementary Note 10. The semiconductor device according to Supplementary Note 9, wherein the third main terminal is conductively joined to the second connecting portion.Supplementary Note 11. The semiconductor device according to any one of Supplementary Notes 1 to 10, further comprising a third conductive portion arranged on the main surface, at least a portion of the third conductive portion being arranged between the third wiring portion and the fourth wiring portion in the first direction, and the second main terminal being conductive to the third conductive portion and electrically connected to the plurality of second semiconductor elements via the third conductive portion.Supplementary Note 12. The semiconductor device according to any one of Supplementary Notes 1 to 11, further comprising at least one first conductive member that electrically connects the plurality of first semiconductor elements arranged in the first wiring portion to the third wiring portion, wherein each of the at least one first conductive member has a first portion bonded to the first semiconductor element and a second portion bonded to the third wiring portion, and at least one of the second portions of the at least one first conductive member is disposed on the third wiring portion between the second semiconductor elements adjacent in the second direction. Supplementary Note 13. The semiconductor device according to any one of Supplementary Notes 1 to 12, further comprising at least one second conductive member that electrically connects the plurality of first semiconductor elements arranged in the second wiring portion to the fourth wiring portion, wherein each of the at least one second conductive member has a third portion bonded to the first semiconductor element and a fourth portion bonded to the fourth wiring portion, and at least one of the fourth portions of the at least one second conductive member is disposed on the fourth wiring portion between the second semiconductor elements adjacent in the second direction. Supplementary Note 14. The semiconductor device according to any one of Supplements 1 to 13, further comprising a plurality of control terminals for controlling the plurality of first semiconductor elements and the plurality of second semiconductor elements, wherein each of the plurality of control terminals is disposed on the main surface and extends to one side in the thickness direction. Supplementary Note 15. The semiconductor device according to any one of Supplements 1 to 14, further comprising a plurality of units each configured to include the insulating substrate, the first conductive portion, the second conductive portion, the plurality of first semiconductor elements, the plurality of second semiconductor elements, the first main terminal, the second main terminal, and the third main terminal, wherein the plurality of units are disposed adjacent to each other in the first direction. Supplementary Note 16. The semiconductor device according to Supplementary Note 15, further comprising a heat sink disposed on the other side in the thickness direction with respect to the insulating substrate of each of the plurality of units, wherein the plurality of units are supported by the heat sink.

[0126] A1, A11, A2, A21: semiconductor device U1, U2: unit 10A: first semiconductor element 10B: second semiconductor element 101: element main surface 102: element back surface 11: first main surface electrode 12: second main surface electrode 13: third main surface electrode 15: back surface electrode 17: thermistor 19: conductive bonding material 3: supporting substrate 31: insulating substrate 311: main surface 312: back surface 32: supporting conductor 32A: first conductive portion 32B: second conductive portion 32C: third conductive portion 320A, 320B: supporting surface 321: first wiring portion 321a: first end portion 322: second wiring portion 322a: second end portion 323: third wiring portion 323a: third end portion 324: fourth wiring portion 324a: fourth end portion 325A: First connecting portion 325B: Second connecting portion 326A: First gate portion 326B: Second gate portion 327A: First detecting portion 327B: Second detecting portion 328: Thermistor mounting portion 329: First relay portion 33: Back surface metal layer 332: Bottom surface 39: Bonding material 41: First main terminal 411: External connecting portion 411a: Connection hole 412: Internal connecting portion 413: Intermediate portion 419: Nut 42: Second main terminal 42 421: External connecting portion 421a: Connection hole 422: Internal connecting portion 423: Intermediate portion 429: Nut 43: Third main terminal 431: External connecting portion 431a: Connection hole 432: Internal connecting portion 433: Intermediate portion 45: Control terminal 451: Holder 452: Metal pin 459: Conductive bonding material 46A, 46B, 46C, 46D, 46E: First control terminal 47A, 47B, 47C: Second control terminal 51: Wire (first conductive member) 511: First part 512: Second part 52: Wire (second conductive member) 521: Third part 522: Fourth part 53, 54, 551, 552, 561, 562, 57, 581, 582: Wire 6: Case 611: First side wall 611a: Locking claw 612: Second side wall 62: Mounting part 621: Mounting member 621a: Mounting hole 63, 64: Terminal support part 65: Pin 7: Heat sink 71: Plate part 72: Fin 73: Bolt 81: Sealing part 82: Lid 821: Metal plate 822: Opening.

Claims

1. an insulating substrate having a main surface facing one side in a thickness direction; a first conductive portion and a second conductive portion disposed on the main surface; a plurality of first semiconductor elements mounted on the first conductive portion, each of the first semiconductor elements having a switching function; a plurality of second semiconductor elements mounted on the second conductive portion, each of the second semiconductor elements having a switching function; a first main terminal, a second main terminal, and a third main terminal; the first main terminal is conductively connected to the first conductive portion and is electrically connected to the first semiconductor elements via the first conductive portion; the second main terminal is electrically connected to the second semiconductor elements; the third main terminal is conductive to the second conductive portion and is electrically connected to both the first semiconductor elements and the second semiconductor elements via the second conductive portion; the first conductive portion has a first wiring portion and a second wiring portion arranged at a distance from each other on one side and the other side in a first direction perpendicular to the thickness direction, the second conductive portion is disposed between the first wiring portion and the second wiring portion in the first direction, and includes a third wiring portion and a fourth wiring portion spaced apart from each other on one side and the other side in the first direction, the first semiconductor elements are arranged in a plurality of rows in each of the first wiring portion and the second wiring portion along a second direction perpendicular to both the thickness direction and the first direction, the second semiconductor elements are arranged in a plurality of rows along the second direction in each of the third wiring portion and the fourth wiring portion, the first semiconductor elements arranged in the first wiring portion and the second semiconductor elements arranged in the third wiring portion are arranged alternately in the second direction, A semiconductor device, wherein the first semiconductor elements arranged in the second wiring portion and the second semiconductor elements arranged in the fourth wiring portion are arranged alternately in the second direction.

2. 2 . The semiconductor device according to claim 1 , wherein the first semiconductor elements arranged in the first wiring portion and the second semiconductor elements arranged in the third wiring portion do not overlap when viewed in the first direction.

3. 2 . The semiconductor device according to claim 1 , wherein the first semiconductor elements arranged in the second wiring portion and the second semiconductor elements arranged in the fourth wiring portion do not overlap when viewed in the first direction.

4. 2 . The semiconductor device according to claim 1 , wherein the first semiconductor elements arranged in the first wiring portion and the first semiconductor elements arranged in the second wiring portion are arranged alternately in the second direction.

5. the first main terminal and the second main terminal are disposed on one side in the second direction with respect to the first conductive portion and the second conductive portion, The semiconductor device according to claim 1 , wherein the third main terminal is disposed on the other side in the second direction with respect to the first conductive portion and the second conductive portion.

6. the first wiring portion has a first end portion located on the other side in the second direction, the second wiring portion has a second end portion located on the other side in the second direction, The semiconductor device according to claim 5 , wherein the first end and the second end are electrically connected to each other.

7. The semiconductor device according to claim 6 , wherein the first conductive portion has a first connection portion connected to both the first end portion and the second end portion.

8. the third wiring portion has a third end portion located on the other side in the second direction, the fourth wiring portion has a fourth end portion located on the other side in the second direction, The semiconductor device according to claim 5 , wherein the third end and the fourth end are electrically connected to each other.

9. The semiconductor device according to claim 8 , wherein the second conductive portion has a second connection portion connected to both the third end portion and the fourth end portion.

10. The semiconductor device according to claim 9 , wherein the third main terminal is conductively joined to the second connecting portion.

11. Further comprising a third conductive portion disposed on the main surface, at least a portion of the third conductive portion is disposed between the third wiring portion and the fourth wiring portion in the first direction; The semiconductor device according to claim 1 , wherein the second main terminal is electrically connected to the third conductive portion and is electrically connected to the plurality of second semiconductor elements via the third conductive portion.

12. at least one first conductive member that electrically connects the first semiconductor elements arranged in the first wiring portion to the third wiring portion; each of the at least one first conductive member has a first portion joined to the first semiconductor element and a second portion joined to the third wiring portion; 2 . The semiconductor device according to claim 1 , wherein at least one of the second portions of the at least one first conductive member is disposed between the second semiconductor elements adjacent in the second direction on the third wiring portion.

13. at least one second conductive member that electrically connects the first semiconductor elements arranged in the second wiring portion to the fourth wiring portion; each of the at least one second conductive member has a third portion joined to the first semiconductor element and a fourth portion joined to the fourth wiring portion; 2 . The semiconductor device according to claim 1 , wherein at least one of the fourth portions of the at least one second conductive member is disposed between the second semiconductor elements adjacent in the second direction on the fourth wiring portion.

14. a plurality of control terminals for controlling the plurality of first semiconductor elements and the plurality of second semiconductor elements; The semiconductor device according to claim 1 , wherein each of said plurality of control terminals is disposed on said main surface and extends to one side in said thickness direction.

15. a plurality of units each including the insulating substrate, the first conductive portion, the second conductive portion, the plurality of first semiconductor elements, the plurality of second semiconductor elements, the first main terminal, the second main terminal, and the third main terminal; The semiconductor device according to claim 1 , wherein the plurality of units are arranged adjacent to each other in the first direction.

16. a heat sink disposed on the other side of the insulating substrate of each of the plurality of units in the thickness direction; The semiconductor device according to claim 15 , wherein the units are supported by the heat sink.