Semiconductor testing apparatus

Abstract

This semiconductor testing apparatus comprises: a first node to which one end of a semiconductor switching device is electrically connected; a second node to which the other end of the semiconductor switching device is electrically connected; a first power source which is for high-voltage and low-current applications and which generates a first voltage and a first current; a second power source which is for low-voltage and high-current applications and which generates a second voltage lower than the first voltage and a second current greater than the first current; a first relay that has a withstand voltage equal to or higher than the first voltage and that is electrically interposed between the first node and the first power source; a second relay that has a withstand voltage equal to or higher than the second voltage and that is electrically interposed between the first node and the second power source; a third relay that has a withstand voltage equal to or higher than the first voltage and that is connected in parallel to the second relay; and a fourth relay that has a withstand voltage equal to or higher than the second voltage and that is connected in parallel to the second power source.

Description

Semiconductor Test Equipment

[0001] This application claims priority to Patent Application No. 2022-124695 filed with the Japan Patent Office on August 4, 2022, the entire contents of which are incorporated herein by reference. The present disclosure relates to a semiconductor testing apparatus.

[0002] Patent Document 1 discloses a semiconductor testing device that performs a thermal resistance test, a surge test, a switching characteristic test, and a continuous operation test on power semiconductor elements. Patent Document 2 discloses a semiconductor testing device that inspects the switching characteristics (dynamic characteristics) and saturation voltage (static characteristics) of power semiconductor elements.

[0003] JP 2010-107432 A JP 2012-229971 A

[0004] One embodiment provides a semiconductor testing apparatus capable of performing high-voltage, low-current testing and low-voltage, high-current testing on semiconductor switching devices.

[0005] One embodiment provides a semiconductor testing device including: a first node section to which one end of a semiconductor switching device is electrically connected; a second node section to which the other end of the semiconductor switching device is electrically connected; a first high-voltage, low-current power supply that generates a first voltage and a first current; a low-voltage, high-current second power supply that generates a second voltage lower than the first voltage and a second current higher than the first current; a first relay having a withstand voltage equal to or greater than the first voltage and electrically interposed between the first node section and the first power supply; a second relay having a withstand voltage equal to or greater than the second voltage and electrically interposed between the first node section and the second power supply; a third relay having a withstand voltage equal to or greater than the first voltage and connected in parallel to the second relay; and a fourth relay having a withstand voltage equal to or greater than the second voltage and connected in parallel to the second power supply.

[0006] The above and other objects, features, and advantages will become apparent from the following description of the embodiments with reference to the accompanying drawings.

[0007] FIG. 1 is a circuit diagram showing the electrical configuration of a semiconductor testing device according to one embodiment. FIG. 2 is a circuit diagram showing the circuit operation of the semiconductor testing device during a high-voltage, small-current test. FIG. 3 is a circuit diagram showing the circuit operation of the semiconductor testing device during a low-voltage, large-current test. FIG. 4 is a plan view showing the semiconductor rectifier shown in FIG. 1. FIG. 5 is a cross-sectional view taken along line VV shown in FIG. 4. FIG. 6 is a plan view showing an example of a semiconductor switching device (device under test). FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 6. FIG. 8 is a plan view showing the internal configuration of the semiconductor switching device shown in FIG. 6. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 8.

[0008] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrated, and are not necessarily to scale. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0009] When a term such as "substantially equal" is used in a description in which a comparison target is present, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the embodiments, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not attached with the intent of limiting the names of each structure.

[0010] 1 is a circuit diagram showing the electrical configuration of a semiconductor testing device 1 according to one embodiment. The semiconductor testing device 1 is a device that tests the electrical characteristics of a semiconductor switching device SW as a device under test. The semiconductor testing device 1 may also be called a "characteristics testing device" or a "semiconductor inspection device."

[0011] The semiconductor switching device SW is a semiconductor device including a transistor, and may include at least one of a metal insulator semiconductor field effect transistor (MISFET), an insulated gate bipolar transistor (IGBT), and a bipolar junction transistor (BJT).

[0012] The semiconductor switching device SW may have a Si-transistor including a Si (silicon) single crystal. The semiconductor switching device SW preferably has a wide bandgap semiconductor-transistor including a single crystal of a wide bandgap semiconductor. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of Si. Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond).

[0013] It is particularly preferable that the semiconductor switching device SW has a SiC-transistor including a SiC (silicon carbide) single crystal as an example of a wide bandgap semiconductor. In this embodiment, the semiconductor switching device SW is a SiC-MISFET (field effect transistor). The semiconductor switching device SW may include a planar gate type transistor or a trench gate type transistor.

[0014] The semiconductor switching device SW is preferably a power semiconductor switching device (power transistor) having a first breakdown voltage VB1 of 500 V or more. The first breakdown voltage VB1 may be 3000 V or less.

[0015] The first breakdown voltage VB1 may have a value belonging to any one of the ranges of 500V to 750V, 750V to 1000V, 1000V to 1250V, 1250V to 1500V, 1500V to 1750V, 1750V to 2000V, 2000V to 2250V, 2250V to 2500V, 2500V to 2750V, and 2750V to 3000V.

[0016] The semiconductor switching device SW includes a first terminal T1 (one end), a second terminal T2 (the other end), and a control terminal T3 (control end). In this embodiment, the first terminal T1, the second terminal T2, and the control terminal T3 are the drain terminal, source terminal, and gate terminal of a MISFET. If the semiconductor switching device SW includes an IGBT, the first terminal T1, the second terminal T2, and the control terminal T3 are the collector terminal, emitter terminal, and gate terminal of the IGBT. If the semiconductor switching device SW includes a BJT, the first terminal T1, the second terminal T2, and the control terminal T3 are the collector terminal, emitter terminal, and base terminal of the BJT.

[0017] In this embodiment, the semiconductor switching device SW includes a body diode BD electrically connected to the first terminal T1 and the second terminal T2, with the body diode BD having an anode electrically connected to the second terminal T2 and a cathode electrically connected to the first terminal T1.

[0018] The semiconductor testing device 1 includes a first node N1 (high potential application end) on one side (high potential side) and a second node N2 (low potential application end) on the other side (low potential side). In this embodiment, the second node N2 is connected to ground potential (e.g., zero potential). A first terminal T1 of a semiconductor switching device SW is electrically connected to the first node N1. A second terminal T2 of the semiconductor switching device SW is electrically connected to the second node N2. The first node N1 and the second node N2 are open ends except during testing, and the first terminal T1 and the second terminal T2 of the semiconductor switching device SW are electrically connected during testing.

[0019] The semiconductor testing device 1 includes a first power supply P1 for high-voltage, low-current testing that generates a relatively high first voltage VH and a relatively small first current IL. The first power supply P1 is configured to avoid high voltage and large current for safety reasons. The first power supply P1 has a first power switch S1 that is switchable between an on state and an off state. The first power supply P1 has a positive electrode on the first node N1 side and a negative electrode on the second node N2 side.

[0020] When the first power supply switch S1 is on, the first power supply P1 applies a first voltage VH and a first current IL to the first node N1. That is, the first power supply P1 applies the first voltage VH and the first current IL to the first terminal T1 of the semiconductor switching device SW. In the high-voltage, small-current test, a high voltage is applied to the semiconductor switching device SW in the off state, and a leakage current Ioff is measured as an off current flowing through the semiconductor switching device SW.

[0021] The first voltage VH is preferably lower than the first breakdown voltage VB1 of the semiconductor switching device SW. The first voltage VH may be 500 V or higher. The first voltage VH may be 3000 V or lower.

[0022] The first voltage VH may have a value belonging to any one of the ranges of 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or less, 2250V or more and 2500V or less, 2500V or more and 2750V or less, and 2750V or more and 3000V or less.

[0023] The first current IL is 1 A or less. Preferably, the first current IL is less than 1 A. Particularly preferably, the first current IL is 0.01 mA or more and 100 mA or less. The first current IL may have a value belonging to any one of the following ranges: 0.01 mA or more and 0.05 mA or less, 0.05 mA or more and 0.1 mA or less, 0.1 mA or more and 0.5 mA or less, 0.5 mA or more and 1 mA or less, 1 mA or more and 5 mA or less, 5 mA or more and 10 mA or less, 10 mA or more and 25 mA or less, 25 mA or more and 50 mA or less, 50 mA or more and 75 mA or less, and 75 mA or more and 100 mA or less. Preferably, the first current IL is 0.1 mA or more and 5 mA or less.

[0024] The semiconductor testing device 1 includes a second power supply P2 for low-voltage, high-current testing that generates a relatively low second voltage VL and a relatively large second current IH. Specifically, the second voltage VL is lower than the first voltage VH, and the second current IH is greater than the first current IL. The second power supply P2 is configured to avoid high voltage and high current for safety reasons. The second power supply P2 has a second power switch S2 that can be switched between an on state and an off state. The second power supply P2 has a positive electrode on the first node N1 side and a negative electrode on the second node N2 side.

[0025] The second power supply P2 applies a second voltage VL and a second current IH to the first node N1 when the second power supply switch S2 is on. That is, the second power supply P2 applies the second voltage VL and the second current IH to the first terminal T1 of the semiconductor switching device SW. In the low-voltage, large-current test, the on-resistance Ron of the semiconductor switching device SW is measured with a large current being applied to the semiconductor switching device SW in the on-state.

[0026] The second voltage VL may be equal to or less than 100 V. The second voltage VL may be equal to or greater than 0.1 V. The second voltage VL may have a value belonging to any one of the ranges of 0.1 V to 1 V, 1 V to 5 V, 5 V to 10 V, 10 V to 25 V, 25 V to 50 V, 50 V to 75 V, and 75 V to 100 V.

[0027] The second current IH may be 1 A or more. Preferably, the second current IH is greater than 1 A. The second current IH may be 100 A or less. The second current IH may have a value belonging to any one of the ranges of 1 A or more and 5 A or less, 5 A or more and 10 A or less, 10 A or more and 25 A or less, 25 A or more and 50 A or less, 50 A or more and 75 A or less, and 75 A or more and 100 A or less. It is particularly preferable that the second current IH be 10 A or more and 75 A or less.

[0028] The semiconductor testing device 1 includes a first relay R1 electrically connected between the first node N1 and the first power supply P1. For example, the first relay R1 may be an electromagnetic relay including an electromagnetic coil (electromagnet) and contacts (electromagnetic contacts). The first relay R1 is a high-voltage, low-current relay that can withstand the load caused by the first power supply P1. In other words, the first relay R1, like the first power supply P1, is configured to avoid high voltage and large current for safety reasons.

[0029] The first relay R1 is configured to switch between a conductive state (ON state) in which the first power source P1 is electrically connected to the first node N1 and a non-conductive state (OFF state) in which the first power source P1 is electrically disconnected from the first node N1. When the first relay R1 is in the conductive state, the first voltage VH and the first current IL of the first power source P1 are applied to the semiconductor switching device SW via the first node N1. When the first relay R1 is in the non-conductive state, the first voltage VH and the first current IL of the first power source P1 are cut off.

[0030] The first relay R1 has a first withstand voltage that is equal to or greater than the first voltage VH of the first power source P1. This prevents failure of the first relay R1 due to the voltage load of the first power source P1. The first withstand voltage is preferably greater than the first voltage VH. The first withstand voltage may be equal to or greater than 1 time and equal to or less than 100 times the first voltage VH. The first withstand voltage is preferably equal to or less than 10 times the first voltage VH. The first withstand voltage may be equal to or greater than 500V and equal to or less than 3000V.

[0031] The first withstand voltage may have a value belonging to any one of the ranges of 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or less, 2250V or more and 2500V or less, 2500V or more and 2750V or less, and 2750V or more and 3000V or less.

[0032] The first relay R1 has a first rated current flowing through it that is equal to or greater than the first current IL of the first power source P1, thereby preventing failure of the first relay R1 due to a current load on the first power source P1. The first rated current flowing through it is preferably greater than the first current IL.

[0033] The first rated current may be 1 to 100 times the first current IL. The first rated current is preferably 10 times the first current IL or less. The first rated current may be 1 A or less. The first rated current is preferably less than 1 A. The first rated current is particularly preferably 0.01 mA to 100 mA.

[0034] The first rated current may have a value belonging to any one of the ranges of 0.01 mA to 0.05 mA, 0.05 mA to 0.1 mA, 0.1 mA to 0.5 mA, 0.5 mA to 1 mA, 1 mA to 5 mA, 5 mA to 10 mA, 10 mA to 25 mA, 25 mA to 50 mA, 50 mA to 75 mA, and 75 mA to 100 mA. The first rated current may be 1 mA or more. The first rated current may be 5 mA or less.

[0035] The semiconductor testing device 1 includes a second relay R2 electrically connected between the first node N1 and the second power supply P2. For example, the second relay R2 may be an electromagnetic relay including an electromagnetic coil (electromagnet) and contacts (electromagnetic contacts). The second relay R2 is a low-voltage, high-current relay that can withstand the load caused by the second power supply P2. In other words, the second relay R2, like the second power supply P2, is configured to avoid high voltage and high current for safety reasons.

[0036] The second relay R2 is configured to switch between a conductive state (ON state) in which the second power source P2 is electrically connected to the first node N1 and a non-conductive state (OFF state) in which the second power source P2 is electrically disconnected from the first node N1. When the second relay R2 is in the conductive state, the second voltage VL and the second current IH of the second power source P2 are applied to the semiconductor switching device SW via the first node N1. When the second relay R2 is in the non-conductive state, the second voltage VL and the second current IH of the second power source P2 are cut off.

[0037] The second relay R2 has a second withstand voltage that is equal to or greater than the second voltage VL of the second power source P2. This prevents the second relay R2 from failing due to the voltage load of the second power source P2. The second withstand voltage is preferably greater than the second voltage VL. The second withstand voltage may be equal to or less than the first voltage VH of the first power source P1 (the first withstand voltage of the first relay R1). The second withstand voltage may be less than the first voltage VH of the first power source P1 (the first withstand voltage of the first relay R1).

[0038] The second withstand voltage may be 1 to 100 times the second voltage VL. The second withstand voltage is preferably 10 times or less the second voltage VL. The second withstand voltage may be 0.1 V to 100 V. The second withstand voltage may have a value belonging to any one of the ranges of 0.1 V to 1 V, 1 V to 5 V, 5 V to 10 V, 10 V to 25 V, 25 V to 50 V, 50 V to 75 V, and 75 V to 100 V. The second withstand voltage is preferably 1 V or more. It is particularly preferably 10 V or more.

[0039] The second relay R2 has a second rated conduction current that is equal to or greater than the second current IH of the second power source P2. This prevents failure of the second relay R2 due to a current load on the second power source P2. The second rated conduction current is preferably greater than the second current IH. The second rated conduction current may be equal to or greater than 1 time and equal to or less than 100 times the second current IH. The second rated conduction current is preferably equal to or less than 10 times the second current IH.

[0040] The second rated energization current may be 1 A or more and 200 A or less. The second rated energization current is preferably greater than 1 A. The second rated energization current may have a value belonging to any one of the following ranges: 1 A or more and 5 A or less, 5 A or more and 10 A or less, 10 A or more and 25 A or less, 25 A or more and 50 A or less, 50 A or more and 75 A or less, 75 A or more and 100 A or less, 100 A or more and 125 A or less, 125 A or more and 150 A or less, 150 A or more and 175 A or less, and 175 A or more and 200 A or less. The second rated energization current is preferably 10 A or more.

[0041] The semiconductor testing device 1 includes a third relay R3 connected in parallel to the second relay R2. For example, the third relay R3 may be an electromagnetic relay including an electromagnetic coil (electromagnet) and contacts (electromagnetic contacts). The third relay R3 is a high-voltage, low-current relay that can withstand the load caused by the first power supply P1. In other words, the third relay R3, like the first power supply P1, is configured to avoid high voltage and large current for safety reasons.

[0042] The third relay R3 is configured to switch between a conductive state (ON state) in which the second relay R2 is short-circuited and a non-conductive state (OFF state) in which the second relay R2 is not short-circuited. The third relay R3 has a third withstand voltage that is equal to or greater than the second voltage VL of the second power source P2. In other words, the third withstand voltage is equal to or greater than the second withstand voltage of the second relay R2. This prevents the third relay R3 from failing due to the voltage load of the second power source P2. It is particularly preferable that the third withstand voltage be greater than the second voltage VL of the second power source P2 (the second withstand voltage of the second relay R2).

[0043] In this embodiment, the third relay R3 shorts the second relay R2, thereby fixing the voltage across the second relay R2 to zero and protecting the second relay R2 from the voltage load caused by the first voltage VH of the first power source P1. Therefore, the third withstand voltage is equal to or greater than the first voltage VH of the first power source P1. This prevents the third relay R3 from failing due to the voltage load of the first power source P1. It is preferable that the third withstand voltage be greater than the first voltage VH.

[0044] The third withstand voltage may be 1 to 100 times the first voltage VH. The third withstand voltage is preferably 10 times or less the first voltage VH. The third withstand voltage may be 500V to 3000V.

[0045] The third withstand voltage may have a value belonging to any one of the ranges of 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or less, 2250V or more and 2500V or less, 2500V or more and 2750V or less, and 2750V or more and 3000V or less.

[0046] The third withstand voltage may be equal to or greater than the first withstand voltage of the first relay R1. The third withstand voltage may be less than the first withstand voltage. The third withstand voltage may be approximately equal to the first withstand voltage. In this case, the third relay R3 may be configured by the same type of relay as the first relay R1.

[0047] The third relay R3 has a third rated conduction current equal to or greater than the first current IL of the first power source P1. This prevents the first relay R1 from failing due to a current load on the first power source P1. The third rated conduction current is preferably greater than the first current IL. The third rated conduction current is less than the second current IH of the second power source P2.

[0048] The third rated current may be 1 to 100 times the first current IL. The third rated current is preferably 10 times the first current IL or less. It is particularly preferable that the third rated current is 2 times the first current IL or less. The third rated current may be 1 A or less. It is preferable that the third rated current is less than 1 A. It is particularly preferable that the third rated current is 0.01 mA or more and 100 mA or less.

[0049] The third rated current may have a value belonging to any one of the ranges of 0.01 mA to 0.05 mA, 0.05 mA to 0.1 mA, 0.1 mA to 0.5 mA, 0.5 mA to 1 mA, 1 mA to 5 mA, 5 mA to 10 mA, 10 mA to 25 mA, 25 mA to 50 mA, 50 mA to 75 mA, and 75 mA to 100 mA. The third rated current may be 1 mA or more. The third rated current may be 5 mA or less.

[0050] The semiconductor testing device 1 includes a fourth relay R4 connected in parallel to the second power supply P2. For example, the fourth relay R4 may be an electromagnetic relay including an electromagnetic coil (electromagnet) and contacts (electromagnetic contacts). The fourth relay R4 is a low-voltage, high-current relay that can withstand the load caused by the second power supply P2. In other words, like the second power supply P2, the fourth relay R4 is configured to avoid high voltage and high current for safety reasons.

[0051] The fourth relay R4 is configured to switch between a conductive state (ON state) in which the second power source P2 is short-circuited and a non-conductive state (OFF state) in which the second power source P2 is not short-circuited. The fourth relay R4 has a fourth withstand voltage that is equal to or greater than the second voltage VL of the second power source P2. This suppresses failure of the fourth relay R4 due to the voltage load of the second power source P2. The fourth withstand voltage is preferably greater than the second voltage VL. The fourth withstand voltage may be equal to or less than the first voltage VH of the first power source P1 (the first withstand voltage of the first relay R1). The fourth withstand voltage may be less than the first voltage VH of the first power source P1 (the first withstand voltage of the first relay R1).

[0052] The fourth withstand voltage may be 1 to 100 times the second voltage VL. The fourth withstand voltage is preferably 10 times or less the second voltage VL. The fourth withstand voltage may be 0.1 V to 100 V. The fourth withstand voltage may have a value belonging to any one of the ranges of 0.1 V to 1 V, 1 V to 5 V, 5 V to 10 V, 10 V to 25 V, 25 V to 50 V, 50 V to 75 V, and 75 V to 100 V. The fourth withstand voltage is preferably 1 V or more. It is particularly preferably 10 V or more.

[0053] The fourth withstand voltage may be equal to or greater than the second withstand voltage of the second relay R2. The fourth withstand voltage may be less than the second withstand voltage. The fourth withstand voltage may be approximately equal to the second withstand voltage. In this case, the fourth relay R4 may be configured by the same type of relay as the second relay R2.

[0054] The fourth relay R4 has a fourth rated conduction current that is equal to or greater than the first current IL of the first power source P1. The fourth rated conduction current is greater than the first current IL. The fourth rated conduction current is preferably equal to or greater than the second current IH of the second power source P2. This prevents failure of the fourth relay R4 due to a current load on the second power source P2. It is particularly preferable that the fourth rated conduction current be greater than the second current IH.

[0055] The fourth rated current may be 1 to 100 times the second current IH. The fourth rated current is preferably 10 times or less the second current IH. The fourth rated current may be 500 mA to 200 A.

[0056] The fourth rated current may have a value belonging to any one of the ranges of 500 mA to 1 A, 1 A to 5 A, 5 A to 10 A, 10 A to 25 A, 25 A to 50 A, 50 A to 75 A, 75 A to 100 A, 100 A to 125 A, 125 A to 150 A, 150 A to 175 A, and 175 A to 200 A. The fourth rated current may be 1 A or more. The fourth rated current may be greater than 1 A. The fourth rated current is preferably 10 A or less.

[0057] The semiconductor testing apparatus 1 includes a semiconductor rectifier D electrically connected between the first node N1 and the second power supply P2. The semiconductor rectifier D may also be referred to as a "rectifier," a "diode," or a "protection diode." The semiconductor rectifier D may include at least one of a pn junction diode, a pin junction diode, a Schottky barrier diode, and a fast recovery diode.

[0058] The semiconductor rectifier D may have a Si-diode including a Si single crystal. The semiconductor rectifier D preferably has a wide bandgap semiconductor-diode including a single crystal of a wide bandgap semiconductor. The semiconductor rectifier D particularly preferably has a SiC-diode including a SiC single crystal. In this form, the semiconductor rectifier D includes a SiC-Schottky barrier diode.

[0059] The semiconductor rectifier D has a second breakdown voltage VB2 that is equal to or greater than the second voltage VL of the second power supply P2. The second breakdown voltage VB2 is preferably greater than the second voltage VL. The second breakdown voltage VB2 is preferably equal to or greater than the first voltage VH of the first power supply P1. It is particularly preferable that the second breakdown voltage VB2 be greater than the first voltage VH.

[0060] The second breakdown voltage VB2 is preferably equal to or greater than the first breakdown voltage VB1 of the semiconductor switching device SW. The second breakdown voltage VB2 may be greater than the first breakdown voltage VB1. The second breakdown voltage VB2 may be equal to or greater than 500V. The second breakdown voltage VB2 may be equal to or less than 3000V.

[0061] The second breakdown voltage VB2 may have a value belonging to any one of the ranges of 500V to 750V, 750V to 1000V, 1000V to 1250V, 1250V to 1500V, 1500V to 1750V, 1750V to 2000V, 2000V to 2250V, 2250V to 2500V, 2500V to 2750V, and 2750V to 3000V.

[0062] The semiconductor rectifier D is electrically connected between the second relay R2 and the second power supply P2. The semiconductor rectifier D is connected in a reverse bias direction with respect to the voltage application direction of the first power supply P1. Specifically, the semiconductor rectifier D includes an anode electrically connected to the second power supply P2 and a cathode electrically connected to the second relay R2. From another perspective, the anode of the semiconductor rectifier D is electrically connected to the fourth relay R4, and the cathode is electrically connected to the third relay R3.

[0063] The semiconductor testing apparatus 1 includes a measurement unit MU electrically connected to the semiconductor switching device SW. For example, the measurement unit MU includes an ammeter that measures the current flowing through the semiconductor switching device SW and a voltmeter that measures the voltage across the semiconductor switching device SW.

[0064] The ammeter may be incorporated in a location where it can measure the current of the semiconductor switching device SW. For example, the ammeter may be electrically connected between the first node N1 and the first terminal T1 of the semiconductor switching device SW. For example, the ammeter may be electrically connected between the second node N2 and the second terminal T2 of the semiconductor switching device SW.

[0065] The voltmeter may be incorporated in a location where it can measure the voltage between the terminals of the semiconductor switching device SW. For example, the voltmeter may be connected between the first node portion N1 and the second node portion N2 (i.e., the first terminal T1 and the second terminal T2 of the semiconductor switching device SW). The measurement unit MU may be configured to measure a resistance value (on-resistance Ron) based on the voltage between the terminals and the current.

[0066] The semiconductor testing device 1 includes a drive unit DU electrically connected to the control terminal T3 of the semiconductor switching device SW. The drive unit DU includes a drive IC (gate driver circuit). The drive unit DU generates control signals for controlling the on / off of the semiconductor switching device SW and outputs the control signals to the control terminal T3 of the semiconductor switching device SW. The control signals include an on signal for controlling the semiconductor switching device SW to an on state and an off signal for controlling the semiconductor switching device SW to an off state.

[0067] The semiconductor testing apparatus 1 includes a control unit CU electrically connected to a first power supply P1, a second power supply P2, a first relay R1, a second relay R2, a third relay R3, a fourth relay R4, a driving unit DU, and a measuring unit MU. For example, the control unit CU includes a CPU, a memory (e.g., a ROM, a RAM, a non-volatile memory, etc.), and an electronic circuit, and is configured to control the first power supply P1, the second power supply P2, the first relay R1, the second relay R2, the third relay R3, the fourth relay R4, the driving unit DU, and the measuring unit MU based on a predetermined program (recipe) stored in the memory.

[0068] The control unit CU is configured to, when a high-voltage, small-current test is performed, control the semiconductor switching device SW to an off state, control the first power supply P1 to an on state, control the second power supply P2 to an off state, control the first relay R1 to a conductive state, control the second relay R2 to a non-conductive state, control the third relay R3 to a conductive state, and control the fourth relay R4 to a conductive state.

[0069] The control unit CU is configured to, during a low-voltage, high-current test, control the semiconductor switching device SW to an on state, control the first power supply P1 to an off state, control the second power supply P2 to an on state, control the first relay R1 to a non-conductive state, control the second relay R2 to a conductive state, control the third relay R3 to a non-conductive state, and control the fourth relay R4 to a non-conductive state.

[0070] Hereinafter, a high-voltage, small-current test and a low-voltage, large-current test for the semiconductor switching device SW will be described with reference to Figures 2 and 3. Figure 2 is a circuit diagram showing the circuit operation of the semiconductor testing device 1 during a high-voltage, small-current test. Figure 3 is a circuit diagram showing the circuit operation of the semiconductor testing device 1 during a low-voltage, large-current test. In Figures 2 and 3, for clarity, energized parts are indicated by thick lines and non-energized parts are indicated by dashed lines.

[0071] The high-voltage, small-current test (see FIG. 2) and the low-voltage, large-current test (see FIG. 3) may be performed in any order. Thus, the high-voltage, small-current test (see FIG. 2) may be followed by the low-voltage, large-current test (see FIG. 3), or the low-voltage, large-current test (see FIG. 3) may be performed followed by the high-voltage, small-current test (see FIG. 2). The high-voltage, small-current test (see FIG. 2) may be performed one or more times. The low-voltage, large-current test (see FIG. 3) may be performed one or more times.

[0072] 2, the high-voltage small-current test is performed on the semiconductor switching device SW in the off state. When the high-voltage small-current test is performed, the semiconductor switching device SW is controlled to the off state, the first power supply P1 (first power switch S1) is controlled to the on state, the second power supply P2 (second power switch S2) is controlled to the off state, the first relay R1 is controlled to the conductive state, the second relay R2 is controlled to the non-conductive state, the third relay R3 is controlled to the conductive state, and the fourth relay R4 is controlled to the conductive state.

[0073] This forms a parallel circuit in which the semiconductor switching device SW and the semiconductor rectifier D are connected in parallel to the first power supply P1. In this parallel circuit, a first voltage VH is applied to the semiconductor switching device SW in the off state, and a leakage current Ioff is generated in the semiconductor switching device SW from the first terminal T1 to the second terminal T2. The leakage current Ioff is measured by a measurement unit MU (ammeter). Here, the leakage current Ioff is measured in a voltage range less than the first breakdown voltage VB1 of the semiconductor switching device SW. The leakage current Ioff is less than the first current IL.

[0074] The third relay R3, the fourth relay R4, and the semiconductor rectifier D constitute a protection circuit that protects the second relay R2 and the second power supply P2 from a load caused by the first power supply P1. The third relay R3 shorts out the second relay R2, fixing the voltage across the second relay R2 to zero. Therefore, failure of the second relay R2 caused by the first voltage VH is suppressed.

[0075] Meanwhile, the third relay R3 is applied with the first voltage VH as a load, but the third relay R3 has a third withstand voltage equal to or greater than the first voltage VH. Therefore, a failure of the third relay R3 caused by the first voltage VH is suppressed. The fourth relay R4 short-circuits the second power supply P2 in the OFF state, fixing the voltage between the terminals of the second power supply P2 to the ground voltage. Therefore, a failure of the second power supply P2 caused by the first voltage VH is suppressed.

[0076] The semiconductor rectifier D is electrically connected to the first node N1 via the third relay R3 and to the second node N2 via the fourth relay R4. The semiconductor rectifier D is electrically connected between the third relay R3 and the fourth relay R4, thereby creating a voltage drop from the first voltage VH to the ground voltage toward the third relay R3 and the fourth relay R4. In other words, the fourth relay R4 (the voltage between the terminals of the second power supply P2) can be considered to be fixed to zero voltage by the semiconductor rectifier D.

[0077] Although the first voltage VH is applied to the semiconductor rectifier D as a load, the semiconductor rectifier D has a second breakdown voltage VB2 that is equal to or greater than the first voltage VH. Therefore, the semiconductor rectifier D does not break down due to the first voltage VH. Furthermore, because the semiconductor rectifier D does not break down due to the first voltage VH, the current path between the third relay R3 and the fourth relay R4 is blocked by the semiconductor rectifier D. This prevents device failures (e.g., failures of the second power supply P2, the third relay R3, the fourth relay R4, etc.) that may be caused by breakdown of the semiconductor rectifier D.

[0078] In this embodiment, the second relay R2 and the fourth relay R4 are low-voltage, high-current types and may have relatively large parasitic capacitance, but since the current path between the second relay R2 and the fourth relay R4 is blocked by the semiconductor rectifier D, deterioration in the detection accuracy of the leakage current Ioff caused by the parasitic capacitance of the second relay R2 and the parasitic capacitance of the fourth relay R4 is suppressed.

[0079] 3, the low-voltage, large-current test is performed on the semiconductor switching device SW in the ON state. When the low-voltage, large-current test is performed, the semiconductor switching device SW is controlled to the ON state, the first power supply P1 (first power switch S1) is controlled to the OFF state, the second power supply P2 (second power switch S2) is controlled to the ON state, the first relay R1 is controlled to the non-conductive state, the second relay R2 is controlled to the conductive state, the third relay R3 is controlled to the non-conductive state, and the fourth relay R4 is controlled to the non-conductive state.

[0080] As a result, a series circuit (closed circuit) is formed including the second power source P2, the second relay R2, the semiconductor rectifier D, and the semiconductor switching device SW (see the thick line). This series circuit does not include the first power source P1, the first relay R1, the third relay R3, or the fourth relay R4 (see the dashed line). The second current IH (large current) from the second power source P2 is applied to the semiconductor switching device SW via the second relay R2 and the semiconductor rectifier D, which can tolerate large currents.

[0081] As a result, an on-current Ion (drain-source current) flows through the semiconductor switching device SW from the first terminal T1 to the second terminal T2. The on-resistance Ron of the semiconductor switching device SW is measured by the measurement unit MU. For example, the on-resistance Ron is calculated from the division of the terminal voltage of the semiconductor switching device SW and the on-current Ion of the semiconductor switching device SW (Ron=V1 / Ion). Because the first relay R1, the third relay R3, and the fourth relay R4 are in a non-conductive state, a failure caused by the second current IH is avoided.

[0082] As described above, the semiconductor testing device 1 includes a first node unit N1, a second node unit N2, a first power supply P1 for high-voltage, small-current testing, a second power supply P2 for low-voltage, large-current testing, a first relay R1, a second relay R2, a third relay R3, and a fourth relay R4. The first node unit N1 is configured to be electrically connected to one end of the semiconductor switching device SW. The second node unit N2 is configured to be electrically connected to the other end of the semiconductor switching device SW.

[0083] The first power supply P1 is configured to generate a first voltage VH and a first current IL. The second power supply P2 is configured to generate a second voltage VL lower than the first voltage VH and a second current IH higher than the first current IL. The first relay R1 has a first withstand voltage equal to or greater than the first voltage VH and is electrically connected between the first node N1 and the first power supply P1. The second relay R2 has a second withstand voltage equal to or greater than the second voltage VL and is electrically connected between the first node N1 and the second power supply P2.

[0084] The third relay R3 has a third withstand voltage equal to or greater than the first voltage VH and is connected in parallel to the second relay R2. The fourth relay R4 has a fourth withstand voltage equal to or greater than the second voltage VL and is connected in parallel to the second power supply P2. This configuration makes it possible to provide a semiconductor testing device 1 that can perform a high-voltage, small-current test (see FIG. 2) and a low-voltage, large-current test (see FIG. 3) on the semiconductor switching device SW.

[0085] The semiconductor testing device 1 preferably includes a semiconductor rectifier D electrically connected between the second power supply P2 and the second relay R2. With this configuration, the withstand voltage of the semiconductor rectifier D can be utilized to protect the second power supply P2 from a load caused by the first power supply P1.

[0086] The semiconductor test device 1 is effective for testing power semiconductor devices used under high-load (high-voltage, large-current) environments. The semiconductor test device 1 is effective for testing wide-bandgap semiconductor switching devices. The semiconductor test device 1 is particularly effective for testing SiC semiconductor switching devices.

[0087] An example of the semiconductor rectifier D shown in Fig. 1 will be described below. Fig. 4 is a plan view showing the semiconductor rectifier D shown in Fig. 1. Fig. 5 is a cross-sectional view taken along line VV shown in Fig. 4. Referring to Figs. 4 and 5, the semiconductor rectifier D includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape).

[0088] The chip 2 may be a Si chip including a Si single crystal. That is, the semiconductor rectifier D may be a "Si semiconductor rectifier." The chip 2 is preferably made of a wide bandgap semiconductor chip including a single crystal of a wide bandgap semiconductor. That is, the semiconductor rectifier D is preferably a "wide bandgap semiconductor rectifier."

[0089] In this embodiment, chip 2 is a SiC chip including a hexagonal SiC single crystal. In other words, semiconductor rectifier D is a "SiC semiconductor rectifier." Hexagonal SiC single crystal has a variety of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which chip 2 includes a 4H-SiC single crystal, but the selection of other polytypes is not excluded.

[0090] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the chip 2. The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of a SiC single crystal.

[0091] In this case, it is preferable that the first main surface 3 is formed by the silicon surface of the SiC single crystal, and the second main surface 4 is formed by the carbon surface of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane. The off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be greater than 0° and not more than 10°. The off angle is preferably not more than 5°.

[0092] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. The first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0093] The semiconductor rectifier D includes an n-type first semiconductor region 6 formed in a region (surface layer) on the first main surface 3 side of the chip 2. The first semiconductor region 6 is formed in a layer shape extending along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is made of an epitaxial layer (SiC epitaxial layer).

[0094] The semiconductor rectifier D includes an n-type second semiconductor region 7 formed in a region (surface layer) on the second main surface 4 side within the chip 2. The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6, and is electrically connected to the first semiconductor region 6 within the chip 2. The second semiconductor region 7 is formed in a layer shape extending along the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0095] In this embodiment, the second semiconductor region 7 is made of a semiconductor substrate (SiC substrate). That is, the chip 2 has a layered structure including a substrate and an epitaxial layer. The thickness of the second semiconductor region 7 may be greater than the thickness of the first semiconductor region 6. The thickness of the second semiconductor region 7 may be less than the thickness of the first semiconductor region 6. Of course, a configuration not including the second semiconductor region 7 (semiconductor substrate) may also be employed. That is, the chip 2 may have a single-layer structure made of an epitaxial layer.

[0096] The semiconductor rectifier D includes an n-type diode region 8 formed in a surface layer portion of the first main surface 3. In this embodiment, the diode region 8 is formed by utilizing the first semiconductor region 6. The diode region 8 is formed in an inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The diode region 8 is formed in a polygonal shape (a quadrangular shape in this embodiment) in a plan view.

[0097] The semiconductor rectifier D includes a p-type (second conductivity type) guard region 9 formed in a surface layer portion of the first main surface 3. The guard region 9 is formed in a surface layer portion of the first semiconductor region 6 at a distance inward from the periphery of the first main surface 3. The guard region 9 is formed in a polygonal ring shape (a quadrangular ring in this embodiment) surrounding the diode region 8 in a plan view. The guard region 9 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the periphery side of the first main surface 3.

[0098] The semiconductor rectifier D includes a main surface insulating film 10 that selectively covers the first main surface 3. The main surface insulating film 10 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the main surface insulating film 10 has a single-layer structure including a silicon oxide film. It is particularly preferable that the main surface insulating film 10 include a silicon oxide film made of an oxide of the chip 2.

[0099] The main surface insulating film 10 has a contact opening 11 that exposes the inner edge portions of the diode region 8 and the guard region 9. The contact opening 11 may be formed in a polygonal shape (a quadrangular shape in this embodiment) that extends along the periphery of the diode region 8 (the inner edge portion of the guard region 9) in a plan view. The main surface insulating film 10 covers the first main surface 3 so as to be continuous with the periphery of the first main surface 3. Of course, the main surface insulating film 10 may cover the first main surface 3 at a distance inward from the periphery of the first main surface 3 so as to expose the periphery of the first main surface 3.

[0100] The semiconductor rectifier D includes a first polarity terminal 12 that forms a Schottky junction with the diode region 8. The first polarity terminal 12 is formed as an anode terminal (the anode of the semiconductor rectifier D). The first polarity terminal 12 extends from above the main surface insulating film 10 into the contact opening 11 and is electrically connected to the inner edges of the diode region 8 and the guard region 9. The first polarity terminal 12 is disposed inwardly from the periphery of the first main surface 3 at a distance, and is formed in a polygonal shape (a quadrangle in this embodiment) that follows the periphery of the first main surface 3 in a plan view.

[0101] The first polarity terminal 12 has a laminated structure including a first electrode film 13 and a second electrode film 14 laminated in this order from the first main surface 3 side. The first electrode film 13 is a Schottky barrier electrode film that forms a Schottky junction with the diode region 8. The material of the first electrode film 13 is arbitrary as long as a Schottky junction is formed.

[0102] The first electrode film 13 may be made of a metal film containing at least one of magnesium (Mg), aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), cobalt (Co), nickel (Ni), copper (Cu), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten (W), platinum (Pt), and gold (Au). Of course, the first electrode film 13 may also be made of an alloy film containing at least one of these metal species. In this embodiment, the first electrode film 13 is made of a Ti film.

[0103] The second electrode film 14 is made of a Cu-based metal film or an Al-based metal film and has a thickness greater than that of the first electrode film 13. The second electrode film 14 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the second electrode film 14 has a single-layer structure made of an AlCu alloy film.

[0104] The semiconductor rectifier D includes an upper insulating film 15 that covers the first polarity terminal 12. The upper insulating film 15 is preferably thicker than the first polarity terminal 12. The thickness of the upper insulating film 15 is preferably less than the thickness of the chip 2. The upper insulating film 15 is formed spaced inward from the periphery of the first main surface 3, and covers the periphery of the first polarity terminal 12. The upper insulating film 15 defines a pad opening 16 on the inner side of the chip 2, and defines a street region 17 on the periphery side of the chip 2.

[0105] The pad opening 16 exposes the inner portion of the first polarity terminal 12. The pad opening 16 is formed in a polygonal shape (a quadrangle in this embodiment) that follows the periphery of the first polarity terminal 12 in a plan view. The street region 17 extends along the periphery of the chip 2 and exposes the main surface insulating film 10. Of course, if the main surface insulating film 10 exposes the periphery of the first main surface 33, the street region 17 may also expose the periphery of the first main surface 33.

[0106] In this embodiment, the upper insulating film 15 has a laminated structure including an inorganic insulating film 18 (inorganic film) and an organic insulating film 19 (organic film), which are laminated in this order from the first polarity terminal 12 side. The inorganic insulating film 18 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film 18 preferably includes an insulating material different from that of the main surface insulating film 10. In this embodiment, the inorganic insulating film 18 has a single-layer structure including a silicon nitride film. The inorganic insulating film 18 preferably has a thickness smaller than that of the first polarity terminal 12.

[0107] The organic insulating film 19 is thicker than the inorganic insulating film 18 and covers the inorganic insulating film 18. The organic insulating film 19 preferably has a thickness greater than the thickness of the first polarity terminal 12. The organic insulating film 19 is preferably made of a photosensitive resin film. The organic insulating film 19 may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0108] The organic insulating film 19 may expose the inner edge of the inorganic insulating film 18 in the pad opening 16. The organic insulating film 19 may expose the outer edge of the inorganic insulating film 18 in the street region 17. The organic insulating film 19 may expose either or both of the inner edge and the outer edge of the inorganic insulating film 18.

[0109] In this embodiment, the organic insulating film 19 exposes both the inner and outer edge portions of the inorganic insulating film 18, and defines the pad opening 16 and the street region 17 together with the inorganic insulating film 18. Of course, the organic insulating film 19 may cover both the inner and outer edge portions of the inorganic insulating film 18.

[0110] The semiconductor rectifier D includes a second polarity terminal 20 covering the second main surface 4. The second polarity terminal 20 is formed as a cathode terminal (the cathode of the semiconductor rectifier D). The second polarity terminal 20 is electrically connected to the second semiconductor region 7 exposed from the second main surface 4. The second polarity terminal 20 may include at least one of an Al-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film.

[0111] For example, second polarity terminal 20 may have a layered structure including a Ti film, a Ni film, and an Au film stacked in this order from the second main surface 4. For example, second polarity terminal 20 may have a layered structure including an AlSi alloy film, a Ti film, a Ni film, and an Au film stacked in this order from the second main surface 4. For example, second polarity terminal 20 may have a layered structure including a Ti film, a Ni film, an Au film, and an Ag film stacked in this order from the second main surface 4.

[0112] An example of the semiconductor switching device SW shown in Fig. 1 will be described below. Fig. 6 is a plan view showing an example of the semiconductor switching device SW (device under test). Fig. 7 is a cross-sectional view taken along line VII-VII shown in Fig. 6. Fig. 8 is a plan view showing the internal configuration (transistor structure 38) of the semiconductor switching device SW shown in Fig. 6. Fig. 9 is a cross-sectional view taken along line IX-IX shown in Fig. 8.

[0113] 6 to 9, the semiconductor switching device SW includes a chip 32 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). The chip 32 may be a Si chip including a Si single crystal. That is, the semiconductor switching device SW may be a "Si semiconductor switching device." The chip 32 is preferably made of a wide bandgap semiconductor chip including a single crystal of a wide bandgap semiconductor. That is, the semiconductor switching device SW is preferably a "wide bandgap semiconductor switching device."

[0114] In this embodiment, the chip 32 is a SiC chip including a hexagonal SiC single crystal. In other words, the semiconductor switching device SW is a "SiC semiconductor switching device." The hexagonal SiC single crystal has a variety of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which the chip 32 includes a 4H-SiC single crystal, but the selection of other polytypes is not excluded.

[0115] The chip 32 has a first main surface 33 on one side, a second main surface 34 on the other side, and first to fourth side surfaces 35A to 35D connecting the first main surface 33 and the second main surface 34. The first main surface 33 and the second main surface 34 are formed in a quadrangular shape in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the chip 32. The first main surface 33 and the second main surface 34 are preferably formed by the c-plane of a SiC single crystal.

[0116] In this case, it is preferable that the first main surface 33 is formed by a silicon surface of the SiC single crystal, and the second main surface 34 is formed by a carbon surface of the SiC single crystal. The first main surface 33 and the second main surface 34 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane. The off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be greater than 0° and not more than 10°. The off angle is preferably not more than 5°.

[0117] The first side surface 35A and the second side surface 35B extend in a first direction X along the first main surface 33 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 35C and the fourth side surface 35D extend in the second direction Y and face the first direction X. The first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0118] The semiconductor switching device SW includes an n-type first semiconductor region 36 formed in a region (surface layer portion) on the first main surface 33 side of the chip 32. The first semiconductor region 36 is electrically connected to the above-mentioned first node portion N1. The first semiconductor region 36 is formed in a layer shape extending along the first main surface 33 and is exposed from the first main surface 33 and the first to fourth side surfaces 35A to 35D. In this embodiment, the first semiconductor region 36 is made of an epitaxial layer (SiC epitaxial layer).

[0119] The semiconductor switching device SW includes an n-type second semiconductor region 37 formed in a region (surface layer portion) on the second main surface 34 side within the chip 32. The second semiconductor region 37 has a higher n-type impurity concentration than the first semiconductor region 36, and is electrically connected to the first semiconductor region 36 within the chip 32. The second semiconductor region 37 is formed in a layer shape extending along the second main surface 34, and is exposed from the second main surface 34 and the first to fourth side surfaces 35A to 35D.

[0120] In this embodiment, the second semiconductor region 37 is made of a semiconductor substrate (SiC substrate). That is, the chip 32 has a layered structure including a substrate and an epitaxial layer. The thickness of the second semiconductor region 37 may be greater than the thickness of the first semiconductor region 36. The thickness of the second semiconductor region 37 may be less than the thickness of the first semiconductor region 36. Of course, a configuration not including the second semiconductor region 37 (semiconductor substrate) may also be employed. That is, the chip 32 may have a single-layer structure made of an epitaxial layer.

[0121] The semiconductor switching device SW includes a transistor structure 38 formed on the first main surface 33. In this embodiment, the transistor structure 38 is of a trench gate type. The transistor structure 38 will be described in detail below.

[0122] The semiconductor switching device SW includes a p-type body region 39 formed in a surface layer portion of the first main surface 33. The body region 39 forms a p-n junction as a body diode BD with the first semiconductor region 36 and is electrically connected to the above-mentioned second node portion N2. The body region 39 may also be referred to as a "base region" or a "channel region." The body region 39 is formed from the bottom of the first semiconductor region 36 toward the first main surface 33 at a distance, and extends in a layered manner in the surface layer portion of the first main surface 33. The body region 39 may also be formed in an inner portion of the first main surface 33 at a distance from the periphery of the first main surface 33.

[0123] The semiconductor switching device SW includes an n-type source region 40 formed in a surface layer portion of the body region 39. The source region 40 is electrically connected to the second node portion N2 described above. The source region 40 may be formed in an inner portion of the first main surface 33 at a distance from the periphery of the first main surface 33.

[0124] The source region 40 has a higher n-type impurity concentration than the first semiconductor region 36. The source region 40 is formed at an interval from the bottom of the body region 39 toward the first major surface 33, and extends in a layered manner in the surface portion of the first major surface 33. The source region 40 forms a channel together with the first semiconductor region 36 in the body region 39.

[0125] The semiconductor switching device SW includes a plurality of first trench structures 41 formed in the first main surface 33. The first trench structures 41 are electrically connected to the aforementioned drive unit DU, and receive control signals from the drive unit DU. The first trench structures 41 control inversion and non-inversion of the channel. The first trench structures 41 may also be referred to as "trench gate structures."

[0126] The first trench structure 41 penetrates the body region 39 and the source region 40 to reach the first semiconductor region 36. The multiple first trench structures 41 may be arranged at intervals in the first direction X in a plan view, and may each be formed in a strip shape extending in the second direction Y. The multiple first trench structures 41 are formed at intervals from the bottom of the first semiconductor region 36 toward the first main surface 33.

[0127] Each first trench structure 41 includes a first trench 42, a first insulating film 43, and a first buried electrode 44. The first trench 42 is formed in the first main surface 33 and defines the wall surface of the first trench 42. The first insulating film 43 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first insulating film 43 has a single-layer structure including a silicon oxide film. It is particularly preferable that the first insulating film 43 include a silicon oxide film made of an oxide of the chip 32.

[0128] The first insulating film 43 covers the wall surface of the first trench 42. The first buried electrode 44 may include conductive polysilicon. The first buried electrode 44 is buried in the first trench 42 with the first insulating film 43 sandwiched between them. The first buried electrode 44 faces the channel with the first insulating film 43 sandwiched between them.

[0129] The semiconductor switching device SW includes a plurality of second trench structures 45 formed in the first main surface 33. The plurality of second trench structures 45 are electrically connected to the second node portion N2 described above. The second trench structures 45 may also be referred to as "trench source structures." The plurality of second trench structures 45 are each formed in a region between two adjacent first trench structures 41.

[0130] The second trench structures 45 may each be formed in a strip shape extending in the second direction Y in a plan view. The second trench structures 45 extend through the body region 39 and the source region 40 to the first semiconductor region 36. The second trench structures 45 are formed at intervals from the bottom of the first semiconductor region 36 toward the first main surface 33.

[0131] In this embodiment, the plurality of second trench structures 45 are formed deeper than the plurality of first trench structures 41. The depth of the second trench structures 45 may be 1.5 to 4 times (preferably 2.5 times) the depth of the first trench structures 41. Of course, the depth of the second trench structures 45 may be approximately equal to the depth of the first trench structures 41.

[0132] Each second trench structure 45 includes a second trench 46, a second insulating film 47, and a second buried electrode 48. The second trench 46 is formed in the first main surface 33 and defines the wall surface of the second trench 46. The second insulating film 47 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0133] In this embodiment, the second insulating film 47 has a single-layer structure including a silicon oxide film. It is particularly preferable that the second insulating film 47 includes a silicon oxide film made of an oxide of the chip 32. The second insulating film 47 covers the wall surface of the second trench 46. The second buried electrode 48 may include conductive polysilicon. The second buried electrode 48 is buried in the second trench 46 with the second insulating film 47 sandwiched therebetween.

[0134] The semiconductor switching device SW includes a plurality of p-type contact regions 49 formed in regions along the plurality of second trench structures 45 within the chip 32. Each contact region 49 has a higher p-type impurity concentration than the body region 39. Each contact region 49 covers the sidewalls and bottom wall of each second trench structure 45 and is electrically connected to the body region 39 in the surface layer portion of the first main surface 3.

[0135] The semiconductor switching device SW includes a plurality of p-type well regions 50 formed in regions along the plurality of second trench structures 45 within the chip 32. Each well region 50 has a p-type impurity concentration higher than that of the body region 39 and lower than that of the contact region 49. Each well region 50 covers the corresponding second trench structure 45 with the corresponding contact region 49 sandwiched therebetween. Each well region 50 covers the sidewalls and bottom wall of the corresponding second trench structure 45 and is electrically connected to the body region 39 in the surface layer portion of the first main surface 3.

[0136] The semiconductor switching device SW includes a main surface insulating film 51 that selectively covers the first main surface 33. In this embodiment, the main surface insulating film 51 includes a first main surface insulating film 52 and a second main surface insulating film 53. The first main surface insulating film 52 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first main surface insulating film 52 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first main surface insulating film 52 include a silicon oxide film made of an oxide of the chip 32.

[0137] The first main surface insulating film 52 is continuous with the first insulating film 43 and the second insulating film 47, and exposes the first buried electrode 44 and the second buried electrode 48. In this embodiment, the first main surface insulating film 52 covers the peripheral portion of the first main surface 33 so as to be continuous with the peripheral portion of the first main surface 33. Of course, the main surface insulating film 51 may expose the peripheral portion of the first main surface 33.

[0138] The second main surface insulating film 53 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the second main surface insulating film 53 includes a silicon oxide film. The second main surface insulating film 53 has a thickness greater than that of the first main surface insulating film 52 and covers the first main surface insulating film 52. The second main surface insulating film 53 covers the multiple first trench structures 41 and the multiple second trench structures 45.

[0139] In this embodiment, the second main surface insulating film 53 covers the peripheral portion of the first main surface 33, sandwiching the first main surface insulating film 52 therebetween, so as to be continuous with the peripheral portion of the first main surface 33. Of course, if the first main surface insulating film 52 exposes the peripheral portion of the first main surface 33, the second main surface insulating film 53 may also expose the peripheral portion of the first main surface 33.

[0140] The semiconductor switching device SW includes a gate terminal 54 disposed on the main surface insulating film 51. The gate terminal 54 is formed as a control terminal T3 of the semiconductor switching device SW. The gate terminal 54 has a layered structure including a first electrode film 55 and a second electrode film 56 layered in this order from the first main surface 33 (main surface insulating film 51) side. The first electrode film 55 includes a Ti-based metal film. The first electrode film 55 may have a single-layer structure or a layered structure including at least one of a Ti film and a TiN film.

[0141] The second electrode film 56 is made of a Cu-based metal film or an Al-based metal film and has a thickness greater than that of the first electrode film 55. The second electrode film 56 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the second electrode film 56 has a single-layer structure made of an AlCu alloy film.

[0142] In this embodiment, the gate terminal 54 is disposed in a region close to the center of one side of the first main surface 33 (the third side surface 35C in this embodiment) in a plan view. The location of the gate terminal 54 is arbitrary. The gate terminal 54 may be disposed at a corner of the first main surface 33 in a plan view. The gate terminal 54 may be disposed at the center of the first main surface 33 in a plan view. In this embodiment, the gate terminal 54 is formed in a polygonal shape (specifically, a quadrangular shape) in a plan view.

[0143] The semiconductor switching device SW includes a source terminal 57 disposed on the main surface insulating film 51 at a distance from the gate terminal 54. The source terminal 57 is formed as a second terminal T2 of the semiconductor switching device SW. Similar to the gate terminal 54, the source terminal 57 has a laminated structure including a first electrode film 55 and a second electrode film 56 laminated in this order from the first main surface 33 (main surface insulating film 51) side.

[0144] In this embodiment, the source terminal 57 is formed in a polygonal shape having a recess that is recessed along the gate terminal 54 in a plan view. Of course, the source terminal 57 may be formed in a quadrangular shape in a plan view. When the gate terminal 54 is disposed in the center of the first main surface 33 in a plan view, the source terminal 57 may surround the gate terminal 54 in a plan view. The source terminal 57 penetrates the main surface insulating film 51 and is electrically connected to the body region 39, the source region 40, and the plurality of second trench structures 45.

[0145] The semiconductor switching device SW includes a gate wiring 58 that is drawn from the gate terminal 54 onto the main surface insulating film 51. Like the gate terminal 54, the gate wiring 58 has a laminated structure that includes a first electrode film 55 and a second electrode film 56 that are laminated in this order from the first main surface 33 (main surface insulating film 51) side.

[0146] The gate wiring 58 extends along the first to fourth side surfaces 35A to 35D so as to surround the source terminal 57 (the inner portion of the first main surface 33) from multiple directions in a plan view. The gate wiring 58 is formed in a strip shape extending along the periphery of the first main surface 33 so as to intersect (specifically, perpendicular to) the ends of the multiple first trench structures 41 in a plan view. The gate wiring 58 penetrates the main surface insulating film 51 and is electrically connected to the multiple first trench structures 41.

[0147] The semiconductor switching device SW includes an upper insulating film 59 that selectively covers the gate terminal 54, the source terminal 57, and the gate wiring 58. The upper insulating film 59 is preferably thicker than the gate terminal 54 and the source terminal 57. The thickness of the upper insulating film 59 is preferably less than the thickness of the chip 32. The upper insulating film 59 is formed at a distance inward from the periphery of the first main surface 33, and covers the periphery of the gate terminal 54, the periphery of the source terminal 57, and the entire area of ​​the gate wiring 58.

[0148] The upper insulating film 59 includes a gate pad opening 60 that exposes the inner portion of the gate terminal 54, and a source pad opening 61 that exposes the inner portion of the source terminal 57. In this embodiment, the gate pad opening 60 is defined in a polygonal shape (specifically, a rectangular shape) that follows the periphery of the gate terminal 54 in a plan view. In this embodiment, the source pad opening 61 is defined in a polygonal shape that follows the periphery of the source terminal 57 in a plan view.

[0149] The upper insulating film 59 defines a street region 62 on the peripheral edge side of the chip 32. The street region 62 extends along the peripheral edge of the first main surface 33 and exposes the main surface insulating film 51. Of course, if the main surface insulating film 51 exposes the peripheral edge of the first main surface 33, the street region 62 may also expose the peripheral edge of the first main surface 33.

[0150] In this embodiment, the upper insulating film 59 has a layered structure including an inorganic insulating film 63 (inorganic film) and an organic insulating film 64 (organic film), which are layered in this order from the first main surface 33 side. The inorganic insulating film 63 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film 63 preferably includes an insulating material different from that of the main surface insulating film 51. In this embodiment, the inorganic insulating film 63 has a single-layer structure including a silicon nitride film. The inorganic insulating film 63 preferably has a thickness smaller than that of the gate terminal 54 (source terminal 57).

[0151] The organic insulating film 64 is thicker than the inorganic insulating film 63 and covers the inorganic insulating film 63. The organic insulating film 64 preferably has a thickness greater than the thickness of the gate terminal 54 (source terminal 57). The organic insulating film 64 is preferably made of a photosensitive resin film. The organic insulating film 64 may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0152] The organic insulating film 64 may expose the edge (gate side edge) of the inorganic insulating film 63 in the gate pad opening 60. The organic insulating film 64 may expose the edge (source side edge) of the inorganic insulating film 63 in the source pad opening 61. The organic insulating film 64 may expose the edge (street side edge) of the inorganic insulating film 63 in the street region 62. Of course, the organic insulating film 64 may cover the entire area of ​​the inorganic insulating film 63.

[0153] The organic insulating film 64 may expose at least one or all of the gate side edge, source side edge, and street side edge. In this embodiment, the organic insulating film 64 exposes all of the gate side edge, source side edge, and street side edge, and defines the gate pad opening 60, the source pad opening 61, and the street region 62 together with the inorganic insulating film 63. Of course, the organic insulating film 64 may cover all of the gate side edge, source side edge, and street side edge.

[0154] The semiconductor switching device SW includes a drain terminal 65 covering the second main surface 34. The drain terminal 65 is formed as a first terminal T1 of the semiconductor switching device SW. The drain terminal 65 is formed as a drain electrode and is electrically connected to the second semiconductor region 37 exposed from the second main surface 34. The drain terminal 65 may include at least one of an Al-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film.

[0155] For example, the drain terminal 65 may have a layered structure including a Ti film, a Ni film, and an Au film stacked in this order from the second main surface 34 side. For example, the drain terminal 65 may have a layered structure including an AlSi alloy film, a Ti film, a Ni film, and an Au film stacked in this order from the second main surface 34 side. For example, the drain terminal 65 may have a layered structure including a Ti film, a Ni film, an Au film, and an Ag film stacked in this order from the second main surface 34 side.

[0156] Although the embodiments have been described above, the embodiments may be implemented in other forms. For example, although a single semiconductor testing device 1 is shown in the above-described embodiments, a semiconductor testing module including multiple semiconductor testing devices 1 may be employed. This module allows high-voltage, small-current testing and low-voltage, large-current testing to be performed simultaneously on multiple semiconductor switching devices SW.

[0157] With respect to the semiconductor switching device SW described above (see FIGS. 6 to 9 ), a p-type second semiconductor region 37 may be employed instead of the n-type second semiconductor region 37. In this case, the semiconductor switching device SW includes an IGBT (Insulated Gate Bipolar Transistor) instead of the MISFET. A specific configuration in this case can be obtained by replacing the "source" of the MISFET with the "emitter" of the IGBT and the "drain" of the MISFET with the "collector" of the IGBT in the above description.

[0158] In the above-described embodiments, the first conductivity type is n-type and the second conductivity type is p-type. However, in each of the above-described embodiments, the first conductivity type may be p-type and the second conductivity type may be n-type. A specific configuration in this case can be obtained by replacing n-type regions with p-type regions and p-type regions with n-type regions in the above description and accompanying drawings.

[0159] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in each of the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiment. The "semiconductor test equipment" related to the following items may also be called a "characteristics test equipment" or a "semiconductor inspection equipment" depending on the necessary part.

[0160] [A1] A power supply having a first node (N1) to which one end (T1) of a semiconductor switching device (SW) is electrically connected, a second node (N2) to which the other end (T2) of the semiconductor switching device (SW) is electrically connected, a first power supply (P1) for high voltage and small current that generates a first voltage (VH) and a first current (IL), a second power supply (P2) for low voltage and large current that generates a second voltage (VL) lower than the first voltage (VH) and a second current (IH) higher than the first current (IL), and a withstand voltage equal to or higher than the first voltage (VH), a first relay (R1) electrically connected between the first node section (N1) and the first power supply (P1); a second relay (R2) having a withstand voltage equal to or greater than the second voltage (VL) and electrically connected between the first node section (N1) and the second power supply (P2); a third relay (R3) having a withstand voltage equal to or greater than the first voltage (VH) and connected in parallel to the second relay (R2); and a fourth relay (R4) having a withstand voltage equal to or greater than the second voltage (VL) and connected in parallel to the second power supply (P2).

[0161] [A2] The semiconductor testing device (1) described in A1, wherein when a high-voltage, low-current test is performed on the semiconductor switching device (SW), the first power supply (P1) is controlled to an on state, the second power supply (P2) is controlled to an off state, the first relay (R1) is controlled to a conductive state, the second relay (R2) is controlled to a non-conductive state, the third relay (R3) is controlled to a conductive state, and the fourth relay (R4) is controlled to a conductive state.

[0162] [A3] The semiconductor testing device (1) described in A1 or A2, wherein when a low-voltage, high-current test is performed on the semiconductor switching device (SW), the first power supply (P1) is controlled to an off state, the second power supply (P2) is controlled to an on state, the first relay (R1) is controlled to a non-conductive state, the second relay (R2) is controlled to a conductive state, the third relay (R3) is controlled to a non-conductive state, and the fourth relay (R4) is controlled to a non-conductive state.

[0163] [A4] The semiconductor testing device (1) according to any one of A1 to A3, wherein the first voltage (VH) is lower than a breakdown voltage (VB1) of the semiconductor switching device (SW).

[0164] [A5] The semiconductor testing device (1) according to any one of A1 to A4, wherein the first voltage (VH) is 500 V or more.

[0165] [A6] The semiconductor testing device (1) according to any one of A1 to A5, wherein the first current (IL) is 1 A or less.

[0166] [A7] The semiconductor testing device (1) according to A6, wherein the first current (IL) is 100 mA or less.

[0167] [A8] The semiconductor testing device (1) according to any one of A1 to A7, wherein the second voltage (VL) is 100 V or less.

[0168] [A9] The semiconductor testing device (1) according to any one of A1 to A8, wherein the second current (IH) is 1 A or more.

[0169] [A10] The semiconductor testing device (1) according to A9, wherein the second current (IH) is 10 A or more.

[0170] [A11] The semiconductor testing device (1) according to any one of A1 to A10, wherein the semiconductor switching device (SW) has a breakdown voltage (VB1) of 500V or more.

[0171] [A12] The semiconductor testing device (1) according to any one of A1 to A11, wherein the semiconductor switching device (SW) includes a wide band gap semiconductor.

[0172] [A13] The semiconductor testing device (1) according to any one of A1 to A12, wherein the semiconductor switching device (SW) includes an insulated gate transistor.

[0173] [A14] The semiconductor testing device (1) according to A13, wherein the transistor is a trench gate type.

[0174] [A15] The semiconductor testing device (1) according to any one of A1 to A14, further comprising a semiconductor rectifier device (D) electrically interposed between the second power supply (P2) and the second relay (R2).

[0175] [A16] The semiconductor testing device (1) according to A15, wherein the semiconductor rectifier device (D) has a breakdown voltage (VB2) equal to or greater than the second voltage (VL).

[0176] [A17] The semiconductor testing device (1) according to A16, wherein the breakdown voltage (VB2) of the semiconductor rectifier device (D) is equal to or greater than the breakdown voltage (VB1) of the semiconductor switching device (SW).

[0177] [A18] The semiconductor testing device (1) according to A16 or A17, wherein the breakdown voltage (VB2) of the semiconductor rectifier device (D) is 500 V or more.

[0178] [A19] The semiconductor test device (1) according to any one of A15 to A18, wherein the semiconductor rectifier device (D) includes a wide band gap semiconductor.

[0179] [A20] The semiconductor test device (1) according to any one of A15 to A19, wherein the semiconductor rectifier device (D) includes a Schottky barrier diode.

[0180] Although the embodiments have been described in detail above, these are merely specific examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiments.

[0181] 1 Semiconductor testing device SW Semiconductor switching device T1 First terminal (one end) of semiconductor switching device T2 Second terminal (other end) of semiconductor switching device T3 Control terminal of semiconductor switching device N1 First node section N2 Second node section P1 First power supply VH First voltage IL First current P2 Second power supply VL Second voltage IH Second current R1 First relay R2 Second relay R3 Third relay R4 Fourth relay D Semiconductor rectifier VB1 First breakdown voltage VB2 Second breakdown voltage

Claims

1. a first node portion to which one end of the semiconductor switching device is electrically connected; a second node portion to which the other end of the semiconductor switching device is electrically connected; a first high voltage, low current power supply generating a first voltage and a first current; a second low-voltage, high-current power supply generating a second voltage lower than the first voltage and a second current higher than the first current; a first relay having a withstand voltage equal to or higher than the first voltage and electrically connected between the first node unit and the first power source; a second relay having a withstand voltage equal to or higher than the second voltage and electrically connected between the first node unit and the second power source; a third relay having a withstand voltage equal to or greater than the first voltage and connected in parallel to the second relay; a fourth relay having a withstand voltage equal to or greater than the second voltage and connected in parallel to the second power supply.

2. 2. The semiconductor testing apparatus according to claim 1, wherein, when a high-voltage, low-current test is performed, the first power supply is controlled to an on state, the second power supply is controlled to an off state, the first relay is controlled to a conductive state, the second relay is controlled to a non-conductive state, the third relay is controlled to a conductive state, and the fourth relay is controlled to a conductive state.

3. 2. The semiconductor testing apparatus according to claim 1, wherein, when a low-voltage high-current test is performed, the first power supply is controlled to an off state, the second power supply is controlled to an on state, the first relay is controlled to a non-conductive state, the second relay is controlled to a conductive state, the third relay is controlled to a non-conductive state, and the fourth relay is controlled to a non-conductive state.

4. 2. The semiconductor testing device of claim 1, wherein the first voltage is less than a breakdown voltage of the semiconductor switching device.

5. 2. The semiconductor testing device according to claim 1, wherein the first voltage is 500V or higher.

6. 2. The semiconductor testing device according to claim 1, wherein the first current is equal to or less than 1 A.

7. 7. The semiconductor testing device according to claim 6, wherein the first current is equal to or less than 100 mA.

8. 2. The semiconductor testing device according to claim 1, wherein the second voltage is 100V or less.

9. 2. The semiconductor testing device according to claim 1, wherein the second current is equal to or greater than 1 A.

10. 10. The semiconductor testing device according to claim 9, wherein the second current is 10 A or more.

11. 2. The semiconductor testing device of claim 1, wherein the semiconductor switching device has a breakdown voltage of 500V or more.

12. The semiconductor testing apparatus of claim 1 , wherein the semiconductor switching device comprises a wide bandgap semiconductor.

13. 2. The semiconductor testing device of claim 1, wherein the semiconductor switching device includes an insulated gate transistor.

14. 14. The semiconductor testing device according to claim 13, wherein the transistor is of a trench gate type.

15. 15. The semiconductor testing apparatus according to claim 1, further comprising a semiconductor rectifier device electrically interposed between the second power supply and the second relay.

16. 16. The semiconductor test apparatus of claim 15, wherein the semiconductor rectifier device has a breakdown voltage equal to or greater than the second voltage.

17. 17. The semiconductor testing apparatus of claim 16, wherein the breakdown voltage of the semiconductor rectifier device is greater than or equal to the breakdown voltage of the semiconductor switching device.

18. 17. The semiconductor testing device of claim 16, wherein the breakdown voltage of the semiconductor rectifier device is 500V or greater.

19. 20. The semiconductor test apparatus of claim 15, wherein the semiconductor rectifier device comprises a wide bandgap semiconductor.

20. 16. The semiconductor test apparatus of claim 15, wherein the semiconductor rectifier device includes a Schottky barrier diode.