Semiconductor device

Abstract

This semiconductor device comprises: a first switching element having a first main surface facing one side in a thickness direction; a wiring layer disposed on the one side in the thickness direction with respect to the first switching element; and a second switching element disposed on the one side in the thickness direction with respect to the wiring layer. The first switching element includes a first electrode, a second electrode, and a third electrode that are each formed on the first main surface. The second switching element overlaps the first switching element when viewed in the thickness direction. The second switching element is in electrical communication with the first switching element via the wiring layer.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses an example of a semiconductor device including a lateral-structured semiconductor element (HEMT). The semiconductor device described in Patent Document 1 includes a first semiconductor element, a second semiconductor element, and a control element. The first semiconductor element and the second semiconductor element are lateral-structured switching elements (HEMT). The control element controls the driving of the first semiconductor element and the second semiconductor element. The first semiconductor element, the second semiconductor element, and the control element are mounted on a lead frame and arranged at intervals from one another along the same plane (a plane including the x-direction and the y-direction shown in Figures 1 and 2 of the document, etc.).

[0003] In the conventional semiconductor device described above, multiple elements (a first semiconductor element, a second semiconductor element, and a control element) are arranged along the same plane, resulting in a relatively large planar size. This hinders efforts to miniaturize the semiconductor device. Furthermore, in the configuration of the conventional semiconductor device described above, the paths of the conductive wiring (wires) connecting the multiple elements arranged along the same plane to each other are relatively long. This leads to an increase in parasitic inductance in the wiring of the semiconductor device.

[0004] Japanese Patent Application Laid-Open No. 2020-188085

[0005] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that is suitable for miniaturization and reduction of parasitic inductance in wiring.

[0006] A semiconductor device provided by one aspect of the present disclosure includes a first semiconductor element having a first main surface facing one side in a thickness direction, a wiring layer disposed on one side of the first semiconductor element in the thickness direction, and a second semiconductor element disposed on one side of the wiring layer in the thickness direction. The first semiconductor element has a first electrode, a second electrode, and a third electrode each formed on the first main surface. The second semiconductor element overlaps the first semiconductor element when viewed in the thickness direction. The second semiconductor element is electrically connected to the first semiconductor element via the wiring layer.

[0007] According to the above configuration, it is possible to provide a structure that is favorable for achieving miniaturization and reducing parasitic inductance in wiring.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure, seen through an encapsulation portion. FIG. 3 is a plan view corresponding to FIG. 2, omitting a switching element (second semiconductor element), a control element (third semiconductor element), and some of the connecting wirings. FIG. 4 is a bottom view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 2. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 2. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 2. FIG. 10 is a cross-sectional view taken along line X-X in FIG. 2. FIG. 11 is a cross-sectional view similar to FIG. 5, showing a semiconductor device according to a first modification of the first embodiment. FIG. 12 is a plan view showing a semiconductor device according to a second embodiment of the present disclosure. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12 . FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 12 . FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 12 . FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 12 . FIG. 17 is a cross-sectional view similar to FIG. 14 , showing a semiconductor device according to a first modified example of the second embodiment. FIG. 18 is a plan view showing a semiconductor device according to a third embodiment of the present disclosure. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18 . FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 18 . FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 18 . FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 18 . FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 18 .

[0010] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0011] The terms "first," "second," "third," etc. in this disclosure are used merely for identification purposes and are not intended to necessarily assign any order to their objects.

[0012] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0013] 1 to 10 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A10 of this embodiment includes a switching element 10A, a switching element 10B, a control element 20A, a wiring layer 31, a plurality of connection wires 34, a plurality of interconnection wires 35, a plurality of terminals 40, and a sealing portion 50. The semiconductor device A10 is in a resin package format that is surface-mounted on a wiring substrate.

[0014] FIG. 1 is a plan view showing the semiconductor device A10. FIG. 2 is a plan view showing the semiconductor device A10. FIG. 2 is a plan view showing the semiconductor device A10, with the sealing portion 50 seen through. In FIG. 2, the sealing portion 50 seen through is indicated by an imaginary line (two-dot chain line). FIG. 3 is a plan view of the semiconductor device A10, which, compared to FIG. 2, omits the switching element 10B, the control element 20A, and portions of the multiple connection wirings 34 connected to the switching element 10B and the control element 20A. FIG. 4 is a bottom view showing the semiconductor device A10. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 2. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 2. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 2. FIG. 10 is a cross-sectional view taken along line X-X in FIG. 2.

[0015] In the following description, the mutually orthogonal thickness direction z, first direction x, and second direction y are referred to. The thickness direction z corresponds to the thickness direction of the semiconductor device A10. Furthermore, "plan view" refers to the view in the thickness direction z. The first direction x is orthogonal to the thickness direction z. The second direction y is orthogonal to the thickness direction z and the first direction x. One side of the thickness direction z is referred to as the z1 side of the thickness direction z, and the other side of the thickness direction z is referred to as the z2 side of the thickness direction z. The z1 side of the thickness direction z is sometimes referred to as the upper side, and the z2 side of the thickness direction z is sometimes referred to as the lower side. Terms such as "upper," "lower," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each component in the thickness direction z and do not necessarily define the relationship with the direction of gravity. The semiconductor device A10 is rectangular when viewed in the thickness direction z.

[0016] The semiconductor device A10 converts DC power supplied from an external source to AC power using switching elements 10A and 10B. The semiconductor device A10 is used, for example, in an inverter for driving a motor. The wiring structure of the semiconductor device A10, including the wiring layer 31 and the connection wiring 34, can be formed, for example, by a redistribution layer (RDL) formation technique using patterning and plating.

[0017] The sealing portion 50 covers at least a portion of the switching element 10A and the switching element 10B, the control element 20A, the wiring layer 31, the plurality of connection wires 34, the plurality of interconnection wires 35, and a portion of the plurality of terminals 40. The sealing portion 50 includes, for example, an insulating resin material. The sealing portion 50 has a rectangular shape when viewed in the thickness direction z.

[0018] In this embodiment, the sealing portion 50 includes a first sealing portion 51, a second sealing portion 52, and a third sealing portion 53. The first sealing portion 51 is located on the z2 side of the sealing portion 50 in the thickness direction z. The first sealing portion 51 has a bottom surface 511. The bottom surface 511 faces the z2 side in the thickness direction z. When the semiconductor device A10 is mounted on a wiring substrate, the bottom surface 511 faces the wiring substrate.

[0019] The second sealing portion 52 is disposed on the z1 side in the thickness direction z with respect to the first sealing portion 51. The second sealing portion 52 has a top surface 521. The top surface 521 faces the opposite side to the bottom surface 511 in the thickness direction z (the z1 side in the thickness direction z). The third sealing portion 53 is located between the first sealing portion 51 and the second sealing portion 52 in the thickness direction z. The third sealing portion 53 contacts both the first sealing portion 51 and the second sealing portion 52.

[0020] The switching elements 10A and 10B are transistors (switching elements) primarily used for power conversion. Each of the switching elements 10A and 10B is made of a material containing, for example, a nitride semiconductor. In the semiconductor device A10, each of the switching elements 10A and 10B is a high electron mobility transistor (HEMT) made of a material containing gallium nitride (GaN).

[0021] As shown in FIGS. 2, 3, and 5 to 7, the switching element 10A has a first major surface 101A, a first back surface 102A, a plurality (two) of first electrodes 11, a plurality (two) of second electrodes 12, and a third electrode 13. The first major surface 101A faces the z1 side in the thickness direction z. The first back surface 102A is separated from the first major surface 101A in the thickness direction z. The first back surface 102A faces the side opposite the first major surface 101A (the z2 side in the thickness direction z). The plurality of first electrodes 11, the plurality of second electrodes 12, and the third electrode 13 are formed on the first major surface 101A.

[0022] As shown in FIGS. 2 and 3 , each of the multiple (two) first electrodes 11 and the multiple (two) second electrodes 12 extends in the first direction x. The two first electrodes 11 are located on both sides of the switching element 10A in the second direction y. The two second electrodes 12 are located between the two first electrodes 11 in the second direction y. The two second electrodes 12 are spaced apart from each other in the second direction y. A current corresponding to the power before conversion by the switching element 10A flows through the multiple second electrodes 12. Therefore, the multiple second electrodes 12 correspond to drains of the switching element 10A. A current corresponding to the power after conversion by the switching element 10A flows through the multiple first electrodes 11. Therefore, the multiple first electrodes 11 correspond to sources of the switching element 10A.

[0023] As shown in FIG. 3 , the third electrode 13 is disposed closer to the end of the switching element 10A in the first direction x and closer to the end in the second direction y. A gate voltage for driving the switching element 10A is applied to the third electrode 13. This third electrode 13 corresponds to the gate of the switching element 10A. When viewed in the thickness direction z, the area of ​​the third electrode 13 is smaller than the area of ​​each of the multiple first electrodes 11 and the multiple second electrodes 12. The shapes, quantities, and arrangements of the first electrodes 11, second electrodes 12, and third electrodes 13 in the switching element 10A are merely examples and can be modified in various ways. The switching element 10A configured as described above is an example of a “first semiconductor element” in the present disclosure.

[0024] In this embodiment, at least a portion of the switching element 10A is covered by the first sealing portion 51. In the illustrated example, the portions of the switching element 10A other than the first main surface 101A are covered by the first sealing portion 51. Therefore, the first back surface 102A is covered by the first sealing portion 51. The first main surface 101A is in contact with the third sealing portion 53. The multiple first electrodes 11, the multiple second electrodes 12, and the third electrode 13 face the third sealing portion 53.

[0025] 5 to 9, the switching element 10B is disposed on the z1 side of the switching element 10A in the thickness direction z. The switching element 10B overlaps with the switching element 10A when viewed in the thickness direction z. As shown in FIG. 2, the area of ​​the switching element 10B is smaller than the area of ​​the switching element 10A when viewed in the thickness direction z.

[0026] As shown in FIGS. 2 , 5 , 8 , and 9 , the switching element 10B has a second main surface 101B, a second back surface 102B, and a plurality (two) of fourth electrodes 14, fifth electrodes 15, and sixth electrodes 16. The second main surface 101B faces the z2 side in the thickness direction z. The second main surface 101B faces the first main surface 101A of the switching element 10A. The second back surface 102B is spaced apart from the second main surface 101B in the thickness direction z. The second back surface 102B faces the opposite side to the second main surface 101B (the z1 side in the thickness direction z). The plurality of fourth electrodes 14, fifth electrodes 15, and sixth electrodes 16 are formed on the second main surface 101B.

[0027] As shown in FIGS. 2 and 9 , each of the multiple (two) fourth electrodes 14 and the fifth electrode 15 extends in the first direction x. The two fourth electrodes 14 are located on both sides of the switching element 10B in the second direction y. As can be seen from FIGS. 2 , 3 , 5 , and 6 , the two fourth electrodes 14 individually overlap with the two second electrodes 12 of the switching element 10A when viewed in the thickness direction z. The fifth electrode 15 is located between the two fourth electrodes 14 in the second direction y. A current corresponding to the power before conversion by the switching element 10B flows through the fifth electrode 15. Therefore, the fifth electrode 15 corresponds to the drain of the switching element 10B. A current corresponding to the power after conversion by the switching element 10B flows through the multiple fourth electrodes 14. Therefore, the multiple fourth electrodes 14 correspond to the sources of the switching element 10B.

[0028] As shown in FIG. 2 , the sixth electrode 16 is disposed closer to the end of the switching element 10B in the first direction x and closer to the end in the second direction y. A gate voltage for driving the switching element 10B is applied to the sixth electrode 16. This sixth electrode 16 corresponds to the gate of the switching element 10B. As viewed in the thickness direction z, the area of ​​the sixth electrode 16 is smaller than the area of ​​each of the multiple fourth electrodes 14 and the fifth electrode 15. As shown in FIGS. 5 and 6 , the switching element 10B is electrically connected to the switching element 10A via the wiring layer 31. The shapes, quantities, and arrangements of the fourth electrode 14, fifth electrode 15, and sixth electrode 16 in the switching element 10B are merely examples and may be modified in various ways. The switching element 10B configured as described above is an example of a “second semiconductor element” in the present disclosure.

[0029] In this embodiment, at least a portion of the switching element 10B is covered with the second sealing portion 52. In the example shown in the figure, the entire switching element 10B is covered with the second sealing portion 52.

[0030] The semiconductor device A10 is configured as, for example, a half-bridge switching circuit. In this case, the switching element 10B configures an upper arm circuit of the semiconductor device A10, and the switching element 10A configures a lower arm circuit. The switching elements 10B and 10A are connected in series.

[0031] 6 to 8 and 10, the control element 20A is disposed on the z1 side in the thickness direction z with respect to the switching element 10A. The control element 20A overlaps with the switching element 10A when viewed in the thickness direction z. As shown in FIG. 2, the area of ​​the control element 20A is smaller than the areas of the switching elements 10A and 10B when viewed in the thickness direction z.

[0032] The control element 20A is electrically connected to the switching element 10A and the switching element 10B. The control element 20A is a gate driver that applies a gate voltage to the third electrode 13 of the switching element 10A and the sixth electrode 16 of the switching element 10B.

[0033] As shown in FIGS. 2, 6 to 8, and 10, the control element 20A has a third main surface 201A and multiple (four) pads 21. The third main surface 201A faces the z2 side in the thickness direction z. The third main surface 201A faces the first main surface 101A of the switching element 10A. The multiple pads 21 are formed on the third main surface 201A. As shown in FIGS. 2, 6 to 8, and 10, each of the multiple pads 21 is rectangular when viewed in the thickness direction. The shape, number, and arrangement of the multiple pads 21 in the control element 20A are merely examples and can be modified in various ways. The control element 20A configured as described above is an example of a "third semiconductor element" of the present disclosure.

[0034] 5 to 10 , the wiring layer 31 is located between the switching element 10A and the switching element 10B and the control element 20A in the thickness direction z. As a result, the wiring layer 31 is located on the z1 side of the switching element 10A in the thickness direction z. The switching element 10B and the control element 20A are located on the z1 side of the wiring layer 31 in the thickness direction z. The wiring layer 31 is located between the third sealing portion 53 and the second sealing portion 52. At least a portion of the wiring layer 31 is housed in the second sealing portion 52. The constituent material of the wiring layer 31 is not particularly limited and includes, for example, copper (Cu).

[0035] As shown in FIGS. 2 , 3 , and 5 to 10 , the wiring layer 31 includes a first wiring 311, a second wiring 312, a third wiring 313, a fourth wiring 314, a fifth wiring 315, and a control wiring 316. In the illustrated example, the first wiring 311 is provided in two locations separated from each other. The two first wirings 311 are arranged corresponding to the multiple (two) first electrodes 11 of the switching element 10A. Each first wiring 311 overlaps with the first electrode 11 when viewed in the thickness direction z. As shown in FIGS. 5 , 6 , and 10 , each first electrode 11 of the switching element 10A is electrically connected to the first wiring 311 via one of the multiple connection wirings 34.

[0036] The second wiring 312 is bifurcated to correspond to the multiple (two) second electrodes 12 of the switching element 10A and the multiple (two) fourth electrodes 14 of the switching element 10B. The second wiring 312 overlaps the multiple second electrodes 12 and the multiple fourth electrodes 14 when viewed in the thickness direction z. As shown in FIGS. 5 and 6 , each second electrode 12 of the switching element 10A is electrically connected to the second wiring 312 via one of the multiple connection wirings 34. Furthermore, each fourth electrode 14 of the switching element 10B is electrically connected to the second wiring 312 via one of the multiple connection wirings 34. That is, the fourth electrode 14 of the switching element 10B is electrically connected to the second electrode 12 of the switching element 10A via the wiring layer 31 (second wiring 312).

[0037] The third wiring 313 is disposed in correspondence with the fifth electrode 15 of the switching element 10B. The third wiring 313 overlaps with the fifth electrode 15 when viewed in the thickness direction z. As shown in FIGS. 5 , 6 , and 9 , the fifth electrode 15 is electrically connected to the third wiring 313 via any of the plurality of connection wirings 34.

[0038] The fourth wiring 314 is arranged to correspond to the third electrode 13 of the switching element 10A and one of the multiple pads 21 of the control element 20A. The fourth wiring 314 overlaps the third electrode 13 and one of the multiple pads 21 when viewed in the thickness direction z. As shown in FIGS. 7 and 10 , the third electrode 13 is electrically connected to the fourth wiring 314 via one of the multiple connection wirings 34. Furthermore, one of the multiple pads 21 is electrically connected to the fourth wiring 314 via one of the multiple connection wirings 34. As a result, the control element 20A (one of the multiple pads 21) is electrically connected to the third electrode 13 via the fourth wiring 314. Furthermore, the pad 21 electrically connected to the fourth wiring 314 via the fourth wiring 314 overlaps the third electrode 13 when viewed in the thickness direction z.

[0039] The fifth wiring 315 is arranged to correspond to the sixth electrode 16 of the switching element 10B and one of the plurality of pads 21 of the control element 20A. The fifth wiring 315 overlaps the sixth electrode 16 and one of the plurality of pads 21 when viewed in the thickness direction z. As shown in FIG. 8 , the sixth electrode 16 is electrically connected to the fifth wiring 315 via one of the plurality of connection wirings 34. Furthermore, one of the plurality of pads 21 is electrically connected to the fifth wiring 315 via one of the plurality of connection wirings 34. As a result, the control element 20A (one of the plurality of pads 21) is electrically connected to the sixth electrode 16 via the fifth wiring 315.

[0040] The control wiring 316 is arranged corresponding to one of the plurality of pads 21 of the control element 20A. In the illustrated example, the control wiring 316 is provided in two locations separated from each other. The two control wirings 316 are arranged corresponding to the two pads 21 of the control element 20A. Each control wiring 316 overlaps with a pad 21 when viewed in the thickness direction z. As shown in FIGS. 6 and 10 , each of the two pads 21 is electrically connected to the control wiring 316 via one of the plurality of connection wirings 34.

[0041] 5 to 10 , the multiple connection wires 34 are housed in either the second sealing portion 52 or the third sealing portion 53. As shown in FIGS. 2 and 3 , when viewed in the thickness direction z, each of the multiple connection wires 34 overlaps with one of the switching element 10A, the switching element 10B, and the control element 20A. Each of the multiple connection wires 34 is connected to the wiring layer 31 (one of the first wiring 311, the second wiring 312, the third wiring 313, the fourth wiring 314, the fifth wiring 315, and the control wiring 316).

[0042] As shown in FIGS. 2, 3, and 5 to 10, the plurality of connection wirings 34 include a plurality of first connection wirings 341, a plurality of second connection wirings 342, and a plurality of third connection wirings 343.

[0043] 5 to 7 and 10, the multiple first connection wirings 341 are interposed between the switching element 10A and the wiring layer 31 in the thickness direction z. In the illustrated example, the multiple first connection wirings 341 are housed in the third sealing portion 53. Each of the multiple first connection wirings 341 is connected to any of the multiple (two) first electrodes 11, the multiple (two) second electrodes 12, and the third electrode 13 of the switching element 10A. The constituent material of the multiple first connection wirings 341 is the same as the constituent material of the wiring layer 31, and includes, for example, copper (Cu).

[0044] 5 , 6 , 8 , and 9 , the plurality of second connection wirings 342 are interposed between the switching element 10B and the wiring layer 31 in the thickness direction z. In the illustrated example, the plurality of second connection wirings 342 are housed in the second sealing portion 52. Each of the plurality of second connection wirings 342 is connected to one of the plurality (two) fourth electrodes 14, fifth electrodes 15, and sixth electrodes 16 of the switching element 10B. The constituent material of the plurality of second connection wirings 342 is not particularly limited, and may be, for example, a conductive bonding material such as solder.

[0045] 6 to 8 and 10, the plurality of third connection wirings 343 are interposed between the control element 20A and the wiring layer 31 in the thickness direction z. In the illustrated example, the plurality of third connection wirings 343 are housed in the second sealing portion 52. Each of the plurality of third connection wirings 343 is connected to one of the plurality of (four) pads 21 of the control element 20A. The constituent material of the plurality of third connection wirings 343 is not particularly limited, and may be, for example, a conductive bonding material such as solder.

[0046] As shown in FIGS. 5 , 6 , and 9 , the multiple interconnections 35 are housed in the second sealing portion 52 and the third sealing portion 53. As shown in FIGS. 2 , 3 , 5 , 6 , and 9 , when viewed in the thickness direction z, each of the multiple interconnections 35 overlaps with the wiring layer 31 (any of the first wiring 311, the second wiring 312, the third wiring 313, and the control wiring 316). As shown in FIGS. 5 , 6 , and 9 , each of the multiple interconnections 35 is connected to the wiring layer 31 (any of the first wiring 311, the second wiring 312, the third wiring 313, and the control wiring 316). The constituent material of the multiple interconnections 35 is the same as the constituent material of the wiring layer 31, and includes, for example, copper (Cu).

[0047] As shown in FIGS. 2, 3, 5, 6, and 9, the plurality of interconnections 35 include a plurality of first interconnections 351, a plurality of second interconnections 352, a plurality of third interconnections 353, and a plurality of fourth interconnections 354.

[0048] 2, 3, 5, and 6, the plurality of first connecting wires 351 are connected to the first wires 311 and the first terminals 41 described later. As shown in FIGS. 2, 3, and 9, the plurality of second connecting wires 352 are connected to the second wires 312 and the second terminals 42 described later. As shown in FIGS. 2, 3, and 9, the plurality of third connecting wires 353 are connected to the third wires 313 and the third terminals 43 described later. As shown in FIGS. 2, 3, and 6, each of the plurality of fourth connecting wires 354 is connected to one of the plurality (two) control wires 316 and one of the plurality of control terminals 44 described later.

[0049] As shown in FIGS. 5 , 6 , and 9 , a portion of each of the multiple terminals 40 is housed in the first sealing portion 51. Each of the multiple terminals 40 is disposed on the z1 side in the thickness direction z with respect to the first main surface 101A of the switching element 10A. Each of the multiple terminals 40 is exposed from the bottom surface 511 of the first sealing portion 51. Each of the multiple terminals 40 is connected to one of the multiple interconnection wires 35 (the multiple first interconnection wires 351, the multiple second interconnection wires 352, the multiple third interconnection wires 353, and the multiple fourth interconnection wires 354). As a result, each of the multiple terminals 40 is electrically connected to at least one of the switching element 10A, the switching element 10B, and the control element 20A via the wiring layer 31 (one of the first interconnection wires 311, the second interconnection wires 312, the third interconnection wires 313, and the control interconnection wire 316). The constituent material of the multiple terminals 40 is the same as the constituent material of the wiring layer 31, and includes, for example, copper (Cu).

[0050] As shown in Figures 2, 3, 5, 6, and 9, the multiple terminals 40 include multiple (two) first terminals 41, second terminals 42, third terminals 43, and multiple (two) control terminals 44.

[0051] As shown in Figures 2, 3, and 5, each of the two first terminals 41 is electrically connected to the first wiring 311 via a plurality of first interconnection wirings 351. As shown in Figures 2, 3, and 9, the third terminal 43 is electrically connected to the third wiring 313 via a plurality of third interconnection wirings 353. DC power, which is the target of conversion by the switching element 10A and the switching element 10B, is input to the two first terminals 41 and the third terminal 43. The two first terminals 41 are negative poles (N terminals). The third terminal 43 is a positive pole (P terminal).

[0052] 2, 3, and 9, the second terminal 42 is electrically connected to the second wiring 312 via a plurality of second connecting wirings 352. The AC power converted by the switching elements 10A and 10B is output from the second terminal 42.

[0053] Each of the multiple (two) control terminals 44 is electrically connected to the control wiring 316 via one of the multiple fourth connection wirings 354. Therefore, each of the multiple control terminals 44 is electrically connected to the control element 20A. Power for driving the control element 20A is input to one of the multiple control terminals 44. An electrical signal to the control element 20A is input to one of the multiple control terminals 44.

[0054] Unlike the illustrated example, a coating layer may be provided to cover the bottom surface 511 of the sealing portion 50 (first sealing portion 51). The coating layer may be made of, for example, solder resist. Furthermore, a plurality of openings are formed in the coating layer. The plurality of openings penetrate the coating layer in the thickness direction z, and one of the plurality of terminals 40 is exposed to the outside from each of the plurality of openings. This allows each of the plurality of terminals 40 to be conductively bonded to the wiring board, for example, via solder, when the semiconductor device A10 is mounted on the wiring board. This configuration of providing a coating layer can be similarly applied to each of the modified examples and embodiments described below.

[0055] Next, the operation of this embodiment will be described.

[0056] The semiconductor device A10 includes a switching element 10A (first semiconductor element), a wiring layer 31 disposed on the z1 side of the switching element 10A in the thickness direction z, and a switching element 10B (second semiconductor element) disposed on the z1 side of the wiring layer 31 in the thickness direction z. The switching element 10A has a first main surface 101A facing the z1 side of the thickness direction z, and a first electrode 11, a second electrode 12, and a third electrode 13 formed on the first main surface 101A. The switching element 10B is, for example, a horizontal HEMT. The switching element 10B is electrically connected to the switching element 10A via the wiring layer 31 and overlaps the switching element 10A in the thickness direction z. This configuration allows multiple elements, including the horizontal switching element 10A, to be stacked in the thickness direction z. This reduces the planar size (size as viewed in the thickness direction z) of the semiconductor device A10, thereby enabling the miniaturization of the semiconductor device A10.

[0057] Furthermore, with the above configuration, it is possible to shorten the mutual conduction paths between the multiple elements (switching elements 10A and 10B) compared to when the multiple elements are arranged along the same plane, which contributes to reducing parasitic inductance in the wiring inside the semiconductor device A10.

[0058] The switching element 10B has a second main surface 101B and a fourth electrode 14, a fifth electrode 15, and a sixth electrode 16, each formed on the second main surface 101B. The second main surface 101B faces the z2 side in the thickness direction z and faces the first main surface 101A of the switching element 10A. This configuration appropriately shortens the path length between one of the electrodes (second electrode 12) of the switching element 10A and one of the electrodes (fourth electrode 14) of the switching element 10B, which are electrically connected via the wiring layer 31 (second wiring 312). This is advantageous for reducing parasitic inductance within the semiconductor device A10.

[0059] The wiring layer 31 includes a first wiring 311, a second wiring 312, and a third wiring 313. In the semiconductor device A10, as shown in FIGS. 5 and 6 , the second electrode 12 (drain) of the switching element 10A (lower arm) and the fourth electrode 14 (source) of the switching element 10B (upper arm) are electrically connected to the second wiring 312. The fourth electrode 14 overlaps the second electrode 12 in the thickness direction z. In the illustrated example, two fourth electrodes 14 individually overlap with two second electrodes 12 in the thickness direction z. This configuration allows the paths of the second electrode 12 of the switching element 10A and the fourth electrode 14 of the switching element 10B, which are electrically connected to each other, to be linearly formed along the thickness direction z. This shortens the length of the conductive path between the second electrode 12 and the fourth electrode 14, which is more suitable for reducing parasitic inductance within the semiconductor device A10.

[0060] The semiconductor device A10 includes a control element 20A (third semiconductor element) disposed on the z1 side in the thickness direction z of the wiring layer 31. The control element 20A overlaps with the switching element 10A (first semiconductor element) as viewed in the thickness direction z. This configuration makes it possible to reduce the planar size (size as viewed in the thickness direction z) of the semiconductor device A10 including multiple elements (laterally structured switching elements 10A and 10B and control element 20A), making it more suitable for miniaturizing the semiconductor device A10.

[0061] The wiring layer 31 includes a fourth wiring 314 and a fifth wiring 315. The control element 20A has a third main surface 201A facing the z2 side in the thickness direction z and a plurality of pads 21 formed on the third main surface 201A. One of the pads 21 is electrically connected to the third electrode 13 (gate) of the switching element 10A via the fourth wiring 314. One of the pads 21 is electrically connected to the sixth electrode 16 (gate) of the switching element 10B via the fifth wiring 315. This configuration appropriately shortens the path length between the third electrode 13 and the sixth electrode 16 of the switching elements 10A and 10B, which are electrically connected via the wiring layer 31 (the fourth wiring 314 and the fifth wiring 315), and one of the pads 21 of the control element 20A. This is advantageous for reducing parasitic inductance within the semiconductor device A10.

[0062] Other embodiments and modifications of the semiconductor device of the present disclosure will be described below. The configurations of the components in each embodiment and each modification can be combined with each other to the extent that no technical contradiction occurs.

[0063] Fig. 11 shows a semiconductor device according to a first modification of the first embodiment. Fig. 11 is a cross-sectional view showing a semiconductor device A11 of this modification, and shows the same cross section as Fig. 5 of the above embodiment. In Fig. 11 and subsequent figures, elements that are the same as or similar to those of the semiconductor device A10 of the above embodiment are given the same reference numerals as in the above embodiment, and descriptions thereof will be omitted as appropriate.

[0064] In the semiconductor device A11 of this modified example, the first back surface 102A of the switching element 10A and the second back surface 102B of the switching element 10B are each exposed from the sealing portion 50. Specifically, the first back surface 102A of the switching element 10A is exposed from the first sealing portion 51. In the example shown, the first back surface 102A of the switching element 10A is flush with the bottom surface 511 of the first sealing portion 51. The second back surface 102B of the switching element 10B is exposed from the second sealing portion 52. In the example shown, the second back surface 102B of the switching element 10B is flush with the top surface 521 of the second sealing portion 52.

[0065] In the semiconductor device A11, the first back surface 102A of the switching element 10A is exposed from the first sealing portion 51, and the second back surface 102B of the switching element 10B is exposed from the second sealing portion 52. With this configuration, heat generated in each of the switching elements 10A and 10B can be efficiently dissipated to the outside of the semiconductor device A11, thereby improving the heat dissipation performance of the semiconductor device A11.

[0066] Furthermore, in the semiconductor device A11, the first back surface 102A exposed from the first sealing portion 51 (sealing portion 50) can be bonded to, for example, a wiring substrate, and the second back surface 102B exposed from the second sealing portion 52 (sealing portion 50) can be bonded to, for example, a heat dissipation member. This configuration can further enhance the heat dissipation performance of the semiconductor device A11. Although not shown in detail, the surface of the control element 20A facing the z1 side in the thickness direction z may be exposed from the second sealing portion 52 (sealing portion 50). In this case, heat generated by the control element 20A can be efficiently dissipated to the outside of the semiconductor device A11. Additionally, the semiconductor device A11 exhibits the same effects as the semiconductor device A10 of the above embodiment.

[0067] 12 to 16 show a semiconductor device A20 according to a second embodiment of the present disclosure. FIG. 12 is a plan view showing the semiconductor device A20, with the sealing unit 50 seen through. In FIG. 12, the see-through sealing unit 50 is indicated by an imaginary line (two-dot chain line). FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 12. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 12. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 12.

[0068] The semiconductor device A20 includes a switching element 10C, a switching element 10D, a control element 20A, a wiring layer 32, a plurality of connection wires 34, a plurality of interconnection wires 35, a plurality of terminals 40, and a sealing portion 50. In this embodiment, the planar shapes and arrangement of the switching elements 10C, 10D, and the control element 20A, the arrangement of the electrodes 11 to 16 of the switching elements 10C, 10D, the arrangement of the plurality of pads 21 of the control element 20A, the electrical connection relationship between the electrodes of the switching elements 10C, 10D and the wires of the wiring layer 32, the arrangement of the plurality of connection wires 34, the plurality of interconnection wires 35, and the plurality of terminals 40, and the like are different from those of the semiconductor device A10 of the above embodiment.

[0069] In the semiconductor device A20, each of the switching elements 10C and 10D is a HEMT made of a material containing gallium nitride (GaN). As shown in Figures 12 to 16, the switching element 10C has a first main surface 101C, a first back surface 102C, a first electrode 11, a second electrode 12, and a third electrode 13. The first main surface 101C faces the z1 side in the thickness direction z, and the first electrode 11, the second electrode 12, and the third electrode 13 are formed on this first main surface 101C.

[0070] 12 to 14, the first electrode 11 and the second electrode 12 each extend in the first direction x. The first electrode 11 and the second electrode 12 are located on either side of the switching element 10C in the second direction y. The first electrode 11 corresponds to the source of the switching element 10C, and the second electrode 12 corresponds to the drain of the switching element 10C.

[0071] 12, 14, and 16, the third electrode 13 is disposed closer to the end of the switching element 10C in the first direction x and closer to the end in the second direction y. The third electrode 13 corresponds to the gate of the switching element 10C. The shapes, quantities, and arrangements of the first electrode 11, second electrode 12, and third electrode 13 in the switching element 10C are merely examples and can be modified in various ways. The switching element 10C configured as described above is an example of a "first semiconductor element" in the present disclosure.

[0072] As shown in Figures 13 to 15, the switching element 10D is disposed on the z1 side in the thickness direction z relative to the switching element 10C. The switching element 10D overlaps with the switching element 10C when viewed in the thickness direction z. As shown in Figures 12 to 15, the switching element 10D has a second main surface 101D, a second back surface 102D, and a plurality (two) of fourth electrodes 14, fifth electrodes 15, and sixth electrodes 16. The second main surface 101D faces the z2 side in the thickness direction z, and the plurality of fourth electrodes 14, fifth electrodes 15, and sixth electrodes 16 are formed on this second main surface 101D.

[0073] 12 and 15, each of the multiple (two) fourth electrodes 14 and the fifth electrode 15 extends in the first direction x. The two fourth electrodes 14 are located on both sides of the switching element 10D in the second direction y. The fifth electrode 15 is located between the two fourth electrodes 14 in the second direction y. As can be seen from FIGS. 12 to 14, the fifth electrode 15 overlaps the first electrode 11 of the switching element 10C when viewed in the thickness direction z. The multiple fourth electrodes 14 correspond to the sources of the switching element 10D, and the fifth electrode 15 corresponds to the drain of the switching element 10D.

[0074] As shown in Figures 12, 14, and 15, the sixth electrode 16 is disposed closer to the end of the switching element 10D in the first direction x and closer to the end in the second direction y. The sixth electrode 16 corresponds to the gate of the switching element 10D. As shown in Figures 13, 14, etc., the switching element 10D is electrically connected to the switching element 10C via the wiring layer 32. The shapes, quantities, and arrangements of the fourth electrode 14, fifth electrode 15, and sixth electrode 16 in the switching element 10D are merely examples and can be modified in various ways. The switching element 10D configured as described above is an example of a "second semiconductor element" in the present disclosure.

[0075] The semiconductor device A20 is configured as, for example, a half-bridge switching circuit. In this case, the switching element 10C configures an upper arm circuit of the semiconductor device A20, and the switching element 10D configures a lower arm circuit. The switching elements 10C and 10D are connected in series.

[0076] 14 and 16, the control element 20A is disposed on the z1 side in the thickness direction z with respect to the switching element 10C. The control element 20A overlaps with the switching element 10C when viewed in the thickness direction z. As shown in FIG. 12, the area of ​​the control element 20A is smaller than the areas of the switching elements 10C and 10D when viewed in the thickness direction z.

[0077] The control element 20A is electrically connected to the switching element 10C and the switching element 10D. The control element 20A is a gate driver that applies a gate voltage to the third electrode 13 of the switching element 10C and the sixth electrode 16 of the switching element 10D.

[0078] As shown in FIGS. 12, 14, and 16, the control element 20A has a third main surface 201A and multiple (four) pads 21. The third main surface 201A faces the z2 side in the thickness direction z. The third main surface 201A faces the first main surface 101C of the switching element 10C. The multiple pads 21 are formed on the third main surface 201A. As shown in FIGS. 12, 14, and 16, each of the multiple pads 21 is rectangular when viewed in the thickness direction. The shape, number, and arrangement of the multiple pads 21 in the control element 20A are merely examples and can be modified in various ways. The control element 20A having the above configuration is an example of a "third semiconductor element" of the present disclosure.

[0079] 13 to 16, the wiring layer 32 is located between the switching element 10C and the switching element 10D and the control element 20A in the thickness direction z. As a result, the wiring layer 32 is located on the z1 side of the switching element 10C in the thickness direction z. The switching element 10D and the control element 20A are located on the z1 side of the wiring layer 32 in the thickness direction z. The wiring layer 32 is located between the third sealing portion 53 and the second sealing portion 52. At least a portion of the wiring layer 32 is housed in the second sealing portion 52. The constituent material of the wiring layer 32 is not particularly limited and includes, for example, copper (Cu).

[0080] As shown in FIGS. 12 to 16 , the wiring layer 32 includes a sixth wiring 321, a seventh wiring 322, an eighth wiring 323, a ninth wiring 324, a tenth wiring 325, and a control wiring 326. In the illustrated example, the sixth wiring 321 is provided in two locations separated from each other. The two sixth wirings 321 are arranged corresponding to the multiple (two) fourth electrodes 14 of the switching element 10D. Each sixth wiring 321 overlaps with the fourth electrode 14 when viewed in the thickness direction z. As shown in FIGS. 13 to 15 , each fourth electrode 14 of the switching element 10D is electrically connected to the sixth wiring 321 via one of the multiple connection wirings 34.

[0081] 12 to 14 , the seventh wiring 322 overlaps with the first electrode 11 and the fifth electrode 15 when viewed in the thickness direction z. As shown in FIGS. 13 and 14 , the first electrode 11 of the switching element 10C is electrically connected to the seventh wiring 322 via one of the plurality of connection wirings 34. Furthermore, the fifth electrode 15 of the switching element 10D is electrically connected to the seventh wiring 322 via one of the plurality of connection wirings 34. That is, the fifth electrode 15 of the switching element 10D is electrically connected to the first electrode 11 of the switching element 10C via the wiring layer 32 (seventh wiring 322).

[0082] The eighth wiring 323 is disposed in correspondence with the second electrode 12 of the switching element 10C. The eighth wiring 323 overlaps with the second electrode 12 when viewed in the thickness direction z. As shown in FIGS. 13 and 14 , the second electrode 12 is electrically connected to the eighth wiring 323 via any of the plurality of connection wirings 34.

[0083] The ninth wiring 324 is arranged to correspond to the third electrode 13 of the switching element 10C and one of the multiple pads 21 of the control element 20A. The ninth wiring 324 overlaps the third electrode 13 and one of the multiple pads 21 when viewed in the thickness direction z. As shown in FIGS. 14 and 16 , the third electrode 13 is electrically connected to the ninth wiring 324 via one of the multiple connection wirings 34. Furthermore, one of the multiple pads 21 is electrically connected to the ninth wiring 324 via one of the multiple connection wirings 34. As a result, the control element 20A (one of the multiple pads 21) is electrically connected to the third electrode 13 via the ninth wiring 324. Furthermore, the pad 21 electrically connected to the third electrode 13 via the ninth wiring 324 overlaps the third electrode 13 when viewed in the thickness direction z.

[0084] The tenth wire 325 is arranged to correspond to the sixth electrode 16 of the switching element 10D and one of the plurality of pads 21 of the control element 20A. The tenth wire 325 overlaps the sixth electrode 16 and one of the plurality of pads 21 when viewed in the thickness direction z. As shown in FIG. 14 , the sixth electrode 16 is electrically connected to the tenth wire 325 via one of the plurality of connection wires 34. Furthermore, one of the plurality of pads 21 is electrically connected to the tenth wire 325 via one of the plurality of connection wires 34. As a result, the control element 20A (one of the plurality of pads 21) is electrically connected to the sixth electrode 16 via the tenth wire 325.

[0085] The control wiring 326 is arranged corresponding to one of the plurality of pads 21 of the control element 20A. In the illustrated example, the control wiring 326 is provided in two locations separated from each other. The two control wirings 326 are arranged corresponding to the two pads 21 of the control element 20A. Each control wiring 326 overlaps with a pad 21 when viewed in the thickness direction z. As shown in FIGS. 12 and 16 , each of the two pads 21 is electrically connected to the control wiring 326 via one of the plurality of connection wirings 34.

[0086] 13 to 16, the multiple connection wires 34 are housed in either the second sealing portion 52 or the third sealing portion 53. As shown in FIGS. 12 to 16, when viewed in the thickness direction z, each of the multiple connection wires 34 overlaps with either the switching element 10C, the switching element 10D, or the control element 20A. Each of the multiple connection wires 34 is connected to the wiring layer 32 (any of the sixth wire 321, the seventh wire 322, the eighth wire 323, the ninth wire 324, the tenth wire 325, and the control wire 326).

[0087] As shown in FIGS. 12 to 16, the plurality of connection wires 34 include a plurality of first connection wires 341 , a plurality of second connection wires 342 , and a plurality of third connection wires 343 .

[0088] 13 , 14 , and 16 , the multiple first connection wirings 341 are interposed between the switching element 10C and the wiring layer 32 in the thickness direction z. In the illustrated example, the multiple first connection wirings 341 are housed in the third sealing portion 53. Each of the multiple first connection wirings 341 is connected to any one of the first electrode 11, the second electrode 12, and the third electrode 13 of the switching element 10C. The constituent material of the multiple first connection wirings 341 is the same as the constituent material of the wiring layer 32, and includes, for example, copper (Cu).

[0089] 13 to 15, the plurality of second connection wirings 342 are interposed between the switching element 10D and the wiring layer 32 in the thickness direction z. In the example shown, the plurality of second connection wirings 342 are housed in the second sealing portion 52. Each of the plurality of second connection wirings 342 is connected to one of the plurality (two) fourth electrodes 14, fifth electrodes 15, and sixth electrodes 16 of the switching element 10D. The constituent material of the plurality of second connection wirings 342 is not particularly limited, and may be, for example, a conductive bonding material such as solder.

[0090] 14 and 16 , the plurality of third connection wirings 343 are interposed between the control element 20A and the wiring layer 32 in the thickness direction z. In the example shown, the plurality of third connection wirings 343 are housed in the second sealing portion 52. Each of the plurality of third connection wirings 343 is connected to one of the plurality of (four) pads 21 of the control element 20A. The constituent material of the plurality of third connection wirings 343 is not particularly limited, and may be, for example, a conductive bonding material such as solder.

[0091] As shown in Figures 13 to 16, the multiple interconnections 35 are housed in the second sealing portion 52 and the third sealing portion 53. As shown in Figures 12 to 16, when viewed in the thickness direction z, each of the multiple interconnections 35 overlaps with the wiring layer 32 (any of the sixth wiring 321, the seventh wiring 322, the eighth wiring 323, and the control wiring 326). As shown in Figures 13 to 16, each of the multiple interconnections 35 is connected to the wiring layer 32 (any of the sixth wiring 321, the seventh wiring 322, the eighth wiring 323, and the control wiring 326). The constituent material of the multiple interconnections 35 is the same as the constituent material of the wiring layer 32, and includes, for example, copper (Cu).

[0092] As shown in FIGS. 12 to 16, the plurality of interconnecting wires 35 include a plurality of first interconnecting wires 351 , a plurality of second interconnecting wires 352 , a plurality of third interconnecting wires 353 , and a plurality of fourth interconnecting wires 354 .

[0093] 12 to 15, the plurality of first connecting wires 351 are connected to the sixth wires 321 and the first terminals 41 described later. As shown in FIGS. 12 and 15, the plurality of second connecting wires 352 are connected to the seventh wires 322 and the second terminals 42 described later. As shown in FIGS. 12 to 14, the plurality of third connecting wires 353 are connected to the eighth wires 323 and the third terminals 43 described later. As shown in FIGS. 12 and 16, each of the plurality of fourth connecting wires 354 is connected to one of the plurality (two) control wires 326 and one of the plurality of control terminals 44 described later.

[0094] As shown in FIGS. 13 to 16 , a portion of each of the multiple terminals 40 is housed in the first sealing portion 51. Each of the multiple terminals 40 is disposed on the z1 side in the thickness direction z with respect to the first main surface 101C of the switching element 10C. Each of the multiple terminals 40 is exposed from the bottom surface 511 of the first sealing portion 51. Each of the multiple terminals 40 is connected to one of the multiple interconnection wires 35 (the multiple first interconnection wires 351, the multiple second interconnection wires 352, the multiple third interconnection wires 353, and the multiple fourth interconnection wires 354). As a result, each of the multiple terminals 40 is electrically connected to at least one of the switching element 10C, the switching element 10D, and the control element 20A via the wiring layer 32 (any of the sixth interconnection wires 321, the seventh interconnection wires 322, the eighth interconnection wires 323, and the control interconnection wire 326). The constituent material of the multiple terminals 40 is the same as the constituent material of the wiring layer 32, and includes, for example, copper (Cu).

[0095] As shown in FIGS. 12 to 16, the plurality of terminals 40 includes a plurality (two) of first terminals 41, second terminals 42, third terminals 43, and a plurality (two) of control terminals 44.

[0096] As shown in FIGS. 12 to 15 , each of the two first terminals 41 is electrically connected to the sixth wiring 321 via a plurality of first interconnection wirings 351. As shown in FIGS. 12 to 14 , the third terminal 43 is electrically connected to the eighth wiring 323 via a plurality of third interconnection wirings 353. DC power, which is the target of conversion by the switching element 10D and the switching element 10C, is input to the two first terminals 41 and the third terminal 43. The two first terminals 41 are negative poles (N terminals). The third terminal 43 is a positive pole (P terminal).

[0097] 12 and 15, the second terminal 42 is electrically connected to the seventh wiring 322 via a plurality of second connecting wirings 352. The second terminal 42 outputs AC power converted by the switching elements 10C and 10D.

[0098] Each of the multiple (two) control terminals 44 is electrically connected to the control wiring 326 via one of the multiple fourth connection wirings 354. Therefore, each of the multiple control terminals 44 is electrically connected to the control element 20A. Power for driving the control element 20A is input to one of the multiple control terminals 44. An electrical signal to the control element 20A is input to one of the multiple control terminals 44.

[0099] Next, the operation of this embodiment will be described.

[0100] The semiconductor device A20 includes a switching element 10C (first semiconductor element), a wiring layer 32 disposed on the z1 side of the switching element 10C in the thickness direction z, and a switching element 10D (second semiconductor element) disposed on the z1 side of the wiring layer 32 in the thickness direction z. The switching element 10C has a first main surface 101C facing the z1 side of the thickness direction z, and a first electrode 11, a second electrode 12, and a third electrode 13 formed on the first main surface 101C. The switching element 10D is, for example, a horizontal HEMT. The switching element 10D is electrically connected to the switching element 10C via the wiring layer 32 and overlaps with the switching element 10C as viewed in the thickness direction z. This configuration allows multiple elements, including the horizontally structured switching element 10C, to be stacked in the thickness direction z. This reduces the planar size (size as viewed in the thickness direction z) of the semiconductor device A20, thereby enabling the miniaturization of the semiconductor device A20.

[0101] Furthermore, with the above configuration, it is possible to shorten the mutual conduction paths between the multiple elements (switching elements 10C and 10D) compared to when the multiple elements are arranged on the same plane, which contributes to reducing parasitic inductance in the wiring inside the semiconductor device A20.

[0102] The switching element 10D has a second main surface 101D and a fourth electrode 14, a fifth electrode 15, and a sixth electrode 16, each formed on the second main surface 101D. The second main surface 101D faces the z2 side in the thickness direction z and faces the first main surface 101C of the switching element 10C. This configuration appropriately shortens the path length between one of the electrodes (first electrode 11) of the switching element 10C and one of the electrodes (fifth electrode 15) of the switching element 10D, which are electrically connected via the wiring layer 32 (seventh wiring 322). This is advantageous for reducing parasitic inductance within the semiconductor device A20.

[0103] The wiring layer 32 includes a sixth wiring 321, a seventh wiring 322, and an eighth wiring 323. In the semiconductor device A20, as shown in FIGS. 13 and 14 , the first electrode 11 (source) of the switching element 10C (upper arm) and the fifth electrode 15 (drain) of the switching element 10D (lower arm) are electrically connected to the seventh wiring 322. The fifth electrode 15 overlaps the first electrode 11 in the thickness direction z. This configuration allows the paths between the first electrode 11 of the switching element 10C and the fifth electrode 15 of the switching element 10D, which are electrically connected to each other, to be linearly formed along the thickness direction z. This shortens the length of the electrically conductive path between the first electrode 11 and the fifth electrode 15, which is more suitable for reducing parasitic inductance within the semiconductor device A20.

[0104] The semiconductor device A20 includes a control element 20A (third semiconductor element) disposed on the z1 side in the thickness direction z of the wiring layer 32. The control element 20A overlaps with the switching element 10C (first semiconductor element) as viewed in the thickness direction z. This configuration makes it possible to reduce the planar size (size as viewed in the thickness direction z) of the semiconductor device A20 including multiple elements (laterally structured switching elements 10C and 10D and the control element 20A), making it more suitable for miniaturizing the semiconductor device A20.

[0105] The wiring layer 32 includes a ninth wiring 324 and a tenth wiring 325. The control element 20A has a third main surface 201A facing the z2 side in the thickness direction z and a plurality of pads 21 formed on the third main surface 201A. One of the pads 21 is electrically connected to the third electrode 13 (gate) of the switching element 10C via the ninth wiring 324. One of the pads 21 is also electrically connected to the sixth electrode 16 (gate) of the switching element 10D via the tenth wiring 325. This configuration appropriately shortens the path length between the third electrode 13 and the sixth electrode 16 of the switching elements 10C and 10D, which are electrically connected via the wiring layer 32 (the ninth wiring 324 and the tenth wiring 325), and one of the pads 21 of the control element 20A. This is advantageous for reducing parasitic inductance within the semiconductor device A20.

[0106] Of the multiple pads 21 of the control element 20A, the pad 21 electrically connected to the third electrode 13 via the ninth wiring 324 overlaps the third electrode 13 when viewed in the thickness direction z. With this configuration, the electrical connection path between the third electrode 13 of the switching element 10C and the pad 21 of the control element 20A can be formed linearly along the thickness direction z. This makes it possible to further shorten the length of the electrical connection path between the third electrode 13 and the pad 21, which is more suitable for reducing parasitic inductance inside the semiconductor device A20.

[0107] 17 shows a semiconductor device according to a first modification of the second embodiment. Fig. 17 is a cross-sectional view showing a semiconductor device A21 of this modification, and shows a cross section similar to Fig. 14 of the above embodiment.

[0108] In the semiconductor device A21 of this modified example, a first back surface 102C of the switching element 10C and a second back surface 102D of the switching element 10D are each exposed from the sealing portion 50. Specifically, the first back surface 102C of the switching element 10C is exposed from the first sealing portion 51. In the illustrated example, the first back surface 102C of the switching element 10C is flush with the bottom surface 511 of the first sealing portion 51. The second back surface 102D of the switching element 10D is exposed from the second sealing portion 52. In the illustrated example, the second back surface 102D of the switching element 10D is flush with the top surface 521 of the second sealing portion 52.

[0109] In the semiconductor device A21, the first back surface 102C of the switching element 10C is exposed from the first sealing portion 51, and the back surface 102D of the switching element 10D is exposed from the second sealing portion 52. With this configuration, heat generated in each of the switching elements 10C and 10D can be efficiently dissipated to the outside of the semiconductor device A21, thereby improving the heat dissipation performance of the semiconductor device A21.

[0110] Furthermore, in the semiconductor device A21, the first back surface 102C exposed from the first sealing portion 51 (sealing portion 50) can be bonded to, for example, a wiring substrate, and the second back surface 102D exposed from the second sealing portion 52 (sealing portion 50) can be bonded to, for example, a heat dissipation member. This configuration can further enhance the heat dissipation properties of the semiconductor device A21. Unlike the example shown in FIG. 17 , the surface of the control element 20A facing the z1 side in the thickness direction z may be exposed from the second sealing portion 52 (sealing portion 50). In this case, heat generated by the control element 20A can be efficiently dissipated to the outside of the semiconductor device A21. Additionally, the semiconductor device A21 exhibits the same effects as the semiconductor device A20 of the above embodiment.

[0111] 18 to 23 show a semiconductor device A30 according to a third embodiment of the present disclosure. FIG. 18 is a plan view showing the semiconductor device A30, with the sealing portion 50 seen through. In FIG. 18, the see-through sealing portion 50 is indicated by an imaginary line (two-dot chain line). FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18. FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 18. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 18. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 18. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 18.

[0112] The semiconductor device A30 includes a switching element 10E, a control element 20B, a wiring layer 33, a plurality of connection wires 34, a plurality of interconnection wires 35, a plurality of terminals 40, and a sealing portion 50.

[0113] In the semiconductor device A30, the switching element 10E is a HEMT made of a material containing gallium nitride (GaN). As shown in Figures 18 to 23, the switching element 10E has a first main surface 101E, a first back surface 102E, a first electrode 11, a second electrode 12, and a third electrode 13. The first main surface 101E faces the z1 side in the thickness direction z, and the first electrode 11, the second electrode 12, and the third electrode 13 are formed on this first main surface 101E.

[0114] 18 , 22 , and 23 , the first electrode 11 and the second electrode 12 each extend in the first direction x. The first electrode 11 and the second electrode 12 are located on either side of the switching element 10E in the second direction y. A current corresponding to the power before conversion by the switching element 10E flows through the second electrode 12. The second electrode 12 corresponds to the drain of the switching element 10E. A current corresponding to the power after conversion by the switching element 10E flows through the first electrode 11. The first electrode 11 corresponds to the source of the switching element 10E.

[0115] 18, 20, and 23, the third electrode 13 is disposed closer to the end of the switching element 10E in the first direction x and closer to the end in the second direction y. A gate voltage for driving the switching element 10E is applied to the third electrode 13. This third electrode 13 corresponds to the gate of the switching element 10E. The shapes, quantities, and arrangements of the first electrode 11, second electrode 12, and third electrode 13 in the switching element 10E are merely examples and can be modified in various ways. The switching element 10E configured as described above is an example of a "first semiconductor element" in the present disclosure.

[0116] In the semiconductor device A30, the first back surface 102E of the switching element 10E is exposed from the sealing portion 50. Specifically, the first back surface 102E of the switching element 10E is exposed from the first sealing portion 51. In the example shown in the figure, the first back surface 102E of the switching element 10E is flush with the bottom surface 511 of the first sealing portion 51.

[0117] 20 to 23, the control element 20B is disposed on the z1 side of the switching element 10E in the thickness direction z. The control element 20B overlaps with the switching element 10E when viewed in the thickness direction z. As shown in FIG. 18, the area of ​​the control element 20B is smaller than the area of ​​the switching element 10E when viewed in the thickness direction z.

[0118] The control element 20B is electrically connected to the switching element 10E via the wiring layer 33. The control element 20B is a gate driver that applies a gate voltage to the third electrode 13 of the switching element 10E.

[0119] As shown in Figures 18, 20, 21, and 23, the control element 20B has an element main surface 201B and multiple (three) pads 21. The element main surface 201B faces the z2 side in the thickness direction z. The element main surface 201B faces the first main surface 101E of the switching element 10E. The multiple pads 21 are formed on the element main surface 201B. As shown in Figure 18, each of the multiple pads 21 is rectangular when viewed in the thickness direction. The shape, number, and arrangement of the multiple pads 21 in the control element 20B are merely examples and can be modified in various ways. The control element 20B having the above configuration is an example of a "second semiconductor element" of the present disclosure.

[0120] In the semiconductor device A30, the surface of the control element 20B facing the z1 side in the thickness direction z (the surface facing the opposite side from the element main surface 201B) is exposed from the sealing portion 50. Specifically, the surface of the control element 20B facing the z1 side in the thickness direction z is exposed from the second sealing portion 52. In the example shown in the figure, the surface of the control element 20B facing the z1 side in the thickness direction z is flush with the top surface 521 of the second sealing portion 52.

[0121] As shown in Figures 19 to 23, the wiring layer 33 is located between the switching element 10E and the control element 20B in the thickness direction z. As a result, the wiring layer 33 is located on the z1 side in the thickness direction z of the switching element 10E. Furthermore, the control element 20B is located on the z1 side in the thickness direction z of the wiring layer 33. The wiring layer 33 is located between the third sealing portion 53 and the second sealing portion 52. At least a portion of the wiring layer 33 is housed in the second sealing portion 52. The constituent material of the wiring layer 33 is not particularly limited and includes, for example, copper (Cu).

[0122] 18 to 23, the wiring layer 33 includes an eleventh wiring 331, a twelfth wiring 332, a thirteenth wiring 333, and a control wiring 334. As shown in FIGS. 18 to 22, the eleventh wiring 331 is disposed in correspondence with the first electrode 11 of the switching element 10E. The eleventh wiring 331 overlaps the first electrode 11 when viewed in the thickness direction z. As shown in FIGS. 19 to 22, the first electrode 11 of the switching element 10E is electrically connected to the eleventh wiring 331 via any of the multiple connection wirings 34.

[0123] 18 to 20 and 23, the twelfth wiring 332 is disposed in correspondence with the second electrode 12 of the switching element 10E. The twelfth wiring 332 overlaps the second electrode 12 when viewed in the thickness direction z. As shown in FIGS. 19, 20 and 23, the second electrode 12 of the switching element 10E is electrically connected to the twelfth wiring 332 via any of the multiple connection wirings 34.

[0124] As shown in FIGS. 18 , 20 , and 23 , the 13th wiring 333 is disposed corresponding to the third electrode 13 of the switching element 10E and one of the plurality of pads 21 of the control element 20B. The 13th wiring 333 overlaps the third electrode 13 and one of the plurality of pads 21 when viewed in the thickness direction z. As shown in FIGS. 20 and 23 , the third electrode 13 is electrically connected to the 13th wiring 333 via one of the plurality of connection wirings 34. Furthermore, one of the plurality of pads 21 is electrically connected to the 13th wiring 333 via one of the plurality of connection wirings 34. As a result, the control element 20B (one of the plurality of pads 21) is electrically connected to the third electrode 13 via the 13th wiring 333. Furthermore, the pad 21 electrically connected to the third electrode 13 via the 13th wiring 333 (wiring layer 33) overlaps the third electrode 13 when viewed in the thickness direction z.

[0125] The control wiring 334 is arranged corresponding to one of the plurality of pads 21 of the control element 20B. In the illustrated example, the control wiring 334 is provided in two locations separated from each other. The two control wirings 334 are arranged corresponding to the two pads 21 of the control element 20B. Each control wiring 334 overlaps with a pad 21 when viewed in the thickness direction z. As shown in FIGS. 18 and 21 , each of the two pads 21 is electrically connected to the control wiring 334 via one of the plurality of connection wirings 34.

[0126] 19 to 23, the multiple connection wires 34 are housed in either the second sealing portion 52 or the third sealing portion 53. As shown in FIGS. 18 to 23, when viewed in the thickness direction z, each of the multiple connection wires 34 overlaps either the switching element 10E or the control element 20B. Each of the multiple connection wires 34 is connected to the wiring layer 33 (either the eleventh wire 331, the twelfth wire 332, the thirteenth wire 333, or the control wire 334).

[0127] As shown in FIGS. 19 to 23, the plurality of connection wires 34 include a plurality of fourth connection wires 344 and a plurality of fifth connection wires 345 .

[0128] 19 to 23, the multiple fourth connection wires 344 are interposed between the switching element 10E and the wiring layer 33 in the thickness direction z. In the example shown, the multiple fourth connection wires 344 are housed in the third sealing portion 53. Each of the multiple fourth connection wires 344 is connected to any one of the first electrode 11, the second electrode 12, and the third electrode 13 of the switching element 10E. The constituent material of the multiple fourth connection wires 344 is the same as the constituent material of the wiring layer 33, and includes, for example, copper (Cu).

[0129] 20 , 21 , and 23 , the plurality of fifth connection wires 345 are interposed between the control element 20B and the wiring layer 33 in the thickness direction z. In the example shown, the plurality of fifth connection wires 345 are housed in the second sealing portion 52. Each of the plurality of fifth connection wires 345 is connected to one of the plurality of (three) pads 21 of the control element 20B. The constituent material of the plurality of fifth connection wires 345 is not particularly limited, and may be, for example, a conductive bonding material such as solder.

[0130] As shown in Figures 19 to 21, the multiple interconnecting wires 35 are housed in the second sealing portion 52 and the third sealing portion 53. As shown in Figures 18 to 21, when viewed in the thickness direction z, each of the multiple interconnecting wires 35 overlaps with the wiring layer 33 (any of the eleventh wiring 331, the twelfth wiring 332, and the control wiring 334). As shown in Figures 19 to 21, each of the multiple interconnecting wires 35 is connected to the wiring layer 33 (any of the eleventh wiring 331, the twelfth wiring 332, and the control wiring 334). The constituent material of the multiple interconnecting wires 35 is the same as the constituent material of the wiring layer 33, and includes, for example, copper (Cu).

[0131] As shown in FIGS. 18 to 21, the plurality of interconnecting wires 35 include a plurality of first interconnecting wires 351 , a plurality of second interconnecting wires 352 , and a plurality of fourth interconnecting wires 354 .

[0132] 18 to 21, the plurality of first connecting wires 351 are connected to the eleventh wiring 331 and a first terminal 41, which will be described later. As shown in Figures 18 to 20, the plurality of second connecting wires 352 are connected to the twelfth wiring 332 and a second terminal 42, which will be described later. As shown in Figures 18 and 21, each of the plurality of fourth connecting wires 354 is connected to one of the plurality (two) control wires 334 and one of the plurality of control terminals 44, which will be described later.

[0133] As shown in FIGS. 19 to 21 , a portion of each of the multiple terminals 40 is housed in the first sealing portion 51. Each of the multiple terminals 40 is exposed from the bottom surface 511 of the first sealing portion 51. Each of the multiple terminals 40 is connected to one of the multiple connecting wires 35 (the multiple first connecting wires 351, the multiple second connecting wires 352, and the multiple fourth connecting wires 354). As a result, each of the multiple terminals 40 is electrically connected to at least one of the switching element 10E and the control element 20B via the wiring layer 33 (one of the eleventh wiring 331, the twelfth wiring 332, and the control wiring 334). The constituent material of the multiple terminals 40 is the same as the constituent material of the wiring layer 33, and includes, for example, copper (Cu).

[0134] As shown in FIGS. 18 to 21, the plurality of terminals 40 includes a first terminal 41, a second terminal 42, and a plurality of (two) control terminals 44.

[0135] 18 to 21, the first terminal 41 is electrically connected to the eleventh wiring 331 via a plurality of first connecting wirings 351. Furthermore, the first electrode 11 of the switching element 10E is electrically connected to the eleventh wiring 331 via a plurality of fourth connecting wirings 344. As a result, the first terminal 41 is electrically connected to the first electrode 11 via the eleventh wiring 331. Since the first electrode 11 is the source, the first terminal 41 is a source terminal.

[0136] 18 to 20 , the second terminal 42 is electrically connected to the twelfth wiring 332 via a plurality of second connecting wirings 352. Furthermore, the second electrode 12 of the switching element 10E is electrically connected to the twelfth wiring 332 via a plurality of fourth connecting wirings 344. As a result, the second terminal 42 is electrically connected to the second electrode 12 via the twelfth wiring 332. Since the first electrode 11 is a drain, the second terminal 42 is a drain terminal.

[0137] Each of the multiple (two) control terminals 44 is electrically connected to the control wiring 326 via one of the multiple fourth connection wirings 354. Therefore, each of the multiple control terminals 44 is electrically connected to the control element 20B. Power for driving the control element 20B is input to one of the multiple control terminals 44. An electrical signal for the control element 20B is input to one of the multiple control terminals 44.

[0138] Next, the operation of this embodiment will be described.

[0139] The semiconductor device A30 includes a switching element 10E (first semiconductor element), a wiring layer 33 disposed on the z1 side of the switching element 10E in the thickness direction z, and a control element 20B (second semiconductor element) disposed on the z1 side of the wiring layer 33 in the thickness direction z. The switching element 10E has a first main surface 101E facing the z1 side of the thickness direction z, and a first electrode 11, a second electrode 12, and a third electrode 13 formed on the first main surface 101E. The control element 20B is electrically connected to the switching element 10E via the wiring layer 33 and overlaps the switching element 10E in the thickness direction z. This configuration allows multiple elements, including the horizontally structured switching element 10E, to be stacked in the thickness direction z. This reduces the planar size (size as viewed in the thickness direction z) of the semiconductor device A30, thereby enabling the miniaturization of the semiconductor device A30.

[0140] Furthermore, with the above configuration, it is possible to shorten the mutual conduction paths between the multiple elements (switching element 10E and control element 20B) compared to when the multiple elements are arranged along the same plane, which contributes to reducing parasitic inductance in the wiring inside semiconductor device A30.

[0141] The control element 20B has an element main surface 201B facing the z2 side in the thickness direction z and a plurality of pads 21 formed on the element main surface 201B. Any of the plurality of pads 21 is electrically connected to the third electrode 13 (gate) of the switching element 10E via the wiring layer 33 (thirteenth wiring 333). This configuration allows the path length between the third electrode 13 of the switching element 10E, which is electrically connected via the wiring layer 33 (thirteenth wiring 333), and any of the plurality of pads 21 of the control element 20B to be appropriately shortened. This is advantageous for reducing parasitic inductance within the semiconductor device A30.

[0142] Of the multiple pads 21 of the control element 20B, the pad 21 that is electrically connected to the third electrode 13 via the thirteenth wiring 333 (wiring layer 33) overlaps the third electrode 13 when viewed in the thickness direction z. With this configuration, the electrical connection path between the third electrode 13 of the switching element 10E and the pad 21 of the control element 20B can be formed linearly along the thickness direction z. This makes it possible to further shorten the length of the electrical connection path between the third electrode 13 and the pad 21, which is more suitable for reducing parasitic inductance inside the semiconductor device A30.

[0143] In the semiconductor device A30, the first back surface 102E of the switching element 10E is exposed from the first sealing portion 51, and the surface of the control element 20B facing the z1 side in the thickness direction z is exposed from the second sealing portion 52. With this configuration, heat generated by the switching element 10E and the control element 20B can be efficiently dissipated to the outside of the semiconductor device A30, thereby improving the heat dissipation performance of the semiconductor device A30.

[0144] Furthermore, in the semiconductor device A30, the first back surface 102E exposed from the first sealing portion 51 (sealing portion 50) can be bonded to, for example, a wiring substrate, and the surface of the control element 20B exposed from the second sealing portion 52 (sealing portion 50) facing the z1 side in the thickness direction z can be bonded to, for example, a heat dissipation member. This configuration can further improve the heat dissipation properties of the semiconductor device A30.

[0145] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways.

[0146] The present disclosure includes configurations related to the following supplementary notes. Supplementary note 1. A semiconductor device comprising: a first semiconductor element having a first main surface facing one side in a thickness direction; a wiring layer arranged on one side in the thickness direction of the first semiconductor element; and a second semiconductor element arranged on one side in the thickness direction of the wiring layer, wherein the first semiconductor elements have a first electrode, a second electrode, and a third electrode each formed on the first main surface, the second semiconductor element overlaps the first semiconductor element when viewed in the thickness direction, and the second semiconductor element is electrically connected to the first semiconductor element via the wiring layer. Supplementary note 2. The semiconductor device according to supplementary note 1, wherein the second semiconductor element has a second main surface facing the other side in the thickness direction, and a fourth electrode, a fifth electrode, and a sixth electrode formed on the second main surface. Supplementary note 3. The semiconductor device according to Supplementary Note 2, wherein the wiring layer includes a first wiring, a second wiring, and a third wiring, the first electrode is electrically connected to the first wiring, the second electrode is electrically connected to the second wiring, the fourth electrode is electrically connected to the second wiring, and the fifth electrode is electrically connected to the third wiring.Supplementary Note 4. The semiconductor device according to Supplementary Note 3, wherein the fourth electrode overlaps the second electrode when viewed in the thickness direction.Supplementary Note 5. The semiconductor device according to Supplementary Note 3 or 4, further comprising a third semiconductor element, the third semiconductor element being disposed on one side of the wiring layer in the thickness direction and being electrically connected to the wiring layer, and the third semiconductor element overlapping the first semiconductor element when viewed in the thickness direction.Supplementary Note 6. The semiconductor device according to Supplementary Note 5, wherein the wiring layer includes a fourth wiring and a fifth wiring, and the third semiconductor element is electrically connected to the third electrode via the fourth wiring and to the sixth electrode via the fifth wiring.Appendix 7. The semiconductor device according to Appendix 6, wherein each of the first semiconductor element and the second semiconductor element is a switching element, the third semiconductor element is a control element, each of the first electrode and the fourth electrode is a source, each of the second electrode and the fifth electrode is a drain, and each of the third electrode and the sixth electrode is a gate, the third semiconductor element has a third main surface facing the other side in the thickness direction and a plurality of pads formed on the third main surface, and the plurality of pads includes one that is electrically connected to the fourth wiring and the fifth wiring. Appendix 8. The semiconductor device according to Appendix 2, wherein the wiring layer includes a sixth wiring, a seventh wiring, and an eighth wiring, the first electrode is electrically connected to the seventh wiring, the second electrode is electrically connected to the eighth wiring, the fourth electrode is electrically connected to the sixth wiring, and the fifth electrode is electrically connected to the seventh wiring. Appendix 9. The semiconductor device according to Appendix 8, wherein the fifth electrode overlaps with the first electrode when viewed in the thickness direction. Appendix 10. The semiconductor device according to Appendix 8 or 9, further comprising a third semiconductor element, wherein the third semiconductor element is arranged on one side of the wiring layer in the thickness direction and is conductive with the wiring layer, and the third semiconductor element overlaps with the first semiconductor element when viewed in the thickness direction. Appendix 11. The semiconductor device according to Appendix 10, wherein the wiring layer includes a ninth wiring and a tenth wiring, and the third semiconductor element is conductive with the third electrode via the ninth wiring and is conductive with the sixth electrode via the tenth wiring. Appendix 12. The semiconductor device described in Appendix 11, wherein each of the first semiconductor element and the second semiconductor element is a switching element, the third semiconductor element is a control element, each of the first electrode and the fourth electrode is a source, each of the second electrode and the fifth electrode is a drain, and each of the third electrode and the sixth electrode is a gate, the third semiconductor element has a third main surface facing the other side in the thickness direction and a plurality of pads formed on the third main surface, and the plurality of pads include pads that are conductive to the ninth wiring and the tenth wiring.Supplementary Note 13. The semiconductor device according to Supplementary Note 12, wherein the pad electrically connected to the third electrode via the ninth wiring overlaps with the third electrode when viewed in the thickness direction. Supplementary Note 14. The semiconductor device according to any one of Supplementary Note 7, 12, or 13, further comprising a plurality of terminals arranged on the other side in the thickness direction of the first main surface, wherein the plurality of terminals are electrically connected to any of the first semiconductor element, the second semiconductor element, and the third semiconductor element. Supplementary Note 15. The semiconductor device according to any one of Supplementary Notes 7, 12, and 13, further comprising a plurality of connection wires connected to the wiring layer, the plurality of connection wires including a plurality of first connection wires, a plurality of second connection wires, and a plurality of third connection wires, each of the plurality of first connection wires being interposed between the first semiconductor element and the wiring layer in the thickness direction and being connected to any of the first electrode, the second electrode, and the third electrode, each of the plurality of second connection wires being interposed between the second semiconductor element and the wiring layer in the thickness direction and being connected to any of the fourth electrode, the fifth electrode, and the sixth electrode, and each of the plurality of third connection wires being interposed between the third semiconductor element and the wiring layer in the thickness direction and being connected to any of the plurality of pads. Supplementary Note 16. The semiconductor device according to any one of Supplementary Notes 2 to 15, further comprising a sealing portion covering at least a portion of the first semiconductor element and the second semiconductor element. Supplementary Note 17. The semiconductor device according to Appendix 16, wherein the sealing portion includes a first sealing portion and a second sealing portion, the first sealing portion covers at least a portion of the first semiconductor element, and the second sealing portion is disposed on one side of the first sealing portion in the thickness direction and covers at least a portion of the second semiconductor element. Appendix 18. The semiconductor device according to Appendix 17, wherein the first semiconductor element has a first back surface spaced apart from the first main surface in the thickness direction and facing the other side in the thickness direction, the second semiconductor element has a second back surface spaced apart from the second main surface in the thickness direction and facing one side in the thickness direction, the first back surface being exposed from the first sealing portion, and the second back surface being exposed from the second sealing portion.Supplementary Note 19. The semiconductor device according to Supplementary Note 1, wherein the first semiconductor element is a switching element, the second semiconductor element is a control element, the first electrode is a source, the second electrode is a drain, and the third electrode is a gate, and the second semiconductor element is electrically connected to the third electrode via the wiring layer.

[0147] A10, A11, A20, A21, A30: semiconductor device 10A, 10C, 10E: switching element (first semiconductor element) 10B, 10D: switching element (second semiconductor element) 101A, 101C, 101E: first main surface 101B, 101D: second main surface 102A, 102C, 102E: first back surface 102B, 102D: second back surface 11: first electrode (source) 12: second electrode (drain) 13: third electrode (gate) 14: fourth electrode (source) 15: fifth electrode (drain) 16: sixth electrode (gate) 20A: control element (third semiconductor element) 201A: third main surface 20B: control element (second semiconductor element) 201B: element main surface 21: pad 31, 32, 33: Wiring layers 311: First wiring 312: Second wiring 313: Third wiring 314: Fourth wiring 315: Fifth wiring 316: Control wiring 321: Sixth wiring 322: Seventh wiring 323: Eighth wiring 324: Ninth wiring 325: Tenth wiring 326: Control wiring 331: Eleventh wiring 332: Twelfth wiring 333: Thirteenth wiring 334: Control wiring 34: Connection wiring 341: First connection wiring 342: Second connection wiring 343: Third connection wiring 344: Fourth connection wiring 345: Fifth connection wiring 35: Connection wiring 351: First connection wiring 352: Second connection wiring 353: Third connection wiring 354: Fourth connection wiring 40: Terminal 41: First terminal 42: Second terminal 43: Third terminal 44: Control terminal 50: Sealing section 51: First sealing section 511: Bottom surface 52: Second sealing section 521: Top surface 53: Third sealing section

Claims

1. a first semiconductor element having a first main surface facing one side in a thickness direction; a wiring layer disposed on one side of the first semiconductor element in the thickness direction; a second semiconductor element disposed on one side of the wiring layer in the thickness direction; the first semiconductor element has a first electrode, a second electrode, and a third electrode each formed on the first main surface; the second semiconductor element overlaps with the first semiconductor element when viewed in the thickness direction, The second semiconductor element is electrically connected to the first semiconductor element via the wiring layer.

2. 2 . The semiconductor device according to claim 1 , wherein the second semiconductor element has a second main surface facing the other side in the thickness direction, and a fourth electrode, a fifth electrode and a sixth electrode formed on the second main surface.

3. the wiring layer includes a first wiring, a second wiring, and a third wiring; The first electrode is electrically connected to the first wiring, The second electrode is electrically connected to the second wiring, the fourth electrode is electrically connected to the second wiring; The semiconductor device according to claim 2 , wherein the fifth electrode is electrically connected to the third wiring.

4. The semiconductor device according to claim 3 , wherein the fourth electrode overlaps with the second electrode when viewed in the thickness direction.

5. Further comprising a third semiconductor element; the third semiconductor element is disposed on one side of the wiring layer in the thickness direction and is electrically connected to the wiring layer; The semiconductor device according to claim 3 , wherein the third semiconductor element overlaps with the first semiconductor element when viewed in the thickness direction.

6. the wiring layer includes a fourth wiring and a fifth wiring, The semiconductor device according to claim 5 , wherein the third semiconductor element is electrically connected to the third electrode via the fourth wiring and is electrically connected to the sixth electrode via the fifth wiring.

7. each of the first semiconductor element and the second semiconductor element is a switching element; the third semiconductor element is a control element; each of the first electrode and the fourth electrode is a source; each of the second electrode and the fifth electrode is a drain; each of the third electrode and the sixth electrode is a gate; the third semiconductor element has a third main surface facing the other side in the thickness direction and a plurality of pads formed on the third main surface; 7. The semiconductor device according to claim 6, wherein said plurality of pads include one electrically connected to said fourth wiring and said fifth wiring.

8. the wiring layer includes a sixth wiring, a seventh wiring, and an eighth wiring, The first electrode is electrically connected to the seventh wiring, The second electrode is electrically connected to the eighth wiring, The fourth electrode is electrically connected to the sixth wiring, The semiconductor device according to claim 2 , wherein said fifth electrode is electrically connected to said seventh wiring.

9. The semiconductor device according to claim 8 , wherein the fifth electrode overlaps with the first electrode when viewed in the thickness direction.

10. Further comprising a third semiconductor element; the third semiconductor element is disposed on one side of the wiring layer in the thickness direction and is electrically connected to the wiring layer; The semiconductor device according to claim 8 , wherein the third semiconductor element overlaps with the first semiconductor element when viewed in the thickness direction.

11. the wiring layer includes a ninth wiring and a tenth wiring, The semiconductor device according to claim 10 , wherein the third semiconductor element is electrically connected to the third electrode via the ninth wiring and is electrically connected to the sixth electrode via the tenth wiring.

12. each of the first semiconductor element and the second semiconductor element is a switching element; the third semiconductor element is a control element; each of the first electrode and the fourth electrode is a source; each of the second electrode and the fifth electrode is a drain; each of the third electrode and the sixth electrode is a gate; the third semiconductor element has a third main surface facing the other side in the thickness direction and a plurality of pads formed on the third main surface; 12. The semiconductor device according to claim 11, wherein said plurality of pads include one electrically connected to said ninth wiring and said tenth wiring.

13. The semiconductor device according to claim 12 , wherein the pad, which is electrically connected to the third electrode via the ninth wiring, overlaps with the third electrode when viewed in the thickness direction.

14. a plurality of terminals disposed on the other side of the first main surface in the thickness direction; The semiconductor device according to claim 7 , wherein the plurality of terminals are electrically connected to any one of the first semiconductor element, the second semiconductor element, and the third semiconductor element.

15. Further comprising a plurality of connection wirings connected to the wiring layer, the plurality of connection wirings include a plurality of first connection wirings, a plurality of second connection wirings, and a plurality of third connection wirings; each of the plurality of first connection wirings is interposed between the first semiconductor element and the wiring layer in the thickness direction, and is connected to any one of the first electrode, the second electrode, and the third electrode; each of the plurality of second connection wirings is interposed between the second semiconductor element and the wiring layer in the thickness direction, and is connected to any one of the fourth electrode, the fifth electrode, and the sixth electrode; 8. The semiconductor device according to claim 7, wherein each of said third connection wirings is interposed between said third semiconductor element and said wiring layer in said thickness direction, and is connected to one of said pads.

16. The semiconductor device according to claim 2 , further comprising a sealing portion covering at least a portion of said first semiconductor element and said second semiconductor element.

17. the sealing portion includes a first sealing portion and a second sealing portion, the first sealing portion covers at least a portion of the first semiconductor element, The semiconductor device according to claim 16 , wherein the second sealing portion is disposed on one side in the thickness direction with respect to the first sealing portion, and covers at least a portion of the second semiconductor element.

18. the first semiconductor element has a first back surface that is spaced apart from the first main surface in the thickness direction and faces the other side in the thickness direction; the second semiconductor element has a second back surface that is spaced apart from the second main surface in the thickness direction and faces one side in the thickness direction; the first back surface is exposed from the first sealing portion, The semiconductor device according to claim 17 , wherein the second back surface is exposed from the second sealing portion.

19. the first semiconductor element is a switching element, the second semiconductor element is a control element; the first electrode is a source; the second electrode is a drain; the third electrode is a gate; The semiconductor device according to claim 1 , wherein said second semiconductor element is electrically connected to said third electrode via said wiring layer.