Wiring board and package structure using same

Abstract

A wiring board according to the present disclosure comprises: an insulating board that has a first surface and a second surface which is positioned on the reverse side from the first surface; and a solder resist that is positioned on the first surface. The insulating board comprises: at least one recess which is recessed from the peripheral edge of the insulating board in a direction toward the center when viewed in plan; and a plurality of electrodes which are positioned on the first surface along the recess. The solder resist has an opening from which the electrodes are exposed. The peripheral edge of the solder resist comprises: a first peripheral edge that extends along the recess; and a second peripheral edge that extends along the peripheral edge of the insulating board excluding the recess. The first peripheral edge overlaps with the peripheral edge of the recess; and the second peripheral edge comprises a first region that is connected to the first peripheral edge. When viewed in plan, the first region is positioned closer to the center of the insulating board than the peripheral edge of the insulating board.

Description

Wiring board and mounting structure using same

[0001] The present disclosure relates to a wiring board and a mounting structure using the same.

[0002] For example, there is a wiring board having a processor die mounted on the top surface and an optical module mounted on the periphery to connect to an optical connector (see Patent Documents 1 and 2). The optical module includes a photonics die.

[0003] After mounting the optical module on the wiring board, underfill (encapsulating resin) is filled between the photonics die and the wiring board. Some of the filled underfill (encapsulating resin) may protrude onto the outer side of the board, causing connection problems with the optical connector. This protrusion of underfill (encapsulating resin) is particularly likely to occur when the edge of the solder resist on the top surface of the wiring board is chipped. The outer edge of the wiring board is prone to shocks during transportation, and the relatively fragile edge of the solder resist is easily chipped by the impact.

[0004] Japanese Patent Application Laid-Open No. 2005-286225

[0005] The wiring board according to the present disclosure includes an insulating substrate having a first surface and a second surface located opposite the first surface, and a solder resist located on the first surface. The insulating substrate includes at least one recess recessed from the periphery of the insulating substrate toward the center in a plan view, and a plurality of electrodes located on the first surface along the recess. The solder resist has openings that expose the electrodes. The periphery of the solder resist includes a first periphery along the recess and a second periphery along the periphery of the insulating substrate other than the recess. The first periphery overlaps the periphery of the recess, and the second periphery includes a first region connected to the first periphery. In a plan view, the first region is located toward the center relative to the periphery of the insulating substrate.

[0006] Furthermore, the mounting structure according to the present disclosure includes the above-mentioned wiring board, an adapter located in the recess, and an electronic component connected to the adapter and to a plurality of electrodes located on the first surface of the insulating substrate, and a sealing resin is located between the underside of the electronic component and the solder resist.

[0007] Fig. 2 is an explanatory diagram showing a mounting structure including a wiring board according to an embodiment of the present disclosure. Fig. 3 is an explanatory diagram showing a wiring board according to an embodiment of the present disclosure. Fig. 4 is a plan view of region X shown in Fig. 2. Fig. 5 is an enlarged explanatory diagram showing a connection portion between an adapter and an optical connector in the mounting structure shown in Fig. 1. Fig. 6 is an enlarged explanatory diagram showing a state of sealing resin at a connection portion between an adapter and an optical connector in the mounting structure shown in Fig. 1.

[0008] As described above, a portion of the filled sealing resin may overflow onto the outer peripheral side surface of the substrate, causing a connection failure with the optical connector. Therefore, there is a need for a wiring board and a mounting structure using the same that can prevent overflow of the filled sealing resin onto the outer peripheral side surface of the wiring board even if a portion of the filled sealing resin overflows.

[0009] The wiring board and mounting structure according to the present disclosure have the configuration described in the section on means for solving the above problems, and therefore, even if part of the filled sealing resin overflows, it can be prevented from overflowing to the outer side surface of the wiring board.

[0010] A wiring board according to an embodiment of the present disclosure will be described with reference to Figures 1 to 5. Figure 1 is an explanatory diagram showing a mounting structure 10 including a wiring board 1 according to an embodiment of the present disclosure. Figure 2 is an explanatory diagram showing the wiring board 1 according to an embodiment of the present disclosure. The wiring board 1 according to an embodiment includes an insulating substrate 2 and a solder resist 3.

[0011] The insulating substrate 2 has a first surface f1 and a second surface f2 located on the opposite side of the first surface f1. Examples of insulating layers constituting the insulating substrate 2 include a core insulating layer and a build-up insulating layer.

[0012] The build-up insulating layer is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed together.

[0013] The build-up insulating layer may contain a reinforcing material. Examples of reinforcing materials include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more reinforcing materials may be used in combination. Furthermore, the build-up insulating layer may have dispersed therein an inorganic insulating filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. Two or more inorganic insulating fillers may be used in combination.

[0014] 2, the build-up insulating layers are located on the upper and lower surfaces of the core insulating layer. The thickness of the build-up insulating layers is not particularly limited, and is, for example, 10 μm to 50 μm.

[0015] Via-hole conductors are located in the build-up insulating layer to electrically connect the upper and lower surfaces of the build-up insulating layer. The via-hole conductors are located in via holes that penetrate the upper and lower surfaces of the build-up insulating layer. The via-hole conductors are formed of a metal such as copper, specifically a metal plating such as copper plating. The via-hole conductors may fill the via holes or may be formed only on the inner wall surfaces of the via holes. The via-hole conductors are connected to conductor layers located on the upper and lower surfaces of the build-up insulating layer.

[0016] The core insulating layer is also not particularly limited as long as it is made of an insulating material. As with the build-up insulating layer, examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Furthermore, as with the build-up insulating layer, the core insulating layer may contain a reinforcing material and may have an inorganic insulating filler dispersed therein.

[0017] The core insulating layer is located approximately at the center in the thickness direction of the wiring board 1 and is usually thicker than the build-up insulating layer. The thickness of the core insulating layer is not particularly limited and is, for example, 100 μm to 1500 μm.

[0018] A through-hole conductor is located in the core insulating layer to electrically connect the upper and lower surfaces of the core insulating layer. The through-hole conductor is located in a through-hole that penetrates the upper and lower surfaces of the core insulating layer. The through-hole conductor is formed of a metal such as copper, specifically a metal plating such as copper plating. The through-hole conductor may be formed only on the inner wall surface of the through-hole, or may fill the through-hole. The through-hole conductor is connected to conductor layers located on the upper and lower surfaces of the core insulating layer.

[0019] The shape of the insulating substrate 2 is not limited. When viewed from above, the insulating substrate 2 may have a rectangular shape as shown in FIG. 2 , or may have a polygonal shape other than a rectangular shape, a circular shape, or an elliptical shape. When viewed from above, the insulating substrate 2 has a recess 21 recessed from the periphery of the insulating substrate 2 toward the center. At least one recess 21 is included in the insulating substrate 2. When the insulating substrate 2 has a rectangular shape as shown in FIG. 2 , the recess 21 is positioned so as to recess from one side (first side) of the sides constituting the rectangular shape toward the center.

[0020] The size of the recess 21 is set appropriately according to the size of the adapter 4 to be positioned in the recess 21. At least one recess 21 needs to be included in the insulating substrate 2, and if the insulating substrate 2 has a polygonal shape such as a square shape, multiple recesses 21 may be included on one side.

[0021] A plurality of electrodes 8 are located along the recess 21 on the first surface f1 of the insulating substrate 2. The first surface f1 of the insulating substrate 2 is the upper surface on the surface side in the thickness direction of the wiring board 1, and the second surface f2 is the lower surface located on the opposite side of the first surface f1 in the thickness direction of the wiring board 1. The electrodes 8 are formed of a metal such as copper and are part of a conductor layer located on the first surface f1 of the insulating substrate 2. On the first surface f1 of the insulating substrate 2, the electrodes 8 are located not only along the recess 21 but also, for example, in approximately the center of the insulating substrate 2 as shown in FIG. 2 . Terminals of the processor die are connected to these central electrodes 8 via solder 7, which will be described later.

[0022] 2, a solder resist 3 is located on the first surface f1 of the insulating substrate 2. The solder resist 3 is made of a resin, such as an acrylic-modified epoxy resin. The solder resist 3 has a thickness of, for example, 10 μm to 50 μm.

[0023] The solder resist 3 has openings that individually expose the electrodes 8. In Fig. 2, solder 7 is attached to the electrodes 8 exposed in the openings.

[0024] In plan view, the solder resist 3 is formed according to the shape of the insulating substrate 2. The periphery of the solder resist 3 includes a first periphery 31 that follows the recess 21 of the insulating substrate 2, and a second periphery 32 that follows the periphery of the insulating substrate 2 other than the recess 21. The first periphery 31 of the solder resist 3 overlaps the periphery of the recess 21 of the insulating substrate 2. In other words, the side surface of the first periphery 31 and the side surface of the recess 21 are positioned so as to be substantially flush with each other.

[0025] The first periphery 31 of the solder resist 3 overlaps with the periphery of the recess 21 of the insulating substrate 2, thereby ensuring a sufficient width for the solder resist 3. As a result, for example, the thermal influence on the wiring board 1 when mounting the electronic component 5 described below is reduced. Furthermore, the gap between the lower surface of the electronic component 5 and the mounting area of ​​the wiring board 1 (solder resist 3) becomes uniform, and the filling of the sealing resin 6 becomes uniform.

[0026] As shown in FIG. 3 , the second periphery 32 of the solder resist 3 includes a first region 321 connected to the first periphery 31. In plan view, the first region 321 is located closer to the center than the periphery of the insulating substrate 2 other than the recess 21. FIG. 3 is a plan view of region X shown in FIG. 2 . As shown in FIG. 2 , when the insulating substrate 2 has a rectangular shape, the first region 321 of the second periphery 32 is located closer to the center than the first side of the insulating substrate 2. Because the first region 321 is located closer to the center than the periphery of the insulating substrate 2, when filling the sealing resin 6 between the wiring board 1 and the electronic component 5, for example, the overflowing sealing resin 6 is contained on the first surface f1 of the insulating substrate 2 exposed from the solder resist 3.

[0027] A step is formed between the periphery (second periphery 32) of the solder resist 3 and the periphery of the insulating substrate 2. By forming such a step, the sealing resin 6 is less likely to spill out onto the outer circumferential side surface of the wiring board 1, as shown in Fig. 4. Even if the sealing resin 6 flows up to the step portion, as shown in Fig. 5, the sealing resin 6 flows along the step and is less likely to spill out onto the outer circumferential side surface of the wiring board 1. As a result, as shown in Figs. 4 and 5, the optical connector 41 is well connected to the wiring board 1 via the adapter 4. Figs. 4 and 5 are enlarged explanatory views showing the connection portion between the adapter 4 and the optical connector 41 in the mounting structure 10 shown in Fig. 1.

[0028] Furthermore, because the solder resist 3 is relatively fragile, chips or scratches are likely to occur at the periphery. By positioning the second periphery 32 toward the center, the second periphery 32 is less likely to be subjected to impacts that occur during transportation, etc. As a result, chips and scratches are less likely to occur at the second periphery 32 of the solder resist 3. Chips that occur at the periphery of the solder resist 3 become starting points for the sealing resin 6 to flow out onto the outer peripheral side surface of the wiring board 1. Therefore, reducing the occurrence of chips is also advantageous in terms of preventing the sealing resin 6 from flowing out.

[0029] There are no limitations on the distance (third distance L3) between the first region 321 and the edge of the insulating substrate 2 that is closest to the first region 321, as long as the first region 321 is located closer to the center than the edge of the insulating substrate 2. The third distance L3 may be, for example, 50 μm or more and 500 μm or less.

[0030] The electrodes 8 located on the first surface f1 of the insulating substrate 2 include a first electrode 81 located closest to the first periphery 31 and a second electrode 82 located closest to the first region 321 of the second periphery 32. In the wiring substrate 1 according to one embodiment, the distance between the first periphery 31 and the first electrode 81 (first distance L1) may be shorter than the distance between the first region 321 of the second periphery 32 and the second electrode 82 (second distance L2). Specifically, the first distance L1 may be 100 μm or more and 400 μm or less, and the second distance L2 may be 200 μm or more and 600 μm or less. When the first distance L1 is shorter than the second distance L2, the width of the recess 21 is sufficiently secured while maintaining sufficient electrical insulation reliability between the multiple electrodes 8 located along the recess 21. Furthermore, an area where the sealing resin 6 can remain along the outer periphery side of the wiring substrate 1 can be secured, further reducing the risk of the sealing resin 6 flowing out onto the outer periphery side.

[0031] The difference between the first distance L1 and the second distance L2 may be, for example, 100 μm or more. If the difference between the first distance L1 and the second distance L2 is 100 μm or more, the sealing resin 6 is more likely to fill the gap between the electronic component 5 and the wiring board 1 (solder resist 3). As a result, improved electrical insulation reliability between the multiple electrodes 8 can be expected. Furthermore, the risk of the sealing resin 6 flowing out onto the outer peripheral side surface of the wiring board 1 can be further reduced. The difference between the first distance L1 and the second distance L2 may be, for example, 200 μm or less.

[0032] The third distance L3 may be shorter than the first distance L1. By making the third distance L3 shorter than the first distance L1, it becomes easier to sufficiently fill the spaces between the multiple electrodes 8 located along the recess 21 with the sealing resin 6, thereby improving the electrical insulation reliability. Furthermore, by making the third distance L3 shorter than the first distance L1, the exposed portion of the first surface f1 of the insulating substrate 2 is reduced, allowing the wiring substrate 1 to be made smaller.

[0033] The arithmetic mean roughness of each of the first surface f1 of the insulating substrate 2 and the surface of the solder resist 3 is not limited. For example, the arithmetic mean roughness of the first surface f1 of the insulating substrate 2 exposed along the second periphery 32 may be greater than the arithmetic mean roughness of the surface of the solder resist 3. Specifically, the arithmetic mean roughness of the surface of the solder resist 3 may be 200 nm or more and 400 nm or less. The arithmetic mean roughness of the first surface f1 of the insulating substrate 2 exposed along the second periphery 32 may be 500 nm or more and 800 nm or less. The arithmetic mean roughness can be measured, for example, using a laser microscope.

[0034] When the arithmetic mean roughness of the first surface f1 of the insulating substrate 2 exposed along the second periphery 32 is greater than the arithmetic mean roughness of the surface of the solder resist 3, sufficient wettability is ensured on the surface of the solder resist 3. As a result, the sealing resin 6 is more easily filled. Furthermore, the wettability of the first surface f1 of the insulating substrate 2 exposed along the second periphery 32 is improved. Therefore, even if the sealing resin 6 flows onto the exposed first surface f1 of the insulating substrate 2, as shown in FIG. 5 , for example, the sealing resin 6 is more likely to spread onto the exposed first surface f1 along the corner between the end face of the solder resist 3 and the exposed first surface f1. As a result, the sealing resin 6 is less likely to spill onto the outer peripheral side surface of the wiring substrate 1.

[0035] 1, a mounting structure 10 according to an embodiment of the present disclosure includes the wiring board 1 according to the embodiment described above, an adapter 4, an electronic component 5, an optical connector 41, and a sealing resin 6.

[0036] The adapter 4 is a member for connecting the optical connector 41 to the wiring board 1, and is located in the recess 21 of the insulating substrate 2. In a direction along the periphery of the insulating substrate 2, the width L4 of the first region 321 may be longer than the width L5 of the optical connector 41 in a direction along the first region 321. With this configuration, the portion of the optical connector 41 that faces the outer peripheral side surface of the wiring board 1 is contained within the first region 321. Because the first region 321 is located closer to the center of the wiring board 1 than the periphery of the insulating substrate 2, it is possible to reduce the outflow of the sealing resin 6 onto the outer peripheral side surface of the wiring board 1, thereby improving the connectivity between the optical connector 41 and the wiring board 1.

[0037] The electronic components 5 are connected to a plurality of electrodes 8 located on the adapter 4 and the first surface f1 of the insulating substrate 2. Examples of the electronic components 5 include optoelectronic elements and interface elements. The sealing resin 6 is located between the lower surfaces of the electronic components 5 and the solder resist 3. The sealing resin 6 is used to fix the electronic components 5 to the wiring substrate 1. Examples of the sealing resin 6 include epoxy resin, polyimide resin, and urethane resin.

[0038] Although the embodiments of the present disclosure have been described above, the invention according to the present disclosure is not limited to the above-described embodiments, and various modifications and improvements are possible within the scope of the present disclosure as shown in (1) and (7) below.

[0039] (1) A wiring board according to the present disclosure includes an insulating substrate having a first surface and a second surface located opposite the first surface, and a solder resist located on the first surface. The insulating substrate includes at least one recess recessed from the periphery of the insulating substrate toward the center in a plan view, and a plurality of electrodes located on the first surface along the recess. The solder resist has openings that expose the electrodes. The periphery of the solder resist includes a first periphery along the recess and a second periphery along the periphery of the insulating substrate other than the recess. The first periphery overlaps the periphery of the recess, and the second periphery includes a first region connected to the first periphery. In a plan view, the first region is located toward the center relative to the periphery of the insulating substrate.

[0040] Regarding the embodiments of the present disclosure, the following embodiments (2) to (6) and (8) are further disclosed.

[0041] (2) In the wiring board described in (1) above, in a plan view, the insulating substrate has a rectangular shape including a first side, the recess is recessed from the first side toward the center, and the first region of the second periphery is located toward the center from the first side of the insulating substrate in a plan view. (3) In the wiring board described in (1) or (2) above, the arithmetic mean roughness of the first surface of the insulating substrate exposed along the second periphery is greater than the arithmetic mean roughness of the surface of the solder resist. (4) In the wiring board described in any one of (1) to (3) above, the multiple electrodes include a first electrode located closest to the first periphery and a second electrode located closest to the first region of the second periphery, and the first distance between the first periphery and the first electrode is shorter than the second distance between the first region of the second periphery and the second electrode. (5) In the wiring board described in (4) above, the difference between the first distance and the second distance is 100 μm or more. (6) In the wiring board according to (4) or (5) above, a third distance between the first region and the edge of the insulating substrate that is closest to the first region is shorter than the first distance.

[0042] (7) A mounting structure according to the present disclosure includes the wiring board according to any one of (1) to (6) above, an adapter located in the recess, and an electronic component connected to the adapter and to a plurality of electrodes located on the first surface of the insulating substrate, and a sealing resin is located between the underside of the electronic component and the solder resist. (8) In the mounting structure according to (7) above, the adapter is connected to an optical connector on the side opposite to the recess, and the width of the first region in the direction along the periphery of the insulating substrate is longer than the width of a portion of the optical connector facing the first region.

[0043] REFERENCE SIGNS LIST 1 wiring substrate 2 insulating substrate 21 recess 3 solder resist 31 first periphery 32 second periphery 321 first region 4 adapter 41 optical connector 5 electronic component 6 sealing resin 7 solder 8 electrode 81 first electrode 82 second electrode 10 mounting structure f1 first surface f2 second surface

Claims

1. An insulating substrate having a first surface and a second surface located on the opposite side of the first surface, A solder resist located on the first surface, Including, The insulating substrate includes at least one recess that is recessed from the periphery of the insulating substrate toward the center in a plan view, and a plurality of electrodes located on the first surface along the recess, The solder resist has an opening that exposes the electrodes, The periphery of the solder resist includes a first periphery along the recess and a second periphery along the periphery of the insulating substrate other than the recess, The first periphery overlaps the periphery of the recess, The second periphery includes a first region connected to the first periphery, In a plan view, the first region is located in the central direction rather than the periphery of the insulating substrate, A wiring board.

2. In a plan view, the insulating substrate has a rectangular shape including a first side, and the recess is recessed from the first side toward the center, In a plan view, the first region of the second periphery is located in the central direction rather than the first side of the insulating substrate. The wiring board according to claim 1.

3. The arithmetic mean roughness of the first surface of the insulating substrate exposed along the second periphery is larger than the arithmetic mean roughness of the surface of the solder resist. The wiring board according to claim 1.

4. The plurality of electrodes include a first electrode located closest to the first periphery and a second electrode located closest to the first region of the second periphery, A first distance between the first periphery and the first electrode is shorter than a second distance between the first region of the second periphery and the second electrode. The wiring board according to claim 1.

5. A difference between the first distance and the second distance is 100 μm or more. The wiring board according to claim 4.

6. A third distance between the first region and the periphery of the insulating substrate located closest to the first region is shorter than the first distance. The wiring board according to claim 4.

7. The wiring board according to any one of claims 1 to 6, An adapter located in the recess, An electronic component connected to the adapter and the plurality of electrodes located on the first surface of the insulating substrate, Including, A sealing resin is located between the lower surface of the electronic component and the solder resist, A mounting structure.

8. The adapter is connected to an optical connector on the side opposite to the recess, The mounting structure according to claim 7, wherein in a direction along the periphery of the insulating substrate, the width of the first region is longer than the width of the portion of the optical connector facing the first region.