Circuit board, and method for manufacturing circuit board

Abstract

This circuit board comprises a fluorine resin layer, a to-be-adhered layer, and an adhesive layer adhering the fluorine resin layer with the to-be-adhered layer. The fluorine resin layer includes polytetrafluoroethylene and a first inorganic filler. The content of the first inorganic filler in the fluorine resin layer is 50 vol% to 66 vol%. The adhesive layer includes a resin and a second inorganic filler. The content of the fluorine resin in the resin is 5 mass% or less. The content of the second inorganic filler in the adhesive layer is 29 vol% to 47 vol%. A through-hole penetrating through the fluorine resin layer and the adhesive layer is formed.

Description

Circuit board and method for manufacturing the circuit board

[0001] This application claims priority from Japanese Patent Application No. 2022-162209, filed on October 7, 2022, and incorporates by reference all of the contents of that application.

[0002] In order to improve the high frequency characteristics of printed wiring boards, the use of a fluororesin layer containing a fluororesin such as polytetrafluoroethylene and an inorganic filler such as silica as a dielectric layer has been investigated (Patent Document 1).

[0003] A bonding sheet is used to laminate a substrate (circuit board) on which a circuit is formed by processing the metal layer of the substrate, with another substrate or another circuit board. For example, the circuit board, bonding sheet, and other substrate are laminated in this order, and then heated until the bonding sheet softens. Once the bonding sheet is softened, it is pressurized and deformed. The circuit board and other substrate are bonded together while the bonding sheet fills the gaps between the circuits (Patent Document 2).

[0004] International Publication No. 2021 / 235276 Japanese Patent Application Laid-Open No. 2016-27131

[0005] The circuit board of the present disclosure comprises: a fluororesin layer; an adherend layer; and an adhesive layer that adheres the fluororesin layer and the adherend layer; the fluororesin layer contains polytetrafluoroethylene and a first inorganic filler, and the fluororesin layer has a first inorganic filler content of 50% by volume or more and 66% by volume or less; the adhesive layer contains a resin and a second inorganic filler, and the fluororesin content of the resin is 5% by mass or less, and the adhesive layer has a second inorganic filler content of 29% by volume or more and 47% by volume or less; and a through hole is formed through the fluororesin layer and the adhesive layer.

[0006] The method for manufacturing a circuit board according to the present disclosure is the method for manufacturing the circuit board described above, further comprising the step of maintaining a laminate in which the fluororesin layer, the adhesive layer, and the adherend layer are laminated in this order at a temperature of 180°C or less to soften the adhesive layer, thereby bonding the fluororesin layer and the adherend layer together.

[0007] The method for manufacturing a circuit board according to the present disclosure includes the steps of: preparing a fluororesin laminate including a fluororesin layer including a first main surface and a second main surface opposite the first main surface, and a second metal layer made of metal and provided on the second main surface; preparing a first resin laminate including a first resin layer including a third main surface and a fourth main surface opposite the third main surface, and a first metal layer provided on the third main surface; preparing an adhesive layer; laminating the fluororesin laminate, the adhesive layer, and the first resin laminate in this order such that the first main surface is in contact with the adhesive layer, and maintaining the adhesive layer at a temperature of 180°C or less to soften the adhesive layer, thereby bonding the fluororesin laminate and the first resin laminate to form a first laminate; removing at least a portion of the fluororesin layer and at least a portion of the adhesive layer to form a through hole penetrating the fluororesin layer and the adhesive layer; and forming a connection portion on an inner wall surface of the fluororesin layer that defines a portion of the through hole and on an inner wall surface of the adhesive layer that defines a portion of the through hole, wherein the fluororesin layer contains polytetrafluoroethylene and a first inorganic filler, and the content of the first inorganic filler in the fluororesin layer is 50% by volume or more and 66% by volume or less, the adhesive layer contains a resin and a second inorganic filler, and the fluororesin content of the resin is 5% by mass or less, and the content of the second inorganic filler in the adhesive layer is 29% by volume or more and 47% by volume or less.

[0008] FIG. 1 is a schematic cross-sectional view of a circuit board according to embodiment 1. FIG. 2A is a diagram illustrating a method for manufacturing a circuit board according to embodiment 2. FIG. 2B is a diagram illustrating a method for manufacturing a circuit board according to embodiment 2. FIG. 2C is a diagram illustrating a method for manufacturing a circuit board according to embodiment 2. FIG. 3 is a schematic cross-sectional view of a circuit board according to embodiment 3. FIG. 4A is a diagram illustrating a method for manufacturing a circuit board according to embodiment 3. FIG. 4B is a diagram illustrating a method for manufacturing a circuit board according to embodiment 3. FIG. 4C is a diagram illustrating a method for manufacturing a circuit board according to embodiment 3. FIG. 5 is a schematic cross-sectional view of a circuit board according to embodiment 4. FIG. 6 is a schematic cross-sectional view of a circuit board according to embodiment 5. FIG. 7A is a diagram illustrating a method for manufacturing a circuit board according to embodiment 5. FIG. 7B is a diagram illustrating a method for manufacturing a circuit board according to embodiment 5. FIG. 8 is a diagram illustrating a gouge. FIG. 9 is a diagram illustrating a method for measuring the length of the gouge.

[0009] [Problem to be Solved by the Present Disclosure] In recent years, the amount of information communication has been increasing. For example, in devices such as IC cards and mobile phone terminals, communication in high frequency ranges such as microwaves and millimeter waves has become popular. For this reason, there is a demand for printed wiring boards with excellent high frequency characteristics, for example, printed wiring boards with low transmission loss in high frequency ranges. As a substrate for manufacturing such high frequency printed wiring boards, a laminate in which a metal layer (e.g., copper foil) is laminated on a dielectric layer is generally used.

[0010] Bonding sheets with low softening temperatures can be bonded using a general-purpose press and are highly productive. However, the inventors discovered a problem: laminates fabricated using bonding sheets with low softening temperatures are prone to pitting when through-holes for via holes are formed by laser processing. The pitting problem will be explained with reference to FIG. 8 . A circuit board 1 includes an adhesive layer 12 (corresponding to a bonding sheet) primarily composed of polypropylene. When a through-hole extending from the fluororesin layer 10 to the first metal layer 13 through the fluororesin layer 10 and the adhesive layer 12 is formed by laser processing, a pit 25 occurs near the interface between the fluororesin layer 10 and the adhesive layer 12. The inner wall surfaces of the fluororesin layer 10 and the adhesive layer 12 are plated to form via holes. However, the pit 25 is difficult to plate. This results in insufficient plating in the via holes, which can easily reduce the reliability of the circuit board.

[0011] The present disclosure aims to provide a circuit board in which a fluororesin layer and an adherend layer are bonded by low-temperature pressing, and in which, when a through hole is formed through the fluororesin layer and the adhesive layer, the occurrence of gouging near the interface between the fluororesin layer and the adhesive layer is suppressed.

[0012] [Advantages of the Present Disclosure] According to the present disclosure, it is possible to provide a circuit board in which a fluororesin layer and an adherend layer are bonded by low-temperature pressing. Furthermore, the present disclosure can provide a circuit board in which, when a through hole is formed penetrating the fluororesin layer and the adhesive layer, the occurrence of gouging near the interface between the fluororesin layer and the adhesive layer is suppressed.

[0013] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be described. (1) A circuit board of the present disclosure is a circuit board comprising: a fluororesin layer; an adherend layer; and an adhesive layer that adheres the fluororesin layer to the adherend layer, wherein the fluororesin layer contains polytetrafluoroethylene and a first inorganic filler, the fluororesin layer has a first inorganic filler content of 50% by volume or more and 66% by volume or less, the adhesive layer contains a resin and a second inorganic filler, the resin has a fluororesin content of 5% by mass or less, and the adhesive layer has a second inorganic filler content of 29% by volume or more and 47% by volume or less, and through holes are formed through the fluororesin layer and the adhesive layer.

[0014] According to the present disclosure, it is possible to provide a circuit board in which a fluororesin layer and an adherend layer are bonded by pressing at low temperatures. Furthermore, according to the present disclosure, it is possible to provide a circuit board in which the occurrence of gouging near the interface between the fluororesin layer and the adhesive layer is suppressed even when a through hole penetrating the fluororesin layer and the adhesive layer is formed. In the present disclosure, "low temperature" means a temperature of 180°C or lower.

[0015] (2) In the above (1), the first inorganic filler may contain silica. This reduces the thermal expansion coefficient of the fluororesin layer. Here, the thermal expansion coefficient of the fluororesin layer is the linear expansion coefficient in the thickness direction of the fluororesin layer (the thermal expansion coefficient along the axis perpendicular to the layer surface of the fluororesin layer).

[0016] (3) In the above (1) or (2), the second inorganic filler may contain silica, which can further suppress the occurrence of cavities.

[0017] (4) In any one of the above (1) to (3), the second inorganic filler may contain boron nitride, which can further suppress the occurrence of cavities.

[0018] (5) In any one of the above (1) to (4), at least one of an inner wall surface of the fluororesin layer that defines a portion of the through hole and an inner wall surface of the adhesive layer that defines a portion of the through hole may have a recess, and the recess may have a length of less than 25 μm. This improves the reliability of the circuit board.

[0019] (6) In any of the above (1) to (5), the ratio A / B of the adhesive layer's elastic modulus A at 160°C to its elastic modulus B at 20°C may be 0.08 or less. This improves the adhesion between the fluororesin layer and the metal layer at low temperatures.

[0020] (7) In any one of the above (1) to (6), the resin may contain a polyolefin or a polystyrene-based elastomer, which improves the adhesion between the fluororesin layer and the metal layer at low temperatures.

[0021] (8) In any of the above (1) to (7), the adherend layer may include a first metal layer and a first resin layer, and the first metal layer may be provided on a surface of the first resin layer facing the fluororesin layer.

[0022] This allows the formation of circuits in the first metal layer.

[0023] (9) In any one of the above (1) to (7), the adherend layer may include a first metal layer and a first resin layer, and the first resin layer may be provided on a surface of the first metal layer facing the fluororesin layer. This allows a circuit to be formed on the first metal layer.

[0024] (10) In the above (8) or (9), the fluororesin layer may include a first main surface facing the adhesive layer and a second main surface opposite the first main surface, and the circuit board may further include a second metal layer provided on the second main surface.

[0025] This allows the circuit to be formed in the second metal layer.

[0026] (11) In the above (10), a connection portion may be further provided that electrically connects the first metal layer and the second metal layer, and the connection portion may be formed in the through hole.

[0027] This allows the first metal layer and the second metal layer to be electrically connected.

[0028] (12) In the above (10) or (11), the first metal layer may be formed in a region that overlaps with the through hole when viewed from a direction perpendicular to the second main surface, thereby enabling the shape of the connection portion to be defined with high precision.

[0029] (13) In the above (10) or (11), the second metal layer may be formed in a region that overlaps with the through hole when viewed from a direction perpendicular to the first main surface, thereby enabling the shape of the connection portion to be defined with high precision.

[0030] (14) The method for manufacturing a circuit board according to the present disclosure is a method for manufacturing a circuit board according to any one of (1) to (13) above, comprising a step of maintaining a laminate in which the fluororesin layer, the adhesive layer, and the adherend layer are laminated in this order at a temperature of 180°C or less to soften the adhesive layer, thereby bonding the fluororesin layer and the adherend layer together.

[0031] According to the present disclosure, it is possible to provide a circuit board in which a fluororesin layer and an adherend layer are bonded by pressing at low temperatures. Furthermore, according to the present disclosure, it is possible to provide a circuit board in which the occurrence of gouging near the interface between the fluororesin layer and the adhesive layer is suppressed even when a through hole is formed through the fluororesin layer and the adhesive layer.

[0032] (15) A method for manufacturing a circuit board according to the present disclosure includes the steps of: preparing a fluororesin laminate including a fluororesin layer having a first main surface and a second main surface opposite to the first main surface, and a second metal layer provided on the second main surface; preparing a first resin laminate including a first resin layer having a third main surface and a fourth main surface opposite to the third main surface, and a first metal layer provided on the third main surface; preparing an adhesive layer; laminating the fluororesin laminate, the adhesive layer, and the first resin laminate in this order such that the first main surface is in contact with the adhesive layer, and maintaining the adhesive layer at a temperature of 180°C or less to soften the adhesive layer, thereby bonding the fluororesin laminate and the first resin laminate to form a first laminate; removing at least a portion of the fluororesin layer and at least a portion of the adhesive layer to form a through hole penetrating the fluororesin layer and the adhesive layer; and forming a connection portion on an inner wall surface of the fluororesin layer that defines a portion of the through hole and on an inner wall surface of the adhesive layer that defines a portion of the through hole, wherein the fluororesin layer contains polytetrafluoroethylene and a first inorganic filler, and the content of the first inorganic filler in the fluororesin layer is 50% by volume or more and 66% by volume or less, the adhesive layer contains a resin and a second inorganic filler, and the fluororesin content of the resin is 5% by mass or less, and the content of the second inorganic filler in the adhesive layer is 29% by volume or more and 47% by volume or less.

[0033] According to the present disclosure, it is possible to provide a circuit board in which a fluororesin layer and an adherend layer are bonded by pressing at low temperatures. Furthermore, according to the present disclosure, it is possible to provide a circuit board in which the occurrence of gouging near the interface between the fluororesin layer and the adhesive layer is suppressed even when a through hole is formed through the fluororesin layer and the adhesive layer.

[0034] (16) In the above (15), the step of preparing the first resin laminate may further include a step of forming a first circuit in the first resin laminate by etching at least a part of the first metal layer, thereby making it possible to embed the first circuit in the adhesive layer.

[0035] (17) In the above (15) or (16), the step of preparing the fluororesin laminate may further include a step of forming a second circuit in the fluororesin laminate by etching at least a part of the second metal layer, whereby the formation of the second circuit increases the wiring density of the circuit board.

[0036] (18) In the above (15) or (16), the step of forming the first laminate may further include the step of forming a second circuit in the fluororesin laminate by etching at least a part of the second metal layer, thereby increasing the wiring density of the circuit board by forming the second circuit.

[0037] (19) In any one of the above (15) to (18), the through holes may be formed by laser processing. This allows the through holes to be formed with high precision.

[0038] (20) In any one of the above (15) to (19), at least one of the inner wall surface of the fluororesin layer and the inner wall surface of the adhesive layer may have a recess, and the length of the recess may be less than 25 μm. This improves the reliability of the circuit board.

[0039] [Details of the embodiment of the present disclosure] The circuit board and its manufacturing method of the present disclosure will be described below with reference to the drawings. In the drawings of the present disclosure, the same reference numerals represent the same or corresponding parts. Dimensional relationships such as length, width, thickness, and depth have been changed as appropriate for clarity and simplification of the drawings, and do not necessarily represent actual dimensional relationships.

[0040] In this disclosure, the expression "from A to B" (A and B are numerical values) means a range from an upper limit to a lower limit (not less than A and not more than B). When no unit is specified for A and only a unit is specified for B, the unit of A and the unit of B are the same.

[0041] In the present disclosure, when a compound is represented by a chemical formula without limiting the atomic ratio, the compound includes compounds with any conventionally known atomic ratio, and is not limited to compounds within a stoichiometric range.

[0042] In the present disclosure, when the lower limit and the upper limit of a numerical range each are one or more numerical values, a combination of any one numerical value stated as the lower limit and any one numerical value stated as the upper limit is considered to be disclosed. For example, when a1, b1, and c1 are stated as the lower limit and a2, b2, and c2 are stated as the upper limit, a1 to a2, a1 to b2, a1 to c2, b1 to a2, b1 to b2, b1 to c2, c1 to a2, c1 to b2, and c1 to c2 are considered to be disclosed.

[0043] [Embodiment 1: Circuit Board (1)] A circuit board according to one embodiment of the present disclosure (hereinafter also referred to as "Embodiment 1") and a manufacturing method thereof will be described with reference to FIG. 1 . The circuit board 1 of Embodiment 1 includes a fluororesin layer 10, an adherend layer 17, and an adhesive layer 12 that bonds the fluororesin layer 10 and the adherend layer 17. The fluororesin layer 10 contains polytetrafluoroethylene and a first inorganic filler. The fluororesin layer 10 contains a first inorganic filler content of 50% by volume or more and 66% by volume or less. The adhesive layer 12 contains a resin and a second inorganic filler. The fluororesin content of the resin is 5% by mass or less. The adhesive layer 12 contains a second inorganic filler content of 29% by volume or more and 47% by volume or less. The circuit board 1 has through holes formed therein that penetrate the fluororesin layer 10 and the adhesive layer 12.

[0044] The circuit board 1 of the first embodiment is a circuit board in which the fluororesin layer 10 and the adherend layer 17 are bonded by the adhesive layer 12 by low-temperature pressing. In the circuit board 1, even when a through-hole is formed penetrating the fluororesin layer 10 and the adhesive layer 12, the occurrence of gouging near the interface between the fluororesin layer 10 and the adhesive layer 12 is suppressed. Therefore, the circuit board 1 of the first embodiment can have excellent reliability.

[0045] In the present disclosure, the circuit board is not limited to a board in which a circuit is formed by processing a metal layer of a substrate, but also includes a laminate formed by bonding a substrate or another circuit board to a circuit board using a bonding sheet, and a laminate provided with connection holes such as via holes.

[0046] <Structure> As shown in FIG. 1 , the circuit board 1 of embodiment 1 includes a fluororesin layer 10, an adherend layer 17, and an adhesive layer 12 that bonds the fluororesin layer 10 and the adherend layer 17. The fluororesin layer 10 includes a first main surface 10a facing the adhesive layer 12 and a second main surface 10b opposite the first main surface 10a. The adherend layer 17 includes a first resin layer 16 and a first metal layer 13 provided on a portion of the surface of the first resin layer 16. The first resin layer 16 may be a laminate including, in addition to the resin layer, a metal layer, a glass cloth layer, a nonwoven fabric layer, or the like. The resin layer may contain an inorganic filler. As shown in FIG. 1 , the first main surface 10a may be adjacent to the adhesive layer 12.

[0047] The first A surface 13a of the first metal layer 13 is the surface of the first metal layer 13 opposite to the surface that is in contact with the first resin layer 16. The first B surface 12a of the adhesive layer 12 is the surface of the adhesive layer 12 opposite to the surface that is in contact with the fluororesin layer 10. The first A surface 13a is in contact with the first B surface 12a. At least a portion of the first metal layer 13 is embedded in the adhesive layer 12. The third main surface 16a of the first resin layer 16 is the surface facing the first metal layer 13. The region of the third main surface 16a where the first metal layer 13 is not provided is in contact with the adhesive layer 12.

[0048] The circuit board 1 further includes a second metal layer 11 provided on the second main surface 10b of the fluororesin layer 10. The second metal layer 11 is made of metal. The fluororesin layer 10 and the second metal layer 11 may be in contact with each other. The fluororesin layer 10 and the second metal layer 11 may be bonded to each other by disposing a thin adhesive film (not shown) between them.

[0049] The circuit board 1 further includes a connection portion 14. The connection portion 14 is made of metal and electrically connects the first metal layer 13 and the second metal layer 11. A through hole is formed in the circuit board 1, penetrating the fluororesin layer 10 and the adhesive layer 12. That is, the fluororesin layer 10 and the adhesive layer 12 have a through hole penetrating the fluororesin layer 10 and the adhesive layer 12. The connection portion 14 is formed in the through hole. More specifically, the connection portion 14 is formed on the inner wall surface of the fluororesin layer 10 that defines a portion of the through hole and on the inner wall surface that defines a portion of the adhesive layer 12. The first metal layer 13 defines the bottom surface of the through hole, and the connection portion 14 is also formed on the bottom surface.

[0050] When the circuit board 1 is viewed from a direction perpendicular to the second main surface 10b, the second metal layer 11 is not formed in the region overlapping the through hole. The second metal layer 11 has an opening that leads to the through hole. When the circuit board 1 is viewed from a direction perpendicular to the second main surface 10b, the first metal layer 13 is formed in the region overlapping the through hole. The first metal layer 13 is a via bottom that fills the through hole.

[0051] The cross-sectional area of ​​the through hole increases continuously from the first metal layer 13 to the second metal layer 11. In the present disclosure, the cross-sectional area of ​​the through hole is the cross-sectional area when viewed in a cross section perpendicular to the direction from the first metal layer 13 to the second metal layer 11.

[0052] <Fluororesin Layer> In the first embodiment, the fluororesin layer contains polytetrafluoroethylene and a first inorganic filler. Polytetrafluoroethylene has a small dielectric constant and a small dielectric loss tangent. Therefore, a circuit board using the fluororesin layer as an insulating layer has good high-frequency characteristics.

[0053] In embodiment 1, the volumetric content of the first inorganic filler in the fluororesin layer is 50 vol% or more and 66 vol% or less. This results in a small thermal expansion coefficient of the fluororesin layer, resulting in excellent dimensional stability. Furthermore, the electrical connection reliability of the connection portion provided on the inner wall surface of the fluororesin layer is excellent. From the viewpoint of reducing the thermal expansion coefficient, the lower limit of the content of the first inorganic filler in the fluororesin layer is 50 vol%, or may be 60 vol%, or may be 63 vol%. If the content of the first inorganic filler in the fluororesin layer is 50 vol% or more, the thermal expansion coefficient of the fluororesin layer is reduced; if the content is 60 vol% or more, the thermal expansion coefficient is further reduced; and if the content is 63 vol% or more, the thermal expansion coefficient is further reduced. The upper limit of the content of the first inorganic filler in the fluororesin layer is 66 vol% or more, or may be 65 vol%. If the content of the first inorganic filler in the fluororesin layer is 66 vol% or less, the electrical connection stability of the connection portion is excellent; and if the content is 65 vol% or less, the electrical connection stability of the connection portion is even more excellent. The content of the first inorganic filler in the fluororesin layer may be 60% by volume or more and 66% by volume or less, or 63% by volume or more and 65% by volume or less.

[0054] In the present disclosure, the volumetric content of the first inorganic filler in the fluororesin layer is measured as follows: The circuit board is cut by argon ion polishing to expose the cross section of the fluororesin layer. The cross section is a plane perpendicular or parallel to the lamination surface of the circuit board. If the cross section is a plane parallel to the lamination surface of the circuit board, the cross section tends to have a large area. If the cross section is a plane perpendicular to the lamination surface, the cross section is easily formed. The cross section of the fluororesin layer is observed at 10,000 magnification using a high-resolution scanning electron microscope (SEM) (SU8020 manufactured by Hitachi High-Tech Corporation) at a low acceleration voltage to obtain an SEM image. A rectangular measurement area of ​​8 μm × 12 μm is set in the SEM image. The area-based content (area percentage) of the first inorganic filler in this measurement area is measured. The area percentage measurement is performed by extracting the first inorganic filler portion using multi-value image analysis processing software. The area percentage of the first inorganic filler is measured for 30 different measurement areas, and the average area percentage is calculated. Next, 10 new measurement areas whose area percentages have not yet been measured are added to the measurement areas whose area percentages have already been measured, resulting in a total of 40 measurement areas, and the average area percentage of the first inorganic filler is calculated. If the difference between the average area percentage before the 10 measurement areas are added and the average area percentage of the measurement areas after the 10 measurement areas are added is within 1%, the average value of the area percentages of the measurement areas after the addition is taken as the volumetric content of the first inorganic filler in the fluororesin layer. If the difference is greater than 1%, 10 measurement areas whose area percentages have not yet been measured are added, and the average value of the area percentages of the measurement areas after the addition is calculated. This process is repeated until the difference before and after the addition of the measurement area is within 1%. When the difference before and after the addition of the measurement area is within 1%, the average value of the area percentages is taken as the volumetric content of the first inorganic filler in the fluororesin layer.

[0055] In embodiment 1, the mass-based content of the first inorganic filler in the fluororesin layer may be 50% by mass or more and 67% by mass or less. This reduces the thermal expansion coefficient of the fluororesin layer, resulting in excellent dimensional stability. Furthermore, the electrical connection reliability of the connection portion provided on the inner wall surface of the fluororesin layer is excellent. From the viewpoint of reducing the thermal expansion coefficient, the lower limit of the content of the first inorganic filler in the fluororesin layer may be 50% by mass, 60% by mass, or 63% by mass. If the content of the first inorganic filler in the fluororesin layer is 50% by mass or more, the thermal expansion coefficient of the fluororesin layer is reduced; if the content is 60% by mass or more, the thermal expansion coefficient is further reduced; and if the content is 63% by mass or more, the thermal expansion coefficient is further reduced. The upper limit of the content of the first inorganic filler in the fluororesin layer may be 67% by mass or more or 66% by mass. If the content of the first inorganic filler in the fluororesin layer is 67% by mass or less, the electrical connection stability of the connection portion is excellent, and if the content is 67% by mass or less, the electrical connection stability of the connection portion is even more excellent. The content of the first inorganic filler in the fluororesin layer may be 50% by mass or more and 67% by mass or less, 60% by mass or more and 66% by mass or less, or further 63% by mass or more and 65% by mass or less.

[0056] In the present disclosure, the mass-based content of the first inorganic filler in the fluororesin layer is measured as follows: The fluororesin layer is heated in a nitrogen atmosphere using a thermogravimetric differential scanning calorimeter (TG-DSC), and the temperature of the fluororesin layer is increased from 30°C to 700°C at a rate of 20°C / min. The initial weight of the fluororesin layer and the recovered weight of the recovered material after heating are measured. The ratio of the recovered weight to the initial weight is defined as the mass-based content of the first inorganic filler in the fluororesin layer.

[0057] The first inorganic filler may be a nonmetallic inorganic filler and may contain silica. Silica is inexpensive and easily available. The dielectric loss tangent of silica is smaller than that of many other inorganic fillers. Because the dielectric constant of silica is close to that of fluororesin, even if the first inorganic filler contains a large amount of silica, the dielectric constant of the first inorganic filler does not change significantly. From the viewpoint of reducing a decrease in the dielectric loss tangent of the fluororesin layer, the silica content of the first inorganic filler may be 80% by mass or more, 90% by mass or more, or 92% by mass or more. The upper limit of the silica content of the first inorganic filler may be 100% by mass. From the viewpoint of suppressing a decrease in the dielectric loss tangent of the fluororesin layer, the silica content of the first inorganic filler may be 80% by mass or more and 100% by mass or less, 90% by mass or more and 100% by mass or less, or 92% by mass or more and 100% by mass or less.

[0058] In the present disclosure, the method for measuring the mass-based silica content of the first inorganic filler in the fluororesin layer is as follows. First, the recovered weight of the recovered material obtained by the above-described method for measuring the mass-based silica content of the first inorganic filler in the fluororesin layer is measured. Using the recovered material, the silicon (Si) content in the recovered material is measured by high-frequency inductively coupled plasma (ICP) analysis. When silica is SiO ２ The silica content in the recovered material is calculated from the silicon content, assuming that the composition is as follows: This content is the silica content by mass of the first inorganic filler in the fluororesin layer.

[0059] The silica in the first inorganic filler may be a naturally occurring product or a synthetic product. The silica in the first inorganic filler may be crystalline or amorphous. The silica in the first inorganic filler may be silica produced by a dry process or silica produced by a wet process. From the viewpoints of availability and quality, the silica in the first inorganic filler may be synthetic silica produced by a dry process.

[0060] The silica in the first inorganic filler may contain spherical silica. This improves processability, such as drilling, during the manufacturing process of the circuit board. The content of spherical silica in the silica may be 80% by mass or more and 100% by mass or less, 90% by mass or more and 100% by mass or less, or 95% by mass or more and 100% by mass or less. If the content of spherical silica in the silica is 80% by mass or more and 100% by mass or less, the processability of the circuit board will be good, if it is 90% by mass or more and 100% by mass or less, the processability of the circuit board will be even better, and if it is 95% by mass or more and 100% by mass or less, the processability of the circuit board will be even better. In the present disclosure, spherical silica refers to silica having a sphericity of 0.80 or more.

[0061] The average particle size of the spherical silica may be 0.2 μm or more and 7.0 μm or less. This provides a fluororesin layer with a large elongation at break, excellent mechanical strength, and excellent processability, such as cutting and perforation. From the viewpoint of mechanical strength, such as elongation at break, the lower limit of the average particle size of the spherical silica may be 0.2 μm, 0.5 μm, or 1.0 μm. When the average particle size of the spherical silica is 0.2 μm or more, the mechanical strength of the fluororesin layer is excellent; when it is 0.5 μm or more, the mechanical strength of the fluororesin layer is even better; and when it is 1.0 μm or more, the mechanical strength of the fluororesin layer is even better. From the viewpoint of processability, such as cutting and perforation, the upper limit of the average particle size of the spherical silica may be 7.0 μm, 5.0 μm, or 3.0 μm. When the average particle size of the spherical silica is 7.0 μm or less, the processability of the fluororesin layer is excellent; when it is 5.0 μm or less, the processability of the fluororesin layer is even better; and when it is 3.0 μm or less, the processability of the fluororesin layer is even better. The average particle size of the spherical silica may be 0.2 μm or more and 7.0 μm or less, 0.5 μm or more and 5.0 μm or less, or 1.0 μm or more and 3.0 μm or less.

[0062] In the present disclosure, the average particle size of spherical silica is the average particle size of primary particles. The average particle size is expressed as the mode diameter of the volumetric particle size distribution. In the present disclosure, the average particle size of spherical silica in the fluororesin layer is measured as follows. Using a thermogravimetric differential scanning calorimeter (TG-DSC), the fluororesin layer is heated under a nitrogen atmosphere, and the temperature of the fluororesin layer is increased from 30°C to 700°C at a rate of 20°C / min to obtain a recovered material. The recovered material contains silica. The recovered material is observed using an SEM. 100 silica particles are randomly selected, their particle sizes are measured to determine the particle size distribution, and the average particle size is calculated.

[0063] The first inorganic filler may contain titanium oxide. Since titanium oxide has a large dielectric constant, the dielectric constant of the fluororesin layer can be adjusted by adding a small amount of titanium oxide to the first inorganic filler. The titanium oxide content of the first inorganic filler may be 1% by mass or more, or 2% by mass or more. The upper limit of the titanium oxide content of the first inorganic filler may be 20% by mass or 10% by mass. The titanium oxide content of the first inorganic filler may be 1% by mass or more and 20% by mass or less, or 2% by mass or more and 10% by mass or less.

[0064] The method for measuring the mass-based content of titanium oxide in the first inorganic filler in the fluororesin layer is as follows. First, the recovered weight of the recovered material obtained by the method for measuring the mass-based content of the first inorganic filler in the fluororesin layer described above is measured. The recovered material is used to measure the titanium (Ti) content in the recovered material by ICP analysis. When titanium oxide is TiO ２ The titanium oxide content in the recovered material is calculated from the titanium content, assuming that the composition is as follows: This content is the titanium oxide content of the first inorganic filler on a mass basis.

[0065] The first inorganic filler may contain both silica and titanium oxide, which improves the temperature stability of the dielectric constant because the dielectric constant of titanium oxide has temperature change characteristics opposite to those of silica.

[0066] The first inorganic filler may contain a non-metallic inorganic filler other than silica and titanium oxide (hereinafter also referred to as "other inorganic filler") as long as the effects of the present disclosure are not impaired. Generally, since the thermal expansion coefficient of inorganic fillers is small, when the first inorganic filler contains an inorganic filler other than silica and titanium oxide, the content of silica or titanium oxide can be reduced depending on the content of the other inorganic filler. Examples of other inorganic fillers include aluminum oxide, magnesium oxide, calcium oxide, talc, barium sulfate, boron nitride, zinc oxide, potassium titanate, glass, and mica. One or more of these inorganic fillers may be used.

[0067] The fluororesin layer may be composed of polytetrafluoroethylene, a first inorganic filler, and inevitable impurities. The fluororesin layer may contain a resin other than polytetrafluoroethylene (another fluororesin). That is, the fluororesin layer may be composed of polytetrafluoroethylene, a first inorganic filler, another fluororesin, and inevitable impurities. In this case, the upper limit of the content of the other fluororesin may be 10% by mass or 5% by mass.

[0068] The fluororesin layer may contain components other than polytetrafluoroethylene and the first inorganic filler, provided that the effects of the present disclosure are not impaired. The content of polytetrafluoroethylene, etc. is specified relative to the total of polytetrafluoroethylene, the first inorganic filler, other fluororesins, inevitable impurities, and components that may be contained in the fluororesin layer, provided that the effects of the present disclosure are not impaired, being 100%.

[0069] The fluororesin layer does not have to contain glass cloth. A fluororesin layer that does not contain glass cloth is less likely to cause irregularities on the inner wall surface, and provides excellent electrical connection reliability when a connection portion is formed on the inner wall surface.

[0070] The lower limit of the average thickness of the fluororesin layer may be 20 μm, 40 μm, or 60 μm. If the average thickness is less than 20 μm, the mechanical strength may be insufficient. Furthermore, dimensional errors may have a significant effect on the high-frequency characteristics of the circuit board, which may make circuit design and manufacturing of circuit components difficult. The upper limit of the average thickness of the fluororesin layer may be 500 μm, 300 μm, or 150 μm. If the average thickness exceeds 500 μm, the circuit board may become too thick. Furthermore, if flexibility is required for the circuit board, the flexibility may be insufficient. The average thickness of the fluororesin layer may be 20 μm or more and 500 μm or less, 40 μm or more and 300 μm or less, or 60 μm or more and 150 μm or less.

[0071] In this disclosure, "average thickness" refers to the distance between the mean line of the interface close to the front surface of the circuit board and the mean line of the interface close to the back surface of the circuit board in a cross section cut in the thickness direction of the object. The "mean line" is an imaginary line drawn along the interface such that the total area of ​​the peaks (total area above the imaginary line) and the total area of ​​the valleys (total area below the imaginary line) defined by the interface and this imaginary line are equal. The average thickness of each layer described below is also defined in the same way.

[0072] Area is 1m ２ In the fluororesin layer, the upper limit of the difference between the maximum and minimum thicknesses of the fluororesin layer (maximum minus minimum) may be 10 μm, 5 μm, or 2 μm. If the difference is 10 μm or less, 5 μm or less, or 2 μm or less, circuit design and manufacturing of circuit components become easier. The maximum and minimum thicknesses of the fluororesin layer are measured using an outside micrometer MDH-25MB manufactured by Mitutoyo Corporation, with the terminal surface of the measurement terminal considered to be "flat."

[0073] <Adhesive Layer> To reduce the transmission loss of the substrate, it is conceivable to use a fluororesin for the adhesive layer, just like the dielectric layer of the substrate. However, because fluororesin has a high softening temperature, a press capable of pressing at high temperatures is required. In addition, the time required for heating and cooling reduces productivity. Furthermore, when fluororesin is cooled to room temperature and changes from a softened state to a hardened state, it experiences significant thermal shrinkage and has poor dimensional stability. For this reason, there is a demand for an adhesive layer that is primarily made of a resin with a small dielectric dissipation factor and can bond at low temperatures.

[0074] In embodiment 1, the adhesive layer contains a resin and a second inorganic filler. The circuit board of embodiment 1 includes a laminate in which the adhesive layer and the above-mentioned fluororesin layer are bonded together in contact with each other. This circuit board suppresses the occurrence of gouging near the interface between the fluororesin layer and the adhesive layer, even when a through-hole penetrating the fluororesin layer and the adhesive layer is formed. The adhesive layer also has excellent adhesive strength to both the fluororesin layer and the adherend layer. Therefore, the reliability of the circuit board of embodiment 1 is improved. The fluororesin content of the resin of the adhesive layer is 5 mass% or less. The resin of the adhesive layer has a reduced content of fluororesin, which has a high softening temperature. Therefore, this adhesive layer can bond the fluororesin layer and the adherend layer at low temperatures.

[0075] The resin may contain a polyolefin or polystyrene elastomer, which has a small dielectric loss tangent, thereby reducing transmission loss in the circuit, and a low softening temperature, allowing bonding at temperatures of 180°C or less.

[0076] The polyolefin may be, for example, polyethylene or polypropylene. The polyolefin may be an acid-modified polyolefin. This is because the acid-modified polyolefin has strong adhesive strength to the fluororesin layer and the metal layer. The acid-modified polyolefin is a polyolefin containing a carboxyl group.

[0077] The lower limit of the polyolefin content of the resin may be 70 mass%, 80 mass%, or 90 mass% from the viewpoint of lowering the softening temperature of the adhesive layer and obtaining good mechanical strength. The upper limit of the polyolefin content of the resin may be 100 mass% or 95 mass%. The polyolefin content of the resin may be 70 mass% or more and 100 mass% or less, 80 mass% or more and 97 mass% or less, or 90 mass% or more and 95 mass% or less.

[0078] The lower limit of the acid-modified polyolefin content of the resin may be 70 mass%, 80 mass%, or 90 mass%, from the viewpoint of lowering the softening temperature of the adhesive layer and obtaining good mechanical strength. The upper limit of the acid-modified polyolefin content of the resin may be 100 mass% or 95 mass%. The acid-modified polyolefin content of the resin may be 70 mass% or more and 100 mass% or less, 80 mass% or more and 97 mass% or less, or 90 mass% or more and 95 mass% or less.

[0079] Examples of polystyrene elastomers include styrene-ethylene-butylene-styrene block copolymer (SEBS), styrene-ethylene-propylene-styrene copolymer (SEPS), and styrene-ethylene-ethylene-propylene-styrene block copolymer (SEEPS).

[0080] The lower limit of the polystyrene elastomer content of the resin may be 50 mass%, 55 mass%, or 60 mass%, from the viewpoint of lowering the softening temperature of the adhesive layer and obtaining good mechanical strength. The upper limit of the polystyrene elastomer content of the resin may be 100 mass% or 80 mass%. The polystyrene elastomer content of the resin may be 50 mass% or more and 100 mass% or less, 55 mass% or more and 90 mass% or less, or 60 mass% or more and 80 mass% or less.

[0081] The adhesive layer may contain a resin other than polyolefin and polystyrene elastomer (an other resin), such as polyphenylene ether.

[0082] In the adhesive layer, the upper limit of the content of other resins may be 30 mass %, 20 mass %, or 10 mass % when the resin is a polyolefin, and may be 50 mass %, 45 mass %, or 40 mass % when the resin is a polystyrene-based elastomer.

[0083] In embodiment 1, the volumetric content of the second inorganic filler in the adhesive layer is 29 vol% or more and 47 vol% or less. This allows the length of the cavity to be reduced to less than 25 μm. Because the softening temperature of the adhesive layer is low, a high thermal expansion coefficient of the adhesive layer is not a problem. Therefore, the adhesive layer does not need to contain a second inorganic filler to reduce the thermal expansion coefficient of the adhesive layer. The lower limit of the content of the second inorganic filler in the adhesive layer may be 29 vol%, 33 vol%, or 38 vol%, from the viewpoint of further reducing the length of the cavity. The upper limit of the content of the second inorganic filler in the adhesive layer may be 47 vol%, 43 vol%, or 40 vol%, from the viewpoint of maintaining strong adhesive strength. The content of the second inorganic filler in the adhesive layer may be 29 vol% or more and 47 vol% or less, 33 vol% or more and 43 vol% or less, or 38 vol% or more and 40 vol% or less.

[0084] In the present disclosure, the volumetric content of the second inorganic filler in the adhesive layer is measured as follows: The circuit board is cut by argon ion polishing to expose the cross section of the adhesive layer. The cross section is a plane perpendicular to the lamination surface of the circuit board or a perpendicular plane. If the cross section is a plane parallel to the lamination surface of the circuit board, the cross section area is likely to be large. If the cross section is a plane perpendicular to the lamination surface, the cross section is easily formed. The cross section of the adhesive layer is observed at 10,000 magnification using a high-resolution scanning electron microscope (SEM) (SU8020 manufactured by Hitachi High-Tech Corporation) at a low acceleration voltage to obtain an SEM image. A rectangular measurement area of ​​5 μm × 12 μm is set in the SEM image. The area-based content (area percentage) of the second inorganic filler in the measurement area is measured. The area percentage is measured by extracting the second inorganic filler portion using multi-value image analysis processing software. The area percentage of the second inorganic filler is measured for 30 different measurement areas, and the average area percentage is calculated. Next, 10 new measurement areas whose area percentages have not yet been measured are added to the measurement areas whose area percentages have already been measured, resulting in a total of 40 measurement areas, and the average area percentage of the second inorganic filler is calculated. If the difference between the average area percentage before the 10 measurement areas is added and the average area percentage of the measurement areas after the 10 measurement areas are added is within 1%, the average area percentage of the measurement areas after the addition is taken as the volumetric content of the second inorganic filler in the adhesive layer. If the difference is greater than 1%, 10 measurement areas whose area percentages have not yet been measured are added, and the average area percentage of the measurement areas after the addition is calculated. This process is repeated until the difference before and after the addition of the measurement area is within 1%. When the difference before and after the addition of the measurement area is within 1%, the average area percentage is taken as the volumetric content of the second inorganic filler in the adhesive layer.

[0085] In embodiment 1, the mass-based content of the second inorganic filler in the adhesive layer may be 40% by mass or more and 70% by mass or less. This allows the length of the cavities to be smaller than 25 μm. The lower limit of the content of the second inorganic filler in the adhesive layer may be 40% by mass, 50% by mass, or 55% by mass. The upper limit of the content of the second inorganic filler in the adhesive layer may be 70% by mass, 67% by mass, or 63% by mass. The content of the second inorganic filler in the adhesive layer may be 40% by mass or more and 70% by mass or less, 50% by mass or more and 67% by mass or less, or 55% by mass or more and 63% by mass or less.

[0086] In the present disclosure, the mass content of the second inorganic filler in the adhesive layer is measured as follows: The adhesive layer is heated in a thermogravimetric differential scanning calorimeter (TG-DSC) under a nitrogen atmosphere, and the temperature of the adhesive layer is increased from 30°C to 700°C at a rate of 20°C / min. The initial weight of the adhesive layer and the recovered weight of the recovered material after heating are measured. The ratio of the recovered weight to the initial weight is taken as the mass content of the second inorganic filler in the adhesive layer.

[0087] When the mass-based content of the first inorganic filler in the fluororesin layer is X (mass%) and the mass-based content of the second inorganic filler in the adhesive layer is Y (mass%), the absolute value Z of the difference between X and Y may be 0 or more and 17 or less, further may be 0 or more and 10 or less, or further may be 0 or more and 7 or less. This allows the length of the gouge to be further reduced.

[0088] The second inorganic filler may be a non-metallic inorganic filler and may contain silica. Silica has a relatively low specific gravity. The surface of silica is easily treated with, for example, a silane coupling agent. Therefore, silica is easily mixed with the resin of the adhesive layer. Silica is inexpensive and easily available. The silica content of the second inorganic filler may be 50% by mass or more and 100% by mass or less, 70% by mass or more and 100% by mass or less, or 90% by mass or more and 100% by mass or less.

[0089] In the present disclosure, the method for measuring the mass-based silica content of the second inorganic filler in the adhesive layer is as follows. First, the recovered weight of the recovered material obtained by the method for measuring the mass-based silica content of the second inorganic filler in the adhesive layer described above is measured. The recovered material is then used to measure the silicon (Si) content by ICP analysis. When silica is SiO ２ The silica content in the recovered material is calculated from the silicon content, assuming that the composition is as follows: This content is the silica content of the second inorganic filler in the adhesive layer on a mass basis.

[0090] The second inorganic filler may contain boron nitride. Because boron nitride has a low dielectric constant, even if the second inorganic filler contains a large amount of boron nitride, the dielectric constant of the adhesive layer does not change significantly. Furthermore, because boron nitride has high thermal conductivity, the heat dissipation properties of the circuit board can be improved by having the second inorganic filler contain boron nitride. From the viewpoint of improving thermal conductivity, the boron nitride content of the second inorganic filler may be 20% by mass or more, 40% by mass or more, or 60% by mass or more. The upper limit of the boron nitride content of the second inorganic filler may be 100% by mass. The boron nitride content of the second inorganic filler may be 20% by mass or more and 100% by mass or less, 40% by mass or more and 100% by mass or less, or 60% by mass or more and 100% by mass or less.

[0091] In the present disclosure, the method for measuring the mass-based content of boron nitride of the second inorganic filler in the adhesive layer is as follows. First, the recovered weight of the recovered material obtained in the method for measuring the mass-based content of the second inorganic filler in the adhesive layer described above is measured. Using the recovered material, the boron content of the recovered material is measured by ICP analysis. Assuming that boron nitride has a composition of BN, the boron nitride content of the recovered material is calculated from the boron content. This content is the mass-based content of boron nitride of the second inorganic filler in the adhesive layer.

[0092] The second inorganic filler can contain both silica and boron nitride. This can suppress the occurrence of gouging and improve the heat dissipation performance of the circuit board. Furthermore, even if the second inorganic filler contains a large amount of silica and boron nitride, the dielectric constant of the adhesive layer does not change significantly.

[0093] The second inorganic filler may contain a non-metallic inorganic filler other than silica and boron nitride (hereinafter also referred to as "other inorganic filler") as long as the effects of the present disclosure are not impaired. Examples of other inorganic fillers include titanium nitride, aluminum oxide, magnesium oxide, calcium oxide, talc, barium sulfate, boron nitride, zinc oxide, potassium titanate, glass, and mica. One or more of these other inorganic fillers may be used.

[0094] The adhesive layer may be composed of a resin, a second inorganic filler, and inevitable impurities. The adhesive layer may also contain components other than the resin and the second inorganic filler, as long as the effects of the present disclosure are not impaired. Examples of components other than the resin and the second inorganic filler include flame retardants, flame retardant assistants, pigments, antioxidants, reflectivity imparting agents, opacifying agents, lubricants, processing stabilizers, plasticizers, and foaming agents. The adhesive layer may contain one or more of these components. The upper limit of the content of the components in the adhesive layer may be 25% by mass or 10% by mass.

[0095] The ratio A / B of the adhesive layer's modulus of elasticity A at 160°C to its modulus of elasticity B at 20°C may be 0.08 or less. This allows the adhesive layer to fill between the circuits of the metal layer even when pressed at a temperature of 180°C or less. Furthermore, the adhesive layer and the metal layer are closely attached, improving the adhesive strength between the adhesive layer and the metal layer. From the viewpoint of ensuring adhesiveness, the upper limit of the ratio A / B may be 0.08, 0.05, or 0.02. The lower limit of the ratio A / B may be 0.0001, 0.0005, or 0.001. The ratio A / B may be 0.0001 or more and 0.08 or less, 0.0005 or more and 0.05 or less, or 0.001 or more and 0.02 or less.

[0096] In the present disclosure, the elastic modulus B of the adhesive layer at 20°C and the elastic modulus A at 160°C are measured as follows: Using a dynamic viscosity measurement (DMS) device, a vibration of 1 Hz frequency is applied to the bonding sheet constituting the adhesive layer, while the bonding sheet is heated to increase the temperature of the bonding sheet from 15°C to 170°C at a rate of 10°C / min, and the elastic moduli at 20°C and 160°C are measured.

[0097] The glass transition temperature of the adhesive layer may be 160°C or lower. This improves adhesion when the fluororesin layer and the metal layer are pressed together at a temperature of 180°C or lower. The upper limit of the glass transition temperature of the adhesive layer may be 160°C, 150°C, 120°C, or 100°C. If the glass transition temperature of the adhesive layer is 150°C or lower, adhesion is further improved, if it is 120°C or lower, adhesion is further improved, and if it is 100°C or lower, adhesion is still further improved. The lower limit of the glass transition temperature of the adhesive layer may be 10°C. If the glass transition temperature of the adhesive layer is 10°C or higher, heat resistance is improved. Therefore, the possibility of blistering or peeling of the adhesive layer during reflow soldering of a circuit board or high-temperature reliability evaluation is reduced. The glass transition temperature of the adhesive layer may be 30°C or higher and 160°C or lower, 30°C or higher and 150°C or lower, or 30°C or higher and 120°C or lower. When the adhesive layer has multiple glass transition temperatures, the glass transition temperature of the adhesive layer is determined to be the highest glass transition temperature among the glass transition temperatures attributable to resins whose volume ratio to the total volume of all resins is 10% or more.

[0098] In this disclosure, the glass transition temperature of the adhesive layer is measured as follows. A dynamic viscosity measurement (DMS) device is used to measure the glass transition temperature of the adhesive layer. While applying a vibration of 1 Hz to the bonding that constitutes the adhesive layer, the bonding sheet is heated to increase the temperature of the bonding sheet from 15°C to 170°C at a rate of 10°C / min. Within this temperature range, the complex modulus of elasticity of the bonding sheet is measured, and the temperature at which tanδ peaks, where δ is the phase angle, is considered to be the glass transition temperature.

[0099] The lower limit of the average thickness of the adhesive layer may be 5 μm, 20 μm, or 30 μm from the viewpoint of adhesiveness. The upper limit of the average thickness of the adhesive layer may be 100 μm, 70 μm, or 50 μm from the viewpoint of finishing the laminate thin. The average thickness of the adhesive layer may be 5 μm or more and 100 μm or less, 20 μm or more and 70 μm or less, or 30 μm or more and 50 μm or less.

[0100] The average thickness of the adhesive layer may be equal to or greater than the thickness of the circuit from the viewpoint of filling the gap between the circuits. The average thickness of the adhesive layer may be 10 μm or more thicker than the thickness of the circuit, or may be 20 μm or more thicker than the thickness of the circuit.

[0101] According to the first embodiment, even when a through hole penetrating the fluororesin layer 10 and the adhesive layer 12 is formed, the occurrence of gouging near the interface between the fluororesin layer 10 and the adhesive layer 12 is suppressed on the inner wall surface of the fluororesin layer and the inner wall surface of the adhesive layer. Even when gouging occurs in the fluororesin layer, the length of the gouging can be made very small. In the circuit board of the first embodiment, at least one of the inner wall surface of the fluororesin layer and the inner wall surface of the adhesive layer has a gouging. The length of the gouging may be less than 25 μm, less than 20 μm, or less than 15 μm. In the circuit board of the first embodiment, the inner wall surface of the fluororesin layer and the inner wall surface of the adhesive layer do not have to have a gouging.

[0102] A method for measuring the length of a cavity in the present disclosure will be described with reference to FIG. 9 . First, the circuit board 1 is cut along a plane including the central axis L1 of the through hole to expose a cross section of the laminate of the fluororesin layer 10 and the adhesive layer 12. In FIG. 9 , the central axis L1 corresponds to a line connecting the center (geometric center) of the opening of the through hole in the second main surface 10b of the fluororesin layer 10 and the center (geometric center) of the opening of the through hole in the first B surface 12a of the adhesive layer 12. Below, a method for measuring the length of a cavity in this cross section will be described. The interface between the fluororesin layer 10 and the adhesive layer 12 is defined as interface P1. A line that is between the interface P1 and the fluororesin layer 10, parallel to the interface P1, and 10 μm away from the interface P1 is defined as line P1F. A line that is between the interface P1 and the adhesive layer 12, parallel to the interface P1, and 10 μm away from the interface P1 is defined as line P1B. A gouge is identified in the region between interface P1 and line P1F, or in the region between interface P1 and line P1F. In FIG. 9, gouge 25 exists in the region between interface P1 and line P1F. When the interface has irregularities, the interface is defined by its mean line. The "mean line" is an imaginary line drawn along the interface in the cross section, and refers to a line such that the total area of ​​the peaks (total area above the imaginary line) and the total area of ​​the valleys (total area below the imaginary line) defined by the interface and this imaginary line are equal.

[0103] In the region between lines P1F and P1B on the cross section, point S1 closest to the central axis L1 of the inner wall surface 27 is identified. Then, the end S2 of the gouge at the position farthest from the central axis L1 is identified. The line L2 is perpendicular to the interface P1 and passes through point S1. The line L3 is parallel to L2 and passes through end S2 of the gouge. The distance L between lines L2 and L3 is measured. Distance L is the length of the gouge.

[0104] <Adherend Layer> In the first embodiment, the adherend layer 17 may include a first resin layer 16 and a first metal layer 13 provided on a portion of the surface of the first resin layer 16. In FIG. 1 , the adherend layer 17 includes the first metal layer 13 and the first resin layer 16. The first metal layer 13 is made of metal. The first metal layer 13 is provided closer to the first main surface 10a of the fluororesin layer 10 than the first resin layer 16. The positional relationship between the first resin layer 16 and the first metal layer 13 may be reversed. Specifically, the first resin layer 16 may be provided closer to the first main surface 10a than the first metal layer 13.

[0105] <First Metal Layer> In the first embodiment, the first metal layer 13 forms an electric circuit. In the present disclosure, the electric circuit includes an antenna.

[0106] The first metal layer may contain copper. Copper has low resistance and small transmission loss. The copper content of the first metal layer may be 90% by mass or more and 100% by mass or less, 95% by mass or more and 100% by mass or less, or 99% by mass or more and 100% by mass or less. The first metal layer may be a layer made of copper and inevitable impurities.

[0107] The first metal layer may contain a metal other than copper, such as silver, nickel, cobalt, zinc, or chromium. One or more of these metals may be used.

[0108] The average thickness of the first metal layer may be 1 μm or more, 5 μm or more, or 10 μm or more from the viewpoint of reducing electrical resistance. The upper limit of the average thickness of the first metal layer may be 100 μm, 70 μm, or 50 μm from the viewpoint of ease of production. The average thickness of the first metal layer may be 1 μm or more and 100 μm or less, 5 μm or more and 70 μm or less, or 10 μm or more and 50 μm or less.

[0109] The upper limit of the maximum height roughness Rz of the surface of the first metal layer facing the first resin layer may be 2 μm or 1 μm. If the maximum height roughness Rz is 2 μm or less, the unevenness in the area where high-frequency signals concentrate due to the skin effect is small, making it easier for current to flow linearly. Therefore, transmission loss can be suppressed, and the high-frequency characteristics of the circuit board can be further improved. "Maximum height roughness Rz" refers to the maximum height roughness measured in accordance with JIS-B-0601 (1982). Specifically, the maximum height roughness Rz is measured using a laser microscope VK-X200 manufactured by Keyence Corporation.

[0110] <First Resin Layer> In the first embodiment, the first resin layer 16 may contain an epoxy resin and a glass cloth. This allows the circuit board to be manufactured inexpensively. The dielectric loss tangent of the first resin layer 16 may be 0.01 or less, 0.005 or less, or 0.002 or less. This reduces the transmission loss of the first metal layer, resulting in excellent high-frequency characteristics. The first resin layer 16 may contain a fluororesin and an inorganic filler. This reduces the transmission loss of the first metal layer, resulting in excellent high-frequency characteristics.

[0111] <Second Metal Layer> In the first embodiment, the second metal layer 11 forms an electric circuit. In the present disclosure, the electric circuit includes an antenna.

[0112] The second metal layer 11 may contain copper. Copper has low resistance and small transmission loss. The copper content of the second metal layer 11 may be 90% by mass or more and 100% by mass or less, 95% by mass or more and 100% by mass or less, or 99% by mass or more and 100% by mass or less. The second metal layer may be a layer made of copper and inevitable impurities.

[0113] The second metal layer 11 may contain a metal other than copper. Examples of the metal other than copper include silver, nickel, cobalt, zinc, and chromium. One or more of these metals may be used.

[0114] The average thickness of the second metal layer 11 may be 1 μm or more, 5 μm or more, or 10 μm or more from the viewpoint of reducing electrical resistance. The upper limit of the average thickness of the second metal layer 11 may be 100 μm, 70 μm, or 50 μm from the viewpoint of ease of production. The average thickness of the second metal layer 11 may be 1 μm or more and 100 μm or less, 5 μm or more and 70 μm or less, or 10 μm or more and 50 μm or less.

[0115] <Connection Portion> In the first embodiment, the connection portion 14 forms a via hole. In FIG. 1 , the connection portion 14 is formed on an end face of the second metal layer 11 that defines a portion of the through hole, a region of the outer surface of the second metal layer 11 near the through hole, the inner wall surfaces of the fluororesin layer 10 and the adhesive layer 12, and a surface (first A surface 13a) of the first metal layer 13 near the adhesive layer that defines a portion of the through hole. The location where the connection portion 14 is formed is not limited to the embodiment shown in FIG. 1 . The connection portion 14 may be formed electrically between the first metal layer 13 and the second metal layer 11. For example, the connection portion 14 may be formed in the through hole. More specifically, the connection portion 14 may be formed on the inner wall surfaces of the fluororesin layer 10 and the adhesive layer 12, and the connection portion 14 near the fluororesin layer 10 may be in contact with at least a portion of the second metal layer 11, and the connection portion 14 near the adhesive layer 12 may be in contact with at least a portion of the first metal layer 13.

[0116] The connection portion may contain copper, which provides high electrical conductivity and reduces transmission loss.

[0117] The connecting portion may contain a metal other than copper. Examples of the metal other than copper include silver, nickel, cobalt, zinc, and chromium. One or more of these metals may be used.

[0118] The average thickness of the connection portion may be 1 μm or more, 5 μm or more, or 10 μm or more from the viewpoint of improving electrical reliability. The upper limit of the average thickness of the connection portion may be 100 μm, 50 μm, or 30 μm from the viewpoint of ease of manufacture. The average thickness of the connection portion may be 1 μm or more and 100 μm or less, 5 μm or more and 50 μm or less, or 10 μm or more and 30 μm or less.

[0119] 1 , the cross-sectional area of ​​the through hole increases continuously from the first metal layer 13 to the second metal layer 11. However, the change in the cross-sectional area of ​​the through hole is not limited to this. The cross-sectional area of ​​the through hole may be constant or may decrease continuously from the first metal layer 13 to the second metal layer 11.

[0120] <Adhesive Film> The circuit board of the embodiment may include an adhesive film disposed between the fluororesin layer and the second metal layer, which can improve the adhesive strength between the fluororesin layer and the second metal layer.

[0121] The adhesive film may include a fluororesin, such as perfluoroalkoxyalkane (PFA) or perfluoroethylenepropene copolymer (FEP).

[0122] The average thickness of the adhesive thin film may be 3 μm or 2 μm or less so as not to impair the function of the fluororesin layer.

[0123] <Method for manufacturing circuit board> The method for manufacturing a circuit board of embodiment 1 includes a step of holding a laminate in which a fluororesin layer, an adhesive layer, and an adherend layer are laminated in this order at a temperature of 180°C or less to soften the adhesive layer, thereby bonding the fluororesin layer and the adherend layer together. This prevents gouging near the interface between the fluororesin layer and the adhesive layer, even when a through hole is formed through the fluororesin layer and the adhesive layer.

[0124] [Embodiment 2: Circuit Board Manufacturing Method (1)] A circuit board manufacturing method according to one embodiment of the present disclosure (hereinafter also referred to as "Embodiment 2") will be described with reference to FIGS. 1, 2A, 2B, and 2C. The method for manufacturing the circuit board 1 of the second embodiment includes: a step of preparing a fluororesin laminate 20 (hereinafter also referred to as a "first step") including a fluororesin layer 10 including a first main surface 10a and a second main surface 10b opposite to the first main surface 10a, and a second metal layer 11 provided on the second main surface 10b (see FIG. 2A ); a step of preparing a first resin laminate 22 (hereinafter also referred to as a "second step") including a first resin layer 16 including a third main surface 16a and a fourth main surface 16b opposite to the third main surface 16a, and a first metal layer 13 provided on the third main surface 16a (see FIG. 2A ); a step of preparing an adhesive layer 12 (hereinafter also referred to as a "third step") (see FIG. 2A ); the step of laminating a fluororesin laminate (20), an adhesive layer (12), and a first resin laminate (22) in this order so that the first main surface (10a) is in contact with the adhesive layer (12), and maintaining the adhesive layer (12) at a temperature of 180°C or less to soften the adhesive layer (12) and thereby bonding the fluororesin laminate (20) and the first resin laminate (22) to obtain a first laminate (24) (hereinafter also referred to as the "fourth step") (see FIG. 2B); the step of removing at least a part of the fluororesin layer (10) and at least a part of the adhesive layer (12) to form a through hole penetrating the fluororesin layer (10) and the adhesive layer (12) (hereinafter also referred to as the "fifth step") (see FIG. 2C); and the step of forming a connection part (14) on the inner wall surface of the fluororesin laminate (20) that defines a part of the through hole and on the inner wall surface of the adhesive layer (12) that defines a part of the through hole to obtain a circuit board (hereinafter also referred to as the "sixth step") (see FIG. 1 ), The method for manufacturing a circuit board includes: the fluororesin layer (10) includes polytetrafluoroethylene and a first inorganic filler, and the content of the first inorganic filler in the fluororesin layer (10) is 50% by volume or more and 66% by volume or less; the adhesive layer (12) includes a resin and a second inorganic filler, and the fluororesin content of the resin is 5% by mass or less; and the content of the second inorganic filler in the adhesive layer (12) is 29% by volume or more and 47% by volume or less.

[0125] In embodiment 2, the fluororesin layer 10, adhesive layer 12, first metal layer 13, second metal layer 11, first resin layer 16, and connecting portion 14 can be the same as those in embodiment 1. The first, second, third, fourth, fifth, and sixth steps will be described below. The order of steps 1, 2, and 3 does not have to be in this order, and any of these steps can be performed first. Steps 1, 2, and 3 can be performed simultaneously. Steps 1, 2, and 3 are followed by steps 4, 5, and 6, in this order.

[0126] <First Step> In the first step, a fluororesin laminate 20 is prepared, which includes a fluororesin layer 10 including a first main surface 10a and a second main surface 10b opposite to the first main surface 10a, and a second metal layer 11 provided on the second main surface 10b. Methods for providing the second metal layer 11 on the second main surface 10b include, for example, a method of thermocompression bonding the fluororesin layer 10 and the second metal layer 11 together using a high-temperature press, a method of bonding the fluororesin layer 10 and the second metal layer 11 by disposing a thin adhesive film between them, a method of vapor-depositing a metal that will form the second metal layer 11 on the fluororesin layer 10, and a method of plating the metal that will form the second metal layer 11 on the fluororesin layer 10.

[0127] The first step (the step of preparing a fluororesin laminate) may further include a step of forming a second circuit on the fluororesin laminate 20 by etching at least a part of the second metal layer 11. Examples of a method for etching at least a part of the second metal layer 11 include known etching methods such as a wet etching method in which a resist pattern is formed and then the laminate is immersed in a chemical solution containing an acid or an alkali, and a dry etching method using an ion beam.

[0128] <Second step> In the second step, a first resin laminate 22 is prepared, which includes a first resin layer 16 including a third main surface 16 a and a fourth main surface 16 b opposite to the third main surface 16 a, and a first metal layer 13 provided on the third main surface 16 a.

[0129] Methods for providing the first metal layer 13 on one main surface of the first resin layer 16 include, for example, a method of thermocompression bonding the first resin layer 16 and the first metal layer 13 using a high-temperature press, a method of placing a thin adhesive film between the first resin layer 16 and the first metal layer 13 and bonding them together, a method of vapor-depositing the metal that constitutes the first metal layer 13 onto the first resin layer 16, and a method of plating the metal that constitutes the first metal layer 13 onto the first resin layer 16.

[0130] The second step (the step of preparing the first resin laminate) may further include a step of forming a first circuit in the first resin laminate 22 by etching at least a part of the first metal layer 13. Examples of a method for etching at least a part of the first metal layer 13 include known etching methods such as a wet etching method in which a resist pattern is formed and then the laminate is immersed in a chemical solution containing an acid or alkali, and a dry etching method using an ion beam.

[0131] <Third Step> In the third step, the adhesive layer 12 is prepared.

[0132] <Fourth Step> In the fourth step, the fluororesin laminate 20, the adhesive layer 12, and the first resin laminate 22 are laminated in this order so that the first main surface 10a is in contact with the adhesive layer 12, and the adhesive layer 12 is softened by maintaining it at a temperature of 180°C or less, thereby bonding the fluororesin laminate 20 and the first resin laminate 22 to obtain the first laminate 24. In the second embodiment, the first metal layer 13 is disposed so as to be in contact with the adhesive layer 12 during lamination.

[0133] The temperature at which the adhesive layer is maintained may be 140°C or higher and 180°C or lower, or 160°C or higher and 180°C or lower. Heat may be applied to the adhesive layer while applying pressure to the laminate of the fluororesin laminate 20, the adhesive layer 12, and the first resin laminate 22. The pressure may be 0.5 MPa or higher and 8 MPa or lower, 1 MPa or higher and 6 MPa or lower, or 3 MPa or higher and 5 MPa or lower. The time for maintaining the adhesive layer at the above temperature and applying the above pressure to the laminate may be 20 minutes or higher and 120 minutes or lower.

[0134] The fourth step (the step of forming the first laminate) may further include a step of etching at least a portion of the second metal layer 11 to form a second circuit in the fluororesin laminate 20. Examples of a method for etching at least a portion of the second metal layer 11 include known etching methods such as a wet etching method in which a resist pattern is formed and then the laminate is immersed in a chemical solution containing an acid or alkali, and a dry etching method using an ion beam. The second circuit may be formed in the first step or the fourth step.

[0135] <Fifth Step> In the fifth step, at least a part of the fluororesin layer 10 and at least a part of the adhesive layer 12 are removed to form through-holes that penetrate the fluororesin layer 10 and the adhesive layer 12 .

[0136] First, a dry film is attached to the second metal layer 11, and the second metal layer 11 is etched by exposure. The dry film is then peeled off to form an opening in the second metal layer 11. Using the area of ​​the second metal layer 11 other than the opening as a mask (shielding layer), laser processing is performed on the fluororesin layer 10 and the adhesive layer 12 through the opening. This removes at least a portion of the fluororesin layer 10 and at least a portion of the adhesive layer 12, forming an opening in the second metal layer 11 and a through hole penetrating the fluororesin layer 10 and the adhesive layer 12. The second metal layer 11 may also serve as a laser shielding layer. Using the second metal layer 11 as a laser shielding layer allows for control of the shape of the through hole.

[0137] For laser processing, CO ２ A laser may also be used. ２ When a laser is used, it is easy to use the second metal layer 11 as a laser blocking layer.

[0138] In FIG. 2C, the through hole does not penetrate through the first metal layer 13 and is a blind via hole.

[0139] The first metal layer 13 may be provided on the third main surface 16 a of the first resin layer 16. In this case, the distance between the first metal layer 13 and the second metal layer 11 is small, allowing wiring to be arranged at a high density. In this case, the circuit formed on the first metal layer 13 is embedded in the adhesive layer 12.

[0140] In circuit boards that take advantage of the high-performance properties of a fluororesin layer, such as circuit boards with high-frequency antennas, the fluororesin layer is often formed near the surface. Therefore, a manufacturing method in which a general-purpose circuit board is first fabricated and then a high-performance fluororesin layer is formed on its surface is rational in terms of ease of circuit design and manufacturing costs. This rational manufacturing method is easily applicable to circuit boards in which blind via holes are formed on the second main surface (10b) of the fluororesin layer (10) and the first metal layer (13) formed on the third main surface (16a) of the first resin layer (16) serves as the via bottom of the blind via hole. However, in circuit boards in which the first metal layer (13) serves as the via bottom of the blind via hole, the laser is reflected by the first metal layer (13) when forming a through hole by laser processing. Therefore, the length of the gouge near the interface between the fluororesin layer (10) and the adhesive layer (12) is larger than in circuit boards in which the laser is not reflected. According to the present disclosure, the gouge length can be suppressed even in circuit boards in which the first metal layer serves as the via bottom of the blind via hole. Therefore, the present disclosure is particularly effective for a circuit board in which the first metal layer is the via bottom of a blind via hole.

[0141] After the through holes are formed, the inner wall surfaces of the fluororesin layer 10 and the adhesive layer 12 may be subjected to a pretreatment step to clean the inner wall surfaces. Examples of surface treatments include potassium permanganate treatment, alkali treatment, and plasma treatment.

[0142] The alkali treatment is a treatment in which the first laminate 24 is immersed in a strong alkaline solution such as potassium hydroxide, thereby etching the surface layers of the inner wall surfaces of the fluororesin layer 10 and the adhesive layer 12 .

[0143] The plasma treatment is a process in which plasma is brought into contact with the inner wall surfaces of the fluororesin layer 10 and the adhesive layer 12, thereby etching the surface of the inner wall surfaces. In atmospheric pressure plasma treatment, which is one example of plasma treatment, a plasma gas such as oxygen, nitrogen, hydrogen, argon, or ammonia is sprayed onto the inner wall surfaces. The entire surface of the first laminate 24 may be plasma-treated by placing the first laminate 24 in a plasma gas atmosphere. In the plasma treatment, plasma of an inert gas containing a compound having a hydrophilic group may be used.

[0144] <Sixth Step> In the sixth step, the connection portions 14 are formed on the inner wall surfaces of the fluororesin laminate 20 and the adhesive layer 12 to obtain the circuit board 1.

[0145] To form the connection portion 14, first, an electroless plating layer is formed by electroless plating on the end face of the second metal layer 11 that defines a portion of the through hole, the area near the opening (through hole) on the outer surface of the second metal layer 11, the inner wall surface of the fluororesin layer 10, the inner wall surface of the adhesive layer 12, and the surface (first A surface 13a) of the first metal layer 13 that defines a portion of the through hole and is near the adhesive layer. Subsequently, a plating layer is formed on the electroless plating layer by electrolytic plating. This plating layer is the connection portion 14.

[0146] [Embodiment 3: Circuit Board (2)] A circuit board according to one embodiment of the present disclosure (hereinafter also referred to as "Embodiment 3") and a manufacturing method thereof will be described with reference to Figures 3, 4A, 4B, and 4C. As shown in Figure 3, circuit board 1 of Embodiment 3 includes fluororesin layer 10, adherend layer 17, and adhesive layer 12 that adheres fluororesin layer 10 to adherend layer 17. Fluororesin layer 10 includes first main surface 10a facing adhesive layer 12 and second main surface 10b opposite first main surface 10a. Adhesion layer 17 includes first resin layer 16 and first metal layer 13 provided on at least a portion of the surface of first resin layer 16. First resin layer 16 and first metal layer 13 may be in contact with each other. A resin layer, a metal layer, an adhesive layer, or a laminate thereof may be disposed between the first resin layer 16 and the first metal layer 13 to bond the first resin layer 16 and the first metal layer 13 together.

[0147] The circuit board 1 of the third embodiment includes a first resin layer 16 provided between the first metal layer 13 and the adhesive layer 12. A fourth main surface 16b of the first resin layer 16, which is farther from the first metal layer 13, is in contact with a first B-surface 12a of the adhesive layer 12, which is farther from the fluororesin layer 10.

[0148] The circuit board 1 further includes a second metal layer 11 provided on the second main surface 10b of the fluororesin layer 10. The fluororesin layer 10 and the second metal layer 11 may be in contact with each other. The fluororesin layer 10 and the second metal layer 11 may be bonded to each other by disposing a thin adhesive film (not shown) between the fluororesin layer 10 and the second metal layer 11.

[0149] The circuit board 1 further includes a connection portion 14. The connection portion 14 is made of metal and electrically connects the first metal layer 13 and the second metal layer 11. The second metal layer 11, the fluororesin layer 10, the adhesive layer 12, and the first resin layer 16 include through holes that penetrate these layers. The connection portion 14 is formed in the through holes. More specifically, the connection portion 14 is formed on the inner wall surface of the second metal layer 11, the inner wall surface of the fluororesin layer 10, the inner wall surface of the adhesive layer 12, and the inner wall surface of the first resin layer 16. The first metal layer 13 defines the bottom surface of the through hole, and the connection portion 14 is also formed on the bottom surface.

[0150] When the circuit board 1 is viewed from a direction perpendicular to the second main surface 10b of the fluororesin layer 10, the second metal layer 11 is not formed in the region overlapping the through hole. The second metal layer 11 has an opening that leads to the through hole. When the circuit board 1 is viewed from a direction perpendicular to the second main surface 10b of the fluororesin layer 10, the first metal layer 13 is formed in the region overlapping the through hole. The first metal layer 13 is the via bottom that closes the through hole. The through hole that penetrates the fluororesin layer 10 and the adhesive layer 12 extends to the first resin layer 16. The connection portion 14 formed on the inner wall surface of the fluororesin layer 10 and the adhesive layer 12 also extends to the first resin layer 16.

[0151] In FIG. 3, the cross-sectional area of ​​the through holes increases continuously from the first metal layer 13 to the second metal layer 11 .

[0152] In the third embodiment, the fluororesin layer 10, adhesive layer 12, first metal layer 13, second metal layer 11, first resin layer 16 and connecting portion 14 can be the same as those in the first embodiment.

[0153] According to the circuit board 1 of the third embodiment, even when a through hole is formed penetrating the fluororesin layer 10 and the adhesive layer 12, the occurrence of gouging of the fluororesin layer 10 is suppressed near the interface between the fluororesin layer 10 and the adhesive layer 12. Therefore, the reliability of the circuit board 1 of the third embodiment is improved.

[0154] <Manufacturing Method> A manufacturing method of the circuit board 1 of Embodiment 3 includes: a step of preparing a fluororesin laminate 20 (hereinafter also referred to as "Step 1B") including a fluororesin layer 10 including a first main surface 10a and a second main surface 10b opposite to the first main surface 10a, and a second metal layer 11 provided on the second main surface 10b (see FIG. 4A ); a step of preparing a first resin laminate 22 (hereinafter also referred to as "Step 2B") including a first resin layer 16 including a third main surface 16a and a fourth main surface 16b opposite to the third main surface 16a, and a first metal layer 13 provided on the third main surface 16a (see FIG. 4A ); a step of preparing an adhesive layer 12 (hereinafter also referred to as "Step 3B") (see FIG. 4A ); the step of laminating a fluororesin laminate (20), an adhesive layer (12), and a first resin laminate (22) in this order so that the first main surface (10a) is in contact with the adhesive layer (12), and maintaining the adhesive layer (12) at a temperature of 180°C or less to soften the adhesive layer (12) and thereby bonding the fluororesin laminate (20) and the first resin laminate (22) to obtain a first laminate (24) (hereinafter also referred to as "step 4B") (see FIG. 4B); the step of removing at least a part of the fluororesin layer (10) and at least a part of the adhesive layer (12) to form through-holes penetrating the fluororesin layer (10) and the adhesive layer (12) (hereinafter also referred to as "step 5B") (see FIG. 4C); and the step of forming connection parts (14) on the inner wall surfaces of the fluororesin laminate (20) and the adhesive layer (12) to obtain a circuit board (hereinafter also referred to as "step 6") (see FIG. 3), The method for manufacturing a circuit board includes: the fluororesin layer (10) includes polytetrafluoroethylene and a first inorganic filler, and the content of the first inorganic filler in the fluororesin layer (10) is 50% by volume or more and 66% by volume or less; the adhesive layer (12) includes a resin and a second inorganic filler, and the fluororesin content of the resin is 5% by mass or less; and the content of the second inorganic filler in the adhesive layer (12) is 29% by volume or more and 47% by volume or less.

[0155] Steps 1B, 2B, and 3B of the third embodiment can be the same as steps 1, 2, and 3 of the second embodiment, respectively.

[0156] Step 4B of the third embodiment can be the same as step 4 of the second embodiment, except that the first resin layer 16 is laminated so as to be in contact with the adhesive layer 12 .

[0157] In step 5B of embodiment 3, at least a portion of the second metal layer 11, at least a portion of the fluororesin layer 10, at least a portion of the adhesive layer 12, and at least a portion of the first resin layer 16 are removed to form a through hole that penetrates these layers.

[0158] The method for forming the through holes can be the same as the method for forming the through holes in the fifth step of embodiment 2. In Fig. 4C, the through holes do not penetrate the first metal layer 13 and are blind via holes.

[0159] After the through holes are formed, a pretreatment process may be performed on the inner wall surfaces of the fluororesin layer 10, the adhesive layer 12, and the first resin layer. The pretreatment process may be the same as the pretreatment process in the second embodiment.

[0160] In step 6B of embodiment 3, connection portions 14 are formed on the end face of second metal layer 11 that defines a portion of the through hole, the region near the opening (through hole) on the outer surface of second metal layer 11, the inner wall surface of fluororesin layer 10, the inner wall surface of adhesive layer 12, the inner wall surface of first resin layer 16, and the surface of first metal layer 13 that defines a portion of the through hole and is near the adhesive layer, thereby obtaining circuit board 1. Connection portions 14 can be formed using the electroless plating and electrolytic plating in embodiment 2.

[0161] [Embodiment 4: Circuit Board (3)] A circuit board according to one embodiment of the present disclosure (hereinafter also referred to as "Embodiment 4") and a method for manufacturing the same will be described with reference to FIG. 5 . The circuit board 1 of Embodiment 4 is basically the same as the circuit board of Embodiment 1. It differs from the circuit board of Embodiment 1 in that it includes a filling portion 26 and a third metal layer 15. The filling portion 26 fills through holes formed in the fluororesin layer 10 and the adhesive layer 12 and contacts the connection portion 14. The third metal layer 15 is provided on the first main surface 10a of the fluororesin layer 10 and is embedded in the adhesive layer 12.

[0162] The filling portion 26 may contain a resin. This can reduce stresses on the connection portion, such as those caused by thermal expansion and contraction of the circuit board and external vibrations, thereby improving the reliability of the electrical connection of the connection portion. The filling portion 26 containing a resin can be easily formed, for example, by screen printing a paste-like material.

[0163] The through-hole may be filled with metal by plating to form the filled portion 26. This can reduce stress on the connection portion, such as stress due to thermal expansion and contraction of the circuit board and external vibration, thereby improving the reliability of the electrical connection of the connection portion. Filling by plating can be easily performed using the connection portion 14, so the filled portion 26 can be produced efficiently.

[0164] The third metal layer 15 forms an electrical circuit and may have the same structure as the first metal layer 13.

[0165] The method for manufacturing a circuit board according to the fourth embodiment is basically the same as the method for manufacturing a circuit board according to the second embodiment. Differences from the method for manufacturing a circuit board according to the second embodiment will be described below.

[0166] In embodiment 4, in the first step of embodiment 2, a fluororesin laminate 20 is prepared, which includes a fluororesin layer 10 including a first main surface 10a and a second main surface 10b opposite to the first main surface 10a, a second metal layer 11 provided on the second main surface 10b, and a third metal layer 15 provided on the first main surface 10a, and at least a part of the second metal layer 11 and at least a part of the third metal layer 15 are etched to form circuits on the second main surface 10b and the first main surface 10a.

[0167] In the fourth embodiment, after the sixth step of the second embodiment, a step is performed in which the through holes in the fluororesin layer 10 and the adhesive layer 12 are filled with, for example, a resin to form a filled portion 26 that contacts the connecting portion 14. This allows the circuit board 1 of the fourth embodiment to be obtained.

[0168] [Embodiment 5: Circuit Board (4)] A circuit board according to one embodiment of the present disclosure (hereinafter also referred to as "Embodiment 5") and a method for manufacturing the same will be described with reference to Figures 6, 7A, and 7B. Circuit board 1 of Embodiment 5 includes fluororesin layer 10, adherend layer 17, and adhesive layer 12 that bonds fluororesin layer 10 and adherend layer 17. Fluororesin layer 10 includes first main surface 10a facing adhesive layer 12 and second main surface 10b opposite first main surface 10a. Adhesion layer 17 is composed of first metal layer 13 and first resin layer 16.

[0169] The fourth main surface 16 b of the first resin layer 16 is in contact with the first B surface 12 a of the adhesive layer 12 that is farther from the fluororesin layer 10 .

[0170] The circuit board 1 further includes a second metal layer 11 provided on the second main surface 10b of the fluororesin layer 10. The fluororesin layer 10 and the second metal layer 11 may be in contact with each other. The fluororesin layer 10 and the second metal layer 11 may be bonded to each other by disposing a thin adhesive film (not shown) between the fluororesin layer 10 and the second metal layer 11.

[0171] The circuit board 1 further includes a connection portion 14. The connection portion 14 is made of metal and electrically connects the first metal layer 13 and the second metal layer 11. The circuit board 1 has a through hole formed therein that penetrates the first resin layer 16, the fluororesin layer 10, and the adhesive layer 12. That is, the first resin layer 16, the fluororesin layer 10, and the adhesive layer 12 have through holes that penetrate therethrough. The connection portion 14 is formed in the through hole. More specifically, the connection portion 14 is formed near the through hole on the inner wall surface of the fluororesin layer 10, the inner wall surface of the adhesive layer 12, the inner wall surface of the first resin layer 16, and the end face and outer surface of the first metal layer. The second metal layer 11 defines the bottom surface of the through hole, and the connection portion 14 is also formed on that bottom surface.

[0172] When the circuit board 1 is viewed from a direction perpendicular to the first main surface 10a, the first metal layer 13 is not formed in the region overlapping the through hole. The first metal layer 13 has an opening that leads to the through hole. When the circuit board 1 is viewed from a direction perpendicular to the first main surface 10a, the second metal layer 11 is formed in the region overlapping the through hole. The second metal layer 11 is a via bottom that fills the through hole.

[0173] From the first metal layer 13 to the second metal layer 11, the cross-sectional area of ​​the through-holes decreases continuously.

[0174] The method for manufacturing a circuit board according to the fifth embodiment is basically the same as the method for manufacturing a circuit board according to the second embodiment. Differences from the method for manufacturing a circuit board according to the second embodiment will be described below.

[0175] A first laminate 24 is obtained in the same manner as in steps 1 to 4 of embodiment 2 (see FIG. 7A ). In embodiment 5, in step 5 of embodiment 2, an opening is formed in the first metal layer 13. Using the area of ​​the first metal layer 13 other than the opening as a mask, laser processing is performed on the first resin layer 16, the adhesive layer 12, and the fluororesin layer 10 through the opening. As a result, at least a portion of the first resin layer 16, at least a portion of the adhesive layer 12, and at least a portion of the fluororesin layer 10 are removed, and through-holes are formed through the openings and the first resin layer 16, the adhesive layer 12, and the fluororesin layer 10 (see FIG. 7B ). In other words, the first resin layer 16, the fluororesin layer 10, and the adhesive layer 12 have through-holes that penetrate them.

[0176] In the sixth step of the second embodiment, an electroless plating layer is first formed by electroless plating on the end face of the first metal layer 13 that defines a portion of the through hole, the area near the opening (through hole) on the outer surface of the first metal layer 13, the inner wall surfaces of the fluororesin layer 10 and the adhesive layer 12, and the surface of the second metal layer 11 that defines a portion of the through hole near the adhesive layer. Subsequently, a plating layer is formed on the electroless plating layer by electrolytic plating (see FIG. 6 ). This plating layer is the connection portion 14.

[0177] In the fifth embodiment, in the laser processing, the layer in contact with the second metal layer 11, which is the via bottom of the blind via hole (the layer that receives more reflected energy from the second metal layer 11), is the fluororesin layer 10, which has excellent heat resistance. Therefore, the length of the gouge is reduced.

[0178] The embodiments will be described in more detail with reference to examples, but the embodiments are not limited to these examples.

[0179] [Preparation of Test Laminates] <Samples 1 to 16> As shown in FIG. 2A , a fluororesin laminate 20 including a fluororesin layer 10 and a second metal layer 11 provided on one main surface of the fluororesin layer was prepared.

[0180] The fluororesin laminate 20 was fabricated by the following procedure. The raw materials listed in the "Fluororesin Layer" column of "Raw Materials" in Tables 1 and 2 were mixed in the mass ratios listed in Tables 1 and 2 to obtain a mixture. For example, for Sample 6, polytetrafluoroethylene powder (referred to as "PTFE" in Tables 1 and 2), silica, and titanium oxide were mixed in a mass ratio of 100:190:10. Next, 17 mass% naphtha was added relative to the total mass of the polytetrafluoroethylene powder, silica, and titanium oxide. This was molded into a sheet and then dried in a constant temperature oven to remove the naphtha, obtaining a fluororesin sheet (corresponding to the fluororesin layer 10) with an average thickness of 130 μm. Next, a perfluoroalkoxyalkane layer with an average thickness of 2 μm was formed on one side of a copper foil (corresponding to the second metal layer) with an average thickness of 18 μm. This copper foil and the fluororesin sheet were laminated together so that the perfluoroalkoxyalkane layer and the fluororesin sheet were in contact with each other. The laminate was heated at 350° C. for 40 minutes while being compressed at a pressure of 4 MPa, to obtain a fluororesin laminate 20 .

[0181] 2A, the first resin laminate 22 is composed of the first metal layer 13 and the first resin layer 16, but the test laminate is composed only of the first metal layer 13. The first metal layer 13 is composed of copper foil with an average thickness of 18 μm.

[0182] The adhesive layer 12, with the exception of Sample 16, was prepared using the following procedure. The raw materials listed in the "Raw Materials" column under "Adhesive Layer" in Tables 1 and 2 were mixed in the mass ratios listed in Tables 1 and 2 to obtain a mixture. For example, for Sample 1, acid-modified polypropylene and epoxy resin were dissolved in a solvent at a mass ratio of 90:10. This solution was mixed with silica so that the mass ratio of acid-modified polypropylene, epoxy resin, and silica was 90:10:100. The solvent was a mixture of methyl ethyl ketone, toluene, ethyl acetate, and cyclohexane in an appropriate ratio to dissolve the acid-modified polypropylene and epoxy resin. A mixture sheet was formed using a doctor blade method, and the solvent was removed by drying to obtain a bonding sheet (corresponding to adhesive layer 12) with an average thickness of 30 μm. The thickness of the mixture sheet can be adjusted using the doctor blade method. In Tables 1 and 2, "SEEPS" represents styrene-ethylene-ethylene-propylene-styrene block copolymer, and "PPE" represents polyphenylene ether. For sample 16, polytetrafluoroethylene powder, perfluoroalkoxyalkane powder (referred to as "PFA" in Tables 1 and 2), and silica were mixed in a mass ratio of 90:10:80. Next, 17 mass% of naphtha was mixed with the total mass of the polytetrafluoroethylene powder, perfluoroalkoxyalkane powder, and silica. This was molded into a sheet, and then dried in a thermostatic oven to remove the naphtha, resulting in a bonding sheet (corresponding to adhesive layer 12) with an average thickness of 30 μm.

[0183] The first metal layer 13, the adhesive layer 12, and the fluororesin laminate 20 were laminated in this order, with the fluororesin layer 10 and the first metal layer 13 in contact with the adhesive layer 12. The laminate was held at a temperature of 170°C for 30 minutes, and a pressure of 3 MPa was applied. As a result, in Samples 1 to 15, the first metal layer 13 and the fluororesin laminate 20 were bonded due to softening of the adhesive layer 12, and a test laminate could be obtained. If a test laminate could be obtained, it is indicated as "OK" in the "Lamination Possible" column in Tables 1 and 2. For Sample 16, it was not possible to bond the first metal layer 13 and the fluororesin laminate 20. If a test laminate could not be obtained, it is indicated as "Not OK" in the "Lamination Possible" column in Tables 1 and 2.

[0184]

[0185]

[0186] <Measurement of Thermal Expansion Coefficient of Fluororesin Layer> The thermal expansion coefficient of the fluororesin layer of each sample before lamination was measured. A thermal dilatometer (LIX-2) manufactured by Advance Riko Co., Ltd. was used to measure the linear expansion coefficient of the fluororesin layer in the thickness direction over a temperature range of 20°C to 120°C. As described above, in the present disclosure, the linear expansion coefficient of the fluororesin layer in the thickness direction is the thermal expansion coefficient of the fluororesin layer. The results are shown in the "Thermal Expansion Coefficient" column of "Fluororesin Layer" in Tables 1 and 2. In the "Evaluation" column of "Thermal Expansion Coefficient," a thermal expansion coefficient of less than 40 ppm / °C is indicated as A, a thermal expansion coefficient of 40 ppm / °C or more but less than 90 ppm / °C is indicated as B, and a thermal expansion coefficient of 90 ppm / °C or more is indicated as C. A rating of A or B indicates that the thermal expansion coefficient of the fluororesin layer is small. A rating of C indicates that the thermal expansion coefficient of the fluororesin layer is large.

[0187] <Composition of Fluororesin Layer and Adhesive Layer> The volume-based content (vol %) and mass-based content (mass %) of the first inorganic filler in the fluororesin layer of each sample are shown in the "vol %" and "mass %" columns of "First inorganic filler content" under "Fluororesin layer" in Tables 1 and 2. Of the raw materials listed in Tables 1 and 2, silica and titanium oxide correspond to the first inorganic filler. When a sample contains both silica and titanium oxide, the content is calculated based on the total of these.

[0188] The volumetric content (volume %) and mass content (mass %) of the second inorganic filler in the adhesive layer of each sample are shown in the "volume %" and "mass %" columns of "Second inorganic filler content" in "Adhesive layer" in Tables 1 and 2. Of the materials listed in Tables 1 and 2, silica and boron nitride correspond to the first inorganic filler. When a sample contains both silica and boron nitride, the content is calculated based on the total of these.

[0189] Based on the mass-based content X (mass%) of the first inorganic filler in the fluororesin layer and the mass-based content Y (mass%) of the second inorganic filler in the adhesive layer, the absolute value Z of the difference between X and Y was calculated. The results are shown in the "Z" column in Tables 1 and 2.

[0190] <Evaluation of adhesive layer> The glass transition temperature of the adhesive layer of each sample was measured. In addition, the elastic modulus B at 20°C and the elastic modulus A at 160°C of the adhesive layer of each sample were measured, and the ratio A / B was calculated. The specific measurement method is described in embodiment 1. The results are shown in the "glass transition temperature" and "A / B" columns of "adhesive layer" in Tables 1 and 2.

[0191] <Evaluation of Peel Strength> Peel strength was evaluated in accordance with JIS-K6854-2 (1999). Specifically, evaluation was performed using a 180° peel test. A 66 μm thick polyimide tape ("P221" manufactured by Nitto Denko Corporation) was attached to the first metal layer of the test laminate of each sample. The thickness of the polyimide tape substrate was 25 μm. The interface between the fluororesin layer and the adhesive layer was used as the peel starting point. The polyimide tape, the first metal layer, and the adhesive layer were pulled at 50 mm / min so that the peel direction was 180° relative to the adhesive surface, and the peel strength was measured. The results are shown in the "Peel Strength" column of Tables 1 and 2.

[0192] <Measurement of the length of the hollow> For each sample laminate, a through hole was formed from the second metal layer, and the length of the hollow in the fluororesin layer near the interface between the fluororesin layer and the adhesive layer was measured. The method for forming the through hole was as follows.

[0193] A dry film is attached to the second metal layer, and the second metal layer is etched by exposure. Thereafter, the dry film is peeled off to form an opening of φ125 μm in the second metal layer.

[0194] CO in the opening ２ A through hole is formed by irradiating a laser. ２ The laser output is set to 18.5 W. As a result, the fluororesin layer and the adhesive layer are removed, and the first metal layer is exposed with a diameter of 110 μm. The through hole is a blind via hole.

[0195] The laminate was cut out so that a cross section including the central axis of the blind via hole was exposed, and the length of the gouge in the fluororesin layer near the interface between the fluororesin layer and the adhesive layer was measured in the cross section. The method for measuring the gouge length is described in embodiment 1. The results are shown in the "Gouge Length" column of Tables 1 and 2. In the "Evaluation" column for gouge length, A is given for a gouge length of less than 15 μm, B is given for a gouge length of 15 μm or more but less than 25 μm, and C is given for a gouge length of 25 μm or more. If the evaluation is A or B, it is determined that gouge occurrence has been suppressed. If the evaluation is C, it is determined that gouge occurrence has not been suppressed.

[0196] <Discussion> Samples 3 to 5, 7 to 10, 12, 14, and 15 are examples. These samples are circuit boards in which a fluororesin layer and an adherend layer are bonded by an adhesive layer by pressing at low temperature. It was confirmed that these samples suppress the occurrence of gouging near the interface between the fluororesin layer and the adhesive layer, even when a through hole penetrating the fluororesin layer and the adhesive layer is formed.

[0197] Samples 1, 2, 6, 11, and 13 are comparative examples. It was confirmed that in these samples, when a through hole penetrating the fluororesin layer and the adhesive layer was formed, the occurrence of gouging was not suppressed.

[0198] In Sample 16, the fluororesin layer and the adherend layer could not be bonded by pressing at low temperatures. This is presumably because the fluororesin (PTFE, PFA) content of the adhesive layer resin was 100 mass %, and the adhesive layer 12 did not soften during the pressing process. Since no test laminate was obtained for Sample 16, the laminate could not be laser-processed. Therefore, the length of the gouge in Sample 16 could not be measured.

[0199] It is intended from the beginning that the configurations of the above-described embodiments and examples may be appropriately combined and modified in various ways. The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined not by the above-described embodiments and examples but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope of the claims.

[0200] REFERENCE SIGNS LIST 1 Circuit board 10 Fluororesin layer 10a First main surface 10b Second main surface 11 Second metal layer 12 Adhesive layer 12a First B surface 13 First metal layer 13a First A surface 14 Connection portion 15 Third metal layer 16 First resin layer 16a Third main surface 16b Fourth main surface 17 Adherend layer 20 Fluororesin laminate 22 First resin laminate 24 First laminate 25 Cavity 26 Filled portion 27 Inner wall surface L1 Central axis P1 Interface

Claims

1. A fluororesin layer; An adherend layer; An adhesive layer that adheres the fluororesin layer and the adherend layer, The fluororesin layer contains polytetrafluoroethylene and a first inorganic filler, The content of the first inorganic filler in the fluororesin layer is 50% by volume or more and 66% by volume or less, The adhesive layer includes a resin and a second inorganic filler, The content of the fluororesin in the resin is 5% by mass or less, The content of the second inorganic filler in the adhesive layer is 29 vol% or more and 47 vol% or less, A circuit board, the circuit board having a through hole formed through the fluororesin layer and the adhesive layer.

2. The circuit board according to claim 1 , wherein the first inorganic filler comprises silica.

3. The circuit board according to claim 1 , wherein the second inorganic filler includes silica.

4. The circuit board according to claim 1 , wherein the second inorganic filler contains boron nitride.

5. At least one of an inner wall surface of the fluororesin layer that defines a portion of the through hole and an inner wall surface of the adhesive layer that defines a portion of the through hole has a recess, The circuit board according to claim 1 or 2, wherein the length of the recess is less than 25 μm.

6. 3. The circuit board according to claim 1, wherein a ratio A / B of a modulus of elasticity A at 160° C. to a modulus of elasticity B at 20° C. of the adhesive layer is 0.08 or less.

7. 3. The circuit board according to claim 1, wherein the resin includes a polyolefin or a polystyrene-based elastomer.

8. The adherend layer includes a first metal layer and a first resin layer, 3. The circuit board according to claim 1, wherein the first metal layer is provided on a surface of the first resin layer facing the fluororesin layer.

9. The adherend layer includes a first metal layer and a first resin layer, 3. The circuit board according to claim 1, wherein the first resin layer is provided on a surface of the first metal layer facing the fluororesin layer.

10. the fluororesin layer includes a first main surface facing the adhesive layer and a second main surface opposite the first main surface; The circuit board according to claim 8 , further comprising a second metal layer provided on the second main surface.

11. a connection portion electrically connecting the first metal layer and the second metal layer; The circuit board according to claim 10 , wherein the connection portion is formed in the through hole.

12. The circuit board according to claim 10 , wherein the first metal layer is formed in an area overlapping with the through hole when viewed from a direction perpendicular to the second main surface.

13. The circuit board according to claim 10 , wherein the second metal layer is formed in an area overlapping with the through hole when viewed from a direction perpendicular to the first main surface.

14. A method for manufacturing the circuit board according to claim 1 or 2, comprising the steps of: a step of maintaining a laminate in which the fluororesin layer, the adhesive layer, and the adherend layer are laminated in this order at a temperature of 180° C. or less to soften the adhesive layer, thereby adhering the fluororesin layer and the adherend layer.

15. A step of preparing a fluororesin laminate including a fluororesin layer including a first main surface and a second main surface opposite to the first main surface, and a second metal layer provided on the second main surface; A step of preparing a first resin laminate including a first resin layer including a third main surface and a fourth main surface opposite to the third main surface, and a first metal layer provided on the third main surface; providing an adhesive layer; a step of laminating the fluororesin laminate, the adhesive layer, and the first resin laminate in this order such that the first main surface is in contact with the adhesive layer, and maintaining the adhesive layer at a temperature of 180° C. or less to soften the adhesive layer, thereby bonding the fluororesin laminate and the first resin laminate to form a first laminate; removing at least a portion of the fluororesin layer and at least a portion of the adhesive layer to form a through hole penetrating the fluororesin layer and the adhesive layer; forming a connection portion on an inner wall surface of the fluororesin layer that defines a portion of the through hole and on an inner wall surface of the adhesive layer that defines a portion of the through hole; The fluororesin layer contains polytetrafluoroethylene and a first inorganic filler, The content of the first inorganic filler in the fluororesin layer is 50% by volume or more and 66% by volume or less, The adhesive layer includes a resin and a second inorganic filler, The content of the fluororesin in the resin is 5% by mass or less, A method for manufacturing a circuit board, wherein the content of the second inorganic filler in the adhesive layer is 29 volume % or more and 47 volume % or less.

16. 16. The method for manufacturing a circuit board according to claim 15, wherein the step of preparing the first resin laminate further comprises the step of forming a first circuit in the first resin laminate by etching at least a portion of the first metal layer.

17. 17. The method for producing a circuit board according to claim 15 or 16, wherein the step of preparing the fluororesin laminate further comprises the step of forming a second circuit in the fluororesin laminate by etching at least a part of the second metal layer.

18. 17. The method for manufacturing a circuit board according to claim 15, wherein the step of forming the first laminate further comprises the step of forming a second circuit in the fluororesin laminate by etching at least a part of the second metal layer.

19. The method for manufacturing a circuit board according to claim 15 or 16, wherein the through holes are formed by laser processing.

20. At least one of the inner wall surface of the fluororesin layer and the inner wall surface of the adhesive layer has a recess, The method for manufacturing a circuit board according to claim 15 or 16, wherein the length of the recess is less than 25 μm.