Method for manufacturing a semiconductor device

Abstract

The present invention comprises: a template substrate including a first seed region and a growth suppression region aligned in a first direction; and a first semiconductor part positioned above the template substrate. The first semiconductor part has a first base section positioned on the first seed region, and a first wing section that is connected to the first base section and that faces the growth suppression region with a first gap therebetween. The first wing section includes a wing edge positioned above the growth suppression region, and with regard to the first gap, the ratio of the width in the first direction to the thickness below the wing edge is 5.0 or more.

Description

Semiconductor substrate, semiconductor substrate manufacturing method and manufacturing apparatus, and semiconductor device manufacturing method

[0001] The present disclosure relates to semiconductor substrates and the like.

[0002] The development of technology for forming semiconductor elements using gallium nitride (GaN) on silicon substrates or sapphire substrates is progressing. However, when a GaN layer is formed on a heterogeneous substrate, the GaN layer is 10 ８ cm －２ On the silicon substrate, ９ cm －２ At defect densities in the low range, threading dislocations occur at the interface between the heterogeneous material (the interface between the substrate and the deposited film), degrading the characteristics and reliability of devices formed thereon. Therefore, the ELO (Epitaxial Lateral Overgrowth) method has been investigated as a technique for forming a low-defect-density GaN layer on a heterogeneous substrate. For example, a mask pattern that prevents the GaN layer from growing is formed on a base substrate including a heterogeneous substrate and a seed layer (e.g., a GaN layer). The GaN layer is then laterally grown on the masked portion, starting from the seed layer exposed in the opening where the masked portion is not present. This reduces the defect density of the GaN layer on the masked portion (see Patent Document 1). However, the laterally growing GaN layer comes into contact with the masked portion, which can reduce the flatness of the GaN layer depending on the deposition conditions.

[0003] In Patent Document 2, a semiconductor layer is grown laterally on the void, and a device layer (semiconductor laminated film) is also formed on the lower surface (back surface) of the semiconductor layer.

[0004] JP 2013-251304 A JP 2017-535051 A

[0005] The technique of Patent Document 2 has a problem in that it is difficult to form a wide device layer.

[0006] The semiconductor substrate according to the present disclosure comprises a template substrate including a first seed region and a growth inhibition region aligned in a first direction, and a first semiconductor portion located above the template substrate, wherein the first semiconductor portion has a first base portion located on the first seed region and a first wing portion connected to the first base and facing the growth inhibition region via a first gap, the first wing portion including wing ends located above the growth inhibition region, and the ratio of the width of the first gap in the first direction to the thickness below the wing ends is 5.0 or greater.

[0007] A wide device layer (functional layer) can be formed.

[0008] 1 is a plan view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 2 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 3 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 4 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 5 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 6 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 7 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 8 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 9 is a block diagram showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 10 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to the present embodiment; FIG. 11 is a block diagram showing an apparatus for manufacturing a semiconductor substrate according to the present embodiment; FIG. 12 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to the present embodiment; FIG. 13 is a Raman spectrum of a base portion and a wing portion of an ELO layer according to a comparative example; FIG. 14 is a Raman spectrum of a base portion and a wing portion of an ELO layer (semiconductor portion) according to the first embodiment; FIG. 15 is a plan view of a semiconductor substrate including an upper layer portion; FIG. 16 is a cross-sectional view of a semiconductor substrate including an upper layer portion; FIG. 17 is a plan view showing a method for element isolation in the first embodiment; FIG. 18 is a cross-sectional view showing a method for element isolation in the first embodiment; 26 is a graph showing the results of an XRD reflection scan measurement of a semiconductor portion of Example 1. FIG. 27 is a plan view showing the configuration of a semiconductor substrate of Example 5. FIG. 28 is a cross-sectional view showing the configuration of a semiconductor substrate of Example 5. FIG. 29 is a cross-sectional view showing a method for manufacturing the semiconductor substrate of FIG. 25. FIG. 29 is a cross-sectional view showing a method for manufacturing the template substrate of FIG. 25. FIG. 30 is a cross-sectional view showing a method for manufacturing the template substrate. FIG. 31 is a cross-sectional view showing the configuration of a semiconductor substrate of Example 6. FIG. 32 is a cross-sectional view showing the configuration of a semiconductor substrate of Example 6. FIG. 33 is a cross-sectional view showing the configuration of a semiconductor substrate of Example 7. FIG. 34 is a flowchart showing a method for manufacturing a semiconductor device of Example 8. FIG. 35 is a cross-sectional view showing a method for manufacturing a semiconductor device of Example 8.

[0009] FIG. 1 is a plan view illustrating the configuration of a semiconductor substrate according to this embodiment. FIG. 2 is a cross-sectional view illustrating the configuration of a semiconductor substrate according to this embodiment. As shown in FIGS. 1 and 2 , a semiconductor substrate 10 includes a template substrate TS including a first seed region S1 and a growth-inhibited region (non-seed region) DA aligned in a first direction X1, and a first semiconductor portion 8A positioned above the template substrate TS. The first semiconductor portion 8A includes a first base portion B1 positioned above the first seed region S1 and a first wing portion F1 connected to the first base portion B1 and facing the growth-inhibited region DA across a first void J1. The first wing portion F1 includes an edge (wing end) E1 positioned above the growth-inhibited region DA. The ratio of the width WJ of the first void J1 in the first direction X1 to the thickness TJ (aspect ratio of the void) is 5.0 or greater. This allows a wide device layer (functional layer) to be formed on the first wing portion F1. The thickness TJ may be the thickness below the wing end E1 in the first gap J1 (the length in the c-axis direction between the lower surface of the wing end E1 and the surface of the template substrate TS). The width of the first wing portion F1 in the first direction X1 may be 5.0 times or more the thickness TJ of the first gap J1.

[0010] The template substrate TS may have a mask pattern 6 including a mask portion 5 that functions as a growth inhibition region DA and a first opening K1 that functions as a first seed region S1 (exposing the upper surface of the seed 3 as the first seed region S1). Specifically, the surface (upper surface) of the mask portion 5 becomes the growth inhibition region DA. The template substrate TS may include a main substrate 1 (heterogeneous substrate) having a lattice constant different from that of the first semiconductor portion 8A, and a seed portion 3. The template substrate TS may have a ridge portion R on its upper surface side, and the first seed region S1 may be located on the upper surface of the ridge portion R. Specifically, the surface (upper surface) of the seed portion 3 becomes the first seed region S1.

[0011] The first gap J1 is the space between the growth inhibition region DA and the first wing portion F1. The direction from the main substrate 1 toward the first semiconductor portion 8A is defined as "upward." Viewing an object with a line of sight parallel to the normal direction of the semiconductor substrate 10 (including perspective) is called "planar view." The first seed region S1 (surface of the seed portion 3) and the growth inhibition region DA (surface of the mask portion 5) are positioned at different positions in the thickness direction of the substrate (vertical direction), but they only need to be aligned in the first direction X1 (direction perpendicular to the thickness direction of the substrate) in the planar view.

[0012] The first semiconductor portion 8A contains a nitride semiconductor as a main component. The nitride semiconductor can be expressed as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), for example. Specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0013] The first semiconductor portion 8A may be doped (e.g., n-type including donors) or non-doped. A semiconductor substrate means a substrate including a semiconductor, and the main substrate 1 of the template substrate TS may or may not include a semiconductor (e.g., silicon, silicon carbide). An example of a main substrate 1 that does not include a semiconductor is a sapphire substrate. The main substrate 1 may be a free-standing substrate (wafer). The main substrate 1 and the seed portion 3 may be collectively referred to as a base substrate. The template substrate TS including the base substrate and the mask pattern 6 may be referred to as a growth substrate.

[0014] The first direction X1 may be the a-axis direction (<11-20> direction) of the first semiconductor portion 8A (nitride semiconductor such as GaN). The second direction X2 may be the m-axis direction (<1-100> direction) of the first semiconductor portion 8A. The thickness direction Z of the semiconductor substrate 10 may be the c-axis direction (<0001> direction) of the first semiconductor portion 8A.

[0015] The first semiconductor portion 8A can be formed by an epitaxial lateral overgrowth (ELO) method, starting from the seed portion 3 exposed below the first opening K1. Of the first semiconductor portion 8A, the base portion B1 located above the first opening K1 becomes a dislocation inherited portion with many threading dislocations, while the first wing portion F1 located above the mask portion 5 becomes a low-defect portion with a lower threading dislocation density than the dislocation inherited portion. The second semiconductor portion 8C grows laterally on the mask portion 5 starting from the seed portion 3 exposed below the second opening K2, and the growth is stopped before joining the first semiconductor portion 8A.

[0016] In this way, by forming the edge E1 of the first wing portion F1 above the growth inhibition region DA and setting the aspect ratio of the first gap J1 (the ratio of the width W1 in the first direction X1 to the thickness TJ) to 5.0 or more, a wide first wing F1 with high crystallinity (low defect density) can be quickly formed, and the flatness of the first wing F1 can be improved. Furthermore, when an upper layer portion (device layer, functional layer) including an active layer is formed on the first semiconductor portion 8A, the phenomenon in which the material of the upper layer portion flows around to the back surface of the first wing portion F1 can be suppressed. The upper layer portion may include, for example, a nitride semiconductor layer (including the active layer).

[0017] The semiconductor substrate 10 may include a second semiconductor portion 8C located above a template substrate TS. The template substrate TS may have a second seed region S2 adjacent to the first seed region S1 across a growth inhibition region DA in a planar view. The second semiconductor portion 8C has a second base portion B2 located on the second seed region S2 and a second wing portion F2 connected to the second base portion B2 and facing the growth inhibition region DA across a second void J2. The first wing portion F1 and the second wing portion F2 are aligned in the first direction X1 with a gap GP interposed therebetween. The ratio of the width WJ in the first direction X1 to the thickness TJ of the second void J2 may be 5.0 or greater. The thickness TJ may be the thickness below the wing end E2 of the second void J2.

[0018] In the following, the first semiconductor portion 8A and the second semiconductor portion 8C may be collectively referred to as semiconductor portion (semiconductor layer) 8, the first wing portion F1 and the second wing portion F2 may be collectively referred to as wing portion F, the first base portion B1 and the second base portion B2 may be collectively referred to as base portion B, the first void J1 and the second void J2 may be collectively referred to as void J, the first opening K1 and the second opening K2 of the mask pattern 6 may be collectively referred to as opening K, and the first seed region S1 and the second seed region S2 may be collectively referred to as seed region S.

[0019] The ratio of the width to the thickness of the first wing portion F1 in the first direction X1 may be 2.0 or more, 5.0 or more, 10 or more, 20 or more, 50 or more, 100 or more, or 200 or more. By setting the ratio of the thickness to the width of the first wing portion F1 to ½ or less, the deviation between the c-axis direction of the first base portion B1 and the c-axis direction of the tip of the first wing portion F1 can be 0.2° or less. The width of the first wing portion F1 in the first direction X1 may be 7.0 μm or more, 10.0 μm or more, 20.0 μm or more, 40.0 μm, or 100 μm or more. The width of the first wing portion F1 in the first direction X1 is preferably 80.0 μm or less. This reduces the risk of the semiconductor portion 8 warping toward the substrate due to gravity. The thickness of the first wing portion F1 may be, for example, 10.0 μm or less, 5.0 μm or less, or 2.0 μm or less. As shown in FIG. 2 , the width of the gap GP may be greater than the thickness of the first gap J1. The ratio of the width of the first wing portion F1 to the width of the first base portion B1 may be 3.0 or more. The thickness of the first gap J1 may be 3.0 μm or less. The thickness of the first wing portion F1 and the first base portion B1 may be the same. The thickness of the mask portion 5 may be 1 μm or less, or may be 50 nm or less. The seed portion 3 is formed by doping argon or oxygen at a concentration of 2×10 １８ / cm ３ It may be made of a nitride semiconductor (AlN, AlON, GaN-based semiconductor, etc.) containing the above.

[0020] 1, each of the first seed region S1 and the growth inhibition region DA may have a shape whose longitudinal direction is a second direction X2 that is perpendicular to the first direction X1. The main substrate 1 may be a silicon substrate, a sapphire substrate, or a silicon carbide substrate, and the first semiconductor portion 8A may include a nitride semiconductor (e.g., a GaN-based semiconductor).

[0021] 2, the template substrate TS may have a ridge portion R on its upper surface side, and the seed portion 3 may be included in the ridge portion R. The upper surface of the ridge portion R may be composed of the seed portion 3, and the side surface of the ridge portion R may be composed of the mask portion 5. That is, the upper surface of the ridge portion R may have the seed portion 3, and the side surface of the ridge portion R may have the mask portion 5. Alternatively, the ridge portion R may have the seed portion 3 on its upper surface, and the side surface of the ridge portion R may be composed of the mask portion 5, and may not have the seed portion 3. The seed portion 3 may be locally arranged in the ridge portion R, and may not be arranged below the mask portion 5.

[0022] The main substrate 1 may include a protrusion Q on its upper surface, and the seed portion 3 may be located on the protrusion Q. The side surface of the ridge portion R may not be in contact with the first wing portion F1. The entire side surface of the ridge portion R may face the first gap J1. This reduces the contact area between the ridge portion R and the wing portion F1, and can reduce defects in the wing portion F1. The seed portion 3 may not be arranged below the mask portion 5. The nitride semiconductor included in the first semiconductor portion 8A may be a GaN-based semiconductor, and the first gap J1 may have a width-to-thickness ratio of 20.0 or more. The first semiconductor portion 8A may have two paired first wing portions F1 extending from the first base portion B1 in the first direction X1 and the opposite direction.

[0023] 3 is a cross-sectional view showing the configuration of the semiconductor substrate according to this embodiment. As shown in Fig. 3, the ridge portion R may include a buffer portion 2 and a seed portion 3. In this case, the base portion consisting of the buffer portion 2 and the seed portion 3 may be arranged in a stripe pattern.

[0024] 4 is a cross-sectional view showing the configuration of the semiconductor substrate according to this embodiment. As shown in FIG. 4, the first wing portion F1 may be thicker than the first base portion B1. The side surface of the ridge portion R (mask portion 5) may be in contact with the first wing portion F1. If the first wing portion F1 does not contact the growth suppression region DA (mask portion 5), a gap J1 is formed, and this does not pose a problem.

[0025] 5 is a cross-sectional view showing the configuration of the semiconductor substrate according to this embodiment. As shown in FIG. 5, the ridge portion R may be located on the flat upper surface of the main substrate 1.

[0026] 6 is a cross-sectional view showing the configuration of the semiconductor substrate according to this embodiment. As shown in FIG. 6, the buffer portion 2 includes a lower portion 2 a and an upper portion 2 b, the lower portion 2 a is planar, and the seed portion 3 and the upper portion 2 b are not disposed below the mask portion 5, but only the lower portion 2 a is disposed. The ridge portion R may include the upper portion 2 b of the buffer portion 2.

[0027] 7 is a cross-sectional view showing the configuration of the semiconductor substrate according to this embodiment. As shown in FIG. 7, the first wing portion F1 may be divided into a plurality of parts PA arranged in a second direction X2 perpendicular to the first direction X1.

[0028] Fig. 8 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. Fig. 9 is a plan view showing the configuration of a semiconductor substrate according to this embodiment. As shown in Figs. 8 and 9, the semiconductor substrate 10 may include an upper layer portion 9 located above the first semiconductor portion 8A and including an active layer and a p-type layer. An anode EA and a cathode EC may be provided on the upper layer portion 9.

[0029] 10A is a flowchart illustrating a method for manufacturing a semiconductor substrate according to this embodiment. The method for manufacturing a semiconductor substrate according to this embodiment includes the steps of: preparing a template substrate TS (S10) including a first seed region S1 and a growth inhibition region DA aligned in a first direction X1; and growing a first semiconductor portion 8A (8A) including a first base portion B1 located on the first seed region S1 and a first wing portion F1 connected to the first base portion B1 and facing the growth inhibition region DA across a first void J1 (S20) such that the width of the first wing portion F1 in the first direction X1 is 5.0 times or more the thickness of the first void J1. A step S30 may be performed in which the growth of the first wing portion F1 and the second wing portion F2, which grows toward the first wing portion F1, is stopped before the first wing portion F1 meets the second wing portion F2. The template substrate TS includes a seed portion 3 including the first seed region S1. The seed portion 3 may be formed by sputtering.

[0030] 10B is a flowchart showing a method for manufacturing a semiconductor substrate according to the present embodiment. After step S10, step S20B may be performed in which a first semiconductor portion 8A having a first base portion B1 located on the first seed region S1 and a first wing portion F1 connected to the first base portion B1 and facing the growth inhibition region DA across a first gap J1 is grown such that the width (Ws) of the first semiconductor portion 8A (as a whole including both wings) in the first direction X1 is 5.0 times or more the thickness (Th) of the first semiconductor portion 8A.

[0031] Fig. 11 is a block diagram showing a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 50 includes an apparatus M10 that performs step S10 of Fig. 10, an apparatus M20 that performs step S20A of Fig. 10A (step S20B of Fig. 10B), and a control device MC that controls the apparatus M10 and the apparatus M20. The apparatus M20 may be an MOCVD apparatus, and the control device MC may perform step S30 via the apparatus M20.

[0032] Example 1 As the main substrate 1, a silicon substrate, a silicon carbide substrate (4H-SiC, 6H-SiC substrate), a sapphire substrate, a nitride substrate (GaN, AlN substrate, etc.), a ScMgAlO substrate, etc. can be used.

[0033] The seed portion 3 is formed above the main substrate 1 and serves as a starting point for growing the semiconductor portion 8. The seed portion 3 only needs to be formed in at least a part of the opening K (of the mask pattern 6), and may be planar or patterned (for example, striped). The seed portion 3 may be formed from a GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, AlGaInN, Al, or the like formed at a low temperature (500°C or less). The thickness of the seed portion 3 is approximately 10 nm to 500 nm.

[0034] A buffer section 2 may be formed between the main substrate 1 and the seed section 3 (e.g., a GaN layer), and the buffer section 2 improves the crystallinity and flatness of the seed section 3. The buffer section 2 may be planar or may have a pattern (e.g., stripe shape) that matches the seed section 3. The buffer section 2 may be made of a GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, AlGaInN, Al, or the like formed at a low temperature (500°C or less). The thickness of the buffer section 2 is approximately 10 nm to 500 nm. When a silicon substrate is used for the main substrate 1, it is desirable that the buffer section 2 in contact with the silicon substrate does not contain gallium in order to suppress meltback.

[0035] The layer between the main substrate 1 and the semiconductor portion 8 may be referred to as an underlayer (including at least one of the buffer portion 2 and the seed portion 3). A GaN layer may be formed as the underlayer (e.g., the seed portion 3) by sputtering. In this case, for example, a sputtering target containing gallium nitride as the main component (containing 25 atm% or more of gallium) and having an oxygen content of 5 atm% or less may be used, and the sputtering gas pressure may be set to less than 0.3 Pa. The sputtering method may be selected appropriately from DC sputtering, RF sputtering, AC sputtering, DC magnetron sputtering, ECR (Electron Cyclotron Resonance) sputtering, RF magnetron sputtering, PSD (Pulse Sputter Deposition), Laser Ablation, and the like.

[0036] The sputtering target used may have an oxygen content of 5 atm% or less, 3 atm% or less, or 1 atm% or less in order to improve the crystallinity of the entire film. The purity is also preferably as high as possible, and the metal impurity content may be less than 0.1% or less than 0.01%. When forming a GaN layer by sputtering, using a gallium nitride target with a low oxygen content can provide effects such as improved surface flatness, improved crystallinity, and suppression of surface hillocks (protrusions).

[0037] When a nitride semiconductor (AlN, GaN, etc.) is formed by sputtering as the underlayer, the degree of vacuum in the apparatus before film formation is set to 3×10 －５ Pa or less or 1 x 10 －５ The pressure may be set to Pa or less. Prior to film formation, a base substrate (such as a main substrate or a main substrate with a buffer) may be pretreated to remove organic layers or irregularities on the surface of the base substrate, thereby enabling epitaxial growth. Specific examples of pretreatment include reverse sputtering, acid treatment, and UV treatment, but reverse sputtering is preferable from the viewpoint of preventing re-adhesion of impurities after treatment. Reverse sputtering is a method of cleaning the surface of the base substrate by bombarding plasmatized atoms with the base substrate. The substrate temperature during film formation may be room temperature, but film quality can be further improved by heating the substrate (for example, at 400° to 1000°).

[0038] The power density during discharge is 5 W / cm ２ or less than 1.5 W / cm ２ The lower limit of the power density is 0.1 W / cm ２ or 0.3 W / cm ２ The power density is the power applied during discharge divided by the area of ​​the sputtering target. If the power density is too high, the raw material may be sputtered from the target in a clustered state.

[0039] In Example 1, a GaN underlayer (e.g., a seed portion) was formed by RF sputtering. A gallium nitride target (oxygen content: 0.4 atom%) was used, the film formation pressure was set to 0.1 Pa, and 20 to 40 sccm of nitrogen gas was introduced. Although argon gas was not used in Example 1, argon gas may of course be introduced. The discharge density was 125 W / cm. ２ The film formation temperature was room temperature.

[0040] When the underlayer (including at least one of the buffer portion 2 and the seed portion 3) is formed using a sputtering method, a laser ablation method, or the like, the internal stress can be controlled from compressive stress to tensile stress depending on the film formation conditions, and therefore the stress on the semiconductor portion 8 can be controlled. The internal stress can also be controlled by the amount of argon taken into the underlayer. The stress on the semiconductor portion 8 may be controlled by locally (pattern-wise) forming the underlayer on the undersubstrate.

[0041] The mask pattern 6 is formed on the base substrate using a material that suppresses vertical growth (growth in the c-axis direction) of the nitride semiconductor and enables lateral growth (e.g., growth in the a-axis direction). The openings K (exposed portions of the seed portions 3) in the mask pattern 6 serve as the starting points for growth of the semiconductor portions 8. Examples of materials for the mask portions 5 of the mask pattern 6 include silicon nitride, silicon carbide, silicon carbonitride, diamond-like carbon, silicon oxide, silicon oxynitride, etc., as well as silicon-free materials such as titanium nitride, molybdenum nitride, tungsten nitride, and tantalum carbide, as well as high-melting-point metals (molybdenum, tungsten, platinum, etc.). The mask portions 5 may be a single-layer film made of one of these materials or a multilayer film made up of a combination of multiple materials. The thickness of the mask portions 5 may be approximately 5 nm to 2 μm.

[0042] FIG. 12 is a cross-sectional view showing the configuration of a semiconductor substrate according to Example 1. In FIG. 12 , a silicon substrate is used as the main substrate 1, and a seed portion 3 is formed on a portion of the upper surface of the main substrate 1. A ridge portion R including the seed portion 3 and the main substrate 1 is formed in a stripe pattern. A mask portion 5 is formed on the side surface of the ridge portion R and on the surface of the main substrate 1. The mask pattern 6 has a first opening K1 on at least a portion of the upper surface of the ridge portion R. A first semiconductor portion 8A is formed above the first opening K1, and a first gap J1 is located below the first wing portion F1. In other words, the first wing portion F1 is spaced apart from the mask portion 5 (growth suppression region DA). The width WJ of the first gap J1 is the distance in the first direction X1 from the side surface of the ridge R to the edge E of the first semiconductor portion 8A. The thickness (height) TJ of the first gap is the distance from the upper surface of the mask portion 5 to the lower surface (back surface) of the first semiconductor portion 8A. The ridge width WR was 5 μm, and the ridge pitch width PR was 55 μm.

[0043] 13 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 1. The semiconductor substrate of Example 1 can be manufactured as follows. A silicon substrate (Si(111) surface) is used as the main substrate 1, and an AlN film (seed portion 3) is formed on the silicon substrate by sputtering. The sputtering method can be a parallel plate type, magnetron sputtering, pulse sputtering, or the like, which enables low-temperature and low-cost film formation. Note that the use of MOCVD allows for the formation of an AlN film with high crystallinity.

[0044] The thickness of the seed portion 3 is set to 100 nm. At high temperatures, there is a problem of mutual reaction between silicon and gallium (so-called melt-back), and in order to suppress this, the thickness of the seed portion 3 may be set to 50 to 500 nm.

[0045] The seed section 3 was deposited at a deposition temperature of 400°C, using a mixture of argon and nitrogen gases (gas ratio of approximately 1:1), with a power input of 500 W and a back pressure of 0.3 Pa during deposition. When using a sapphire substrate, AlN is deposited directly. However, when depositing an AlN layer on a silicon substrate, an Al layer (buffer section 2) of several nanometers in thickness is first formed before the AlN layer is deposited, allowing for the formation of a high-quality AlN layer without nitriding the silicon substrate. To form the Al layer, the Al target is sputtered using only Ar gas (without introducing nitrogen). This allows for the continuous deposition of the Al layer and AlN layer without inserting or removing the substrate in the same chamber. When depositing the Al layer and AlN layer using an MOCVD apparatus, first, only TMA (trimethylaluminum) is introduced to form an Al layer of several nanometers on the silicon substrate, and then NH ３ By introducing the above, a laminated structure of Si substrate / Al layer / AlN layer can be obtained.

[0046] Next, a photolithography process is used to form a stripe-shaped resist Z having a width of about 3 μm on top of the seed portion 3, and a dry etching process is used to form the ridge portion R. At this time, the seed portion 3 and a portion of the main substrate 1 are etched. For example, if the ridge R is formed with an etching thickness of 100 nm for the seed portion 3 (AlN layer) and about 300 nm for the main substrate, the ridge height will be about 400 nm. Here, the resist Z is not removed, and a silicon nitride film SF (e.g., 10 nm) that will become the mask portion 5 is formed on the resist Z.

[0047] When the ELO layer contacts the mask portion (growth-inhibiting region), the thickness of the mask portion must be at least 100 nm, and interference between the mask portion and the ELO layer may impair the surface flatness of the ELO layer. However, in Example 1, the wing portion F is floating in the air and does not contact the mask portion 5, so even if the mask portion 5 is made very thin, the growth of the wing portion F is not inhibited. By making the mask portion 5 thin, the flatness of the back surface of the wing portion F is improved. If the thickness of the mask portion 5 is made 50 nm or less, flatness is improved, and it can also be set to 30 nm or less.

[0048] Next, the resist Z is removed to lift off the silicon nitride film SF on the ridge portion R, and a first opening K1 is formed to form a template substrate TS (selective growth substrate). In this way, by fabricating the template substrate TS without using the MOCVD method, a significant cost reduction can be achieved, which is extremely advantageous for the industry.

[0049] Furthermore, when an AlN layer (underlayer) is formed by sputtering, Ga does not adhere to the silicon substrate surface. When an AlN layer is formed using an MOCVD apparatus used to form a GaN layer, Ga in the furnace may adhere to the silicon substrate surface and melt back during the temperature increase process before film formation, resulting in a decrease in yield. This has resulted in frequent maintenance of the MOCVD apparatus (e.g., cleaning of internal components such as the tray and cover), which has led to high costs. On the other hand, this embodiment is a technique in which the semiconductor portion 8 is formed using an MOCVD apparatus, and the AlN layer (underlayer) and mask layer are formed using a separate sputtering apparatus. When the silicon substrate is introduced into the MOCVD apparatus, the surface is covered with the AlN (underlayer) and mask, preventing a decrease in yield due to melt back, providing significant industrial benefits.

[0050] Next, the template substrate TS is transferred into an MOCVD apparatus, and the semiconductor portion 8 is formed on the template substrate TS by the ELO method. In Example 1, the semiconductor portion 8 is a GaN layer, and the growth temperature is 1000-1200 degrees, the V / III ratio is 500-20000, and the growth pressure is 50 kPa. In order to make the semiconductor portion 8 n-type, SiH ４ Alternatively, doping may be performed by flowing SiH ４ Without introducing Si into the mask portion, a material containing Si, such as SiO ２By using SiN or SiN, it is also possible to perform Si doping with evaporated Si. The film formation conditions are preferably set in at least two stages. In the first stage, the film formation temperature is set to approximately 1030°C, and the V / III is set to approximately 2000, to form a growth nucleus (vertical growth portion) of the ELO layer (semiconductor portion 8) on the opening K. The thickness (height) of the growth nucleus is set to approximately 0.2 to 3.0 μm, and its width may be set to be approximately the same as the width of the ridge R or to a size that slightly protrudes in the a-axis direction (<11-20> direction). In the second stage, the film formation temperature is increased by approximately 100°C, and the GaN layer is grown laterally (in the a-axis direction) from the growth nucleus. Growth was stopped when the width of the gap GP between the semiconductor portions 8 (GaN layers) growing in opposite directions on the void reached a specified value (10 μm or less). The semiconductor substrate 10 obtained as described above (with the semiconductor portion 8 exposed) may be removed from the MOCVD apparatus and stored, or an upper layer portion including an active layer may be subsequently formed in the MOCVD apparatus.

[0051] In Example 1, it was found that even if the crystallinity above the opening K is poor, the poor crystallinity is unlikely to be inherited by the wing portion F above the gap (above the mask portion), and the crystallinity of the wing portion F is increased (the defect density is significantly reduced). Note that, when a nitride semiconductor layer is formed on a seed layer formed by sputtering without using ELO, defects in the seed layer are inherited entirely by the nitride semiconductor layer, making it difficult to obtain a high-quality device.

[0052] Fig. 14 shows Raman spectra of the base and wing portions of the ELO layer according to the comparative example. The ELO layer according to the comparative example is formed on a seed layer formed by MOCVD. Fig. 15 shows Raman spectra of the base and wing portions of the ELO layer (semiconductor portion) according to Example 1. The seed layer is formed by sputtering. Fig. 14 shows that in the comparative example, the half-width of the spectrum of the GaN base is 2.2 cm. －１ The half width of the spectrum of the GaN on the wing is 2.0 cm －１ From FIG. 15, it can be seen that in Example 1, the half width of the spectrum of the GaN base was 2.8 cm －１ The half width of the spectrum of the GaN on the wing is 2.0 cm －１It was found that the wing portion was a very high-quality crystal, comparable to that of the comparative example (seed portion formed by MOCVD). This is a discovery of great industrial significance, as it allows a high-quality semiconductor portion to be obtained using a low-cost template substrate that includes an inexpensive silicon substrate and an underlayer (seed portion or a stack of buffer portion and seed portion) formed by a non-MOCVD apparatus such as a sputtering apparatus or an EB apparatus.

[0053] For the upper layer portion 9 (device layer, functional layer) formed on the semiconductor portion 8, an extremely high-quality element can be fabricated by forming at least the active region (e.g., light-emitting region) above the wing portion. In Example 1, there is also the advantage that the template substrate TS is formed without using an MOCVD apparatus, and the semiconductor portion 8 and the upper layer portion 9 can be formed successively in the MOCVD apparatus.

[0054] FIG. 16 is a plan view of a semiconductor substrate including an upper layer portion. FIG. 17 is a cross-sectional view of a semiconductor substrate including an upper layer portion. The upper layer portion 9 may be formed on the semiconductor portion 8 by changing the film formation conditions (e.g., by lowering the film formation temperature by about 100° C.) after stopping the growth of the semiconductor portion 8. The upper layer portion 9 may include at least one of a p-type layer, an n-type layer, and an electron blocking layer in addition to the active layer. Even when the upper layer portion 9 is formed on the semiconductor substrate 10, the backside transfer phenomenon, in which the upper layer material is supplied to the back side of the semiconductor portion 8, is significantly suppressed, and problems such as light absorption caused by the backside transfer phenomenon are also eliminated.

[0055] In the semiconductor substrate 10 shown in FIGS. 16 and 17 , the anode EA and cathode EC are formed above the wing portions F of the semiconductor portion 8. In a typical LED, the active region (light-emitting region) is directly below the anode EA, which is made of a transparent electrode such as ITO (indium tin oxide). In Example 1, the backlighting phenomenon is suppressed, eliminating the problem of light emitted from the active region being absorbed by the back surface of the wing portions F. At least a portion of the anode EA may be located above the wing portions F, or the entire anode EA may be located above the wing portions F. Because the active region is not generally located directly below the cathode, the cathode EC may be formed above the ridge R. In FIGS. 16 and 17 , the anode EA and cathode EC are formed above the same wing portion F, but this is not limiting. As shown in FIG. 8 , the anode EA may be formed above one of two wing portions F facing each other across the ridge portion R, and the cathode EC may be formed above the other.

[0056] In conventional ELO methods, cracks can occur in the semiconductor layer due to differences in the thermal expansion coefficients of the heterogeneous substrate and the semiconductor layer. In contrast, in Example 1, adjacent semiconductor portions 8 do not meet (there is a gap GP), and the semiconductor portions 8 are located in the void and are physically separated from the mask portion 5. This effectively relieves internal stress and suppresses the occurrence of cracks even when using a heterogeneous substrate (such as a Si substrate or a SiC substrate). By increasing the width of the wing portions F (for example, to 7 μm or more), stress can be relieved by the wing portions F.

[0057] In Example 1, the width WJ of the gap J is 20 μm, the ridge height is 300 nm, and the width of the gap GP is 10 μm. Since the back surface of the semiconductor portion 8 is at the same level as the top surface of the ridge R, the thickness of the gap J is 300 nm, and the aspect ratio of the gap J is 66.6. Although the upper layer portion 9 was formed on the semiconductor portion 8, no lamination of active layer material or the like on the back surface of the semiconductor portion 8 was confirmed, and it was found that the backside transfer phenomenon had been suppressed.

[0058] The width WR of the ridge portion R, which serves as the starting point of growth, may be 1 μm to 20 μm, or 2 μm to 10 μm. The thickness TJ of the gap may be 5 μm or less, 2 μm or less, 1 μm or less, 0.6 μm or less, or 0.3 μm or less. The thickness TJ of the gap is preferably 0.05 μm (50 nm) or more. This facilitates removal of the mask portion 5. The pitch PR of the ridge portion may be 20 μm or more. The thickness TJ of the gap is preferably less than 0.5 μm (500 nm). This reduces the formation of morphology on the back surface and improves the quality of devices formed on the wing portion F. The aspect ratio of the gap J may be 5.0 or more, 10 or more, 20 or more, 30 or more, 50 or more, or 100 or more. This allows the upper layer portion 9 to be formed on the wide wing portion F while suppressing the backside transfer phenomenon, resulting in the formation of a high-quality (e.g., high light extraction efficiency) semiconductor device. The aspect ratio of the gap J may be, for example, 100 to 1000. This reduces the risk of the semiconductor portion 8 warping upward due to gravity. Furthermore, by setting the width of the gap GP to 30 μm or less, or 10 μm or less, the backside bending phenomenon can be more effectively suppressed. In other words, no active layer material is stacked on the backside of the wing portion F formed in this manner. This reduces the risk of current leakage in the device formed on the wing portion F. The width of the gap GP can be set to 1 / 5 to 1 / 100 of the width of the wing portion F. This allows for the formation of wide wing portions F while suppressing the backside bending phenomenon, thereby increasing the degree of freedom of the device.

[0059] FIG. 18 is a plan view showing the element isolation method in Example 1. FIG. 19 is a cross-sectional view showing the element isolation method in Example 1. As shown in FIGS. 18 and 19 , the element body 20 (including the wing portion F, the upper layer portion 9, the anode EA, and the cathode EC) is separated from the template substrate. Because there is a gap J below the wing portion F, by applying downward pressure to the element body 20 with an adhesive pressing body YS (adhesive plate, adhesive sheet, etc.), the base portion of the element body 20 (the connection portion with the template substrate TS) easily cracks, and the element body 20 is separated from the template substrate TS. Specifically, the element body 20 is peeled off from the template substrate TS while being held by the pressing body YS. In this way, the gap J functions effectively in element isolation, allowing the element body 20 to be peeled off without damaging the element body 20.

[0060] Specific examples of the element 20 include a light emitting diode (LED), a semiconductor laser, a Schottky diode, a photodiode, and a transistor (including a power transistor and a high electron mobility transistor).

[0061] 20 is a schematic diagram showing the configuration of an electronic device according to Example 1. The electronic device 30 includes an element assembly 20, a drive substrate 23 on which the element assembly 20 is mounted, and a control circuit 25 that controls the drive substrate 23. The control circuit 25 may include a processor. Examples of the electronic device 30 include a display device, a laser emission device (including a Fabry-Perot type and a surface-emitting type), a lighting device, a communication device, an information processing device, a sensing device, and a power control device.

[0062] In Figure 20, the element body 20 is bonded and electrically connected to the drive substrate 23 in a state where it has been peeled off from the template substrate TS, but it may also be bonded and electrically connected to the drive substrate 23 in an unpeeled state (the template substrate TS and the element body 20 thereon).

[0063] Example 2 In Example 2, the semiconductor substrate 10 shown in FIG. 3 was formed. Specifically, a silicon substrate was used as the main substrate 1. A 3-nm thick Al layer (not shown) was then formed on the main substrate 1. A 200-nm thick AlN layer was then formed as the buffer portion 2 using a sputtering method. The film formation temperature was 400°C, and a mixed gas of argon and nitrogen gas was used. The gas ratio was approximately 1:1, the input power was 500 W, and the back pressure during film formation was 0.3 Pa. Next, a 400-nm-thick GaN layer serving as the seed portion 3 was formed on the buffer portion 2 (AlN layer) using a sputtering method using a GaN target. Thereafter, a ridge portion R and a SiN film were formed using the method described above, and the SiN film on the ridge portion was lifted off to form a template substrate TS (selective growth substrate) including a mask pattern 6. The bottom surface of the ridge portion R reached the main substrate 1, which was recessed by approximately 400 nm. Thereafter, the semiconductor portion 8 was formed on the template substrate TS using the MOCVD method, thereby obtaining the semiconductor substrate 10.

[0064] In Example 2, the height of the ridge portion R was 200 nm (thickness of the AlN layer) + 400 nm (thickness of the GaN layer) + 400 nm (depth of recess in the main substrate) = 1000 nm (1.0 μm). The width of the ridge portion R was 3 μm, the pitch width of the ridge portion was 40 μm, the width of the gap GP was 5 μm, and the width WJ of the void J was 16 μm. Because the heights of the top surface of the ridge portion R and the back surface of the semiconductor portion 8 were the same, the thickness TJ of the void J was 1 μm, and the aspect ratio of the void J was 16.0.

[0065] In Example 2, by changing the film formation conditions of the ELO method (for example, by changing the partial pressures of nitrogen and hydrogen used in the gas flow and increasing the amount of hydrogen), it is possible to achieve the configuration shown in FIG. 4 , in which the height of the back surface of the wing portion F is lower than the upper surface of the ridge portion R. In this case, film formation ended when the back surface of the wing portion F was about 600 nm lower than the upper surface of the ridge portion R, so the thickness TJ of the gap J was 400 nm. The width of the ridge portion R was 8 μm, the pitch width of the ridge portion was 78 μm, and the width of the gap GP was 30 μm. As a result, the width WJ of the gap J was 20 μm, and the aspect ratio of the gap J was 50.

[0066] Example 3 In Example 3, the semiconductor substrate 10 shown in FIG. 2 was formed. Specifically, a sapphire substrate was used as the main substrate 1, and a 200-nm-thick AlN layer was formed on the main substrate 1 using a sputtering method as the seed portion 3. The film formation temperature was 500°C, and a mixed gas of argon gas and nitrogen gas was used. The gas ratio was approximately 1:1, the input power was 500 W, and the back pressure during film formation was 0.3 Pa. Subsequently, a ridge portion R and a SiN film were formed using the method described above, and the SiN film on the ridge portion was lifted off to form a template substrate TS (selective growth substrate) including a mask pattern 6. The bottom surface of the ridge portion R reached the main substrate 1 (sapphire substrate), and the main substrate 1 was recessed by approximately 10 nm. Then, a semiconductor portion 8 was formed on the template substrate TS using an MOCVD method.

[0067] In Example 3, the height of the ridge portion R was 200 nm (thickness of the AlN layer) + 10 nm (depth of recess in the main substrate) = 210 nm. The width of the ridge portion R was 2 μm, the pitch width of the ridge portion was 30 μm, the width of the gap GP was 2 μm, and the width WJ of the void J was 13 μm. Since the heights of the upper surface of the ridge portion R and the back surface of the semiconductor portion 8 were the same, the thickness TJ of the void J was 200 nm, and the aspect ratio of the void J was 65. Although the upper layer portion 9 was formed on the semiconductor portion 8, no active layer material or the like was found to be stacked on the back surface of the semiconductor portion 8, and it was found that the backside transfer phenomenon had been suppressed.

[0068] Example 4 Figure 21 is a cross-sectional view showing the configuration of a semiconductor substrate of Example 4. In Example 4, in a template substrate TS, a seed portion 3 having a two-layer structure of an AlGaN layer (2 μm) and a GaN layer (1.5 μm) was formed by MOCVD on an AlN layer (200 nm) that was a buffer portion 2. The height of the ridge portion R was 300 nm, and the bottom surface of the ridge portion R was within the GaN layer (the layer below the seed portion 3). A semiconductor portion 8 was formed on the template substrate TS by MOCVD.

[0069] In Example 4, the width WR of the ridge portion R was 3 μm, the pitch width PR of the ridge portion was 55 μm, the width of the gap GP was 10 μm, and the width WJ of the void J was 21 μm. The back surface of the wing portion F was about 50 nm lower than the top surface of the ridge portion R, and the thickness TJ of the void J was 250 nm, so the aspect ratio of the void J was 84.

[0070] FIG. 22 is a graph showing the results of an XRD reflection scan of the ELO layer of the comparative example. The ELO layer of the comparative example was laterally grown so as to contact the mask portion. FIG. 23 is a graph showing the results of an XRD reflection scan of the semiconductor portion of Example 1. In FIG. 22, three peaks corresponding to the base portion and the two wing portions (paired wing portions) sandwiching it were detected. The central peak is the base peak, and the crystal axis (c-axis) of the c-plane is substantially perpendicular to the mask portion surface. In FIG. 22, the angle difference Δ between the peaks from the two wing portions was 1.1 degrees. This result shows that in the comparative example, the c-axes of the two wing portions are offset from the center by approximately 0.5 degrees to opposite sides. This c-axis tilt indicates poor flatness of the ELO layer. On the other hand, in FIG. 23, the angle difference Δ between the peaks from the two wing portions was 0.17 degrees, less than one-fifth of that of the comparative example. This result shows that the flatness of the semiconductor portion 8 in Example 1 was significantly improved compared to that of the comparative example. It should be noted that values ​​of Δ=0.2 degrees or less were also obtained in other examples. This is thought to be due to the fact that the wing portions F were grown on the voids J and that the gaps GP were formed without causing adjacent semiconductor portions 8 to meet. It was found that such good flatness was achieved in the wide wing portions F (e.g., 7 μm or more), which resulted in uniform incorporation of In (indium) within the surface during the formation of the upper layer portion 9 (see, for example, FIG. 17 ), significantly improving the quality (e.g., luminous efficiency) and yield of the element body 20.

[0071] Example 5 FIG. 24 is a plan view illustrating the configuration of a semiconductor substrate according to Example 5. FIG. 24 is a cross-sectional view illustrating the configuration of a semiconductor substrate according to Example 5. As shown in FIGS. 24 and 25 , the semiconductor substrate includes a template substrate TS including a first seed region S1 and a growth-inhibited region (non-seed portion) DA aligned in a first direction X1, and a first semiconductor portion 8A positioned above the template substrate TS. The first semiconductor portion 8A has a first base portion B1 positioned above the first seed region S1 and a first wing portion F1 connected to the first base portion B1 and facing the growth-inhibited region DA across a first gap J1. The first wing portion F1 includes a wing end (edge) E1 positioned above the growth-inhibited region DA, and the ratio of the width of the first gap J1 in the first direction X1 to the thickness TJ is 5.0 or greater. This allows a wide device layer (functional layer) to be formed on the first wing portion F1. The thickness TJ of the first gap J1 may be the thickness below the wing end E1 in the first gap J1.

[0072] In the semiconductor substrate 10, the template substrate TS includes a main substrate 1 and an underlayer 4, with the underlayer 4 being unmodified in the first seed region S1 and modified in the growth inhibition region DA. Furthermore, the first semiconductor portion 8A includes a first protrusion R1 located on the first seed region S1, and a growth inhibition film 7 is provided in contact with the first protrusion R1. The first protrusion R1 is formed in a mesa shape on the first seed region S1 and is connected to the first base portion B1. The growth inhibition film 7 may be in contact with the side and top surfaces of the first protrusion R1, or may be located on the growth inhibition region DA.

[0073] Fig. 26 is a cross-sectional view showing a method for manufacturing the semiconductor substrate of Fig. 25. Fig. 26 shows the steps of preparing a template substrate TS including a first seed region S1 and a growth inhibition region DA, forming a first raised portion R1 from the first region S1 above the template substrate TS, forming a growth inhibition film 7 in contact with the first raised portion R1, and forming a first base portion B1 located above the first raised portion R1 and a first wing portion F1 connected to the first base portion B1, separated from the growth inhibition region DA, and located above the gap J1.

[0074] 26 , the first base B1 and the first wing F1 may be formed using the corner RC of the first protrusion R1 as the growth starting point. While the corner RC may be used as the growth starting point in this manner, this is not limitative. Alternatively, a defect (e.g., a minute opening) may be formed in the growth inhibiting film 7 on the first protrusion R1, and the defect in the growth inhibiting film 7 may be used as the growth starting point for the first base B1 and the first wing F1.

[0075] The first protrusion R1, the growth suppression film 7, the first base B1, and the first wing F1 may be successively formed using an MOCVD apparatus. The first protrusion R1 includes a GaN-based semiconductor, the growth suppression film 7 is silicon nitride, and a gallium source material (organic material such as trimethylgallium (TMG) or triethylgallium (TEG)) and a nitrogen source material (ammonia gas (NH ３ )) to form the first protrusion R1, and while maintaining the supply of the raw material that serves as the nitrogen source, the supply of the raw material that serves as the gallium source is stopped to supply a silicon-based material (e.g., SiH ４ The growth suppression film 7 may be formed by supplying a silicon-based material to the first base portion B1 and the first wing portion F1. The first base portion B1 and the first wing portion F1 may contain a GaN-based semiconductor, and the first base portion B1 and the first wing portion F1 may be formed by stopping the supply of the silicon-based material and supplying a gallium-based material while maintaining the supply of the nitrogen-based material. The supply of a small amount of silicon-based material may also be continued at a doping level. By making the first protrusion R1 the same GaN-based semiconductor as the first wing portion F1, lattice defects resulting from the difference in lattice constant between the first protrusion R1 and the first wing portion F1 are reduced.

[0076] By forming the growth suppression film 7 in this manner, it is possible to continuously form the film while forming the first gap J1 below the wing portion F without removing it from the MOCVD apparatus, thereby reducing the manufacturing time and manufacturing costs. By forming the first gap J1 and forming the wing portion F so that it does not come into contact with the underlayer 4 (growth suppression region DA), it is possible to effectively relieve stress, etc., applied to the semiconductor portion 8 from the main substrate 1 and the underlayer 4.

[0077] Fig. 27 is a cross-sectional view showing a method for manufacturing the template substrate of Fig. 25. As shown in Fig. 27, the template substrate TS of Fig. 25 may be obtained by performing the steps of forming an underlayer 4 containing an underlayer material, depositing a resist RZ on the underlayer 4, patterning the resist RZ, subjecting the exposed underlayer material to plasma treatment, and removing the resist RZ. The underlayer 4 may be formed by sputtering.

[0078] In the plasma treatment, for example, argon plasma is irradiated onto the exposed surface 4D of the underlayer 4 to modify the surface of the irradiated region, thereby forming a growth-inhibited region DA. By introducing not only argon gas but also oxygen gas, nitrogen gas, hydrogen gas, or the like into the chamber, the plasma treatment can also use oxygen plasma, nitrogen plasma, hydrogen plasma, or a mixture of these plasmas in addition to argon plasma. As a result, the growth-inhibited region DA may contain argon, oxygen, nitrogen, or the like as impurities. In such a case, the underlayer material may be aluminum nitride, and the growth-inhibited region DA may be aluminum oxynitride. Alternatively, the underlayer material may be AlScN (aluminum scandium nitride), and the growth-inhibited region DA may be AlScON (aluminum scandium oxynitride).

[0079] 28 is a cross-sectional view showing a method for manufacturing a template substrate. As shown in FIG. 28 , the following steps may be performed: patterning a resist RZ on an underlayer 4 (e.g., an AlN layer); forming a coating CM (e.g., a silicon nitride film of approximately 10 nm) covering the underlayer 4 and the resist RZ; removing the resist RZ (lift-off patterning the coating CM); annealing the coating CM and the underlayer 4 (e.g., heat treatment at 1000°C); and removing the coating CM (e.g., removing the silicon nitride film using BHF). In this way, interdiffusion between the coating CM and the underlayer 4 during annealing can form a growth suppression region DA located below the coating CM on the surface of the underlayer 4. Note that by forming the coating CM by sputtering, surface modification below the coating CM can be performed without annealing. The underlayer material may be AlScN, ScN, ZnO, CrN, or the like, containing a different material (e.g., a metal element other than Group III elements) such as Sc (scandium), Zn, or Cr. The underlayer 4 may have a single-layer structure or a multilayer structure, or may have a multilayer structure including a periodic structure.

[0080] FIG. 29 is a cross-sectional view showing a method for manufacturing a template substrate. As shown in FIG. 29 , the process may include patterning a resist RZ on an underlayer 4 (e.g., an AlN layer), implanting impurity ions into the exposed underlayer material, and removing the resist RZ. Examples of impurities include silicon (Si), iron (Fe), and magnesium (Mg). The implantation process involves implanting impurity ions into the exposed surface 4D of the underlayer 4 to modify the surface and form a growth suppression region DA. The underlayer material may be AlScN, ScN, ZnO, CrN, or the like, containing a heterogeneous material (e.g., a metal element other than Group III) such as Sc (scandium), Zn, or Cr. The underlayer 4 may have a single-layer structure or a multilayer structure. It may also have a multilayer structure including a periodic structure.

[0081] 30 and 31 are cross-sectional views showing the configuration of a semiconductor substrate according to Example 6. As shown in FIGS. 30 and 31 , the semiconductor substrate includes a template substrate TS including a first seed region S1 and a growth-inhibited region (non-seed portion) DA aligned in a first direction X1, and a first semiconductor portion 8A positioned above the template substrate TS. The first semiconductor portion 8A has a first base portion B1 positioned above the first seed region S1 and a first wing portion F1 connected to the first base portion B1 and facing the growth-inhibited region DA across a first gap J1. The first wing portion F1 includes a wing end (edge) E1 positioned above the growth-inhibited region DA. The ratio of the width (WJ) of the first wing portion F1 in the first direction X1 to the thickness TJ of the first gap J1 may be 5.0 or greater. The width (single wing width Wf) of the first wing portion F1 in the first direction X1 may be 5.0 times or greater than the thickness TJ of the first gap J1. The thickness TJ may be the thickness of the first gap J1 below the wing end E1, or may be the distance (spacing) from the growth suppression region DA to the wing end E1. In this way, a wide device layer (upper layer, functional layer) can be formed on the first wing portion F1. When the threading dislocation density of the first wing portion F1 is 5×10 ６ [pcs / cm ２ The first wing portion F1 may have a ratio of its width in the first direction X1 (single wing width Wf) to its thickness Th (wing thickness) of 5.0 or more.

[0082] The template substrate TS in FIG. 30 includes a main substrate 1, a buffer portion (planar buffer layer) 2, and a seed portion 3. The buffer portion 2 is a growth suppression layer (a layer that suppresses the growth of nitride semiconductor crystals) and includes a ridge portion (protrusion) R1. The buffer portion 2 may include at least one of a 4H—SiC layer, a 6H—SiC layer, a 3C—SiC layer, a sapphire layer, a diamond layer, and a ScAlMgO layer. A seed portion 3 (e.g., AlN) including a first seed region S1 is formed on the ridge portion R1, and the region of the upper surface of the buffer portion 2 that does not overlap with the seed portion 3 functions as a growth suppression region DA. A silicon substrate, a silicon carbide substrate, a sapphire substrate, or the like can be used for the main substrate 1.

[0083] The template substrate TS in Figure 31 includes a main substrate 1 and a seed portion 3. The main substrate 1 is a growth-inhibiting substrate (a substrate that inhibits the growth of nitride semiconductor crystals) and includes a ridge portion (convex portion) R1. The main substrate 1 may be a 4H-SiC substrate, a 6H-SiC substrate, a 3C-SiC substrate, a sapphire substrate, a diamond substrate, or an ScAlMgO substrate. A seed portion 3 (e.g., AlN) including a first seed region S1 is formed on the ridge portion R1, and the region of the upper surface of the main substrate 1 that does not overlap with the seed portion 3 functions as a growth-inhibiting region DA.

[0084] 32 is a cross-sectional view showing the configuration of a semiconductor substrate of Example 7. The semiconductor substrate 10 in Fig. 32 includes a template substrate TS including a first seed region S1 and a first semiconductor portion 8 located above the template substrate TS, the first semiconductor portion 8 having a first base portion B1 located on the first seed region S1 and a first wing portion F1 adjacent to the first base portion B1 in the first direction X1 and connected to the first base portion B1, the template substrate TS includes a growth-inhibited region DA facing the first wing portion F1 across a first gap J1, the first wing portion F1 including a wing end (edge) E1 located above the growth-inhibited region DA, and a ratio of a length WJ of the first gap J1 in the first direction X1 to a thickness TJ of the first gap J1 is 5.0 or greater.

[0085] The template substrate TS includes a main substrate 1 having a lattice constant different from that of the first semiconductor portion 8, and a seed portion 3 located above the main substrate 1, the upper surface of the seed portion 3 being the first seed region S1, and the side surface of the seed portion 3 may be covered with the same material as the growth inhibition region DA.

[0086] As shown in FIG. 32 , a flat buffer portion 2 (e.g., a planar AlN layer) may be formed on a main substrate 1, and a mesa-shaped seed portion 3 (ridge portion R1) including a first seed region S1 may be formed on the buffer portion 2. The seed portion 3 may be a GaN-based semiconductor. By using the same GaN-based semiconductor as the first semiconductor portion 8, lattice defects caused by the difference in lattice constant between the seed portion 3 and the first semiconductor portion 8 are reduced. In the example shown in FIG. 32 , the thickness TJ below the wing end in the first gap J1 is 482 nm, the width of the first gap J1 is 20.1 μm, the width of the opening K is 3.06 μm, the overall width (length in the first direction) Ws of the first semiconductor portion 8 including both wings is 44.1 μm, and the thickness (wing thickness) Th of the first semiconductor portion 8 is 2.22 μm. Regarding the thickness of the first gap J1, the thickness below the wing base may differ from the thickness below the wing tip by approximately 0 to 5%. In this case, the thickness of the first gap J1 may be the thickness below the wing tip (TJ) or the minimum thickness throughout the first gap J1.

[0087] Example 8 FIG. 33 is a flowchart illustrating a method for manufacturing a semiconductor device according to Example 8. FIG. 34 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 8. As illustrated in FIGS. 33 and 34 , a semiconductor body 20 (semiconductor device) or a semiconductor device 21 including the semiconductor body 20 and the transfer substrate PS may be obtained by performing steps S60 of preparing a semiconductor substrate 10, S70 of forming an upper layer 9 above a first wing portion F1, and S80 of peeling the first wing F1 from the template substrate TS while the first wing portion F1 and the upper layer 9 are held on the transfer substrate PS. In step S70, the upper layer 9 does not need to be formed below (on the back surface of) the first wing F1. The upper layer 9 (functional layer) may be, for example, a nitride semiconductor layer (e.g., a GaN-based semiconductor layer) including an active layer, and an electrode, an insulating film, or the like may be provided on the upper layer 9. The semiconductor devices (20 and 21) may include electrodes, insulating films, or the like.

[0088] 35, the growth suppression film 7 is located on the first protrusion R1, so the bond between the first protrusion R1 and the first wing portion F1 is weak, and the first wing portion F1 can be easily peeled off. Because the first protrusion R1 and the first base portion B1 are made of nitride semiconductor crystal, cleavage may occur at the boundary between them.

[0089] (Additional Note) The above disclosure is intended for purposes of illustration and description, and is not intended to be limiting. Based on these examples and descriptions, many variations will be obvious to those skilled in the art, and it should be noted that these variations are also included in the embodiments.

[0090] REFERENCE SIGNS LIST 1 Main substrate 2 Buffer portion 3 Seed portion 4 Underlayer 5 Mask portion 6 Mask pattern 8A First semiconductor portion 8C Second semiconductor portion 9 Upper layer portion 10 Semiconductor substrate 20 Element body (semiconductor device) 21 Semiconductor device 50 Semiconductor substrate manufacturing apparatus R Ridge portion E1 Edge B1 First base portion B2 Second base portion F1 First wing portion F2 Second wing portion J1 First gap J2 Second gap S1 First seed region S2 Second seed region DA Growth inhibition region TS Template substrate

Claims

1. A process for preparing a semiconductor substrate comprising: a template substrate including a first seed region and a non-seed portion aligned in a first direction; and a first semiconductor portion located above the template substrate, the first semiconductor portion having a first base portion located on the first seed region and a first wing portion connected to the first base and facing the non-seed portion via a first gap, the first wing portion including a wing end located above the non-seed portion, the first gap having a ratio of its width in the first direction to its thickness below the wing end of 5.0 or greater; forming an upper layer portion above the first wing portion; and peeling the first wing portion from the template substrate while the first wing portion and the upper layer portion are held on a transfer substrate.

2. The method of claim 1 , wherein the upper layer portion is not formed below the first wing portion.

3. A method for manufacturing a semiconductor element as described in claim 1, comprising a step of forming an anode and a cathode on the upper layer.

4. A method for manufacturing a semiconductor element as described in claim 3, wherein the entire anode is formed above the first wing portion.

5. A method for manufacturing a semiconductor element as described in claim 3, wherein the anode and the cathode are formed so as to be aligned in a second direction perpendicular to the first direction.

6. a second semiconductor portion located above the template substrate; the template substrate has a second seed region adjacent to the first seed region via the non-seed portion in a plan view; the second seed region is located above the non-seed portion, the second semiconductor portion has a second base portion located on the second seed region and a second wing portion connected to the second base portion and facing the non-seed portion with a second gap therebetween; the second wing portion includes a wing end located above the non-seed portion; the first wing portion and the second wing portion are aligned in the first direction with a gap therebetween, The method of claim 1 , wherein the second gap has a ratio of a width in the first direction to a thickness under the wing end of 5.0 or more.

7. The method for manufacturing a semiconductor element according to any one of claims 1 to 6, wherein the template substrate has a mask pattern including a mask portion that functions as the non-seed portion and an opening that overlaps with the first seed region in a planar view.

8. A method for manufacturing a semiconductor element described in any one of claims 1 to 6, comprising a step of separating the first wing portion into a plurality of parts arranged in a second direction perpendicular to the first direction.

9. A method for manufacturing a semiconductor element according to claim 1, wherein the upper layer includes an active layer and a p-type layer.

10. A method for manufacturing a semiconductor element according to claim 1, wherein the first semiconductor portion includes a nitride semiconductor.

11. A method for manufacturing a semiconductor element as described in claim 10, wherein the first direction is the a-axis direction of the nitride semiconductor.

12. The method of claim 1 , wherein the first wing portion has a ratio of width in the first direction to thickness of 5.0 or more.

13. The method of claim 6 , wherein the width of the gap is greater than a thickness of the first cavity under the wing ends.

14. the template substrate has a seed portion including the first seed region; 7. The method for manufacturing a semiconductor device according to claim 1, wherein the seed portion is formed by a sputtering method.

15. The template substrate having a seed portion including the first seed region, The seed section is filled with argon at 2×10 １８ / cm ３ The method for producing a semiconductor device according to any one of claims 1 to 6, which is made of a nitride semiconductor containing the above.