Method and apparatus for manufacturing a semiconductor substrate and a template substrate

Abstract

A semiconductor substrate comprising: a template substrate including a first seed region and a growth suppression region; and a first semiconductor part having a first base portion positioned above the first seed region and a first wing portion connected to the first base portion and positioned above the growth suppression region. The template substrate has a main substrate, a metal layer positioned above the main substrate, and an aluminum-based nitride layer positioned above the metal layer and containing argon. The first semiconductor part includes a nitride semiconductor.

Description

Semiconductor substrate, template substrate, and template substrate manufacturing method and manufacturing apparatus

[0001] The present disclosure relates to a semiconductor substrate, a template substrate, and a method and apparatus for manufacturing a template substrate.

[0002] Patent Document 1 describes a technique in which an aluminum nitride (AlN) layer is formed as a buffer layer using a silicon (Si) substrate on which a selective growth mask having an opening is formed, and then a gallium nitride (GaN) layer is selectively grown. In the technique described in Patent Document 1, the AlN layer and the GaN layer are formed using a metalorganic chemical vapor deposition (MOCVD) method.

[0003] Japanese Patent Application Publication No. 2008-235709

[0004] In one aspect of the present disclosure, a semiconductor substrate comprises a template substrate including a first seed region and a growth inhibition region, and a first semiconductor portion having a first base portion located above the first seed region and a first wing portion connected to the first base and located above the growth inhibition region, wherein the template substrate has a main substrate, a metal layer located above the main substrate, and an aluminum-based nitride layer containing argon located above the metal layer, and the first semiconductor portion includes a nitride semiconductor.

[0005] In one aspect of the present disclosure, a semiconductor substrate comprises a template substrate including a first seed region and a growth inhibition region, and a first semiconductor portion having a first base portion located above the first seed region and a first wing portion connected to the first base and located above the growth inhibition region, wherein the template substrate has a main substrate and an aluminum-based nitride layer containing argon, the nitrogen-polarity surface of which is bonded to the main substrate, and the first semiconductor portion includes a nitride semiconductor.

[0006] A template substrate according to one aspect of the present disclosure includes a main substrate, a metal layer located above the main substrate, and an aluminum-based nitride layer containing argon located above the metal layer.

[0007] A method for manufacturing a template substrate according to one aspect of the present disclosure is a method for manufacturing a template substrate including a main substrate, and includes the steps of forming a metal layer above the main substrate and forming an aluminum-based nitride layer above the metal layer by sputtering.

[0008] A method for manufacturing a template substrate according to one aspect of the present disclosure is a method for manufacturing a template substrate including a main substrate, and includes the steps of forming a metal layer on a temporary substrate, forming an aluminum-based nitride layer above the metal layer by sputtering, and transferring the aluminum-based nitride layer from the temporary substrate to the main substrate.

[0009] FIG. 1 is a plan view schematically showing a configuration of a semiconductor substrate in an embodiment of the present disclosure. FIG. 2 is a cross-sectional view schematically showing a configuration of a semiconductor substrate in an embodiment of the present disclosure. FIG. 3 is a flowchart showing an example of a manufacturing method of a semiconductor substrate in an embodiment of the present disclosure. FIG. 4 is a cross-sectional view schematically showing a configuration of a semiconductor substrate in another embodiment of the present disclosure. FIG. 5 is a flowchart showing an example of a manufacturing method of a semiconductor substrate in another embodiment of the present disclosure. FIG. 6 is a block diagram showing an example of a manufacturing apparatus in an embodiment of the present disclosure. FIG. 7 is a cross-sectional view schematically showing a configuration of a template substrate in Example 1. FIG. 8 is a cross-sectional view showing a manufacturing method of a template substrate in Example 1. FIG. 9 is a cross-sectional view schematically showing a configuration of a semiconductor substrate in Example 1. FIG. 10 is a cross-sectional view showing an example of lateral growth of a semiconductor portion. FIG. 11 is a plan view showing another example of a configuration of a semiconductor substrate in Example 1. FIG. 12 is a cross-sectional view showing another example of a configuration of a semiconductor substrate in Example 1. FIG. 13 is a cross-sectional view showing another example of a configuration of a semiconductor substrate in Example 1. FIG. 14 is a cross-sectional view showing another example of a configuration of a semiconductor substrate in Example 1. FIG. 15 is a cross-sectional view showing another example of a configuration of a semiconductor substrate in Example 1. FIG. 1 is a plan view schematically showing the configuration of a semiconductor substrate in Example 2. FIG. 2 is a cross-sectional view schematically showing the configuration of a semiconductor substrate in Example 2. FIG. 3 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate in Example 2. FIG. 4 is a cross-sectional view showing another example of a configuration of a semiconductor substrate in Example 2. FIG. 5 is a cross-sectional view showing another example of a configuration of a semiconductor substrate in Example 2. FIG. 6 is a cross-sectional view showing another example of a configuration of a semiconductor substrate in Example 2. FIG. 7 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate in Example 3. FIG. 8 is a cross-sectional view showing an example of a method for manufacturing a template substrate of another example of a configuration of Example 3. FIG. 9 is a cross-sectional view showing an example of a method for manufacturing a template substrate of another example of a configuration of Example 3. FIG. 10 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate in Example 4.

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, the following description is intended to provide a better understanding of the gist of the present disclosure and does not limit the present disclosure unless otherwise specified. The shapes and dimensions (length, width, etc.) of the configurations shown in the drawings in this application do not necessarily reflect the actual shapes and dimensions, and have been changed as appropriate for the clarity and simplification of the drawings.

[0011] [Semiconductor Substrate] Fig. 1 is a plan view that schematically illustrates the configuration of a semiconductor substrate 10 according to an embodiment of the present disclosure. Fig. 2 is a cross-sectional view that schematically illustrates the configuration of a semiconductor substrate 10 according to an embodiment of the present disclosure. Note that, as in Fig. 1 and the like in the present disclosure, hatching may be applied to each component in the plan view for clarity of illustration, and this also applies to the other drawings described below.

[0012] 1 and 2 , the semiconductor substrate 10 includes a template substrate TS including a first seed region S1 and a growth inhibition region DA, and a first semiconductor portion 8A located above the template substrate TS. The first semiconductor portion 8A has a first base portion B1 located above the first seed region S1 and a first wing portion F1 connected to the first base portion B1 and located above the growth inhibition region DA. The template substrate TS includes a main substrate 1, a metal layer ML located above the main substrate 1, and an argon-containing aluminum-based nitride layer (Al-based nitride layer) 2 located above the metal layer ML. The first semiconductor portion 8A includes a nitride semiconductor.

[0013] In the semiconductor substrate 10 of this embodiment, the template substrate TS may have a mask pattern 6, and the mask pattern 6 may include a mask portion 5 that functions as a growth inhibition region DA and a first opening K1 that corresponds to the first seed region S1. Specifically, the surface (upper surface) of the mask portion 5 may be the growth inhibition region DA.

[0014] The first semiconductor portion 8A may contain a nitride semiconductor as a main component. The nitride semiconductor can be expressed as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), for example. Specific examples include GaN-based semiconductors, AlN, InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0015] The first semiconductor portion 8A may be doped (e.g., n-type including donors) or non-doped. The semiconductor substrate refers to a substrate including a nitride semiconductor. The main substrate 1, the metal layer ML, and the Al-based nitride layer 2 may be collectively referred to as a base substrate.

[0016] The main substrate 1 is a heterogeneous substrate having a different lattice constant from that of the first semiconductor portion 8A, and the Al-based nitride layer 2 may be a seed layer including a first seed region S1 and may be in contact with the first base portion B1. The Al-based nitride layer 2 may be, for example, an AlN layer. The first semiconductor portion 8A does not contain argon. Specifically, the surface (top surface) of the Al-based nitride layer 2 may be the first seed region S1.

[0017] The first semiconductor portion 8A can be formed on the template substrate TS by an epitaxial lateral overgrowth (ELO) method. In the ELO method, for example, a heterogeneous substrate having a lattice constant different from that of the nitride semiconductor is used as the main substrate 1, an inorganic compound film is used as the mask portion 5, and the first seed region S1 exposed in the first opening K1 can be used as the starting point for crystal growth. This allows an initial growth layer to be formed on the first seed region S1, and then the first semiconductor portion 8A including the nitride semiconductor can be grown laterally from the initial growth layer onto the mask portion 5.

[0018] Of the first semiconductor portion 8A, the first base portion B1 located above the first opening K1 becomes a dislocation inheritance portion with a large number of threading dislocations, and the first wing portion F1 located above the mask portion 5 becomes a low-defect portion with a lower threading dislocation density than the dislocation inheritance portion.

[0019] The template substrate TS may have a second seed region S2 adjacent to the first seed region S1 in the first direction X1 with a growth inhibition region DA interposed therebetween. The mask pattern 6 may include a second opening K2 corresponding to the second seed region S2. The template substrate TS may have a shape in which the first seed region S1 and the growth inhibition region DA aligned in the first direction X1 each have a longitudinal direction that is a second direction X2 perpendicular to the first direction X1.

[0020] The semiconductor substrate 10 in this embodiment may include a second semiconductor portion 8C including a nitride semiconductor. The second semiconductor portion 8C is located above the second seed region S2 and above the growth inhibition region DA. The second semiconductor portion 8C may have a second base portion B2 located above the second seed region and a second wing portion F2 connected to the second base portion B2 and located above the growth inhibition region DA. The first wing portion F1 and the second wing portion F2 may be aligned in the first direction X1 with a gap GP interposed therebetween.

[0021] The second semiconductor portion 8C grows laterally on the mask portion 5 starting from the second seed region S2 exposed in the second opening K2, and the growth may be stopped before joining the first semiconductor portion 8A. This causes the semiconductor substrate 10 to have a gap GP between the first semiconductor portion 8A and the second semiconductor portion 8C. As described above for the first semiconductor portion 8A, of the second semiconductor portion 8C, the second base portion B2 located above the second opening K2 becomes a dislocation inherited portion, and the second wing portion F2 located above the mask portion 5 becomes a low-defect portion.

[0022] Hereinafter, the first semiconductor portion 8A and the second semiconductor portion 8C may be collectively referred to as semiconductor portion 8, the first base portion B1 and the second base portion B2 as base portion B, and the first wing portion F1 and the second wing portion F2 as wing portion F. In addition, the first opening K1 and the second opening K2 of the mask pattern 6 may be collectively referred to as opening K, and the first seed region S1 and the second seed region S2 may be collectively referred to as seed region S. The semiconductor portion 8 may be a semiconductor layer 8, and the mask portion 5 may be a mask layer 5.

[0023] In the following description, the direction from the main substrate 1 to the semiconductor portion 8 will be referred to as "upward," and viewing an object from a line of sight parallel to the normal direction of the semiconductor substrate 10 (including perspective views) will be referred to as "planar view." The seed region S and the growth inhibition region DA may be aligned in a first direction X1 (a direction perpendicular to the thickness direction of the substrate) in a planar view. The seed region S (e.g., the surface of the Al-based nitride layer 2) and the growth inhibition region DA (e.g., the surface of the mask portion 5) may have different positions (heights) in the thickness direction (vertical direction) of the semiconductor substrate 10, or may be the same or approximately the same.

[0024] The first direction X1 may be the a-axis direction (<11-20> direction) of the semiconductor portion 8 (nitride semiconductor crystal such as GaN). The second direction X2 orthogonal to the first direction X1 may be the m-axis direction (<1-100> direction) of the semiconductor portion 8. The thickness direction of the semiconductor substrate 10 may be the c-axis direction (<0001> direction) of the semiconductor portion 8.

[0025] The semiconductor substrate 10 in this embodiment has the metal layer ML above the main substrate 1 and the Al-based nitride layer 2 formed on the metal layer ML, thereby making it possible to reduce, for example, warpage of the semiconductor substrate 10. This will be roughly described together with an overview of the findings of the present disclosure.

[0026] A conventional template substrate (hereinafter, for convenience of explanation, referred to as "conventional template substrate C") includes a base substrate having, in this order, a silicon substrate, an AlN layer serving as a buffer layer, an AlGaN layer serving as a strain relaxation layer, and a GaN underlayer. Conventional template substrate C also has a mask pattern formed on the base substrate. The AlN layer is provided to prevent melting (melt-back) between the silicon substrate and the GaN underlayer and to improve the quality of the GaN underlayer. Generally, the AlN layer is formed by MOCVD to improve its quality as a buffer layer.

[0027] A semiconductor substrate manufactured by loading a conventional template substrate C into an MOCVD apparatus and depositing a GaN layer using the ELO method is prone to warping when the temperature is lowered from the deposition temperature due to the difference in thermal expansion coefficient between the silicon substrate and the GaN layer. Because the conventional template substrate C uses an inexpensive silicon substrate and is formed using the MOCVD method, it is difficult to reduce the manufacturing cost.

[0028] Incidentally, an AlN layer can also be formed on a silicon substrate using a sputtering method (physical vapor deposition) instead of the MOCVD method. However, it has been difficult to form a high-quality AlN layer on a silicon substrate by the sputtering method. After extensive research, the inventors discovered that the quality of the AlN layer can be improved by forming a relatively thick metal layer ML above a main substrate 1 such as a silicon substrate and then forming an AlN layer on the metal layer ML by the sputtering method. Until now, no template substrate has been available that uses a metal layer ML with a thickness of more than 5 nm as a base for forming an AlN layer by the sputtering method, and the significance of such a template substrate was unknown.

[0029] The reason why the quality of the AlN layer is improved by using a thicker metal layer ML than conventionally as a growth base is thought to be that the crystalline state of the metal layer ML (lattice distortion, residual stress, etc.) may affect the quality of the AlN layer. It has also been found that the quality of Al-based nitrides having a structure equivalent to AlN can be improved by using a thicker metal layer ML than conventionally as a growth base.

[0030] The metal layer ML may include a layer whose main component is Al (Al-based metal layer). Here, the term "main component" refers to the metal element with the largest molar content. The metal layer ML may also include one or more metals selected from the group consisting of aluminum, platinum, palladium, silver, gold, hafnium, scandium, yttrium, titanium, and zirconium, and may contain any metal selected from the above group as its main component. The metal layer ML includes at least one metal whose (111) plane of a face-centered cubic lattice or body-centered cubic lattice or the (0001) plane of a hexagonal close-packed lattice is oriented toward the main surface 1a of the main substrate 1. The metal layer ML may also be an alloy.

[0031] The metal layer ML may be formed by a sputtering method, in which case the metal layer ML contains argon. By successively forming the metal layer ML and the Al-based nitride layer 2 in a sputtering apparatus, the manufacturing efficiency of the template substrate TS can be improved.

[0032] When an AlN layer is formed by MOCVD as in the conventional method, the film formation process is performed at a high temperature that exceeds the melting point of the Al film serving as the metal layer, making it difficult to manufacture a template substrate TS having a metal layer ML. In contrast, the sputtering method makes it easy to manufacture a template substrate TS having a metal layer ML because the film formation temperature can be lowered.

[0033] The metal layer ML may be positioned so as to overlap the entire upper surface (main surface 1 a) of the main substrate 1 in a plan view seen in the normal direction of the main substrate 1. The Al-based nitride layer 2 may be positioned so as to overlap the mask portion 5. The thickness of the metal layer ML may be 20 nm or more, and may be 100 nm or more and 2000 nm or less.

[0034] The Al-based nitride layer 2 contains at least aluminum and nitrogen. The Al-based nitride layer 2 may contain a metal other than aluminum, such as scandium (Sc) or zirconium (Zr). The Al-based nitride layer 2 may be, for example, AlScN or AlZrN. The Al-based nitride layer 2 may contain a plurality of metal species, in which case the aluminum content may be the highest among the plurality of metal species, or the aluminum content may be greater than the total content of the metal species other than aluminum.

[0035] The Al-based nitride layer 2 may be positioned so as to overlap the entire upper surface of the main substrate 1 in a plan view seen in the normal direction of the main substrate 1. The Al-based nitride layer 2 may also be positioned so as to overlap the entire upper surface (surface MLS) of the metal layer ML in a plan view. The thickness of the Al-based nitride layer 2 may be, for example, 30 nm or more. The thickness of the Al-based nitride layer 2 may be greater than that of the metal layer ML, and may be, for example, 30 nm or more and 500 nm or less.

[0036] In the semiconductor substrate 10 of this embodiment, the internal stress of the Al-based nitride layer 2 can be adjusted by adjusting the processing conditions of the sputtering method. For example, the Al-based nitride layer 2 contains argon, which is mixed in when the layer is formed by the sputtering method. Therefore, the stress state of the Al-based nitride layer 2 at room temperature can be changed by changing the argon content. For example, in the semiconductor substrate 10, the Al-based nitride layer 2 may be in a compressive stress state and the semiconductor portion 8 (first semiconductor portion 8A) may be in a tensile stress state at room temperature. This can reduce the overall warpage of the semiconductor substrate 10, which is effective for subsequent processes (device layer formation, peeling, etc.). Furthermore, in the semiconductor substrate 10, the Al-based nitride layer 2 and the semiconductor portion 8 (first semiconductor portion 8A) may be in a tensile stress state at room temperature. When the lattice constant of the Al-based nitride layer 2 is smaller than that of the semiconductor portion 8, the tensile stress state of the Al-based nitride layer 2 widens the lattice spacing in a plane perpendicular to the c-axis, thereby mitigating the effect of the difference in lattice constant between the Al-based nitride layer 2 and the semiconductor portion 8. As a result, the crystallinity of the semiconductor portion 8 (particularly the base portion on the seed region S) can be improved. The metal layer ML and the Al-based nitride layer 2 may be in a tensile stress state. When the Al-based nitride layer 2 is an aluminum nitride layer (AlN layer), the ratio of impurity metal elements other than aluminum to the total metal elements in the AlN layer may be less than 0.5 atm%. Room temperature typically refers to room temperature, for example, 20°C or 25°C. The above stress states (compressive stress state and tensile stress state) are defined based on the state of internal stress generated in a plane having the first direction X1 and the second direction X2 as in-plane directions. The stress state in the height direction of the semiconductor substrate 10 and the stress state in the plane having the first direction X1 and the second direction X2 as in-plane directions may differ from each other.

[0037] The semiconductor substrate 10 can be manufactured by manufacturing a template substrate TS on which a relatively high-quality Al-based nitride layer 2 is formed using a sputtering method, and then forming the semiconductor portion 8 on the template substrate TS. The semiconductor portion 8 can have a quality comparable to that of a semiconductor portion 8 formed on a conventional template substrate C having an AlN layer formed using an MOCVD method. The internal stress of the semiconductor substrate 10 is alleviated by the Al-based nitride layer 2 located between the main substrate 1 and the semiconductor portion 8. This effectively reduces warpage that occurs in the semiconductor substrate 10 at room temperature.

[0038] In the semiconductor substrate 10, the nitride semiconductor included in the semiconductor portion 8 may be a GaN-based semiconductor, and the main substrate 1 of the template substrate TS may be a silicon substrate, a silicon carbide substrate, or a glass substrate. The thermal expansion coefficient of the Al-based nitride layer 2 at 1000°C may be greater than that of the main substrate 1 and smaller than that of the semiconductor portion 8 (first semiconductor portion 8A).

[0039] The glass substrate is not specifically limited as long as it is made of a material that is heat resistant to the film formation temperature used when forming the semiconductor portion 8 by the ELO method. By using an inexpensive heterogeneous substrate as the main substrate 1 and forming the template substrate TS by the sputtering method, the manufacturing cost of the template substrate TS can be effectively reduced.

[0040] 3 is a flowchart showing an example of a method for manufacturing the semiconductor substrate 10 in this embodiment. The flowchart shown in FIG. 3 also includes an example of a method for manufacturing the template substrate TS.

[0041] As shown in FIG. 3 , the method for manufacturing a semiconductor substrate 10 first forms a template substrate TS. The method for manufacturing the template substrate TS includes a step (S10) of forming a metal layer ML above a main substrate 1 and a step (S20) of forming an Al-based nitride layer 2 above the metal layer ML using a sputtering method. Next, a step (S30) of forming a mask pattern 6 including mask portions 5 that function as growth suppression regions DA above the Al-based nitride layer 2 may be performed. Thereafter, a step (S40) of forming a semiconductor portion 8 is performed, thereby manufacturing the semiconductor substrate 10. For example, the metal layer ML may be an aluminum layer, and the aluminum layer may be formed using a sputtering method.

[0042] Another Embodiment Fig. 4 is a cross-sectional view schematically illustrating the configuration of a semiconductor substrate 10 according to another embodiment of the present disclosure. Fig. 5 is a flowchart illustrating an example of a method for manufacturing a semiconductor substrate 10 according to another embodiment of the present disclosure. As shown in Figs. 4 and 5 , the template substrate TS does not need to have the metal layer ML. Such a template substrate TS can be formed by forming the metal layer ML and the Al-based nitride layer 2 on a substrate (temporary substrate) separate from the main substrate 1, and then transferring the Al-based nitride layer 2 onto the main substrate 1. The temporary substrate can be made of a material suitable for forming the metal layer ML and the Al-based nitride layer 2.

[0043] 4 , the semiconductor substrate 10 includes a template substrate TS including a first seed region S1 and a growth inhibition region DA, and a first semiconductor portion 8A, and the template substrate TS has a main substrate 1 and an Al-based nitride layer 2. The Al-based nitride layer 2 has a nitrogen-polarity face bonded to the main substrate 1 and contains argon. The first semiconductor portion 8A includes a nitride semiconductor.

[0044] In this specification, the upper surface (growth surface) of the Al-based nitride layer 2 formed on the metal layer ML is referred to as the first surface 2a, and the surface opposite to the first surface 2a, i.e., the surface on the side where growth from the metal layer ML starts, is referred to as the second surface 2b. In the example shown in Figure 4, the Al-based nitride layer 2 formed above the temporary substrate is transferred to the main substrate 1, so that the first surface 2a is the surface facing the main substrate 1, and the second surface 2b is located on the side farther from the main substrate 1. The second surface 2b of the Al-based nitride layer 2 exposed in the opening K serves as the seed region S.

[0045] The first surface (upper surface) 2a of the Al-based nitride layer 2 grown on the metal layer ML in the c-plane may be an aluminum polar surface (Al polar surface). Furthermore, when the Al-based nitride layer 2 grows on the metal layer ML in the -c-plane, the first surface 2a may be a nitrogen polar surface (N polar surface). For example, when the Al-based nitride layer 2 is formed on the temporary substrate by sputtering, the first surface 2a may be an N polar surface, and after transfer to the main substrate 1, the N polar surface may be bonded to the main substrate 1. These points will be described in more detail in the examples below.

[0046] In the example shown in FIG. 5 , the manufacturing method of the template substrate TS includes a step (S100) of forming a metal layer ML above a temporary substrate, a step (S200) of forming an Al-based nitride layer 2 above the metal layer ML using a sputtering method, and a step (S250) of transferring the Al-based nitride layer 2 from the temporary substrate to the main substrate 1. For example, the main substrate 1 and the Al-based nitride layer 2 can be bonded by surface activated bonding. The main substrate 1 and the Al-based nitride layer 2 can be separated from the temporary substrate by removing the metal layer ML. Then, a step (S300) of forming a mask pattern 6 above the Al-based nitride layer 2 can be performed. Then, a step (S400) of forming a semiconductor portion 8 can be performed to manufacture the semiconductor substrate 10. For example, the metal layer ML may be an aluminum layer, and the aluminum layer may be formed using a sputtering method. Note that after the step S250, a semiconductor device can be formed by performing a step of forming electrodes or the like instead of the steps S300 and S400.

[0047] In the template substrate TS manufactured by the manufacturing method of the example shown in FIG. 5 , the Al-based nitride layer 2 is transferred from the temporary substrate to the main substrate 1, and therefore does not inherit the crystal structure of the main substrate 1 at the interface with the main substrate 1. The semiconductor substrate 10 may have a bond trace at the interface between the Al-based nitride layer 2 and the main substrate 1. This bond trace may be any trace of bonding between the main substrate 1 and the Al-based nitride layer 2 that indicates a difference between the Al-based nitride layer 2 that would have been epitaxially grown on the main substrate 1 and the Al-based nitride layer 2 transferred to the main substrate 1. The type of bond trace is not particularly limited, but it can be determined that the Al-based nitride layer 2 has such a bond trace, for example, based on XRD measurement results or the like, if the plane orientation of the surface of the main substrate 1 and the plane orientation of the first surface 2 a of the Al-based nitride layer 2 are not aligned.

[0048] [Semiconductor Substrate Manufacturing Apparatus] FIG. 6 is a block diagram showing an example of a manufacturing apparatus 50 according to an embodiment of the present disclosure. The semiconductor substrate 10 manufacturing apparatus 50 shown in FIG. 6 includes an apparatus A10 that performs the step S10 described above, an apparatus A20 that performs the step S20 described above, an apparatus A30 that performs the step S30 described above, an apparatus A40 that performs the step S40 described above, and an apparatus A50 that controls the apparatuses A10 to A40. Furthermore, the apparatus A10 may perform the step S100 described above, and the apparatus A20 may perform the step S200 described above. The manufacturing apparatus 50 may include an apparatus A25 that performs the step S250 described above. The apparatus A50 may control the apparatus A25. The apparatus A30 may perform the step S300 described above, and the apparatus A40 may perform the step S400 described above.

[0049] The devices A10 and A20 may each include a sputtering device. Furthermore, the manufacturing device 50 may include a single device A12 having the functions of the devices A10 and A20, and the device A12 may include a sputtering device. The device A50 may control the device A12. The device A50 may include a processor and memory. The device A50 may be configured to control the devices A10 and A20 by executing a program stored in, for example, an internal memory, a communication device capable of communication, or an accessible network, and this program and a recording medium on which this program is stored are also included in this embodiment.

[0050] [Semiconductor Device] The semiconductor portion 8 in the semiconductor substrate 10 has wing portions F, which are low-defect portions. A semiconductor device can be formed using the wing portions F. Specific examples of semiconductor devices include light emitters (LED chips, semiconductor laser chips, etc.), light-emitting elements in which light emitters are submounted, and light-emitting modules in which light-emitting elements are packaged. The semiconductor device is not limited to light-emitting semiconductor devices, and may be, for example, a light-receiving element (photodiode).

[0051] Other Embodiments Other embodiments of the present disclosure will be briefly described below, and will be described in more detail in the examples below.

[0052] (a) The metal layer ML may be a single layer or multiple layers containing the aforementioned types of metal. When the metal layer ML is multiple layers, at least one layer may contain aluminum as a main component, and the layer in contact with the Al-based nitride layer 2 (the uppermost layer) may contain aluminum as a main component. The metal layer ML may include a first layer made of a metal material and a second layer made of a metal material different from the first layer. Each of the first layer and the second layer may contain one or more metals selected from the group consisting of aluminum, platinum, palladium, silver, gold, hafnium, scandium, yttrium, titanium, and zirconium.

[0053] (b) In the template substrate TS, the seed region S may be a region that serves as a starting point for the growth of the semiconductor portion 8, and the template substrate TS may have the seed region S above the main substrate 1 and also have a growth inhibition region DA. The template substrate TS may not have, for example, a mask portion 5.

[0054] (c) In one configuration example, the semiconductor substrate 10 may include a metal nitride layer located between the metal layer ML and the Al-based nitride layer 2 .

[0055] (d) In the above-described embodiment, the semiconductor substrate 10 has the semiconductor portion 8 formed by the ELO method, but this is not limiting. In another aspect of the present disclosure, the semiconductor substrate 10 does not need to have the mask pattern 6. The template substrate TS can be used to manufacture semiconductor devices other than optical devices, and examples of such semiconductor devices include transistors such as HEMTs (High Electron Mobility Transistors) and elements for MEMS (Micro Electro Mechanical Systems) such as BAW (Bulk Acoustic Wave) filters.

[0056] (e) In one aspect of the present disclosure, the semiconductor substrate 10 may have a gap between the wing portion F and the mask portion 5, which is the growth inhibition region DA, and for example, the seed region S may be located above the growth inhibition region DA in the thickness direction of the semiconductor substrate 10.

[0057] (f) In one aspect of the present disclosure, in the semiconductor substrate 10, the semiconductor portions 8 that have grown laterally in opposite directions from the first opening K1 and the second opening K2 that are adjacent to each other in the first direction X1 may be in contact with each other (meet) on the mask portion 5. The semiconductor substrate 10 does not need to have a gap GP.

[0058] First Embodiment In the following, first, the template substrate TS before the semiconductor portion 8 is formed will be described, and then the semiconductor substrate 10 will be described.

[0059] (Template Substrate) Fig. 7 is a cross-sectional view schematically showing the configuration of the template substrate TS in Example 1. As shown in Fig. 7, the template substrate TS in Example 1 may have the same general configuration as the template substrate TS in the above-described Embodiment 1. The template substrate TS has a base substrate BS including a main substrate 1, a metal layer ML, and an Al-based nitride layer 2, and a mask pattern 6 may be formed on the base substrate BS.

[0060] The main substrate 1 may be a silicon substrate or various types of glass substrate. The surface orientation of the main substrate 1 is, for example, the (111) surface of a silicon substrate. However, these are merely examples, and the main substrate 1 in Example 1 may have a material and a surface orientation that satisfy the following two conditions, and the specific material and surface orientation of the main substrate 1 are not necessarily limited. That is, the main substrate 1 may be, first, capable of manufacturing a base substrate BS by forming a metal layer ML and an Al-based nitride layer 2 above the main substrate 1. The main substrate 1 may be, second, capable of growing a semiconductor portion 8 by the ELO method using a template substrate TS manufactured by forming a mask pattern 6 above the base substrate BS including the main substrate 1. Using an inexpensive substrate as the main substrate 1 effectively reduces the manufacturing costs of the template substrate TS and the semiconductor substrate 10.

[0061] A silicon carbide (SiC) substrate can also be used as the heterogeneous substrate, the main substrate 1. In this case, the surface orientation of the main substrate 1 may be the 6H-SiC (0001) or 4H-SiC (0001) plane of the SiC substrate. The main substrate 1 may also be 3C-SiC. If using an inexpensive substrate is not important, the main substrate 1 may be a sapphire substrate or a nitride substrate (such as a GaN substrate).

[0062] The metal layer ML may be formed on the main substrate 1. Alternatively, the metal layer ML may be formed above the main substrate 1, and a heterogeneous layer made of a material different from that of the main substrate 1 and the metal layer ML may be interposed between the main substrate 1 and the metal layer ML. In the first embodiment, the metal layer ML may overlap the entire main surface 1a of the main substrate 1 in a plan view. By including the metal layer ML and the Al-based nitride layer 2, the template substrate TS can reduce the possibility of a problem of mutual reaction between silicon and gallium at high temperatures (so-called meltback) even when a silicon substrate or the like is used as the main substrate 1.

[0063] In Example 1, the metal layer ML may be an Al layer, and the thickness of the metal layer ML is, for example, 20 nm or more. This can improve the quality of the Al-based nitride layer 2 formed on the metal layer ML. The Al layer serving as the metal layer ML may be formed by growing Al having a face-centered cubic structure in the <111> direction from the main surface 1a of the main substrate 1 (e.g., the (111) plane of a silicon substrate). In this case, the surface MLS of the metal layer ML on the side farther from the main substrate 1 becomes the (111) plane of the face-centered cubic structure.

[0064] The Al-based nitride layer 2 has a wurtzite structure. The (111) plane in the face-centered cubic structure corresponds to the atomic arrangement of a hexagonal crystal system, so the Al-based nitride layer 2 can be epitaxially grown in the c-axis direction from the surface MLS of the metal layer ML. At the interface between the Al-based nitride layer 2 and the metal layer ML, the surface MLS and the second surface 2b have plane orientations that correspond to each other. Such an Al-based nitride layer 2 can be said to inherit the crystal structure of the metal layer ML.

[0065] The metal layer ML may contain at least one metal whose (111) plane of a face-centered cubic lattice or a body-centered cubic lattice, or whose (0001) plane of a hexagonal close-packed lattice is oriented toward the main surface 1a of the main substrate 1. Examples of such metals include aluminum, as well as platinum, palladium, silver, gold, hafnium, scandium, yttrium, titanium, and zirconium. This allows the surface MLS of the metal layer ML to be the (111) plane of a face-centered cubic lattice or a body-centered cubic lattice, or the (0001) plane of a hexagonal close-packed lattice, making it easier to grow the Al-based nitride layer 2 from the surface MLS.

[0066] Increasing the thickness of the metal layer ML in the range of 20 nm or more can improve the quality (e.g., orientation) of the Al-based nitride layer 2. The quality of the Al-based nitride layer 2 can be evaluated, for example, by measuring an X-ray rocking curve of the Al-based nitride layer 2 after deposition. When the thickness of the metal layer ML is about 1000 nm, the effect of the thickness of the metal layer ML on the quality of the Al-based nitride layer 2 can be reduced. The thickness of the metal layer ML may be 20 nm or more and 2000 nm or less, or may be 100 nm or more and 2000 nm or less.

[0067] According to the study by the inventors, for example, when an AlN layer as the Al-based nitride layer 2 is formed on an Al film as the metal layer ML, and the relationship between the film thickness of the Al film and the half-width of the X-ray rocking curve measurement results of the AlN layer is investigated, it has been found that the greater the thickness of the Al film, the smaller the half-width and the better the quality of the AlN layer tends to be. Since the film formation time of the Al film (i.e., the film thickness of the Al film) is related to the production cost, the film thickness of the Al film can be set in consideration of the balance between the production cost and the quality of the AlN layer.

[0068] In Example 1, the Al-based nitride layer 2 may be an AlN layer, and the thickness of the AlN layer may be, for example, 30 nm or more. The thickness of the AlN layer may be larger than that of the Al film serving as the metal layer ML, and may be, for example, 30 nm or more and 500 nm or less.

[0069] In Example 1, the metal layer ML and the Al-based nitride layer 2 can be continuously formed in a sputtering apparatus using a sputtering method, which can be appropriately selected from DC sputtering, RF sputtering, AC sputtering, DC magnetron sputtering, ECR (Electron Cyclotron Resonance) sputtering, RF magnetron sputtering, PSD (Pulse Sputter Deposition), laser ablation, and the like.

[0070] The metal layer ML formed by sputtering may contain argon derived from the argon gas introduced into the sputtering apparatus. Depending on the metal species contained in the metal layer ML, argon can be detected by SIMS (Secondary Ion Mass Spectrometry).

[0071] For example, the degree of vacuum in the sputtering device before film formation is set to 3×10 －５ Pa or less or 1 x 10 －５ The pressure may be set to Pa or less. By pretreating the main substrate 1 before starting the film formation process, organic layers and irregularities on the main surface 1a of the main substrate 1 may be removed, enabling epitaxial growth of the metal layer ML. Specific examples of pretreatment include reverse sputtering, acid treatment, and UV treatment. Reverse sputtering is a method of cleaning the main surface 1a of the main substrate 1 by bombarding plasma atoms with the main substrate 1, which has the advantage of easily preventing re-adhesion of impurities after treatment. The substrate temperature during film formation may be room temperature, but film quality can be further improved by performing the film formation process while the main substrate 1 is heated. When heating the main substrate 1, the heating temperature can be adjusted depending on the material of the metal layer ML; for example, the heating temperature may be 700°C to 900°C.

[0072] The Al-based nitride layer 2 is formed on the metal layer ML by sputtering, and therefore has higher quality than if it were formed by sputtering directly on the main substrate 1. The Al-based nitride layer 2 contains argon derived from the argon gas introduced into the sputtering apparatus. The argon content of the Al-based nitride layer 2 may be, for example, 0.01 atm % or more and 1.0 atm % or less.

[0073] When the metal layer ML and the Al-based nitride layer 2 are formed by sputtering, the internal stress of the metal layer ML and the Al-based nitride layer 2 can be controlled by adjusting the film formation conditions. For example, by controlling the amount of argon incorporated into the film, the internal stress can be changed from compressive stress to tensile stress. This makes it possible to adjust the mutual stress relationship between the template substrate TS and the semiconductor portion 8 formed on the template substrate TS in the semiconductor substrate 10. This reduces warpage of the semiconductor substrate 10.

[0074] The mask pattern 6 is formed on the base substrate BS using a material that suppresses vertical growth (growth in the c-axis direction) of the nitride semiconductor, and realizes lateral growth (e.g., growth in the a-axis direction) of the nitride semiconductor.

[0075] Examples of materials for the mask portion 5 of the mask pattern 6 include silicon nitride, silicon carbide, silicon carbonitride, diamond-like carbon, silicon oxide, and silicon oxynitride. Examples of materials for the mask portion 5 include silicon-free materials such as titanium nitride, molybdenum nitride, tungsten nitride, and tantalum carbide, as well as high-melting-point metals (molybdenum, tungsten, platinum, etc.). The mask portion 5 may be a single-layer film made of one of these materials, or a multilayer film made of a combination of multiple materials. The thickness of the mask portion 5 may be, for example, approximately 100 nm to 4 μm. The width Wm of the mask portion 5 (size in the first direction X1) may be, for example, 10 μm to 200 μm. In Example 1, the width Wm of the mask portion 5 may be smaller than the size of the metal layer ML or the Al-based nitride layer 2 in the first direction X1.

[0076] The openings K (exposed portions of the seed regions S) in the mask pattern 6 serve as growth starting points for the semiconductor portions 8. The openings K may have a longitudinal shape with the first direction X1 as the width direction and the second direction X2 (see FIG. 1 ) as the longitudinal direction. The mask pattern 6 may have a plurality of openings K aligned in the first direction X1. The openings K may have a tapered shape (a shape whose width narrows downward). The width WK of the openings K (size in the first direction X1) may be, for example, approximately 0.1 μm to 20 μm. The width WK of the openings K may be smaller than the width Wm of the mask portion 5.

[0077] (Method of Manufacturing Template Substrate) FIG. 8 is a cross-sectional view showing a method of manufacturing the template substrate TS in Example 1. For example, a silicon substrate (Si(111) surface) is used as the main substrate 1. In a sputtering device, an Al target is sputtered while Ar gas is introduced, thereby forming an Al film on the silicon substrate. For example, the thickness of the Al film can be 100 nm, and the Al film formation temperature can be 400° C., the input power can be 500 W, and the back pressure during film formation can be 0.3 Pa.

[0078] Next, an AlN film can be formed on the Al film by sputtering the Al target while introducing a mixed gas of argon gas and nitrogen gas (for example, at a gas ratio of about 1:1) into the sputtering device. In this way, an Al film and an AlN film can be formed consecutively in the same chamber without having to take the substrate in and out.

[0079] Generally, when an AlN film is epitaxially grown on a sapphire substrate, for example, the AlN film grows in the

[0001] direction, and the outermost surface becomes an Al-polarity plane. In contrast, in the template substrate TS in Example 1, the first surface 2a of the AlN film can be an N-polarity plane. This is thought to be because, on the Al film serving as the metal layer ML, the AlN film serving as the Al-based nitride layer 2 can be epitaxially grown in the [000-1] direction from the surface MLS. Furthermore, the first surface 2a of the Al-based nitride layer 2 may be an N-polarity plane, or may be a plane in which an Al-polarity plane and an N-polarity plane are mixed (mixed polarity).

[0080] Next, a mask layer MF (e.g., SiN) having a thickness of 300 nm is formed on the Al-based nitride layer 2 by sputtering. Then, a resist is applied to the entire surface of the mask layer MF, and the resist is then patterned by photolithography to form a resist Z having a plurality of stripe-shaped openings each about 3 μm wide. Then, a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) is used to remove portions of the mask layer MF to form a plurality of openings K, and the resist Z is then removed by organic cleaning to form the mask pattern 6.

[0081] If the Al-based nitride layer 2 is formed by MOCVD, a GaN layer may also be formed within the MOCVD apparatus. Therefore, Ga may be present within the MOCVD apparatus, and in this case, Ga may adhere to the main substrate 1. If the adhered Ga causes meltback, the yield will decrease. Therefore, maintenance of the MOCVD apparatus and cleaning of the internal components (tray, cover, etc.) of the apparatus are required frequently, resulting in increased costs. In contrast, if the Al-based nitride layer 2 is formed by sputtering, the surface of the main substrate 1 is covered with the metal layer ML, the Al-based nitride layer 2, and the mask pattern 6 when the substrate is loaded into the MOCVD apparatus to form the semiconductor portion 8. This reduces the possibility of Ga adhering to the surface of the main substrate 1 and reduces the possibility of a decrease in manufacturing yield due to meltback. This is an industrially significant advantage.

[0082] (Semiconductor Substrate) Fig. 9 is a cross-sectional view schematically showing the configuration of a semiconductor substrate 10 in Example 1. Fig. 10 is a cross-sectional view showing an example of lateral growth of a semiconductor portion 8. Fig. 10 shows an example in which a mask portion 5 in a mask pattern 6 has a tapered opening K. The semiconductor substrate 10 in Example 1 has a first semiconductor portion 8A and a second semiconductor portion 8C formed by the ELO method above a template substrate TS.

[0083] 9 , the base B of the semiconductor portion 8 (first semiconductor portion 8A, second semiconductor portion 8C) is in contact with the first surface 2a of the Al-based nitride layer 2 at the openings K (first opening K1, second opening K2). The semiconductor portion 8 may have an initial growth portion SL in the portion in contact with the first surface 2a. The initial growth portion SL may be an initial growth layer SL.

[0084] The semiconductor portion 8 formed by the ELO method can be grown laterally as follows. As shown in FIG. 10 , an initial growth portion SL may be formed on the seed region S exposed from the opening K, and then the semiconductor portion 8 may be grown laterally from the initial growth portion SL. The initial growth portion SL serves as the starting point for the lateral growth of the semiconductor portion 8. By appropriately controlling the ELO film formation conditions, it is possible to control the growth of the semiconductor portion 8 to either the c-axis direction of the nitride semiconductor or the a-axis direction (first direction X1).

[0085] For example, deposition of the initial growth portion SL may be stopped just before the edge of the initial growth portion SL reaches the upper surface of the mask portion 5 (when it is in contact with the upper edge of the side of the mask portion 5) or just after it reaches the upper surface of the mask portion 5 (i.e., at this timing, the ELO deposition conditions may be switched from c-axis deposition conditions to a-axis deposition conditions). By causing the initial growth portion SL to grow laterally from a state in which it slightly protrudes from the mask portion 5, the growth of the semiconductor portion 8 in the c-axis direction (thickness direction) is suppressed, allowing the semiconductor portion 8 to grow laterally at high speed with high crystallinity and reduced raw material consumption. This allows a thin, wide, and low-defect semiconductor portion 8 (crystal of a nitride semiconductor such as GaN) to be formed at low cost. The initial growth portion SL may be formed to a thickness of, for example, 30 nm to 1000 nm, 50 nm to 400 nm, or 70 nm to 350 nm.

[0086] The semiconductor portions 8 that have grown laterally in opposite directions from each of the two adjacent first openings K1 and second openings K2 do not come into contact (meet) with each other on the mask portion 5, and have a gap (gap) GP, which reduces internal stress in the semiconductor portion 8. This reduces cracks and defects (dislocations) that occur in the semiconductor portion 8. The width of the gap GP (size in the first direction X1) can be 5 μm or less, 3 μm or less, or 2 μm or less.

[0087] Of the semiconductor portion 8, the base portion B, which is located on the initial growth portion SL, becomes a dislocation inheritance portion with many threading dislocations, while the wing portion F, which is located on the mask portion 5, becomes a low-defect portion with a threading dislocation density of 1 / 5 or less compared to the dislocation inheritance portion. Threading dislocations are dislocations (defects) that extend in the c-axis direction (<0001> direction) in the semiconductor portion 8. The threading dislocation density can be determined, for example, by subjecting the surface of the semiconductor portion 8 to CL (Cathode Luminescence) measurement and counting the number of black dots in the CL measurement image. The threading dislocation density of the wing portion F is, for example, 5×10 ６ [pcs / cm ２ As will be described later, when an active section (active layer) including a light emitting section is formed above the semiconductor section 8, the light emitting section can be disposed above the wing section F (so as to overlap with the wing section F in plan view).

[0088] For the wing portion F, the ratio (WF / d1) of the width WF (size in the first direction X1) to the thickness d1 can be, for example, 2.0 or more. WF / d1 can be 2.0 or more, 4.0 or more, 5.0 or more, 7.0 or more, or 10.0 or more. By setting WF / d1 to 2.0 or more, the semiconductor substrate 10 can easily reduce internal stress in the semiconductor portion 8. As a result, warpage of the semiconductor substrate 10 can be reduced. The width WF of the wing portion F can be, for example, 7.0 μm or more, 10.0 μm or more, 20.0 μm or more, or 40.0 μm or more. The thickness d1 can be 10.0 μm or less, 5.0 μm or less, or 2.0 μm or less.

[0089] The density of basal plane dislocations in base B is 5 × 10 ８ / cm ２ The basal plane dislocations may be dislocations extending in the in-plane direction of the c-plane of the semiconductor portion 8. The basal plane dislocation density here can be determined, for example, by dividing the semiconductor portion 8 to expose the side surface of the base portion B and measuring the dislocation density of this side surface by CL.

[0090] The semiconductor portion 8 may not contain argon. The semiconductor portion 8 not containing argon means that the argon content in the semiconductor portion 8 is less than 0.01 atm %. Here, the base portion B or the initial growth portion SL in the semiconductor portion 8 may contain a trace amount of argon diffused from the Al-based nitride layer 2 because it is connected to the Al-based nitride layer 2. The wing portion F may not contain argon diffused from the Al-based nitride layer 2. If the wing portion F also contains argon, the argon concentration in the wing portion F may decrease the farther it is from the base portion B. For example, even if the semiconductor portion 8 contains a trace amount of argon diffused from the Al-based nitride layer 2, the argon content in the semiconductor portion 8 is less than 0.01 atm % (the semiconductor portion 8 does not contain argon).

[0091] In Example 1, the semiconductor portion 8 was a GaN layer, and an MOCVD apparatus was used to perform ELO film formation of gallium nitride (GaN) on the template substrate 7. Examples of ELO film formation conditions include a substrate temperature of 1120° C., growth pressure of 50 kPa, TMG (trimethylgallium): 22 sccm, and NH ３ : 15 slm, V / III = 6000 (ratio of the supply amount of group V raw material to the supply amount of group III raw material). ４ Alternatively, the mask portion 5 may be doped with a material containing silicon (e.g., SiO ２ By using a mask (e.g., SiN), Si evaporated from the mask portion 5 can be used for Si doping. The width Wm of the mask portion 5 was 50 μm, the width WK of the opening K was 5 μm, the horizontal width of the semiconductor portion 8 was 53 μm, the width WF of the wing portion F was 24 μm, and the layer thickness of the semiconductor portion 8 was 5 μm. The aspect ratio of the semiconductor portion 8 was 53 μm / 5 μm=10.6, which is a very high aspect ratio.

[0092] Regarding the deposition temperature of the semiconductor portion 8 using the ELO method, a temperature of 1150°C or less is preferable to a high temperature exceeding 1200°C. The semiconductor portion 8 can also be formed at a low temperature below 1000°C, which is preferable from the viewpoint of reducing mutual reactions. In Example 1, interdiffusion may occur between the Al film serving as the metal layer ML and the main substrate 1 or the Al-based nitride layer 2. In the semiconductor substrate 10, the main substrate 1 may have an alloy layer (not shown) formed by mutual reaction with the metal layer ML under ELO deposition conditions. Alternatively, the Al concentration in the main surface 1a of the main substrate 1 may be higher than the Al concentration in the back surface 1b located opposite the main surface 1a. In the semiconductor substrate 10, the Al-based nitride layer 2 may have an Al-rich composition.

[0093] It has been found that when the semiconductor portion 8 contains carbon, the reaction with the mask portion 5 can be reduced, and adhesion between the mask portion 5 and the semiconductor portion 8 can be reduced. Therefore, in low-temperature film formation of the semiconductor portion 8, for example, by reducing the amount of ammonia supplied and performing film formation at a low V / III ratio (<1000), carbon elements in the source material or chamber atmosphere can be incorporated into the semiconductor portion 8, thereby reducing the reaction with the mask portion 5. In low-temperature film formation below 1000°C, it is preferable to use triethylgallium (TEG) as the gallium source gas. Compared to trimethylgallium (TMG), TEG decomposes organic sources more efficiently at low temperatures, thereby increasing the lateral film formation rate.

[0094] In Example 1, the first surface 2 a of the Al-based nitride layer 2 may be an N-polar surface or a surface having a mixture of Al-polar and N-polar surfaces (mixed polarity), and the first surface 2 a may also be the seed region S. Even in such a case, the upper surface 8S, which is the growth surface of the semiconductor portion 8, can be made into a gallium-polar surface (Ga-polar surface) by polarity reversal due to various factors. Alternatively, the upper surface 8S may be an aluminum-polar surface (Al-polar surface). The semiconductor portion 8 can be formed by adjusting the polarity of the upper surface 8S so as to be suitable for the device structure to be manufactured using the semiconductor substrate 10.

[0095] 11 is a plan view showing another example of the configuration of the semiconductor substrate 10 in Example 1. As shown in FIG. 11 , the semiconductor portion 8 of the semiconductor substrate 10 may be separated into a plurality of parts PA arranged in a second direction X2 perpendicular to the first direction X1. A trench TR may be formed between the parts PA adjacent to each other in the second direction X2. The mask portion 5 and the Al-based nitride layer 2 may be exposed in the trench TR.

[0096] In another example of the semiconductor substrate 10, the template substrate TS may have openings K that are periodically divided in the second direction X2, and in this case, the semiconductor portion 8 may also be divided in the second direction X2.

[0097] FIG. 12 is a cross-sectional view showing another example of the configuration of the semiconductor substrate 10 in Example 1. As shown in FIG. 12 , the template substrate TS in the semiconductor substrate 10 may have a metal nitride layer NL between the metal layer ML and the Al-based nitride layer 2. The metal nitride layer NL includes a nitride of a metal other than aluminum. The metal nitride layer NL may include a material whose crystal structure is similar to that of the Al-based nitride layer 2, which facilitates epitaxial growth of the Al-based nitride layer 2. The metal nitride layer NL may include, for example, titanium nitride (TiN), zirconium nitride (ZrN), scandium nitride (ScN), or hafnium nitride (HfN). The metal nitride layer NL may be formed by a sputtering method, in which case the metal nitride layer NL may include argon. The argon content of the metal nitride layer NL may be, for example, 0.01 atm% or more and 1.0 atm% or less.

[0098] FIG. 13 is a cross-sectional view showing another example of the configuration of the semiconductor substrate 10 in Example 1. As shown in FIG. 13 , the template substrate TS in the semiconductor substrate 10 may include a plurality of different metal layers as the metal layer ML, and the metal layer ML may be a multilayer film. The template substrate TS may include, for example, a first metal layer ML1 located on the main substrate 1 and a second metal layer ML2 located on the first metal layer ML1. For example, the first metal layer ML1 may be formed of a material that has a high affinity with the main substrate 1, and the second metal layer ML2 may be formed of a material that has a high affinity with the Al-based nitride layer 2. This makes it easier to improve the quality of the Al-based nitride layer 2.

[0099] The metal layer ML may include three or more types of metal layers. By appropriately switching targets in the sputtering device, multiple metal layers can be formed continuously.

[0100] 14 is a cross-sectional view showing another example of the configuration of the semiconductor substrate 10 in Example 1. As shown in Fig. 14, the template substrate TS in the semiconductor substrate 10 may have a seed portion 3 between the Al-based nitride layer 2 and the mask pattern 6, and in this case, the surface of the seed portion 3 exposed in the opening K may serve as the seed region S. The seed portion 3 may be a seed layer.

[0101] The seed portion 3 only needs to be formed in at least a part of the opening K (of the mask pattern 6), and may be planar or patterned (e.g., striped). A GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, AlGaInN, or Al formed at a low temperature (500°C or less) may be used as the seed portion 3. The seed portion 3 may be formed of a material different from the Al-based nitride layer 2. The seed portion 3 may be formed by a sputtering method, and in this case, the seed portion 3 may contain argon. The argon content of the seed portion 3 may be, for example, 0.01 atm % or more and 1.0 atm % or less. The thickness of the seed portion 3 may be approximately 10 nm to 500 nm.

[0102] For example, when forming the seed portion 3, which is a GaN layer, by RF sputtering, a gallium nitride target (oxygen content: 0.4 atom%) is used, the film formation pressure is set to 0.1 Pa, 20 to 40 sccm of nitrogen gas is introduced, and the discharge density is set to 5 W / cm. ２ The deposition temperature may be room temperature. The introduced gas may contain argon gas.

[0103] Fig. 15 is a cross-sectional view showing another example of the configuration of the semiconductor substrate in Example 1. Fig. 16 is a plan view showing another example of the configuration of the semiconductor substrate in Example 1. As shown in Figs. 15 and 16 , the semiconductor substrate 10 may include an upper layer portion 9 located above the semiconductor portion 8 and including an active layer and a p-type layer.

[0104] After the semiconductor portion 8 is formed in the MOCVD apparatus, the semiconductor substrate 10 may be removed from the MOCVD apparatus with the semiconductor portion 8 exposed and stored. In this case, the stored semiconductor substrate 10 can be loaded into the MOCVD apparatus to form the upper layer portion 9. Alternatively, after the semiconductor portion 8 is formed in the MOCVD apparatus, the upper layer portion 9 may be formed in the MOCVD apparatus subsequently. For example, the upper layer portion 9 may be formed on the semiconductor portion 8 by changing the film formation conditions (e.g., by lowering the film formation temperature by about 100° C.) after stopping the growth of the semiconductor portion 8. The upper layer portion 9 may include at least one of a p-type layer, an n-type layer, and an electron blocking layer in addition to the active layer.

[0105] The semiconductor substrate 10 may have an anode EA and a cathode EC located on the upper layer portion 9. The anode EA may be in contact with a p-type layer in the upper layer portion 9, and the cathode EC may be in contact with an n-type layer in the upper layer portion 9. Without being limited to this, the cathode EC may be in contact with the upper surface 8S of the semiconductor portion 8. In a plan view, at least a portion of the anode EA may be located so as to overlap with the wing portion F, or the entire anode EA may be located so as to overlap with the wing portion F.

[0106] A device structure including the semiconductor portion 8 and the upper layer portion 9 is referred to as a laminated body LB. The semiconductor substrate 10 has a plurality of bar-shaped laminated bodies LB. For the upper layer portion 9 (device layer) formed on the semiconductor portion 8, by forming at least the active region (e.g., light-emitting region) above the wing portion F, a very high-quality device can be fabricated. In Example 1, the template substrate TS is formed without using an MOCVD apparatus, and the semiconductor portion 8 and the upper layer portion 9 can be formed successively in the MOCVD apparatus.

[0107] Fig. 17 is a plan view showing a method for element isolation in Example 1. Fig. 18 is a cross-sectional view showing the method for element isolation in Example 1. As shown in Figs. 17 and 18 , semiconductor substrate 10 may have, on base substrate BS, a plurality of element bodies 20 separated by a plurality of trenches TR. Each element body 20 may include wing portions F, upper layer portions 9, an anode EA, and a cathode EC.

[0108] The semiconductor substrate 10 may have a plurality of element bodies 20 formed therein by forming a plurality of trenches TR in the laminate LB by etching. Alternatively, the semiconductor substrate 10 may be divided into a plurality of parts PA (see FIG. 11 ) by forming a plurality of trenches TR in the semiconductor portion 8, and then the upper layer portion 9, anode EA, and cathode EC may be formed on the parts PA. Alternatively, the semiconductor substrate 10 may have a plurality of element bodies 20 formed therein by cleaving the laminate LB.

[0109] In the example shown in FIGS. 17 and 18 , the mask portion 5 is removed by etching using hydrofluoric acid, buffered hydrofluoric acid (BHF), or the like. This makes it easier to separate the element body 20 from the base substrate BS. For example, the element body 20 may be bonded to the support substrate SK via bonding layers H1 and H2. Next, the bond between the seed region S and the semiconductor portion 8 is broken, thereby allowing the element body 20 to be peeled off from the base substrate BS. The support substrate SK may have a conductive pad in contact with the bonding layer H1 and a conductive pad in contact with the bonding layer H2. The bonding layers H1 and H2 may be formed of a solder material.

[0110] Specific examples of the element 20 include a light emitting diode (LED), a semiconductor laser, a Schottky diode, a photodiode, and a transistor (including a power transistor and a high electron mobility transistor).

[0111] 19 is a plan view showing another example of the configuration of the semiconductor substrate 10 in Example 1. As shown in Fig. 19, the semiconductor substrate 10 may have the anode EA and the cathode EC formed above the same wing portion F (e.g., the first wing portion F1). A trench TR may be formed in a portion of the stacked body LB located above the seed region S.

[0112] [Example 2] Fig. 20 is a plan view schematically showing the configuration of a semiconductor substrate 10 in Example 2. Fig. 21 is a cross-sectional view schematically showing the configuration of a semiconductor substrate 10 in Example 2. In Fig. 21, the black dots shown at the positions indicated by the lead lines of symbols J1 and J2 indicate spaces (gap) between the wing portions F and the template substrate TS.

[0113] 20 and 21 , in the semiconductor substrate 10 of Example 2, the template substrate TS may have a ridge portion R on its upper surface, and a first seed region S1 may be located on the upper surface of the ridge portion R. A first gap J1 may be present between the first semiconductor portion 8A and the mask portion 5. The first gap J1 can also be considered to be a space sandwiched between the growth inhibition region DA and a first wing portion F1. The first wing portion F1 is spaced apart from the mask portion 5, which functions as the growth inhibition region DA. The first seed region S1 (or its surface) is located above the growth inhibition region DA, and the first semiconductor portion 8A has a first base portion B1 located on the first seed region S1 and a first wing portion F1 connected to the first base portion B1 and facing the growth inhibition region DA across the first gap J1.

[0114] In the template substrate TS, the Al-based nitride layer 2 does not have to overlap the mask portion 5 in plan view. In the template substrate TS, at least a part of the metal layer ML may be included in the ridge portion R. In the template substrate TS in Example 2, the metal layer ML and the Al-based nitride layer 2 may be included in the ridge portion R.

[0115] The upper surface (first seed region S1) of the ridge portion R may be formed of the Al-based nitride layer 2, and the side surface of the ridge portion R may be covered with the mask portion 5. The template substrate TS may include a portion of the mask portion 5 on the side surface of the ridge portion R. The metal layer ML and the Al-based nitride layer 2 may not be exposed on the side surface of the ridge portion R. The side surface of the ridge portion R may not be in contact with the first wing portion F1. The entire side surface of the ridge portion R may face the first gap J1. This reduces the contact area between the ridge portion R and the first wing portion F1, and as a result, the defect density of the first wing portion F1 can be reduced.

[0116] The first semiconductor portion 8A can be formed by an epitaxial lateral overgrowth (ELO) method, starting from the Al-based nitride layer 2 exposed below the first opening K1. The Al-based nitride layer 2 may be a seed layer including a first seed region S1. The second semiconductor portion 8C grows laterally on the mask portion 5, starting from the Al-based nitride layer 2 exposed below the second opening K2. Growth may be stopped before the first semiconductor portion 8A and the second semiconductor portion 8C meet. In this case, an edge E1 of the first wing portion F1 can be formed above the growth inhibition region DA.

[0117] The aspect ratio of the first void J1 (the ratio of the width WJ in the first direction X1 to the thickness TJ) can be set to 5.0 or more, which allows for rapid formation of a wide first wing portion F1 with high crystallinity (low defect density). Furthermore, the flatness of the first wing portion F1 is improved. The width WJ of the first void J1 is the distance in the first direction X1 from the side surface of the ridge R to the edge E of the first semiconductor portion 8A. The thickness (height) TJ of the first void is the distance from the upper surface of the mask portion 5 that forms the growth inhibition region DA to the lower surface (back surface) of the first semiconductor portion 8A.

[0118] The ratio of the width to the thickness of the first wing portion F1 in the first direction X1 may be 2.0 or greater. The width of the first wing portion F1 in the first direction X1 may be 7.0 μm or greater, for example, 10.0 μm or greater, 20.0 μm or greater, or 40.0 μm or greater. The width of the first wing portion F1 in the first direction X1 may be 80.0 μm or less. This reduces the possibility of the semiconductor portion 8 warping toward the substrate due to gravity. The thickness of the first wing portion F1 in the first direction X1 may be, for example, 10.0 μm or less, 5.0 μm or less, or 2.0 μm or less. As shown in FIG. 21 , the width of the gap GP may be greater than the thickness TJ of the first void J1.

[0119] The semiconductor substrate 10 may have a second gap J2 between the second semiconductor portion 8C and the mask portion 5, and the second gap J2 may have the same configuration as the first gap J1. Therefore, a repeated description of the second gap J2 will be omitted.

[0120] 22 is a cross-sectional view showing an example of a method for manufacturing the semiconductor substrate 10 in Example 2. The semiconductor substrate 10 in Example 2 can be manufactured, for example, as follows. A silicon substrate (Si(111) surface) is used as the main substrate 1, an Al film is formed on the silicon substrate as the metal layer ML, and then an AlN film is formed on the Al film as the Al-based nitride layer 2. The metal layer ML and the Al-based nitride layer 2 are formed by sputtering.

[0121] Next, a stripe-shaped resist Z having a width of about 3 μm is formed on the Al-based nitride layer 2 using photolithography, and a dry etching process is used to form a ridge portion R. At this time, the Al-based nitride layer 2 and a portion of the metal layer ML are etched. Here, the resist Z is not removed, and a mask layer MF (e.g., a SiN film having a thickness of 10 nm) that will become the mask portion 5 is formed on the main substrate 1 and the resist Z.

[0122] As in the above-described first embodiment, when the semiconductor portion 8 contacts the mask portion 5 above the growth inhibition region DA, the mask portion 5 must be at least approximately 100 nm thick. Contact between the semiconductor portion 8 and the mask portion 5 may interfere with ELO growth and affect the surface flatness of the semiconductor portion 8. In contrast, in the second embodiment, the wing portion F is suspended in midair, so that the wing portion F and the mask portion 5 do not contact each other above the growth inhibition region DA. Therefore, even if the mask portion 5 is made very thin, the growth of the wing portion F is not inhibited, and the internal stress of the semiconductor portion 8 can be reduced. As a result, warping of the semiconductor substrate 10 is easily reduced.

[0123] Furthermore, thinning the mask portion 5 improves the flatness of the rear surface of the wing portion F. The thickness of the mask portion 5 may be, for example, 1 μm or less, or 50 nm or less. When the thickness of the mask portion 5 is 50 nm or less, flatness is improved, and the thickness can also be set to 30 nm or less.

[0124] Next, the resist Z is removed to lift off the mask layer MF on the ridge portion R, and a first opening K1 is formed, thereby forming a template substrate TS (selective growth substrate). By fabricating the template substrate TS without using the MOCVD method, significant cost reductions can be achieved, which is extremely advantageous for the industry.

[0125] Next, the template substrate TS is transferred into an MOCVD apparatus, and the semiconductor portion 8 is formed on the template substrate TS by the ELO method. In Example 2, the semiconductor portion 8 is a GaN layer, and the growth temperature is 1000 to 1200°C, the V / III ratio is 500 to 20,000, and the growth pressure is 50 kPa. Note that, as in Example 1, Si doping may be performed to make the semiconductor portion 8 n-type. The film formation conditions are preferably set in at least two stages. In the first stage, the film formation temperature is set to approximately 1030°C, and the V / III ratio is set to approximately 2,000, to form growth nuclei (vertical growth portions) of the ELO layer (semiconductor portion 8) above the opening K. The thickness (height) of the growth nuclei is set to approximately 0.2 μm to 3 μm, and their width may be approximately the same as the width of the ridge R or may extend slightly in the a-axis direction (<11-20> direction). In the second stage, the film formation temperature was raised by about 100° C., and the GaN layer was grown laterally (in the a-axis direction) from the growth nuclei, and the growth was stopped when the width of the gap GP between the semiconductor portions 8 (GaN layers) growing in opposite directions over the voids reached a specified value (10 μm or less). The semiconductor substrate 10 obtained in this manner (with the semiconductor portions 8 exposed) may be removed from the MOCVD apparatus and stored, or an upper layer including an active layer may be subsequently formed in the MOCVD apparatus.

[0126] FIG. 23 is a cross-sectional view showing another example of the configuration of the semiconductor substrate 10 in Example 2. As shown in FIG. 23 , in the semiconductor substrate 10, the main substrate 1 may include a protrusion Q on the main surface 1 a, and at least a portion of the protrusion Q may be included in the ridge portion R. The metal layer ML and the Al-based nitride layer 2 may be located on the protrusion Q. The protrusion Q can be formed by removing a portion of the main substrate 1 when forming the ridge portion R by a dry etching process. In the example shown in FIG. 23 , the first gap J1 can be formed more reliably, which makes it easier to reduce warpage of the semiconductor substrate 10.

[0127] 24 is a cross-sectional view showing another example of the configuration of the semiconductor substrate 10 in Example 2. As shown in Fig. 24, in the semiconductor substrate 10, the metal layer ML may include a protruding portion MQ on the surface facing the Al-based nitride layer 2, and the Al-based nitride layer 2 may be located on the protruding portion MQ. At least a part of the metal layer ML may be located between the main substrate 1 and the mask portion 5. When the ridge portion R is formed by a dry etching process, part of the metal layer ML on the main substrate 1 remains without being removed, thereby forming the protruding portion MQ.

[0128] 25 is a cross-sectional view showing another example of the configuration of the semiconductor substrate 10 in Example 2. As shown in Fig. 25, in the semiconductor substrate 10, a metal layer ML is located over the entire surface of the main substrate 1, and an Al-based nitride layer 2 may be located locally on the metal layer ML. In the example shown in Fig. 25, the metal layer ML does not need to be included in the ridge portion R.

[0129] 26 is a cross-sectional view showing another example of the configuration of the semiconductor substrate 10 in Example 2. As shown in Fig. 26, the side surface (mask portion 5) of the ridge portion R of the semiconductor substrate 10 may be in contact with the first wing portion F1. As long as the first wing portion F1 does not contact the mask portion 5 in the growth inhibition region DA, the first gap J1 can be formed, and this does not pose a problem.

[0130] [Example 3] In the above Examples 1 and 2, the Al-based nitride layer 2 was formed on the main substrate 1, but this is not limited to this. The Al-based nitride layer 2 can also be formed on a substrate (hereinafter referred to as temporary substrate 1T) separate from the main substrate 1, and then the Al-based nitride layer 2 can be transferred to the main substrate 1.

[0131] FIG. 27 is a cross-sectional view showing an example of a manufacturing method of the semiconductor substrate 10 in Example 3. As shown in FIG. 27, first, a metal layer ML and an Al-based nitride layer 2 are formed above a temporary substrate 1T by sputtering. The temporary substrate 1T may be made of any material as long as it is capable of forming the metal layer ML and the Al-based nitride layer 2. Since the temporary substrate 1T is reusable as described below, even if a relatively expensive substrate is used, the impact on manufacturing costs is small. For example, a 4H—SiC substrate can be used as the temporary substrate 1T. Furthermore, a silicon substrate can be used as the main substrate 1.

[0132] A metal layer ML can be formed on the entire surface of the temporary substrate 1T, and an Al-based nitride layer 2 can be formed on the metal layer ML. Generally, an AlN film is formed on a 4H—SiC substrate by sputtering. As shown in the example of FIG. 27 , by forming the Al-based nitride layer 2 on the temporary substrate 1T via the metal layer ML, an Al-based nitride layer 2 of higher quality than conventional can be formed.

[0133] Next, for example, the first surface 2a of the Al-based nitride layer 2 and the main surface 1a of the main substrate 1 are each subjected to plasma treatment in a vacuum to clean the surfaces. This activates the surfaces (leading to the presence of dangling bonds on the surface). Thereafter, the first surface 2a of the Al-based nitride layer 2 and the main surface 1a of the main substrate 1 are brought into contact with each other, thereby enabling the Al-based nitride layer 2 and the main substrate 1 to be surface activated bonded together.

[0134] Thereafter, the metal layer ML is removed and the temporary substrate 1T is separated, thereby transferring the Al-based nitride layer 2 to the main substrate 1. The subsequent processing may be the same as in the first embodiment, in which a mask pattern 6 is formed on the Al-based nitride layer 2, and the semiconductor portion 8 is formed using the ELO method.

[0135] In Example 3, even if the metal layer ML is formed relatively thick, no problem occurs because the metal layer ML is removed during transfer. This makes it easy to improve the quality of the Al-based nitride layer 2. Furthermore, the temporary substrate 1T can be reused repeatedly by removing the metal layer ML on the surface.

[0136] As described above, in Example 3, for example, a high-quality Al-based nitride layer 2 formed on a 4H—SiC substrate can be transferred onto a silicon substrate serving as the main substrate 1. As a result, a template substrate TS having an Al-based nitride layer 2 of higher quality than conventional ones can be produced on a silicon substrate. Such a template substrate TS can be used to manufacture a semiconductor substrate 10. Therefore, the characteristics of various devices can be improved by using the semiconductor substrate 10.

[0137] In Example 3, since the Al-based nitride layer 2 does not have to be capable of epitaxial growth on the main surface 1a, the main substrate 1 may be, for example, a silicon substrate, and the surface orientation of the main surface 1a may be a (100) plane. Generally, electronic circuits and the like can be formed on the Si(100) plane, so by using, for example, a silicon substrate (Si(100) plane) as the main substrate 1, it becomes possible to integrate light-emitting elements and electronic circuits in a semiconductor device formed using the semiconductor substrate 10.

[0138] The first surface 2a of the Al-based nitride layer 2 facing the principal surface 1a of the main substrate 1 may be, for example, an N-polar surface, and in this case, the second surface 2b of the Al-based nitride layer 2 may be an Al-polar surface. When the plane orientation of the principal surface 1a of the main substrate 1 is a (100) plane, the first surface 2a of the Al-based nitride layer 2 has a hexagonal crystal structure, and therefore the principal surface 1a and the first surface 2a have different crystal atomic arrangement patterns in the in-plane direction.

[0139] Furthermore, when the plane orientation of the main surface 1a of the main substrate 1 is a (111) plane, the x-axis and y-axis directions of the unit lattice in the atomic arrangement of the main surface 1a may differ from the x-axis and y-axis directions of the unit lattice in the atomic arrangement of the first surface 2a of the Al-based nitride layer 2. The presence of such a bond trace, which is a difference between the main surface 1a and the first surface 2a, makes it possible to distinguish between the AlN film epitaxially grown on the main substrate 1 and the Al-based nitride layer 2 transferred onto the main substrate 1. The bond trace can be confirmed, for example, based on the results of X-ray measurement or the like.

[0140] 28 is a cross-sectional view showing an example of a method for manufacturing a template substrate TS having another configuration example in Example 3. As shown in FIG. 28, a 4H—SiC substrate is used as a temporary substrate 1T, and an Al film (film thickness: 100 nm) is formed as a metal layer ML. Then, an Al-based nitride layer 2 is formed on the Al film. The Al-based nitride layer 2 may be a ScAlN film (film thickness: 1000 nm).

[0141] A silicon substrate is used as the main substrate 1, and an intermediate layer IL is formed on the main substrate 1. The intermediate layer IL may be, for example, a molybdenum film (thickness: 1000 nm) and can be formed using a sputtering method. The surface of the intermediate layer IL is cleaned, and the intermediate layer IL and the Al-based nitride layer 2 are activated and bonded together. The metal layer ML is removed, and the Al-based nitride layer 2 is transferred onto the intermediate layer IL of the main substrate 1.

[0142] This makes it possible to manufacture a template substrate TS that includes the main substrate 1, the intermediate layer IL on the main substrate 1, and the Al-based nitride layer 2 on the intermediate layer IL. Such a template substrate TS can be used to manufacture, for example, a BAW filter in which the Al-based nitride layer 2 serves as a piezoelectric layer and the intermediate layer IL serves as an acoustic wave reflector.

[0143] 29 is a cross-sectional view showing an example of a manufacturing method for a template substrate TS having another configuration example in Example 3. As shown in FIG. 29, a 4H—SiC substrate is used as a temporary substrate 1T, and an Al film (thickness: 100 nm) is formed as the metal layer ML. Then, an AlN film (thickness: 200 nm) is formed as the Al-based nitride layer 2 on the Al film. Furthermore, a GaN film (thickness: 1000 nm) is formed as the first layer L1 on the Al-based nitride layer 2, and an AlGaN film (thickness: 10 nm) is formed as the second layer L2 on the first layer L1. The metal layer ML, the Al-based nitride layer 2, the first layer L1, and the second layer L2 are each formed using a sputtering method.

[0144] Next, the second layer L2 is temporarily bonded to the support substrate 1S. The material of the support substrate 1S is not particularly limited, and any known method can be used for temporary bonding. By removing the metal layer ML, the Al-based nitride layer 2, the first layer L1, and the second layer L2 are transferred onto the support substrate 1S.

[0145] Thereafter, for example, in a vacuum, the second surface 2b of the Al-based nitride layer 2 and the main surface 1a of the main substrate 1 are each plasma-treated, and the second surface 2b is brought into contact with the main surface 1a, thereby surface-activating bonding the Al-based nitride layer 2 and the main substrate 1. Then, the temporary bond between the second layer L2 and the support substrate 1S is removed, thereby transferring the Al-based nitride layer 2, the first layer L1, and the second layer L2 to the main substrate 1.

[0146] This makes it possible to manufacture a template substrate TS that includes the main substrate 1, the Al-based nitride layer 2 on the main substrate 1, the first layer L1 on the Al-based nitride layer 2, and the second layer L2 on the first layer L1. Such a template substrate TS can be used to manufacture, for example, a HEMT, in which the first layer L1 serves as an electron passing layer and the second layer L2 serves as an electron generating layer.

[0147] 30 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate 10 in Example 4. As shown in Fig. 30, the semiconductor substrate 10 can be formed into a structure having a ridge portion R (ridge structure) as in Example 2 by using the template substrate TS of Example 3 described above.

[0148] Using a template substrate TS having a main substrate 1 and an Al-based nitride layer 2 located on the main substrate 1, first, a striped resist Z is formed on the Al-based nitride layer 2. A portion of the Al-based nitride layer 2 is etched by a dry etching process. A mask layer MF (e.g., a SiN film with a thickness of 10 nm) that will become a mask portion 5 is formed on the main substrate 1 and the resist Z.

[0149] Thereafter, the template substrate TS and the semiconductor substrate 10 can be manufactured by performing the same processes as those described above in Example 2. The template substrate TS has, on its upper surface side, a ridge portion R in which the first seed region S1 is located. In the semiconductor substrate 10, a first gap J1 exists between the first semiconductor portion 8A and the growth inhibition region DA.

[0150] In the template substrate TS, the growth suppression region DA may be a modified region of the Al-based nitride layer 2, and the first seed region S1 may be an unmodified region of the Al-based nitride layer 2. The Al-based nitride layer 2 can be modified by, for example, performing a plasma treatment on the Al-based nitride layer 2.

[0151] In the plasma treatment, for example, argon plasma is irradiated onto a predetermined region of the Al-based nitride layer 2 to modify the surface of the irradiated region and form a growth-inhibiting region DA. By introducing oxygen gas, nitrogen gas, hydrogen gas, or the like into the chamber in addition to argon gas, the plasma treatment can also use oxygen plasma, nitrogen plasma, hydrogen plasma, or a mixture of these plasmas in addition to argon plasma. As a result, the growth-inhibiting region DA may contain argon, oxygen, nitrogen, or the like as impurities. In such a case, the Al-based nitride layer 2 may be aluminum nitride, and the growth-inhibiting region DA may be aluminum oxynitride. Alternatively, the Al-based nitride layer 2 may be AlScN (aluminum scandium nitride), and the growth-inhibiting region DA may be AlScON (aluminum scandium oxynitride).

[0152] [Additional Notes] The invention according to the present disclosure has been described above based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-described embodiments and examples. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments and examples are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure.

[0153] REFERENCE SIGNS LIST 1 Main substrate 2 Al-based nitride layer 5 Mask portion 6 Mask pattern 8 Semiconductor portion 8A First semiconductor portion 8C Second semiconductor portion 10 Semiconductor substrate B Base portion DA Growth inhibition region F Wing portion GP Gap K Opening ML Metal layer S Seed region TS Template substrate

Claims

1. a template substrate including a first seed region and a growth inhibition region; and a first semiconductor portion having a first base portion located above the first seed region and a first wing portion connected to the first base portion and located above the growth inhibition region; the template substrate includes a main substrate, a metal layer located above the main substrate, and an aluminum-based nitride layer located above the metal layer and containing argon; The first semiconductor portion includes a nitride semiconductor.

2. the aluminum-based nitride layer is an aluminum nitride layer, the main substrate is a heterogeneous substrate having a lattice constant different from that of the first semiconductor portion, the aluminum nitride layer is a seed layer including the first seed region and in contact with the first base; The semiconductor substrate of claim 1 , wherein the first semiconductor portion is free of argon.

3. The semiconductor substrate of claim 1 , wherein the metal layer contains at least one of argon and hydrogen.

4. 2. The semiconductor substrate of claim 1, wherein the metal layer comprises one or more metals selected from the group consisting of aluminum, platinum, palladium, silver, gold, hafnium, scandium, yttrium, titanium, and zirconium.

5. 2. The semiconductor substrate according to claim 1, wherein the metal layer contains at least one metal whose (111) plane of a face-centered cubic lattice or a body-centered cubic lattice or whose (0001) plane of a hexagonal close-packed lattice is oriented on the main surface of the main substrate.

6. The semiconductor substrate of claim 1 , wherein the metal layer includes a first layer made of a metallic material and a second layer made of a metallic material different from the first layer.

7. The semiconductor substrate according to claim 1 , wherein the metal layer overlaps an entire upper surface of the main substrate in a plan view seen in a normal direction of the main substrate.

8. The semiconductor substrate of claim 1 , further comprising a metal nitride layer located between said metal layer and said aluminum-based nitride layer.

9. 2. The semiconductor substrate according to claim 1, wherein the metal layer has a thickness of 20 nm or more.

10. The semiconductor substrate according to claim 1 , wherein the aluminum-based nitride layer has a thermal expansion coefficient at 1000° C. that is larger than that of the main substrate and smaller than that of the first semiconductor portion.

11. The semiconductor substrate according to claim 1 , wherein, at room temperature, the aluminum-based nitride layer is in a compressive stress state, and the first semiconductor portion is in a tensile stress state.

12. The semiconductor substrate according to any one of claims 1 to 11, wherein the template substrate has a mask pattern including a mask portion that functions as the growth inhibition region and an opening that corresponds to the first seed region.

13. The semiconductor substrate of claim 12 , wherein the aluminum-based nitride layer overlaps the mask portion.

14. The semiconductor substrate of claim 12 , wherein the aluminum-based nitride layer does not overlap the mask portion.

15. the template substrate has, on an upper surface side, a ridge portion in which the first seed region is located; The semiconductor substrate according to claim 12 , wherein a gap exists between the first semiconductor portion and the mask portion.

16. The semiconductor substrate according to claim 15 , wherein at least a portion of the metal layer is included in the ridge portion.

17. The main substrate has a convex portion on an upper surface side, The semiconductor substrate according to claim 15 , wherein at least a portion of the protrusion is included in the ridge portion.

18. The semiconductor substrate according to claim 15 , wherein a side surface of the ridge portion includes a part of the mask portion.

19. a template substrate including a first seed region and a growth inhibition region; and a first semiconductor portion having a first base portion located above the first seed region and a first wing portion connected to the first base portion and located above the growth inhibition region; the template substrate includes a main substrate and an aluminum-based nitride layer having a nitrogen polarity surface bonded to the main substrate and containing argon; The first semiconductor portion includes a nitride semiconductor.

20. The semiconductor substrate according to claim 19 , wherein the aluminum-based nitride layer does not inherit a crystal structure of the main substrate at an interface with the main substrate.

21. The semiconductor substrate of claim 19 having a bond mark at an interface between the aluminum-based nitride layer and the main substrate.

22. the template substrate has, on an upper surface side, a ridge portion in which the first seed region is located; The semiconductor substrate according to claim 19 , wherein a gap exists between the first semiconductor portion and the growth inhibition region.

23. The semiconductor substrate according to claim 1 , wherein each of the first seed regions and the growth inhibition regions aligned in a first direction has a shape whose longitudinal direction is a second direction perpendicular to the first direction.

24. a second semiconductor portion including a nitride semiconductor; the template substrate has a second seed region adjacent to the first seed region in a first direction with the growth inhibition region interposed therebetween; the second semiconductor portion has a second base portion located above the second seed region and a second wing portion connected to the second base portion and located above the growth inhibition region; The semiconductor substrate according to claim 1 , wherein the first wing portion and the second wing portion are aligned in the first direction with a gap therebetween.

25. the nitride semiconductor is a GaN-based semiconductor, 20. The semiconductor substrate according to claim 1 or 19, wherein the main substrate is a silicon substrate, a silicon carbide substrate, or a glass substrate.

26. 11. The semiconductor substrate according to claim 1, wherein the aluminum nitride layer and the first semiconductor portion are each in a state of tensile stress at room temperature.

27. the growth inhibition region is a modified region of the aluminum-based nitride layer, The semiconductor substrate according to any one of claims 1 to 11, wherein the first seed region is a non-modified region of the aluminum-based nitride layer.

28. 3. The semiconductor substrate according to claim 2, wherein the aluminum nitride layer contains impurity metal elements other than aluminum at a ratio of less than 0.5 atm % to the total metal elements.

29. A method for manufacturing a template substrate including a main substrate, comprising: forming a metal layer on the temporary substrate; forming an aluminum-based nitride layer on the metal layer by sputtering; and transferring the aluminum-based nitride layer from the temporary substrate to a primary substrate.

30. 30. The method for manufacturing a template substrate according to claim 29, wherein the aluminum-based nitride layer has a nitrogen polarity surface when formed by a sputtering method, and has an Al polarity surface after transfer.

31. The method for manufacturing a template substrate according to claim 29 , further comprising removing the metal layer to separate the main substrate and the aluminum-based nitride layer from the temporary substrate.

32. The method for manufacturing a template substrate according to any one of claims 29 to 31, wherein the temporary substrate is a silicon carbide substrate and the main substrate is a silicon substrate.

33. A template substrate manufacturing apparatus that performs each step according to claim 29.