Wiring board and package structure using same

Abstract

A wiring board according to the present disclosure comprises: a first insulating layer that has a first surface; a land conductor that is located on the first surface; a second insulating layer that covers the first surface and the land conductor and has a second surface on the opposite side from the first insulating layer; a via hole that pierces the second insulating layer so as to extend from the second surface to the land conductor; and a via-hole conductor that is located in the via hole and is in contact with the land conductor. The via-hole conductor includes a first region that is located on the surface of the via-hole conductor and is in contact with the land conductor. The first region partially includes an oxidized nichrome layer.

Description

Wiring board and mounting structure using same

[0001] The present invention relates to a wiring board and a mounting structure using the same.

[0002] In wiring boards, in order to electrically connect conductor layers located on the upper and lower surfaces of an insulating layer, via holes formed in the insulating layer are filled with plating films (via-hole conductors), as shown in Patent Document 1. The via-hole conductors are usually connected to via lands at the bottom of the vias.

[0003] Japanese Patent Application Laid-Open No. 2001-127155

[0004] The wiring board according to the present disclosure includes a first insulating layer having a first surface, land conductors located on the first surface, a second insulating layer covering the first surface and the land conductors and having a second surface opposite the first insulating layer, via holes penetrating from the second surface of the second insulating layer to the land conductors, and via-hole conductors located in the via holes and in contact with the land conductors. The via-hole conductors have a first region on the surface thereof that is in contact with the land conductors. The first region partially has a nichrome oxide layer.

[0005] Furthermore, a mounting structure according to the present disclosure includes the above wiring board and an electronic component located on at least one of the upper and lower surfaces of the wiring board.

[0006] FIG. 2 is an explanatory diagram illustrating a wiring board according to an embodiment of the present disclosure. FIG. 3 is an enlarged cross-sectional view illustrating a region X shown in FIG. 1. FIG. 4 is an explanatory diagram illustrating an example of a method for forming a via-hole conductor in a wiring board according to an embodiment of the present disclosure. FIG. 5 is an explanatory diagram illustrating an example of a method for forming a via-hole conductor in a wiring board according to an embodiment of the present disclosure. FIG. 6 is an explanatory diagram illustrating an example of a method for forming a via-hole conductor in a wiring board according to an embodiment of the present disclosure. FIG. 7 is a cross-sectional photograph illustrating a state of a wiring board according to an embodiment of the present disclosure after a via-hole conductor pull test.

[0007] As described above, a via-hole conductor is usually connected to a via land at the bottom of the via. Due to differences in the thermal expansion coefficient and Young's modulus between the via-hole conductor (e.g., copper) and the resin forming the insulating layer, stress tends to concentrate at the connection between the via bottom and the via land. This makes the connection between the via bottom and the via land prone to breakage, resulting in poor connection reliability for the via-hole conductor. Therefore, there is a demand for a wiring board that provides excellent connection reliability for the via-hole conductor without degrading electrical properties.

[0008] The wiring board according to the present disclosure has a configuration as described in the section on means for solving the above problems, thereby reducing the deterioration of electrical characteristics and providing excellent connection reliability of via-hole conductors.

[0009] A wiring board according to an embodiment of the present disclosure will be described with reference to Figures 1 and 2. Figure 1 is an explanatory diagram for describing a wiring board 1 according to an embodiment of the present disclosure. As shown in Figure 1, the wiring board 1 according to the embodiment includes an insulating layer 2, a conductor layer 3, and a solder resist 4.

[0010] The insulating layer 2 includes a core insulating layer 20, a first insulating layer 21, and a second insulating layer 22. The core insulating layer 20 is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed together.

[0011] The thickness of the core insulating layer 20 is not particularly limited and is, for example, 40 μm or more and 20 mm or less. The core insulating layer 20 is not necessarily required. For example, a core insulating layer is not used in a substrate called a coreless substrate or a 2.3D substrate. For example, the thickness of the core insulating layer 20 may exceed 10 mm, as in a motherboard.

[0012] The core insulating layer 20 may contain a reinforcing material. Examples of reinforcing materials include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more reinforcing materials may be used in combination. Furthermore, the core insulating layer 20 may contain dispersed inorganic insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. Two or more inorganic insulating fillers may be used in combination. Generally, inorganic insulating fillers such as silica and alumina, which are chemically resistant to corrosion by neither acids nor alkalis, are often used in substrates intended for fine wiring. This reduces insulation degradation such as ion migration under high temperature and humidity conditions or under applied voltage.

[0013] A through-hole conductor 20a is located in the core insulating layer 20 to electrically connect the top and bottom surfaces of the core insulating layer 20. The through-hole conductor 20a is located in a through-hole that penetrates from the top surface to the bottom surface of the core insulating layer 20. The through-hole conductor 20a is formed by metal plating such as copper plating. The through-hole conductor 20a is connected to the conductor layers 3 formed on both surfaces of the core insulating layer 20. The through-hole conductor 20a may be located only on the inner wall surface of the through-hole, or may fill the through-hole.

[0014] The conductor layer 3 is not limited as long as it is a conductor such as a metal. Specifically, the conductor layer 3 is formed of a metal foil such as copper foil, or a metal plating such as copper plating. The thickness of the conductor layer 3 is not particularly limited and is, for example, 2 μm or more and 50 μm or less. The thickness of the conductor layer 3 tends to become thinner as the wiring becomes finer.

[0015] Build-up layers are located on both sides of the core insulating layer 20. The build-up layers have a structure in which conductor layers 3 and insulating layers 2 are alternately stacked. In the wiring board 1 according to one embodiment, when focusing on any two contacting insulating layers 2 among the insulating layers 2 constituting the build-up layer, the insulating layer 2 closer to the core insulating layer 20 corresponds to the first insulating layer 21, and the other insulating layer 2 corresponds to the second insulating layer 22.

[0016] Specifically, when the build-up layer has three insulating layers, if we focus on the insulating layer (first insulating layer) located on the surface of the core insulating layer and the insulating layer (second insulating layer) located on the surface of the first insulating layer, the first insulating layer closest to the core insulating layer corresponds to the first insulating layer, and the second insulating layer corresponds to the second insulating layer. If we focus on the second insulating layer and the insulating layer (third insulating layer) located on the surface of the second insulating layer, the second insulating layer closest to the core insulating layer corresponds to the first insulating layer, and the third insulating layer corresponds to the second insulating layer.

[0017] The insulating layers 2 (first insulating layer 21 and second insulating layer 22) constituting the build-up layers, like the core insulating layer 20, are not particularly limited as long as they are made of an insulating material, and as mentioned above, examples include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed together. The insulating layers 2 constituting the build-up layers may be made of the same resin or different resins. The insulating layers 2 constituting the build-up layers and the core insulating layer 20 may be made of the same resin or different resins. The thickness of the insulating layers 2 constituting the build-up layers is not particularly limited, and is, for example, 5 μm or more and 100 μm or less. The insulating layers 2 constituting the build-up layers may have the same thickness or different thicknesses.

[0018] The insulating layer 2 constituting the build-up layer may contain a reinforcing material. Examples of reinforcing materials include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more types of reinforcing materials may be used in combination. Furthermore, the insulating layer 2 constituting the build-up layer may have dispersed therein an inorganic insulating filler such as silica, alumina, aluminum oxide, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. Two or more types of inorganic insulating fillers may be used in combination.

[0019] 1, a solder resist 4 may be positioned on the surface of the build-up layer. The solder resist 4 is made of a resin, such as an acrylic-modified epoxy resin. The solder resist 4 has openings for electrically connecting the conductor layer 3 to the electrodes of the element via solder 5. Examples of the element include a semiconductor integrated circuit element and an optoelectronic element.

[0020] Via-hole conductors 3b are formed in the insulating layers 2 constituting the build-up layers to electrically connect the upper and lower surfaces of the insulating layers 2 constituting the build-up layers. The via-hole conductors 3b are located in via holes 31 formed to penetrate the insulating layers 2 constituting the build-up layers. That is, as shown in FIG. 2, the via-hole conductors 3b are located in the via holes 31 that penetrate from the second surface 222 of the second insulating layer 22 to the land conductors 3a. FIG. 2 is an enlarged cross-sectional view illustrating region X shown in FIG. 1. The second insulating layer 22 covers the first surface 211 of the first insulating layer 21 and the land conductors 3a located on the first surface 211. The second surface 222 of the second insulating layer 22 is the surface opposite to the first insulating layer 21.

[0021] 2 , the via-hole conductor 3b is filled in a via hole 31 formed in the second insulating layer 22, and its bottom (the bottom surface closer to the first surface 211) is in contact with the land conductor 3a. The land conductor 3a and the via-hole conductor 3b are part of the conductor layer 3.

[0022] The land conductor 3a is located on the first surface 211 of the first insulating layer 21 and includes a seed layer 3a1, a plating layer 3a2, and a surface treatment layer 3a3. The seed layer 3a1 may contain, for example, nichrome and have a thickness of 1 nm to 100 nm. The plating layer 3a2 is located on the surface of the seed layer 3a1. The plating layer 3a2 contains, for example, a metal such as copper. The surface treatment layer 3a3 is located so as to cover the plating layer 3a2. The surface treatment layer 3a3 contains a metal or alloy such as tin, titanium, chromium, and nichrome.

[0023] As shown in FIG. 2 , the via-hole conductor 3b includes a nichrome oxide layer 3b1, a nichrome layer 3b2, and a plating layer 3b3. The nichrome oxide layer 3b1 is formed by oxidizing a portion of the nichrome layer 3b2. The thickness of the nichrome oxide layer 3b1 may be, for example, 1 nm or more and 100 nm or less. By providing the nichrome oxide layer 3b1 with such a thickness, the wiring board 1 is provided with excellent connection reliability of the via-hole conductor 3b without deteriorating electrical characteristics.

[0024] 2 is located from the surface of second surface 222 of second insulating layer 22 to the inner wall surface of via hole 31. The region on the surface of second surface 222 of second insulating layer 22 where nichrome oxide layer 3b1 is located is defined as third region 3b13. The region on the inner wall surface of via hole 31 where nichrome oxide layer 3b1 is located is defined as second region 3b12.

[0025] In wiring board 1 according to one embodiment, nichrome oxide layer 3b1 is partially located in a region (first region 3b11) where land conductor 3a and via-hole conductor 3b are in contact. The partial location of nichrome oxide layer 3b1 in first region 3b11 relieves stress applied to the via bottom (first region 3b11). That is, by oxidizing nickel, which has a large Young's modulus, the Young's modulus decreases, and stress applied to first region 3b11 is relieved. Furthermore, the partial location of nichrome oxide layer 3b1 in first region 3b11 provides a stress relief effect without deteriorating electrical resistance.

[0026] In the first region 3b11, the nichrome oxide layer 3b1 is not limited as long as it is partially located. In other words, it can be said that the nichrome oxide layer 3b1 is scattered throughout the first region 3b11 in a planar view. The nichrome oxide layer 3b1 may be unevenly located in the first region 3b11 in a planar view. Scattered locations reduce uneven stress relaxation in the first region 3b11. For example, when viewed from above, the area occupied by the nichrome oxide layer 3b1 may be 30% or more and 70% or less. By locating the nichrome oxide layer 3b1 with such an area, the stress relaxation effect is sufficiently exhibited while maintaining sufficient electrical resistance. The area ratio of the nichrome oxide layer 3b1 in the first region 3b11 may be calculated, for example, by performing a surface analysis so as not to oxidize the first region 3b11. Specifically, the first region 3b11 in the wiring substrate 1 is exposed using a focused ion beam (FIB) or the like, and surface analysis is performed using time-of-flight secondary ion mass spectrometry (TOF-SIMS) or the like in the same chamber used for the focused ion beam or the like.

[0027] The land conductor 3a may have a plurality of recesses 32 (not shown in FIG. 2 ) located in a region (first region 3b11) in contact with the via-hole conductor 3b. A nichrome oxide layer 3b1 may be located in at least one of the recesses 32. When the nichrome oxide layer 3b1 is located in the recess 32, an anchor effect is exerted, further improving adhesion.

[0028] The thickness of the nichrome oxide layer 3b1 may be 1 nm or more and 100 nm or less, as described above, and may be smaller than the depth of the recesses 32. When the thickness of the nichrome oxide layer 3b1 is smaller than the depth of the recesses 32, the nichrome oxide layer 3b1 conforms to the recesses 32. Therefore, the upper surface of the nichrome oxide layer 3b1 becomes curved. As a result, the stress relaxation effect is further enhanced. The thickness of the nichrome oxide layer 3b1 and the depth of the recesses 32 can be measured by checking images using, for example, a scanning electron microscope or a transmission electron microscope.

[0029] The nichrome oxide layer 3b1 may be located from the surface in contact with the via-hole conductor 3b to within the recess 32. With this configuration, the wiring board 1 according to one embodiment has the nichrome oxide layer 3b1 located also at the boundary between the surface of the land conductor 3a and the recess 32, where stress is likely to concentrate. This facilitates stress relaxation. Furthermore, as shown in FIG. 2 , the nichrome oxide may be located in the third region 3b13. With this configuration, the wiring board 1 according to one embodiment can relax the stress between the third region 3b13 and the second insulating layer 22. As a result, for example, peeling of the via-hole conductor 3b from the second insulating layer 22 is reduced.

[0030] 2, in the wiring board 1 according to one embodiment, the nichrome oxide layer 3b1 is located in the second region 3b12 and the third region 3b13. However, the nichrome oxide layer 3b1 does not have to be located in the second region 3b12 and the third region 3b13. For example, if the nichrome oxide layer 3b1 is located in the second region 3b12, the stress relaxation effect can reduce peeling of the via-hole conductor 3b from the second insulating layer 22. Furthermore, the migration of ions from the nichrome layer 3b2 and the plating layer 3b3 to the insulating layer 2 can be reduced.

[0031] As shown in FIG. 6B , the via-hole conductor 3b and the land conductor 3a may have a continuous crystal 7 that straddles the boundary between the via-hole conductor 3b and the land conductor 3a. This configuration increases the connection strength between the via-hole conductor 3b and the land conductor 3a. Furthermore, the continuous crystal 7 may be formed via a nichrome oxide layer 3b1 having a thickness of 1 nm or more and 30 nm or less. This structure provides a stress relaxation effect and further increases the connection strength. The thickness of the nichrome oxide layer 3b1 may be 10 nm or more and 20 nm or less. Having the nichrome oxide layer 3b1 with this thickness effectively achieves a stress relaxation effect without inhibiting the formation of the continuous crystal 7. The presence or absence of the continuous crystal 7 and the boundary between the via-hole conductor 3b and the land conductor 3a can be confirmed using, for example, a scanning electron microscope or a transmission electron microscope.

[0032] The overall effect on the connection strength between the via-hole conductor 3b and the land conductor 3a can be demonstrated by a via-hole conductor pull test. FIG. 6 shows a cross-sectional photograph after the via-hole conductor pull test. FIG. 6A illustrates the via-hole conductor 3b and the land conductor 3a. The fact that the via-hole conductor 3b and the land conductor 3a were torn while still connected in the pull test indicates that the connection between the via-hole conductor 3b and the land conductor 3a was strong and that only a portion of the land conductor 3a was torn in the pull test. FIG. 6B is an enlarged view of the area Y enclosed by a square in FIG. 6A. In FIG. 6B, a nichrome oxide layer 3b1 can be confirmed at the interface between the via-hole conductor 3b and the land conductor 3a, indicating that the nichrome oxide layer 3b1 contributes to stress relaxation. The nichrome oxide layer 3b1 can be easily analyzed using EDX or the like.

[0033] Next, one embodiment of a method for forming via-hole conductors 3b in the via holes 31 will be described with reference to Figures 3 to 5. Figures 3 to 5 are explanatory diagrams for describing one example of a method for forming via-hole conductors 3b in the wiring board 1 according to an embodiment of the present disclosure.

[0034] First, to form land conductors 3a on the first surface 211 of the first insulating layer 21, as shown in Fig. 3A, the first insulating layer 21 is prepared with a seed layer 3a1 deposited on the first surface 211. Next, as shown in Fig. 3B, masking is performed with resist 6 to form a plating layer 3a2. The seed layer 3a1 and plating layer 3a2 are as described above, and detailed description thereof will be omitted.

[0035] 3C, the resist 6 is peeled off to remove the seed layer 3a1 from the portion masked by the resist 6. The seed layer 3a1 can be removed by, for example, etching.

[0036] Next, as shown in Fig. 3D, in order to form recesses 32 on the surface of plating layer 3a2, plating layer 3a2 is subjected to an annealing treatment. The annealing treatment may be performed, for example, at a temperature of 170°C to 220°C for 20 minutes to 90 minutes. By performing the annealing treatment under these conditions, recesses 32 having an opening diameter of 50 nm to 1000 nm and a depth of 50 nm to 300 nm are formed.

[0037] After the annealing treatment, as shown in FIG. 3E , the surface of the plating layer 3a2 on which the recesses 32 are formed is subjected to a soft etching treatment. The soft etching treatment may be performed for 20 to 60 seconds using, for example, a mixture of sulfuric acid and hydrogen peroxide. By performing the soft etching treatment, the opening diameter of the recesses 32 is set to 10 to 500 nm and the depth is set to 5 to 50 nm. In the wiring substrate according to the present disclosure, recesses are not an essential requirement. Therefore, if recesses are not formed, the annealing treatment and soft etching treatment may be omitted.

[0038] Next, as shown in FIG. 4A , the conductor (seed layer 3 a 1 and plating layer 3 a 2) is subjected to a surface treatment. The surface treatment involves tin plating to cover the seed layer 3 a 1 and plating layer 3 a 2, followed by nitric acid treatment and silane coupling treatment. Specifically, a tin layer is formed by the tin plating. The thickness of the tin layer is, for example, 2 nm to 5 nm. After the tin layer is formed, it is treated with nitric acid and coated with a silane coupling agent. The silane coupling agent is a compound having, within its molecule, a functional group that reacts with inorganic materials and a functional group that reacts with organic materials. The silane coupling agent layer has a thickness of, for example, 15 nm or less, and may be thicker than the tin layer.

[0039] 4B , the second insulating layer 22 is laminated on the first surface 211 of the first insulating layer 21. The second insulating layer 22 is as described above, and a detailed description thereof will be omitted. The second insulating layer 22 may be laminated on the first surface 211, for example, by placing an uncured or semi-cured resin sheet on the first surface 211 and curing it by applying heat and pressure.

[0040] Next, via holes 31 are formed that penetrate from the second surface 222 of the second insulating layer 22 to the land conductors 3a. The method for forming the via holes 31 is not limited, and for example, the via holes 31 are formed using a laser. The plating layer 3a2 of the land conductors 3a that has been exposed by the laser irradiation is cleaned. For example, cleaning can be performed by subjecting the plated layer 3a2 to oxygen plasma treatment and then treating it with a potassium permanganate solution. By performing this treatment, an oxide film 33 is formed on the entire surface of the exposed plating layer 3a2. Thereafter, to remove moisture from the resin (insulating layer 2), the substrate is dried at around 125°C for approximately 1 to 2 hours. This drying removes approximately 80% of the moisture.

[0041] 4C, the substrate from which moisture has been removed is subjected to a first sputtering treatment (nitrogen plasma treatment). This first sputtering treatment removes the oxide film 33 on the surface of the plating layer 3a2, leaving the oxide film 33 located in the recesses. By changing the plasma output, it is also possible to partially remove the oxide film 33.

[0042] 5A, the first sputtering process is followed by a second sputtering process (nichrome sputtering process). The second sputtering process forms a nichrome layer 3b2 on the second surface 222 of the second insulating layer 22, the side surface of the via hole 31, and the plating layer 3a2 of the land conductor 3a exposed at the bottom of the via hole 31.

[0043] In the portion of the nichrome layer 3b2 that is in contact with the plating layer 3a2 of the land conductor 3a, the nichrome layer 3b2 located in the recess 32 receives oxygen from the oxide film 33 and changes into a nichrome oxide layer 3b1. The nichrome oxide layer 3b1 may be located across the recess 32 and the flat portion. The stress relaxation effect is enhanced by locating the nichrome oxide layer 3b1 at the boundary (corner) between the recess 32 and the flat portion, where stress is likely to concentrate.

[0044] Next, as shown in Fig. 5B, a plating layer 3b3 is formed by electrolytic plating. When forming the plating layer 3b3, typically, a resist is formed to mask areas other than the vicinity of the via hole 31. After the plating process, the resist is removed, and, if necessary, excess nichrome oxide layer 3b1 and nichrome layer 3b2 formed in unnecessary areas on the second surface 222 of the second insulating layer 22 may be removed. Through these steps, the via-hole conductor 3b included in the wiring board 1 according to an embodiment of the present disclosure is formed.

[0045] Next, a mounting structure according to the present disclosure will be described. The mounting structure according to one embodiment includes a wiring board 1 according to one embodiment and an element located on the surface of the wiring board 1. A conductor layer 3 in an opening of a solder resist 4 is connected to an electrode of the element via solder 5. Examples of the element include a semiconductor integrated circuit element and an optoelectronic element. Elements may be located on both surfaces of the wiring board 1, or the element may be located on one surface and, for example, a motherboard may be located on the other surface.

[0046] The wiring board according to the present disclosure is not limited to the wiring board 1 according to the above-described embodiment. In the wiring board 1 according to the embodiment, the insulating layer 2 constituting the build-up layer has a two-layer structure. However, the insulating layer constituting the build-up layer in the wiring board according to the present disclosure is not limited to a two-layer structure and may have a stacked structure of three or more layers.

[0047] Furthermore, the invention according to the present disclosure is not limited to the above-described embodiments, and various modifications and improvements are possible within the scope of the present disclosure as shown in (1) and (9) below.

[0048] (1) A printed wiring board includes a first insulating layer having a first surface, a land conductor located on the first surface, a second insulating layer covering the first surface and the land conductor and having a second surface opposite the first insulating layer, a via hole penetrating from the second surface of the second insulating layer to the land conductor, and a via hole conductor located in the via hole and in contact with the land conductor. The via hole conductor has a first region on the surface of the via hole conductor that is in contact with the land conductor. The first region has a nichrome oxide layer partially formed thereon.

[0049] The present disclosure further discloses the following embodiments (2) to (8).

[0050] (2) In the wiring board described in (1) above, the area ratio of the nichrome oxide layer in the first region is 30% or more and 70% or less. (3) In the wiring board described in (1) or (2) above, the land conductor has a plurality of recesses on its surface in contact with the via-hole conductor, and the nichrome oxide layer is located in at least one of the recesses. (4) In the wiring board described in (3) above, the thickness of the nichrome oxide layer is smaller than the depth of the recess. (5) In the wiring board described in (3) or (4) above, the nichrome oxide layer is located from the surface in contact with the via-hole conductor to within the recess. (6) In the wiring board described in any of (1) to (5) above, the via-hole conductor has a nichrome oxide layer in a second region of the surface of the via-hole conductor that is in contact with the inner wall of the via hole. (7) In the wiring board described in any of (1) to (6) above, the via-hole conductor and the land conductor have continuous crystals that straddle the boundary between the via-hole conductor and the land conductor. (8) In the wiring board according to any one of (1) to (7) above, the nichrome oxide layer has a thickness of 1 nm or more and 100 nm or less.

[0051] (9) The wiring board according to any one of (1) to (8) above includes an electronic component located on at least one of the upper and lower surfaces of the wiring board.

[0052] REFERENCE SIGNS LIST 1 wiring board 2 insulating layer 20 core insulating layer 20a through-hole conductor 21 first insulating layer 211 first surface 22 second insulating layer 222 second surface 3 conductor layer 31 via hole 3a land conductor 3a1 seed layer 3a2 plating layer 3a3 surface treatment layer 3b via-hole conductor 3b1 nichrome oxide layer 3b11 first region 3b12 second region 3b13 third region 3b2 nichrome layer 3b3 plating layer 32 recess 33 oxide film 4 solder resist 5 solder 6 resist 7 continuous crystal

Claims

1. a first insulating layer having a first surface; a land conductor located on the first surface; a second insulating layer covering the first surface and the land conductor and having a second surface opposite to the first insulating layer; a via hole penetrating from the second surface of the second insulating layer to the land conductor; a via hole conductor located in the via hole and in contact with the land conductor; Equipped with the via-hole conductor has a first region of a surface of the via-hole conductor that is in contact with the land conductor, The first region partially has a nichrome oxide layer. Wiring board.

2. 2. The wiring board according to claim 1, wherein an area ratio of said nichrome oxide layer in said first region is 30% or more and 70% or less.

3. the land conductor has a plurality of recesses on a surface in contact with the via hole conductor, The wiring board according to claim 1 , wherein the nichrome oxide layer is located within at least one of the plurality of recesses.

4. The wiring board according to claim 3 , wherein the thickness of the nichrome oxide layer is smaller than the depth of the recess.

5. 4. The wiring board according to claim 3, wherein the nichrome oxide layer is positioned from the surface in contact with the via-hole conductor to within the recess.

6. 2. The wiring board according to claim 1, wherein the via-hole conductor has the nichrome oxide layer in a second region of a surface of the via-hole conductor that is in contact with an inner wall of the via hole.

7. The wiring board according to claim 1 , wherein the via hole conductor and the land conductor have a continuous crystal that straddles a boundary between the via hole conductor and the land conductor.

8. The wiring board according to claim 1 , wherein the nichrome oxide layer has a thickness of 1 nm or more and 100 nm or less.

9. 9. A mounting structure comprising the wiring board according to claim 1 and an electronic component located on at least one of an upper surface and a lower surface of the wiring board.