Signal transmission device, electronic equipment, and vehicle

Abstract

A signal transmission device, comprising: a signal transmission circuit that transmits a pulse signal from a primary circuit system to a secondary circuit system while insulating between the primary circuit system and the secondary circuit system; a power supply circuit that generates an output voltage of the secondary circuit system from the input voltage of the primary circuit system while insulating between the primary circuit system and the secondary circuit system; a first and a second abnormality detection circuit that detect abnormalities of the primary circuit system and the secondary circuit system; a signal transmission route that transmits the detection result of the second abnormality detection circuit of the primary circuit system from the secondary circuit system while insulating between the primary circuit system and the secondary circuit system; and a self-diagnosis circuit that performs self-diagnosis of the first and the second abnormality detection circuits and the signal transmission route. The first abnormality detection circuit includes a power supply abnormality detection unit that detects abnormalities of the power supply circuit as the diagnostic subject of the self-diagnosis circuit. The self-diagnosis circuit implements self-diagnosis of the power supply abnormality detection unit first (steps #1-3).

Description

Signal transmission devices, electronic devices, vehicles

[0001] The present disclosure relates to a signal transmission device, an electronic device, and a vehicle.

[0002] BACKGROUND ART Signal transmission devices that transmit signals between a primary circuit system and a secondary circuit system while electrically insulating the primary circuit system from the secondary circuit system have been used in various applications (such as power supply devices or motor drive devices).

[0003] An example of the related prior art is Patent Document 1 by the applicant of the present application.

[0004] International Publication No. 2022 / 070944

[0005] However, there was room for consideration regarding the introduction of a power supply circuit that supplies power from the primary circuit system to the secondary circuit system (especially the implementation of a self-diagnosis function and a soft start function).

[0006] For example, a signal transmission device disclosed in this specification includes: a signal transmission circuit configured to transmit a pulse signal from a primary circuit system to a secondary circuit system while insulating the primary circuit system from the secondary circuit system; a power supply circuit configured to generate an output voltage of the secondary circuit system from an input voltage of the primary circuit system while insulating the primary circuit system from the secondary circuit system; a first abnormality detection circuit configured to detect an abnormality in the primary circuit system; a second abnormality detection circuit configured to detect an abnormality in the secondary circuit system; a signal transmission path configured to transmit a detection result of the second abnormality detection circuit from the secondary circuit system to the primary circuit system while insulating the primary circuit system from the secondary circuit system; and a self-diagnosis circuit configured to self-diagnose each of the first abnormality detection circuit, the second abnormality detection circuit, and the signal transmission path, wherein the first abnormality detection circuit includes a power supply abnormality detection unit configured to detect an abnormality in the power supply circuit as a target for diagnosis by the self-diagnosis circuit, and the self-diagnosis circuit performs self-diagnosis of the power supply abnormality detection unit first.

[0007] Furthermore, for example, the power supply circuit disclosed in this specification includes a feedback control circuit configured to control a switch output stage for generating an output voltage for a secondary circuit system from an input voltage for the primary circuit system while isolating the primary circuit system from a secondary circuit system, and an overcurrent protection circuit configured to limit the primary current of the switch output stage to a predetermined overcurrent detection value or less, and the overcurrent protection circuit gradually increases the overcurrent detection value over a soft start period when starting or restarting the output voltage.

[0008] According to the invention disclosed in this specification, a self-diagnosis function can be implemented in a signal transmission device incorporating an isolated power supply circuit.

[0009] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. FIG. 2 is a diagram showing the basic structure of a transformer chip. FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil is formed in the semiconductor device of FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view (separation structure) of region XIII shown in FIG. 7. FIG. 9 is a schematic diagram showing an example layout of a transformer chip. FIG. 10 is a diagram showing a first embodiment of a signal transmission device. FIG. 11 is a diagram showing an example configuration of an electronic device incorporating a signal transmission device. FIG. 12 is a diagram showing an example configuration of a self-diagnosis circuit. FIG. 13 is a diagram showing a first example of self-diagnosis operation (at power-on) in the first embodiment. FIG. 14 is a diagram showing a second example of self-diagnosis operation (at UV2 detection → release) in the first embodiment. FIG. 15 is a diagram showing a second embodiment of a signal transmission device. Fig. 16 is a diagram showing an example of the configuration of a power supply circuit. Fig. 17 is a diagram showing an abnormality protection operation of the power supply circuit. Fig. 18 is a diagram showing a soft start operation of the power supply circuit. Fig. 19 is a diagram (time chart) showing an example of a self-diagnosis operation in the second embodiment. Fig. 20 is a diagram (flowchart) showing an example of a self-diagnosis operation in the second embodiment. Fig. 21 is a diagram showing the appearance of a vehicle in which an electronic device is installed.

[0010] <Signal Transmission Device (Basic Configuration)> Figure 1 shows the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system). For example, the signal transmission device 200 is formed by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0011] The controller chip 210 is a semiconductor chip that operates by receiving a power supply voltage VCC1 (for example, a maximum of 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0012] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. In other words, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signal S11 or S21 in response to the logic level of the input pulse signal IN.

[0013] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0014] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0015] The driver chip 220 is a semiconductor chip that operates by receiving a power supply voltage VCC2 (for example, a maximum of 30 V relative to GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse receiving circuit 223, and a driver 224.

[0016] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0017] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0018] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0019] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0020] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0021] More specifically, the transformer 231 outputs a received pulse signal S12 from the secondary coil 231s in response to a transmitted pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a received pulse signal S22 from the secondary coil 232s in response to a transmitted pulse signal S21 input to the primary coil 232p.

[0022] As described above, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to a rise signal and a fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0023] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, separate from the controller chip 210 and driver chip 220, and these three chips are sealed in a single package.

[0024] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby making it possible to reduce manufacturing costs.

[0025] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (BEVs [battery electric vehicles], HEVs [hybrid electric vehicles], PHEVs / PHVs (plug-in hybrid electric vehicles / plug-in hybrid vehicles), or xEVs such as FCEVs / FCVs (fuel cell electric vehicles / fuel cell vehicles)).

[0026] <Transformer Chip (Basic Structure)> Next, the basic structure of the transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of the transformer chip 230. In the transformer chip 230 shown in this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that face each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that face each other in the vertical direction.

[0027] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0028] The primary coil 231p is laid in a spiral shape starting from a first end connected to the internal terminal X21, surrounding the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. On the other hand, the primary coil 232p is laid in a spiral shape starting from a first end connected to the internal terminal X23, surrounding the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0029] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via the conductive wiring Y21 and the via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via the conductive wiring Y22 and the via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via the conductive wiring Y23 and the via Z23. The external terminals T21 to T23 are arranged in a straight line and are used for wire bonding with the controller chip 210.

[0030] The secondary coil 231s is laid in a spiral shape starting from a first end connected to the external terminal T24, surrounding the periphery of the external terminal T24 in a counterclockwise direction, and its second end corresponding to its end point is connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape starting from a first end connected to the external terminal T26, surrounding the periphery of the external terminal T26 in a clockwise direction, and its second end corresponding to its end point is connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0031] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0032] <Transformer Chip (Two-Channel Type)> Fig. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. Fig. 4 is a plan view of the semiconductor device 5 shown in Fig. 3. Fig. 5 is a plan view showing a layer in which the low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in Fig. 3. Fig. 6 is a plan view showing a layer in which the high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in Fig. 3. Fig. 7 is a cross-sectional view taken along line VIII-VIII shown in Fig. 6.

[0033] 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0034] The wide bandgap semiconductor is a semiconductor with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0035] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0036] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0037] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0038] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating sidewalls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0039] The insulating sidewalls 53A to 53D include a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C, and a fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form ground surfaces that are flush with the chip sidewalls 44A to 44D.

[0040] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and multiple (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The multiple interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, approximately 2 μm).

[0041] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0042] The second insulating layer 59 is formed on the first insulating layer 58. The second insulating layer 59 contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0043] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0044] The semiconductor device 5 includes a first functional device 45 formed in an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inward of the insulating layer 51 and spaced apart from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0045] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the description of the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0046] 5 to 7 , the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0047] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0048] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0049] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0050] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0051] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the form shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0052] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0053] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a plan view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a plan view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0054] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0055] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0056] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0057] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0058] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0059] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0060] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0061] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0062] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in a plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in a plan view.

[0063] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0064] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0065] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0066] The multiple high potential terminals 12 are each formed in a region close to the corresponding transformer 21A to 21D in a plan view. The closeness of the high potential terminal 12 to the transformer 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0067] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0068] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0069] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0070] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0071] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0072] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of the first low potential wirings 31, a plurality of the second low potential wirings 32, a plurality of the first high potential wirings 33, and a plurality of the second high potential wirings 34 are formed.

[0073] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0074] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0075] The plurality of first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. The plurality of first low-potential wirings 31 have the same structure. In the following, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low-potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the description of the structure of the other first low-potential wirings 31, and will be omitted.

[0076] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0077] The through wiring 71, the low-potential connecting wiring 72, the lead-out wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the lead-out wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0079] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0080] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0081] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0082] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0083] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0084] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0085] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0086] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the lead-out wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the lead-out wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the lead-out wiring 73, respectively.

[0087] 6 and 7 , the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A to 12D and the second inner ends 27 of the corresponding transformers 21A to 21D (high-potential coils 23). The plurality of first high-potential wirings 33 each have a similar structure. The following description will be given taking the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0088] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, multiple) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0089] The high-potential connecting wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connecting wiring 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connecting wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connecting wiring 81 is formed spaced apart from the low-potential connecting wiring 72 in a plan view and does not face the low-potential connecting wiring 72 in the normal direction Z. This increases the insulation distance between the low-potential connecting wiring 72 and the high-potential connecting wiring 81, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0090] The plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. Each of the plurality of pad plug electrodes 82 has a planar area that is smaller than the planar area of ​​the high potential connecting wiring 81 in a plan view.

[0091] 7, the distance D1 between the low potential terminal 11 and the high potential terminal 12 preferably exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2<D1). The distance D1 preferably exceeds the total thickness DT of the multiple interlayer insulating layers 57 (DT<D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values ​​of the distance D1 and the distance D2 are arbitrary and are adjusted appropriately depending on the dielectric strength voltage to be achieved.

[0092] 6 and 7, semiconductor device 5 includes dummy patterns 85 embedded in insulating layer 51 so as to be located around transformers 21A to 21D in a plan view.

[0093] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A to 21D. In other words, the dummy pattern 85 does not function as a part of the transformers 21A to 21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses electric field concentration on the high-potential coil 23. In this form, the dummy pattern 85 is routed with a line density per unit area equal to that of the high-potential coil 23. Having the line density of the dummy pattern 85 equal to that of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within a range of ±20% of the line density of the high-potential coil 23.

[0094] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0095] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0096] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0097] The dummy patterns 85 include floating dummy patterns formed in an electrically floating state within the insulating layer 51 so as to be positioned around the transformers 21A to 21D.

[0098] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0099] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0100] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0101] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0102] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0103] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The passive device may include a circuit network in which any two or more of the passive device, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0104] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a bipolar junction transistor (BJT), a metal insulator field effect transistor (MISFET), an insulated gate bipolar junction transistor (IGBT), and a junction field effect transistor (JFET).

[0105] 5 to 7 , the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape spaced apart from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0106] The device region 62 is a region that includes the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. The outer region 63 is a region outside the device region 62.

[0107] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0108] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 that surrounds the device region 62 in plan view.

[0109] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0110] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low-potential terminals 11 and the plurality of high-potential terminals 12. Furthermore, within the insulating layer 51, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating principal surface 52. Within the insulating layer 51, the seal conductor 61 may face a part of the second functional device 60 in a direction parallel to the insulating principal surface 52.

[0111] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (a plurality in this embodiment) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0112] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in a plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0113] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end-shaped form. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) form.

[0114] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0115] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined by the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0116] 7 and 8 , the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the seal conductor 61 to electrically isolate the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0117] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0118] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a band shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 is embedded toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0119] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0120] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed within the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0121] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0122] 7 , the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0123] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. Increasing the total thickness of the inorganic insulating layer 140 can increase the dielectric strength voltage on the high-potential coil 23.

[0124] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable that the first inorganic insulating layer 141 be thicker than the second inorganic insulating layer 142.

[0125] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. However, in this case, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0126] The inorganic insulating layer 140 covers the entire seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the low potential terminal 11. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the high potential terminal 12.

[0127] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0128] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Furthermore, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0129] The organic insulating layer 145 includes a first portion 146 covering the low-potential side region and a second portion 147 covering the high-potential side region. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low-potential terminal openings 148 that expose a plurality of low-potential terminals 11 (low-potential pad openings 143) in a region outside the seal conductor 61. The first portion 146 may have an overlapping portion that rises onto the periphery (overlapping portion) of the low-potential pad opening 143.

[0130] The second portion 147 is formed at a distance from the first portion 146, exposing the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0131] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0132] The embodiments of the present invention can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may also be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0133] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0134] In the above embodiment, an example has been described in which the second functional device 60 is formed. However, the second functional device 60 is not necessarily required and may be removed.

[0135] In the above embodiment, the dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0136] In the above-described embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes a plurality of transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0137] 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0138] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s forming a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s forming a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0139] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0140] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0141] That is, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0142] Pads a7 and b7 are connected to one end of the primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0143] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are drawn out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0144] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0145] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break has occurred in each coil, but also to appropriately reject defective products in which an abnormal resistance value has occurred in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0146] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0147] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0148] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0149] 9, the first transformer 301 to the fourth transformer 304 are arranged in a coupled arrangement according to the respective signal transmission directions. Referring to this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary chip to the secondary chip, are formed into a first pair by a first guard ring 305. Furthermore, for example, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary chip to the primary chip, are formed into a second pair by a second guard ring 306.

[0150] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0151] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0152] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0153] 9, it is desirable that the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are wound so as to form a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. By using such a configuration, the area where the primary coil and the secondary coil overlap each other becomes larger, which makes it possible to improve the transmission efficiency of the transformer.

[0154] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0155] <Signal Transmission Device (First Embodiment)> Figure 10 is a diagram showing a first embodiment of a signal transmission device (= a configuration to be compared with the second embodiment described below). The signal transmission device 400 of the first embodiment is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 400p to the secondary circuit system 400s and drives the gate of a power transistor (not shown) provided in the secondary circuit system 400s while electrically insulating the primary circuit system 400p (VCC1-GND1 system) from the secondary circuit system 400s (VCC2-GND2 system). The signal transmission device 400 can be understood as corresponding to the signal transmission device 200 described above.

[0156] The signal transmission device 400 has a plurality of external terminals (in this figure, power supply terminals VCC1 and VCC2, ground terminals GND1 and GND2, negative power supply terminal VEE2, input terminals INA and INB, output terminals OUT1H and OUT1L, fault terminal FLT, ready terminal RDY, enable terminal ENA, overheat / load power supply abnormality detection terminal TO_VH, short circuit detection terminal SCPIN, self-diagnosis on terminal ON, and self-diagnosis output terminal BISTOUT) as means for establishing electrical connection with the outside of the device.

[0157] On the first side (= the left side in this figure) of the package forming the signal transmission device 400, there are arranged, in order from top to bottom, a ground terminal GND1, a fault terminal FLT, an enable terminal ENA, an input terminal INA, an input terminal INB, a ready terminal RDY, a power supply terminal VCC1, a self-diagnosis output terminal BISTOUT, a self-diagnosis on terminal BISTON, and a ground terminal GND1.

[0158] On the other hand, on the second side of the package (= the side opposite to the first side mentioned above, the right side in this figure), there are arranged, in order from top to bottom, the negative power supply terminal VEE2, output terminal OUT1L, output terminal OUT1H, power supply terminal VCC2, overheat / load power supply abnormality detection terminal TO_VH, ground terminal GND2, short circuit detection terminal SCPIN, and negative power supply terminal VEE2.

[0159] In this way, the external terminals of the primary circuit system 400p (GND1, FLT, ENA, INA and INB, RDY, VCC1, BISTOUT, BISTON) can be concentrated on the first side of the package, and the external terminals of the secondary circuit system 400s (VEE2, OUT1L, OUT1H, VCC2, TO_VH, GND2, SCPIN) can be concentrated on the second side of the package.

[0160] A ground terminal GND1 and a negative power supply terminal VEE2 may be disposed at both ends of each of the first and second sides of the package. That is, two ground terminals GND1 and two negative power supply terminals VEE2 may be provided.

[0161] The signal transmission device 400 can be widely applied to general applications (such as motor drivers or DC / DC converters that handle high voltages) that require signal transmission between the primary circuit system 400p and the secondary circuit system 400s while isolating them from each other.

[0162] Continuing with the description of the internal configuration of the signal transmission device 400, with reference to Fig. 10, the signal transmission device 400 of this configuration example is configured by sealing a controller chip 410 (corresponding to the first chip), a driver chip 420 (corresponding to the second chip), and a transformer chip 430 (corresponding to the third chip) in a single package.

[0163] The controller chip 410 is a semiconductor chip that integrates circuit elements of a primary circuit system 400p that operates upon receiving a power supply voltage VCC1 (for example, up to 7 V relative to GND1). The controller chip 410 also integrates, for example, a logic circuit 411, an under-voltage lock out (UVLO) / over-voltage lock out (OVLO) circuit 412, and NMOSFETs (N-channel type metal oxide semiconductor field effect transistors) 413 to 415.

[0164] The logic circuit 411 generates a drive pulse signal PWM for a power transistor (not shown) in response to the input pulse signals INA and INB. For example, if INB=H (logical level when disabled), PWM=L (fixed value), and if INB=L (logical level when enabled), PWM=INA. The logic circuit 411 also monitors various abnormality detection signals (low voltage, overvoltage, short circuit, open circuit, overheating, load power supply abnormality, etc.) from the signal transmission device 400 and drives NMOSFETs 413 and 414 based on the monitoring results to determine the logical levels of the fault signal FLT and the ready signal RDY. The logic circuit 411 also switches the operation of the entire signal transmission device 400 (enable / disable) in response to the enable signal ENA.

[0165] Furthermore, the logic circuit 411 also has the function of performing a self-diagnosis (so-called BIST (built-in self test)) of each part of the signal transmission device 400 in response to the self-diagnosis on signal BISTON, and determining the logic level of the self-diagnosis output signal BISTOUT by driving the NMOSFET 415 based on the results of the self-diagnosis. In other words, the logic circuit 411 functions as a part of a self-diagnosis circuit incorporated in the signal transmission device 400 (details will be described later).

[0166] The UVLO / OVLO circuit 412 detects undervoltage and overvoltage of the power supply voltage VCC1, respectively, and outputs the detection results to the logic circuit 411.

[0167] The NMOSFET 413 connects / disconnects the fault terminal FLT and the ground terminal in response to an instruction from the logic circuit 411. For example, when the driver chip 420 detects overheating or an abnormality in the load power supply, the NMOSFET 413 turns on, and the fault terminal FLT goes low (= the logical level when an abnormality is detected).

[0168] The NMOSFET 414 connects / disconnects the ready terminal RDY and the ground terminal in response to an instruction from the logic circuit 411. For example, when a low voltage or an overvoltage is detected in either the controller chip 410 or the driver chip 420, the NMOSFET 414 turns on, and the ready terminal RDY goes low (= the logic level when an abnormality is detected).

[0169] The NMOSFET 415 establishes or breaks conduction between the self-diagnosis output terminal BISTOUT and the ground terminal in response to an instruction from the logic circuit 411. For example, when the self-diagnosis result of the signal transmission device 400 is NG, the NMOSFET 415 turns on, and the self-diagnosis output terminal BISTOUT becomes low level (= the logical level when an abnormality is detected).

[0170] The driver chip 420 is a semiconductor chip that integrates circuit elements of the secondary circuit system 400s that operates upon receiving a power supply voltage VCC2 (for example, a maximum of 30 V relative to GND2). The driver chip 420 integrates, for example, a logic circuit 421, a UVLO / OVLO circuit 422, comparators 423 and 424, a PMOSFET [P-channel type MOSFET] 425, and NMOSFETs 426 and 427.

[0171] The logic circuit 421 drives the gates of power transistors (not shown) connected to the output terminals OUT1H and OUT1L by turning on / off the PMOSFET 425 and the NMOSFET 426 in response to a drive pulse signal PWM input via the transformer chip 430. The output terminals OUT1H and OUT1L may be short-circuited to each other outside the signal transmission device 400. The logic circuit 421 also has a function of transmitting various abnormality detection signals (low voltage, overvoltage, short circuit, open, overheat, load power supply abnormality, etc.) from the driver chip 420 to the controller chip 410 via the transformer chip 430.

[0172] Furthermore, the logic circuit 421 also has a function of transmitting the self-diagnosis result (BIST_result) on the driver chip 420 side to the controller chip 410 via the transformer chip 430. In other words, the logic circuit 421 functions as part of a self-diagnosis circuit incorporated in the signal transmission device 400 (details will be described later).

[0173] The UVLO / OVLO circuit 422 detects undervoltage and overvoltage of the power supply voltage VCC2, respectively, and outputs the detection results to the logic circuit 421.

[0174] The comparator 423 monitors the terminal voltage of the overheat / load power supply abnormality detection terminal TO_VH to detect overheating of the power transistor or overvoltage of the load power supply.

[0175] The comparator 424 monitors the terminal voltage of the short circuit detection terminal SCPIN to detect short circuits in the power transistors (detection of penetration between the upper and lower power transistors).

[0176] The PMOSFET 425 establishes or breaks conduction between the power supply terminal and the output terminal OUT1H in response to an instruction from the logic circuit 421. For example, when the drive pulse signal PWM is at a high level, the PMOSFET 425 turns on, and the output terminal OUT1H (and therefore the output pulse signal applied to the gate of the power transistor) becomes a high level.

[0177] The NMOSFET 426 establishes or breaks conduction between the output terminal OUT1L and the ground terminal in response to an instruction from the logic circuit 421. For example, when the drive pulse signal PWM is at a low level, the NMOSFET 426 turns on, and the output terminal OUT1L (and therefore the output pulse signal applied to the gate of the power transistor) becomes a low level.

[0178] In this way, the PMOSFET 425 and the NMOSFET 426 function as a half-bridge output stage (CMOS (complementary MOS) inverter stage) for gate drive.

[0179] The NMOSFET 427 connects / disconnects the ground terminal GND2 and the short-circuit detection terminal SCPIN in response to an instruction from the logic circuit 421. For example, the NMOSFET 427 is turned off when OUT1H=H, and turned on when OUT1H=L. The NMOSFET 427 functions as a discharge switch that discharges an external capacitor (not shown) connected between SCPIN and GND2 by turning on / off in a complementary manner with a power transistor (not shown).

[0180] The transformer chip 430 is a semiconductor chip that integrates a transformer for transmitting signals in both directions while insulating the controller chip 410 and the driver chip 420 from each other.

[0181] The signal transmission device 400 of this configuration example has an independent transformer chip 430 equipped with only a transformer, in addition to the controller chip 410 and the driver chip 420, and these three chips are sealed in a single package.

[0182] With this configuration, the controller chip 410 and the driver chip 420 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby making it possible to reduce manufacturing costs.

[0183] Furthermore, the controller chip 410 and the driver chip 420 can both be manufactured using existing processes with proven results, and there is no need to conduct new reliability tests, which can contribute to shortening development time and reducing development costs.

[0184] Furthermore, even when a DC isolation element other than a transformer (for example, a photocoupler) is used, it is possible to easily accommodate this by simply replacing the transformer chip 430, which eliminates the need to redevelop the controller chip 410 and the driver chip 420, thereby contributing to shortening the development period and reducing development costs.

[0185] 11 is a diagram showing an example of the configuration of an electronic device equipped with the signal transmission device 400. Electronic device A of this example configuration has an upper gate driver IC1H(u / v / w), a lower gate driver IC1L(u / v / w), upper power transistors 2H(u / v / w), lower power transistors 2L(u / v / w), an ECU 3, and a motor 4.

[0186] The upper gate driver IC1H(u / v / w) drives the upper power transistor 2H(u / v / w) by generating an upper gate drive signal in response to an upper gate control signal input from the ECU 3 while insulating the ECU 3 from the upper power transistor 2H(u / v / w).

[0187] The lower gate drivers IC1L(u / v / w) drive the lower power transistors 2L(u / v / w) by generating lower gate drive signals in response to lower gate control signals input from the ECU 3 while insulating the ECU 3 from the lower power transistors 2L(u / v / w).

[0188] The signal transmission device 400 described above can be suitably used as the upper gate driver IC1H(u / v / w) and the lower gate driver IC1L(u / v / w).

[0189] The upper power transistors 2H (u / v / w) serve as upper switches forming a three-phase (U-phase / V-phase / W-phase) half-bridge output stage, and are connected between the power system power supply end (= the application end of the load power supply voltage PVDD) and each phase input end of the motor 4.

[0190] The lower power transistors 2L (u / v / w) are connected between each phase input terminal of the motor 4 and the power system ground terminal as lower switches that form a three-phase (U phase / V phase / W phase) half-bridge output stage.

[0191] In this figure, an IGBT (insulated gate bipolar transistor) is used as each of the upper power transistor 2H (u / v / w) and the lower power transistor 2L (u / v / w), but it is also possible to use, for example, a MOSFET instead of the IGBT.

[0192] The ECU 3 drives the upper power transistors 2H (u / v / w) and the lower power transistors 2L (u / v / w) via the upper gate driver IC1H (u / v / w) and the lower gate driver IC1L (u / v / w), respectively, thereby controlling the rotational driving of the motor 4. The ECU 3 also has the function of monitoring the fault terminals FLT and ready terminals RDY of the upper gate driver IC1H (u / v / w) and the lower gate driver IC1L (u / v / w), and performing various safety controls based on the monitoring results.

[0193] Furthermore, the ECU 3 uses the self-diagnosis on signal BISTON to output the self-diagnosis results of the signal transmission device 400, and also has the function of checking whether the various protection circuits (low voltage protection, overvoltage protection, overheat protection, and short circuit protection) of the signal transmission device 400 are normal or not based on the logic level of the self-diagnosis output signal BISTOUT.

[0194] The motor 4 is a three-phase motor that is rotationally driven in response to three-phase drive voltages U / V / W input from three-phase (U-phase / V-phase / W-phase) half-bridge output stages.

[0195] <Self-diagnosis circuit> Figure 12 is a diagram showing an example of the configuration of a self-diagnosis circuit incorporated in the signal transmission device 400 of the first embodiment (Figure 10). The self-diagnosis circuit B of this example configuration includes the aforementioned logic circuits 411 and 421 as part thereof, as well as switches SW11 to SW14 and switches SW21 to SW28. Furthermore, transformers TR1 to TR5 are integrated into the transformer chip 430 as isolation elements related to the self-diagnosis circuit B.

[0196] First, the controller chip 410 will be described.

[0197] The logic circuit 411 includes functional blocks related to the self-diagnosis circuit B, such as a logic unit 411a, an edge detection unit 411b, a pulse transmission unit 411c, a logic unit 411d, latches 411e and 411f, a NAND gate 411g, a latch 411h, an edge detection unit 411i, and a flip-flop 411j.

[0198] When an undervoltage or overvoltage is detected in either the UVLO / OVLO circuits 412 or 422, the logic unit 411a raises the gate signal S411a of the NMOSFET 414 to a high level to turn on the NMOSFET 414, thereby lowering the ready signal RDY to a low level (= the logic level when an abnormality is detected). The detection results of the UVLO / OVLO circuit 412 (= the overvoltage detection signal OV1 and the undervoltage detection signal UV1) are directly input to the logic unit 411a. On the other hand, the detection results of the UVLO / OVLO circuit 422 (= the overvoltage detection signal OV2 and the undervoltage detection signal UV2) are first input to the logic circuit 421 and then transmitted to the logic unit 411a via transformers TR1 and TR2.

[0199] The edge detection section 411b detects the falling edge of the gate signal S411a (and consequently the rising edge of the ready signal RDY) and outputs the detection result to the pulse transmission section 411c.

[0200] When the edge detection unit 411b detects the falling edge of the gate signal S411a, the pulse transmission unit 411c transmits a pulse signal S411c (= a self-diagnosis command to the driver chip 420) to the logic circuit 421 via the transformer TR3.

[0201] When the driver chip 420 detects overheating (or a load power supply abnormality) or a short circuit (vertical feedthrough) of a power transistor, the logic unit 411d raises the gate signal S411d of the NMOSFET 413 to a high level to turn on the NMOSFET 413, thereby lowering the fault terminal FLT to a low level (= the logic level when an abnormality is detected). The detection result of overheating or short circuiting (= the overheating detection signal OT and the short circuit detection signal SC) is once input to the logic circuit 421 and then transmitted to the logic unit 411d via the transformer TR4.

[0202] The latch 411e latches the gate signal S411d at a predetermined timing to generate a latch signal S411e and outputs it to the NAND gate 411g.

[0203] The latch 411f latches the secondary-side BIST result (=pulse signal S421e) transmitted from the logic circuit 421 via the transformer TR5 at a predetermined timing, thereby generating a latch signal S411f and outputting it to the NAND gate 411g.

[0204] The NAND gate 411g receives the gate signal S411a, the latch signals S411e and S411f, and the overvoltage detection signal OV1 and undervoltage detection signal UV1 as inputs, and generates the NAND signal S411g. Therefore, the NAND signal S411g goes high when at least one of the five signals is low (= the logical level when no abnormality is detected), and goes low when all of the five signals are high (= the logical level when an abnormality is detected).

[0205] The latch 411h latches the NAND signal S411g at a predetermined timing to generate a latch signal S411h and output it to the flip-flop 411j.

[0206] The edge detection unit 411i detects the rising edge of the self-diagnosis ON signal BISTON and generates a pulse in the clock signal S411i of the flip-flop 411j.

[0207] The flip-flop 411j takes in the latch signal S411h at the pulse generation timing of the clock signal S411i and outputs it as a gate signal S411j of the NMOSFET 415. When the gate signal S411j is at a high level, the NMOSFET 415 is turned on and the self-diagnosis output signal BISTOUT is at a low level (= the logic level when the self-diagnosis is NG), and when the gate signal S411j is at a low level, the NMOSFET 415 is turned off and the self-diagnosis output signal BISTOUT is in a high impedance state (= the logic level when the self-diagnosis is OK).

[0208] The UVLO / OVLO circuit 412 is one of the targets to be diagnosed by the self-diagnosis circuit B, and includes comparators 412a and 412b.

[0209] The comparator 412a compares the voltage to be monitored (DIV11 or VCC1) input to the non-inverting input terminal (+) with the overvoltage detection threshold input to the inverting input terminal (-) to generate an overvoltage detection signal OV1. The overvoltage detection signal OV1 goes high (=logical level in the event of an abnormality) when the voltage to be monitored is higher than the overvoltage detection threshold, and goes low (=logical level in the event of a normal state) when the voltage to be monitored is lower than the overvoltage detection threshold.

[0210] The comparator 412b compares the monitored voltage (DIV12 or GND1) input to its inverting input terminal (-) with the low voltage detection threshold input to its non-inverting input terminal (+) to generate the low voltage detection signal UV1. The low voltage detection signal UV1 goes high (= the logic level when an abnormality occurs) when the monitored voltage is lower than the low voltage detection threshold, and goes low (= the logic level when the monitored voltage is higher than the low voltage detection threshold).

[0211] The switch SW11 is connected between the application terminal of the divided voltage DIV11 (= the divided voltage of the power supply voltage VCC1) and the non-inverting input terminal (+) of the comparator 412a. The switch SW11 is turned off during BIST and turned on during non-BIST. On the other hand, the switch SW12 is connected between the application terminal of the power supply voltage VCC1 and the non-inverting input terminal (+) of the comparator 412a. The switch SW12 is turned on during BIST and turned off during non-BIST. That is, the divided voltage DIV11 is input to the non-inverting input terminal (+) of the comparator 412a as the voltage to be monitored mentioned above during non-BIST, and the power supply voltage VCC1 is input during BIST.

[0212] The switch SW13 is connected between the application terminal of the divided voltage DIV12 (=divided voltage of the power supply voltage VCC1) and the inverting input terminal (-) of the comparator 412b. The switch SW13 is turned off during BIST and turned on during non-BIST. On the other hand, the switch SW14 is connected between the application terminal of the ground voltage GND1 and the inverting input terminal (-) of the comparator 412b. The switch SW14 is turned on during BIST and turned off during non-BIST. In other words, the divided voltage DIV12 is input to the inverting input terminal (-) of the comparator 412b as the voltage to be monitored mentioned above during non-BIST, and the ground voltage GND1 is input during BIST.

[0213] The switches SW11 to SW14 are turned on / off in response to the primary self-diagnosis signal BIST 1. For example, the primary self-diagnosis signal BIST 1 is at a low level during BIST and at a high level during non-BIST.

[0214] Next, the explanation will continue with attention being focused on the driver chip 420.

[0215] The logic circuit 421 includes, as functional blocks related to the self-diagnosis circuit B, for example, a logic unit 421a, a pulse receiving unit 421b, a logic unit 421c, an AND gate 421d, and an oscillator 421e.

[0216] The logic unit 421a transmits the detection results (= overvoltage detection signal OV2 and undervoltage detection signal UV2) of the UVLO / OVLO circuit 422 to the logic unit 411a via transformers TR1 and TR2. For example, the logic unit 421a stops generating both pulse signals S421a1 and S421a2 (and thus driving both transformers TR1 and TR2) when an undervoltage or overvoltage is detected. The logic unit 411a detects that the generation of both pulse signals S421a1 and S421a2 (and thus driving both transformers TR1 and TR2) has stopped, and recognizes that an undervoltage or overvoltage has been detected by the logic unit 421a. On the other hand, when the undervoltage or overvoltage detection is released (when no detection is detected), the logic unit 421a drives the transformer TR1 or TR2 using the pulse signal S421a1 or S421a2. For example, when the gate signal (OUTH) of the power transistor is at a high level, the transformer TR1 is driven using the pulse signal S421a1, and when the gate signal (OUTH) is at a low level, the transformer TR2 is driven using the pulse signal S421a2.

[0217] The pulse receiving unit 421b generates a secondary-side self-diagnosis signal BIST2 in response to a pulse signal S411c (=self-diagnosis command to the driver chip 420) received via the transformer TR3.

[0218] The logic unit 421c transmits the overheating or short-circuiting detection result (= overheating detection signal OT and short-circuiting detection signal SC) to the logic unit 411d via the transformer TR4. For example, when overheating or short-circuiting is detected, the logic unit 421c drives the transformer TR4 using a pulse signal S421c.

[0219] The AND gate 421d receives the overvoltage detection signal OV2, the undervoltage detection signal UV2, the overheat detection signal OT, and the short-circuit detection signal SC as inputs and generates an AND signal S421d. Therefore, the AND signal S421d goes low when at least one of the four signals is low (= the logical level when no abnormality is detected), and goes high when all of the four signals are high (= the logical level when an abnormality is detected).

[0220] When the AND signal S421d rises to a high level, the oscillator 421e transmits a pulse signal S421e (= a self-diagnosis result for the controller chip 410, for example, 10 MHz, 3 CLK) to the logic circuit 411 via the transformer TR5.

[0221] The UVLO / OVLO circuit 422 is one of the objects to be diagnosed by the self-diagnosis circuit B, and includes comparators 422a and 422b. The comparators 423 and 424 are also one of the objects to be diagnosed by the self-diagnosis circuit B.

[0222] The comparator 422a compares the voltage to be monitored (DIV21 or VCC2) input to its non-inverting input terminal (+) with the overvoltage detection threshold input to its inverting input terminal (-) to generate an overvoltage detection signal OV2. The overvoltage detection signal OV2 goes high (= a logic level in the event of an abnormality) when the voltage to be monitored is higher than the overvoltage detection threshold, and goes low (= a logic level in the event of a normal state) when the voltage to be monitored is lower than the overvoltage detection threshold.

[0223] The comparator 422b compares the monitored voltage (DIV22 or GND2) input to its inverting input terminal (-) with the low voltage detection threshold input to its non-inverting input terminal (+) to generate the low voltage detection signal UV2. The low voltage detection signal UV2 goes high (= the logic level when an abnormality occurs) when the monitored voltage is lower than the low voltage detection threshold, and goes low (= the logic level when the monitored voltage is higher than the low voltage detection threshold).

[0224] The comparator 423 compares the monitored voltage (TO_VH or GND2) input to its inverting input terminal (-) with the overheat detection threshold input to its non-inverting input terminal (+) to generate an overheat detection signal OT. The overheat detection signal OT goes high (= the logic level in the abnormal state) when the monitored voltage is lower than the overheat detection threshold, and goes low (= the logic level in the normal state) when the monitored voltage is higher than the overheat detection threshold.

[0225] The comparator 424 compares the voltage to be monitored (SCPIN or VREG) input to its non-inverting input terminal (+) with the short circuit detection threshold input to its inverting input terminal (-) to generate a short circuit detection signal SC. The short circuit detection signal SC goes to high level (= logic level in the event of an abnormality) when the voltage to be monitored is higher than the short circuit detection threshold, and goes to low level (= logic level in the event of a normal state) when the voltage to be monitored is lower than the short circuit detection threshold.

[0226] The switch SW21 is connected between the application terminal of the divided voltage DIV21 (= the divided voltage of the power supply voltage VCC2) and the non-inverting input terminal (+) of the comparator 422a. The switch SW21 is turned off during BIST and turned on during non-BIST. On the other hand, the switch SW22 is connected between the application terminal of the power supply voltage VCC2 and the non-inverting input terminal (+) of the comparator 422a. The switch SW22 is turned on during BIST and turned off during non-BIST. That is, the divided voltage DIV21 is input to the non-inverting input terminal (+) of the comparator 422a as the voltage to be monitored mentioned above during non-BIST, and the power supply voltage VCC2 is input during BIST.

[0227] The switch SW23 is connected between the application terminal of the divided voltage DIV22 (=divided voltage of the power supply voltage VCC2) and the inverting input terminal (-) of the comparator 422b. The switch SW23 is turned off during BIST and turned on during non-BIST. On the other hand, the switch SW24 is connected between the application terminal of the ground voltage GND2 and the inverting input terminal (-) of the comparator 422b. The switch SW24 is turned on during BIST and turned off during non-BIST. In other words, the divided voltage DIV22 is input to the inverting input terminal (-) of the comparator 422b as the voltage to be monitored mentioned above during non-BIST, and the ground voltage GND2 is input during BIST.

[0228] The switch SW25 is connected between the application terminal of the short-circuit detection voltage SCPIN (=terminal voltage of the SCPIN terminal) and the non-inverting input terminal (+) of the comparator 424. The switch SW25 is turned off during BIST and turned on during non-BIST. On the other hand, the switch SW26 is connected between the application terminal of the internal voltage VREG and the non-inverting input terminal (+) of the comparator 424. The switch SW24 is turned on during BIST and turned off during non-BIST. That is, the short-circuit detection voltage SCPIN is input to the non-inverting input terminal (+) of the comparator 424 as the aforementioned voltage to be monitored during non-BIST, and the internal voltage VREG is input during BIST. Furthermore, the NMOSFET 427 is turned off during BIST.

[0229] The switch SW27 is connected between the application terminal of the overheat detection voltage TO_VH (= the terminal voltage of the overheat / load power supply abnormality detection terminal TO_VH) and the inverting input terminal (-) of the comparator 423. The switch SW27 is turned off during BIST and turned on during non-BIST. On the other hand, the switch SW27 is connected between the application terminal of the ground voltage GND2 and the inverting input terminal (-) of the comparator 423. The switch SW27 is turned on during BIST and turned off during non-BIST. That is, the overheat detection voltage TO_VH is input to the inverting input terminal (-) of the comparator 423 as the aforementioned voltage to be monitored during non-BIST, and the ground voltage GND2 is input during BIST.

[0230] The switches SW21 to SW28 are turned on / off in response to the secondary self-diagnosis signal BIST2. For example, the secondary self-diagnosis signal BIST2 is at a low level during BIST and at a high level during non-BIST.

[0231] The above-mentioned self-diagnosis circuit B diagnoses the UVLO / OVLO circuit 412 (comparators 412a and 412b), the UVLO / OVLO circuit 422 (comparators 422a and 422b), the overheat detection circuit (comparator 423), and the short-circuit detection circuit (comparator 424), as well as the first signal transmission path (transformers TR1 and TR2 for RDY output, and transformer TR4 for FLT output) that transmits the abnormality detection result of the driver chip 420 to the controller chip 410, and can confirm whether each functional block is operating normally.

[0232] For example, to diagnose whether comparators 412a and 412b, comparators 422a and 422b, and comparators 423 and 424 are operating correctly, a test voltage outside the normal input range (for example, power supply voltages VCC1 and VCC2, or ground voltages GND1 and GND2, or internal voltage VREG) is applied as the monitored voltage input to each of them, and it is confirmed that each abnormality detection signal (OV1 / UV1, OV2 / UV2, SC, OT) is at a high level (= the logical level when an abnormality is detected).

[0233] Furthermore, in order to diagnose whether the above-mentioned first signal transmission path (transformers TR1 and TR2 for RDY output and transformer TR4 for FLT output) is operating correctly, it is sufficient to confirm that the ready signal RDY and the fault signal FLT are at a low level (= the logical level when an abnormality is detected) by the logic units 411a and 411d, in other words, that the gate signals S411a and S411d are at a high level.

[0234] When all of the above-mentioned diagnostic targets are operating correctly, the five signals (S411a, S411e, S411f, OV1, and UV1) input to the NAND gate 411g are all at high level (= the logical level when an abnormality is detected), and the NAND signal S411g is at low level. Therefore, when the self-diagnosis on signal BISTON is raised to high level, the NMOSFET 415 is turned off, and the self-diagnosis output signal BISTOUT is at high impedance (= the logical level when the self-diagnosis is OK).

[0235] On the other hand, if at least one of the above-mentioned diagnostic targets is not operating correctly, at least one of the five signals (S411a, S411e, S411f, OV1, and UV1) input to the NAND gate 411g will be at low level (= the logical level when no abnormality is detected), and the NAND signal S411g will be at high level. Therefore, when the self-diagnosis on signal BISTON is raised to high level, the NMOSFET 415 is turned on, and the self-diagnosis output signal BISTOUT will be at low level (= the logical level when the self-diagnosis is NG).

[0236] As described above, the signal transmission device 400 of this configuration example includes a first abnormality detection circuit (UVLO / OVLO circuit 412) configured to detect an abnormality in the controller chip 410 provided in the primary circuit system 400p, a second abnormality detection circuit (UVLO / OVLO circuit 422, overheat detection comparator 423, short circuit detection comparator 424) configured to detect an abnormality in the driver chip 420 provided in the secondary circuit system 400s, and a first abnormality detection circuit (UVLO / OVLO circuit 422, overheat detection comparator 423, short circuit detection comparator 424) configured to detect an abnormality in the driver chip 420 provided in the secondary circuit system 400p. and a second circuit system 400s, and a self-diagnosis circuit B configured to perform self-diagnosis of each of the first abnormality detection circuit (412), the second abnormality detection circuits (422, 423, 424), and the first signal transmission paths (TR1, TR2, TR4).

[0237] In addition, the self-diagnosis circuit B includes a second signal transmission path (421d, 421e and TR5) configured to transmit the self-diagnosis result of the second abnormality detection circuit (422, 423, 424) from the driver chip 420 of the secondary circuit system 400s to the controller chip 410 of the primary circuit system 400p while insulating the controller chip 410 of the primary circuit system 400p from the driver chip 420 of the secondary circuit system 400s.

[0238] Referring to this figure, it is desirable that the second signal transmission path be configured to transmit the abnormality detection results (OV2, UV2, OT, and SC) in the driver chip 420 to the controller chip 410 as a single pulse signal S421e by using an AND gate 421d, an oscillator 421e, and a transformer TR5.

[0239] 13 is a diagram showing a first example (at power-on) of the self-diagnostic operation in the first embodiment (FIGS. 10 to 12). From top to bottom, the diagram depicts the power supply voltages VCC1 and VCC2, the ready signal RDY, the fault signal FLT, the enable signal ENA, the input pulse signal INA, the output pulse signal OUT1 (corresponding to the aforementioned output pulse signal OUT1H), the self-diagnostic on signal BISTON, the self-diagnostic output signal BISTOUT, and the internal BIST signal BISTINT (= a logic signal generated inside the logic circuit 411 for setting the total self-diagnostic period).

[0240] After power-on, at time t11, the UVLO of each of the power supply voltages VCC1 and VCC2 is released, and when the ready signal RDY rises from low to high (= the ready terminal RDY is in a high impedance state), the internal BIST signal BISTINT rises to high, and the self-diagnostic operation begins.

[0241] At this time, the switches SW11 and SW13, and the switches SW21, SW23, SW25 and SW27 are turned off, and the switches SW12 and SW14, and the switches SW22, SW24, SW26 and SW28 are turned on.

[0242] In other words, a test voltage outside the normal input range (for example, power supply voltages VCC1 and VCC2, or ground voltages GND1 and GND2, or internal voltage VREG) is applied to comparators 412a and 412b, comparators 422a and 422b, and comparators 423 and 424 as the monitored voltage input to each of them.

[0243] The internal BIST signal BISTINT does not depend on the enable signal ENA or the like, but should depend only on the rising edge of the ready signal RDY. The high-level period of the internal BIST signal BISTINT (corresponding to the total self-diagnosis period) can be set in advance by a built-in timer. This configuration eliminates the need for a self-diagnosis operation completion flag.

[0244] During the self-diagnosis operation, the input pulse signals INA and INB and the enable signal ENA may be disabled, i.e., the output pulse signal OUT1 (the aforementioned OUT1H and OUT1L) may be fixed to a low level to maintain the power transistor in an off state.

[0245] Similarly, during the self-diagnosis operation, the self-diagnosis on signal BISTON (and hence the self-diagnosis output signal BISTOUT) may be disabled. For example, the self-diagnosis on signal BISTON may be masked. Therefore, even if the self-diagnosis on signal BISTON is raised to a high level during the self-diagnosis operation, the self-diagnosis output signal BISTOUT remains fixed at a low level.

[0246] Furthermore, during the self-diagnosis operation, neither the ready signal RDY nor the fault signal FLT is fixed, but remains at a logic level according to the internal state of the signal transmission device 400. This makes it possible to confirm from outside the device that the self-diagnosis operation is being performed.

[0247] At time t12, when a predetermined period T1 (e.g., a maximum of 150 μs) has elapsed since the start of the self-diagnostic operation (time t11), switches SW11 and SW13, as well as switches SW21, SW23, SW25, and SW27, are turned on, and switches SW12 and SW14, as well as switches SW22, SW24, SW26, and SW28, are turned off.

[0248] That is, the comparators 412a and 412b, the comparators 422a and 422b, and the comparators 423 and 424 are respectively applied with the voltages to be monitored (divided voltages DIV11 and DIV12, divided voltages DIV21 and DIV22, overheat detection voltage TO_VH, and short circuit detection voltage SCPIN).

[0249] At this time, the ready signal RDY rises to a high level, but the rising edge of the ready signal RDY should be ignored while the internal BIST signal BISTINT is at a high level so that the self-diagnosis operation is not restarted. In other words, even if RDY goes from L to HiZ during the self-diagnosis operation, the built-in timer that counts the high-level period of the internal BIST signal BISTINT is not reset.

[0250] After that, at time t13, when a predetermined period T2 (for example, a maximum of 250 μs) has elapsed since the above-mentioned switch change (time t12), the internal BIST signal BISTINT falls to low level, and the above-mentioned series of self-diagnosis operations are terminated. After this, the input pulse signals INA and INB, the enable signal ENA, and the self-diagnosis on signal BISTON are all enabled.

[0251] For example, when the self-diagnosis on signal BISTON is raised to a high level at any timing, after a predetermined period T3 has elapsed, the self-diagnosis result at that time is latched and output as the self-diagnosis output signal BISTOUT. At this time, if the self-diagnosis result is NG, BISTOUT becomes L (dashed line), and if the self-diagnosis result is OK, BISTOUT becomes HiZ (solid line). The signal latch of the self-diagnosis output signal BISTOUT should be reset at the falling edge of the ready signal RDY.

[0252] If comparator 412b or 422b has failed and the ready signal RDY does not rise to high level even after power is turned on, the self-diagnosis operation cannot be started. However, if the ready signal RDY remains low level even after power is turned on, it is clear that some abnormality has occurred in signal transmission device 400, so there is no particular problem even if the self-diagnosis operation cannot be started.

[0253] 14 is a diagram showing a second example of the self-diagnosis operation (when UV2 is detected and then released) in the first embodiment (FIGS. 10 to 12). As in FIG. 13, this diagram depicts, from top to bottom, the power supply voltages VCC1 and VCC2, the ready signal RDY, the fault signal FLT, the enable signal ENA, the input pulse signal INA, the output pulse signal OUT1 (corresponding to the aforementioned output pulse signal OUT1H), the self-diagnosis on signal BISTON, the self-diagnosis output signal BISTOUT, and the internal BIST signal BISTINT.

[0254] As shown in this diagram, the self-diagnostic operation described above is executed not only at power-on (FIG. 13), but also, for example, after UVLO is detected in the power supply voltage VCC2 at time t20, when the UVLO is released at time t21. Note that the self-diagnostic operation from time t21 onwards is the same as that from time t11 onwards in FIG. 13, and therefore a duplicated explanation will be omitted.

[0255] <Signal Transmission Device (Second Embodiment)> Fig. 15 is a diagram showing a second embodiment of a signal transmission device. The signal transmission device 400 of the second embodiment is based on the first embodiment (Figs. 10 to 12) and further includes a power supply circuit 500.

[0256] The power supply circuit 500 generates a desired output voltage VOUT (e.g., power supply voltage VCC2 of the secondary circuit system 400s) from an input voltage VIN while insulating the primary circuit system 400p from the secondary circuit system 400s. The power supply circuit 500 may also include an overcurrent protection circuit 510 provided in the primary circuit system 400p (details will be described later).

[0257] In this way, the signal transmission device 400 including the isolated power supply circuit 500 does not require a separate power supply IC as means for generating the power supply voltage VCC2 of the secondary circuit system 400s.

[0258] 16 is a diagram showing an example of the configuration of a power supply circuit 500. The power supply circuit 500 of this example configuration includes an overcurrent protection circuit 510, a feedback signal generation circuit 520, a feedback control circuit 530, and various discrete components (a transformer TR, an output transistor M1, a diode D1, a capacitor C1, resistors R1 to R3, and a sense resistor Rsns).

[0259] The transformer TR includes a primary coil Lp (number of turns Np) and a secondary coil Ls (number of turns Ns) that are magnetically coupled to each other while electrically insulating the primary circuit system 400p from the secondary circuit system 400s.

[0260] A first end (winding start end) of the primary coil Lp is connected to the end to which the input voltage VIN is applied. A second end (winding end) of the primary coil Lp is connected to the drain of the output transistor M1 (an NMOSFET in this figure). A gate of the output transistor M1 is connected to the end to which the gate drive signal SG is applied. A source of the output transistor M1 and a first end of the sense resistor Rsns are both connected to the end to which the sense voltage Vsns is applied. A second end of the sense resistor Rsns is connected to the ground end of the primary circuit system 400p.

[0261] The output transistor M1 connected in this manner functions as a switch element for turning on / off the primary current Ip in response to the gate drive signal SG. When an NMOSFET is used as the output transistor M1, the output transistor M1 is turned on when the gate drive signal SG is at a high level, and turned off when the gate drive signal SG is at a low level.

[0262] The sense resistor Rsns also functions as a current / voltage conversion element that generates a sense voltage Vsns (=Ip×Rsns) according to the primary current Ip that flows through the primary coil Lp of the transformer TR via the output transistor M1.

[0263] A first end (winding end) of the secondary coil Ls and the anode of the diode D1 are all connected to the application terminal of the secondary voltage Vs. A cathode of the diode D1 and first ends of the capacitor C1 and resistor R1 are all connected to the application terminal of the output voltage VOUT (=power supply voltage VCC2). A second end (winding start) of the secondary coil Ls and second ends of the capacitor C1 and resistor R1 are all connected to the ground terminal of the secondary circuit system 400s.

[0264] Of the above components, the output transistor M1, transformer TR, diode D1, and capacitor C1 form a flyback-type switch output stage SWO to generate an output voltage VOUT (=power supply voltage VCC2) for the secondary circuit system 400s from the input voltage VIN of the primary circuit system 400p while insulating the primary circuit system 400p from the secondary circuit system 400s.

[0265] The basic operation of the switch output stage SWO will be described below. The switch output stage SWO drives a primary current Ip flowing through a primary coil Lp of a transformer TR, and generates an output voltage VOUT from a secondary voltage Vs induced in a secondary coil Ls of the transformer TR.

[0266] Specifically, during the on-period Ton of the output transistor M1, a primary current Ip flows from the terminal to which the input voltage VIN is applied via the primary coil Lp and the output transistor M1. Therefore, electrical energy is stored in the primary coil Lp. When the output transistor M1 is subsequently turned off, a secondary voltage Vs is induced in the secondary coil Ls, which is magnetically coupled to the primary coil Lp. The secondary voltage Vs is rectified and smoothed via the diode D1 and the capacitor C1. Through this rectification and smoothing operation, the output voltage VOUT (=power supply voltage VCC2) is generated from the secondary voltage Vs. Thereafter, the output transistor M1 is turned on and off, repeating the same switching output operation as described above.

[0267] The numbers of turns Np and Ns of the transformer TR may be adjusted as desired so as to obtain a desired output voltage VOUT (= VIN × (Ns / Np) × (Ton / Toff), where Ton and Toff are the on-time and off-time of the output transistor M1). For example, the greater the number of turns Np or the smaller the number of turns Ns, the lower the output voltage VOUT (= power supply voltage VCC2). Conversely, the smaller the number of turns Np or the larger the number of turns Ns, the higher the output voltage VOUT (= power supply voltage VCC2).

[0268] A first terminal of the resistor R2 is connected to the application terminal of the output voltage VOUT (=power supply voltage VCC2). A second terminal of the resistor R2 and a first terminal of the resistor R3 are both connected to the application terminal of the divided voltage Vdiv. A second terminal of the resistor R3 is connected to the ground terminal of the secondary circuit system 400s.

[0269] The resistors R2 and R3 connected in this manner function as a voltage divider circuit that generates a divided voltage Vdiv (=VOUT×R3 / (R2+R3)) according to the output voltage VOUT (=power supply voltage VCC2).

[0270] The overcurrent protection circuit 510 is one of the power supply abnormality detection units that limits the primary current Ip that flows through the primary coil Lp of the transformer TR via the output transistor M1 to an overcurrent detection value Iocp or less. The overcurrent protection circuit 510, like the UVLO / OVLO circuits 412 and 422, the comparators 423 and 424, and the first signal transmission path (TR1, TR2, TR4), is one of the targets to be diagnosed by the self-diagnosis circuit B.

[0271] Referring to this figure, the overcurrent protection circuit 510 includes a comparator 511 , counters 512 and 513 , an OR gate 514 , a NAND gate 515 , and inverters 516 and 517 .

[0272] When not in BIST mode, the comparator 511 generates an overcurrent detection signal Socp by comparing the sense voltage Vsns input to the non-inverting input terminal (+) with a predetermined threshold voltage Vocp input to the inverting input terminal (-).

[0273] The overcurrent detection signal Socp is at a high level (= a logic level when an overcurrent is detected) when the sense voltage Vsns is higher than the threshold voltage Vocp, and at a low level (= a logic level when an overcurrent is not detected) when the sense voltage Vsns is lower than the threshold voltage Vocp.

[0274] That is, the overcurrent detection signal Socp goes to a high level (=the logic level when an overcurrent is detected) when the primary current Ip is greater than the overcurrent detection value Iocp, and goes to a low level (=the logic level when an overcurrent is not detected) when the primary current Ip is smaller than the overcurrent detection value Iocp.

[0275] The counter 512 receives the internal signal S1 as an input and outputs the internal signal S2. For example, the counter 512 is triggered by the internal signal S1 rising to a high level (= the logical level when an abnormality is detected) to immediately raise the internal signal S2 to a high level (= the logical level when a forced stop occurs). On the other hand, the counter 512 is triggered by the internal signal S1 falling to a low level (= the logical level when no abnormality is detected) to start counting the waiting time Tw (e.g., 40 ms), and when the count expires, the counter 512 lowers the internal signal S2 to a low level (= the logical level when the forced stop is released).

[0276] However, during the soft start operation (details will be described later), the counter 512 does not start counting the waiting time Tw, and immediately drops the internal signal S2 to the low level when the internal signal s1 drops to the low level.

[0277] The counter 513 starts counting a soft start period Tss (e.g., 12.5 ms) when the internal signal S2 falls to a low level (= the logical level when the forced stop is released). The soft start period Tss is used for the soft start operation (= variable control of the threshold voltage Vocp) by the overcurrent protection circuit 510. Details of the soft start operation will be described later.

[0278] The OR gate 514 generates an internal signal S1 by performing a logical OR operation on the overcurrent detection signal Socp and the driver abnormality detection result (overvoltage detection signal OV2 / undervoltage detection signal UV2). The internal signal S1 goes high (=the logical level when an abnormality is detected) when at least one of the overcurrent detection signal Socp and the driver abnormality detection result (OV2 / UV2) is high (=the logical level when an abnormality is detected). On the other hand, the internal signal S1 goes low (=the logical level when an abnormality is not detected) when both the overcurrent detection signal Socp and the driver abnormality detection result (OV2 / UV2) are low (=the logical level when an abnormality is not detected).

[0279] The NAND gate 515 generates an internal signal S4 by performing a NAND operation on the gate control signal S0 and the internal signal S3. The internal signal S4 goes high when at least one of the gate control signal S0 and the internal signal S3 is low. On the other hand, the internal signal S4 goes low when both the gate control signal S0 and the internal signal S3 are high.

[0280] That is, when the internal signal S3 is at a high level, a signal obtained by inverting the logic level of the gate control signal S0 is output as the internal signal S4, whereas when the internal signal S3 is at a low level, the internal signal S4 is fixed at a high level (=the logic level at the time of forced shutdown) regardless of the logic level of the gate control signal S0.

[0281] The inverter 516 inverts the logic level of the internal signal S2 to generate the internal signal S3. Therefore, the internal signal S3 is at a low level when the internal signal S2 is at a high level, and is at a high level when the internal signal S2 is at a low level.

[0282] The inverter 517 inverts the logic level of the internal signal S4 to generate the gate drive signal SG. Therefore, the gate drive signal SG is at a low level when the internal signal S4 is at a high level, and is at a high level when the internal signal S4 is at a low level. In this way, the inverter 517 also functions as a driver that generates the gate drive signal SG.

[0283] In addition to the overcurrent protection circuit 510, examples of the power supply abnormality detection unit that detects abnormalities in the power supply circuit 500 include an overvoltage protection circuit that limits the output voltage VOUT (=power supply voltage VCC2) to an overvoltage detection value Vovp or less.

[0284] The feedback signal generation circuit 520 generates a feedback signal Sfb having pulse information corresponding to the output voltage VOUT (=power supply voltage VCC2) and outputs it from the secondary circuit system 400s to the primary circuit system 400p. Referring to this figure, the feedback signal generation circuit 520 includes an oscillator 521 and a comparator 522. The feedback signal generation circuit 520 is provided in the secondary circuit system 400s (particularly the driver chip 420).

[0285] The oscillator 521 generates a triangular or sawtooth waveform slope voltage Vslp at a predetermined oscillation frequency.

[0286] The comparator 522 generates a feedback signal Sfb by comparing the divided voltage Vdiv input to its non-inverting input terminal (+) with the slope voltage Vslp input to its inverting input terminal (-). The feedback signal Sfb goes high when the divided voltage Vdiv is higher than the slope voltage Vslp. On the other hand, the feedback signal Sfb goes low when the divided voltage Vdiv is lower than the slope voltage Vslp.

[0287] The feedback control circuit 530 receives the feedback signal Sfb and performs duty control of the gate control signal S0 (and hence the gate drive signal SG) so that the output voltage VOUT (=power supply voltage VCC2) matches a target value. That is, the feedback control circuit 530 controls the switch output stage SWO to drive the primary current Ip in accordance with the feedback signal Sfb. The feedback control circuit 530 is provided in the primary circuit system 400p (particularly the controller chip 410).

[0288] Referring to this figure, the feedback control circuit 530 includes a charge pump 531 , a current detection unit 532 , a comparator 533 , an oscillator 534 , an OR gate 535 , and an RS flip-flop 536 .

[0289] The charge pump 531 outputs a charge pump voltage Vcp that increases or decreases in response to the feedback signal Sfb. For example, the charge pump voltage Vcp increases when the feedback signal Sfb is at a high level and decreases when the feedback signal Sfb is at a low level.

[0290] The current detection unit 532 outputs a triangular or sawtooth waveform reference voltage Vref having a DC bias value according to the sense voltage Vsns.

[0291] The comparator 533 compares the charge pump voltage Vcp input to its inverting input terminal (-) with the reference voltage Vref input to its non-inverting input terminal (+) to output a comparison signal CMP. The comparison signal CMP goes low when the charge pump voltage Vcp is higher than the reference voltage Vref. On the other hand, the comparison signal CMP goes high when the charge pump voltage Vcp is lower than the reference voltage Vref.

[0292] The oscillator 534 generates a set signal S (=clock signal) that is pulse-driven at a predetermined switching period Tsw.

[0293] The OR gate 535 generates a reset signal R by performing a logical OR operation on the comparison signal CMP and the overcurrent detection signal Socp. The reset signal R goes high (=the logic level at the time of reset) when at least one of the comparison signal CMP and the overcurrent detection signal Socp is high. On the other hand, the reset signal R goes low (=the logic level at the time of reset release) when both the comparison signal CMP and the overcurrent detection signal Socp are low.

[0294] That is, when the overcurrent detection signal Socp is at a low level (=the logic level when an overcurrent is not detected), the comparison signal CMP is output as a reset signal R. On the other hand, when the overcurrent detection signal Socp is at a high level (=the logic level when an overcurrent is detected), the reset signal R is fixed to a high level (=the logic level when reset) regardless of the logic level of the comparison signal CMP.

[0295] The RS flip-flop 536 determines the logic level of the gate control signal S0 in response to the set signal S and the reset signal R. For example, when the set signal S rises to a high level, the RS flip-flop 536 sets the gate control signal S0 to a high level (= a logic level for turning on the output transistor M1). On the other hand, when the reset signal R falls to a low level, the RS flip-flop 536 resets the gate control signal S0 to a low level (= a logic level for turning off the output transistor M1). The overcurrent protection circuit 510 is provided in the primary circuit system 400p (particularly the controller chip 410).

[0296] The self-diagnosis circuit B diagnoses the overcurrent protection circuit 510. Referring to this figure, the self-diagnosis circuit B includes logic B1 and switches B2 and B3.

[0297] Logic B1 controls switches B2 and B3. Switch B2 is connected between the non-inverting input terminal (+) of comparator 511 and a terminal to which a test voltage is applied. The test voltage may be a voltage outside the normal input range of comparator 511 (for example, power supply voltage VCC1). Switch B3 is connected between the non-inverting input terminal (+) of comparator 511 and a terminal to which a sense voltage Vsns is applied.

[0298] During BIST, logic B1 turns switch B2 on and switch B3 off. Therefore, during BIST, a test voltage (=power supply voltage VCC1) is applied to the non-inverting input terminal (+) of comparator 511. On the other hand, during non-BIST, logic B1 turns switch B2 off and switch B3 on. Therefore, during non-BIST, a sense voltage Vsns is applied to the non-inverting input terminal (+) of comparator 511.

[0299] The logic B1 monitors the overcurrent detection signal Socp during the BIST of the overcurrent protection circuit 510 to determine whether the comparator 511 is normal. The logic B1 then outputs a self-diagnosis output signal BISTOUT in accordance with the BIST result. This self-diagnosis operation is the same as that of the first embodiment (FIGS. 12 to 14).

[0300] 17 is a diagram showing the abnormality protection operation of the power supply circuit 500. In this diagram, from the top, the power supply voltage VCC2, the sense voltage Vsns, and the gate drive signal SG are depicted.

[0301] At time t31, the start-up of the power supply voltage VCC2 (=output voltage VOUT) is completed. When the power supply voltage VCC2 is started up, a soft start operation is performed by the overcurrent protection circuit 510 (details will be described later).

[0302] At time t32, when the power supply voltage VCC2 (=output voltage VOUT) falls below the low voltage detection threshold Vuv2L, the output transistor M1 is forcibly turned off. At this time, counting of the waiting time Tw (>Tsw) starts.

[0303] At time t33, as the waiting time Tw expires, the switching control of the output transistor M1 is resumed and the power supply voltage VCC2 is restarted.

[0304] At time t34, the restart of the power supply voltage VCC2 (=output voltage VOUT) is completed. Note that even when the power supply voltage VCC2 is restarted after the undervoltage protection operation is released, the overcurrent protection circuit 510 performs a soft start operation.

[0305] At time t35, when the power supply voltage VCC2 (=output voltage VOUT) exceeds the overvoltage detection threshold Vov2H, the output transistor M1 is forced to be in the OFF state.

[0306] At time t36, when the power supply voltage VCC2 (=output voltage VOUT) falls below the overvoltage release threshold Vov2L (<Vov2H), counting of the waiting time Tw starts.

[0307] At time t37, as the waiting time Tw expires, the switching control of the output transistor M1 is resumed and the power supply voltage VCC2 is restarted.

[0308] At time t38, the restart of the power supply voltage VCC2 (=output voltage VOUT) is completed. Note that even when the power supply voltage VCC2 is restarted after the overvoltage protection operation is released, the overcurrent protection circuit 510 performs a soft start operation.

[0309] At time t39, when the increase in the primary current Ip causes the sense voltage Vsns to exceed the threshold voltage Vocp, the output transistor M1 is forced to be turned off. At this time, counting of the standby time Tw begins. Note that the sense voltage Vsns exceeding the threshold voltage Vocp means that the primary current Ip has exceeded the overcurrent detection value Iocp.

[0310] At time t3A, as the waiting time Tw expires, switching control of the output transistor M1 is resumed and the power supply voltage VCC2 is restarted.

[0311] At time t3B, the restart of the power supply voltage VCC2 (=output voltage VOUT) is completed. Note that even when the power supply voltage VCC2 is restarted after the overcurrent protection operation is released, the overcurrent protection circuit 510 performs a soft start operation.

[0312] In this way, when the primary current Ip exceeds the overcurrent detection value Iocp after starting or restarting the power supply voltage VCC2 (= output voltage VOUT), the overcurrent protection circuit 510 performs an off-latch type overcurrent protection operation to forcibly turn off the primary current Ip until a waiting time Tw longer than the switching period Tsw of the primary current Ip has elapsed.

[0313] 18 is a diagram showing the soft start operation of the power supply circuit 500. In this diagram, from the top, the power supply voltage VCC1, the gate drive signal SG, the sense voltage Vsns, and the power supply voltage VCC2 are depicted.

[0314] At time t41, when the power supply voltage VCC1 exceeds the low voltage release threshold Vuv1H, switching control of the gate drive signal SG is started, and as a result, the power supply voltage VCC2 (=output voltage VOUT) starts to rise.

[0315] At time t41, counting of the soft start period Tss (for example, 12.5 ms) begins. Referring to this figure, the time from t41 to t47 corresponds to the soft start period Tss.

[0316] Here, the overcurrent protection circuit 510 gradually increases the threshold voltage Vocp (and hence the overcurrent detection value Iocp) over the soft start period Tss.

[0317] For example, from time t41 to time t42, the threshold voltage Vocp is set to the lowest first set value Vocp1. The first set value Vocp1 may be set to 40 mV. The period from time t41 to time t42 may be set to 1 / 5 of the soft start period Tss.

[0318] From time t42 to t43, the threshold voltage Vocp is set to a second set value Vocp2 that is one step higher than the first set value Vocp1. The second set value Vocp2 may be set to 60 mV. The period from time t42 to t43 may be set to 1 / 5 of the soft start period Tss.

[0319] From time t43 to t44, the threshold voltage Vocp is set to a third set value Vocp3, which is one step higher than the second set value Vocp2. The third set value Vocp3 may be set to 80 mV. The period from time t43 to t44 may be set to 1 / 5 of the soft-start period Tss.

[0320] At times t44 to t46 and t46 to t47, the threshold voltage Vocp is set to a fourth set value Vocp4, which is one step higher than the third set value Vocp3. The fourth set value Vocp4 may be set to 100 mV. At times t44 to t46 and t46 to t47, the threshold voltage Vocp may be set to 1 / 5 of the soft-start period Tss.

[0321] After time t47 when the count of the soft start period Tss expires, the threshold voltage Vocp is set to a fifth set value Vocp5, which is one step higher than the fourth set value Vocp4. The fifth set value Vocp5 may be set to 200 mV. The fifth set value Vocp5 is set appropriately taking into consideration the normal range of the primary current Ip that flows in the power supply circuit 500 during steady state.

[0322] Furthermore, when the sense voltage Vsns exceeds the threshold voltage Vocp during startup of the power supply voltage VCC2 (=output voltage VOUT), i.e., before the soft start period Tss has elapsed, the overcurrent protection circuit 510 performs a hiccup-type overcurrent protection operation to forcibly turn off the primary current Ip until the next on timing in the switching period Tsw of the primary current Ip.

[0323] According to the overcurrent protection operation described above, switching control of the primary current Ip is performed so that the primary current Ip gradually increases, and as a result, the power supply voltage VCC2 (=output voltage VOUT) gradually increases from time t41 to t45.

[0324] In this way, with the power supply circuit 500 of this embodiment, it is possible to achieve soft start operation of the power supply voltage VCC2 (= output voltage VOUT) generated by the driver chip 420 without directly monitoring the power supply voltage VCC2 (= output voltage VOUT) with the controller chip 410.

[0325] The above-mentioned soft start operation can be performed not only when the power supply voltage VCC2 (= output voltage VOUT) is started up, but also when the power supply voltage VCC2 (= output voltage VOUT) is restarted after the abnormality protection operation is released (see times t33 to t34, times t36 to t37, and times t39 to t3A in Figure 17 mentioned above).

[0326] <Considerations Regarding the Self-Diagnosis Sequence> If the overcurrent protection circuit 510 incorporated in the power supply circuit 500 does not operate normally, an excessive primary current Ip may continue to flow through the output transistor M1, which may cause the output transistor M1 to heat up and malfunction. Furthermore, if the soft-start operation described above is not performed correctly, an excessive inrush current may flow when the power supply voltage VCC2 (=output voltage VOUT) is started or restarted, which may result in damage to the capacitor C1.

[0327] Therefore, it is desirable to provide a safety design that prohibits the start-up of the power supply circuit 500 if the overcurrent protection circuit 510 does not operate normally. More specifically, it is desirable to include the overcurrent protection circuit 510 in the targets to be diagnosed by the self-diagnosis circuit B.

[0328] However, the output voltage VOUT generated by the power supply circuit 500 is used as the power supply voltage VCC2 for the secondary circuit system 400s. Therefore, the power supply circuit 500 must always be operating while the signal transmission device 400 is in operation. Therefore, the timing when the overcurrent protection circuit 510 can be diagnosed by the self-diagnosis circuit B is limited to when the power supply circuit 500 is stopped, i.e., immediately after the power supply voltage VCC1 is started up.

[0329] In the first embodiment (FIGS. 13 and 14), the self-diagnosis operation is performed when both power supply voltages VCC1 and VCC2 are at their high levels (RDY=H). However, for the reasons described above, it is difficult to apply the self-diagnosis sequence of the first embodiment (FIGS. 13 and 14) directly to the second embodiment.

[0330] In view of the above considerations, a self-diagnosis sequence suitable for the second embodiment (FIG. 15) will be proposed below.

[0331] <Self-Diagnosis Operation (Second Embodiment)> FIG. 19 is a diagram (time chart) showing an example of a self-diagnosis operation in the second embodiment. In this figure, from top to bottom, there are depicted the power supply voltage VCC1, the BIST execution signal (OC_BIST) of the overcurrent protection circuit 510, the gate drive signal SG, the power supply voltage VCC2, the ready signal RDY, the BIST execution signal (UV1 / OV1_BIST) of the UVLO / OVLO circuit 412, the self-diagnosis command (BIST_CMD) to the driver chip 420, the BIST execution signal (UV2 / OV2_BIST) and BIST result signal (UV2 / OV2_result) of the UVLO / OVLO circuit 422, the BIST execution signal (SC_BIST) and BIST result signal (SC_result) of the short-circuit detection comparator 424, the fault signal FLT, the BIST result signal BIST_result, the self-diagnosis on signal BISTON, and the self-diagnosis output signal BISTOUT.

[0332] At time t51, when the power supply voltage VCC1 exceeds the low voltage release threshold Vuv1H, the BIST execution signal (OC_BIST) of the overcurrent protection circuit 510 rises from low to high, causing the self-diagnosis circuit B to first perform self-diagnosis of the overcurrent protection circuit 510, which is one of the power supply abnormality detection units, among multiple diagnosis targets.

[0333] The self-diagnosis operation of the overcurrent protection circuit 510 may be performed by checking whether an expected overcurrent detection signal Socp is output when a test voltage (e.g., power supply voltage VCC1) is applied to the comparator 511. The self-diagnosis operation of the overcurrent protection circuit 510 may be performed for a predetermined time Ta (e.g., 50 μs).

[0334] If the self-diagnosis result of the overcurrent protection circuit 510 is OK, switching control of the gate drive signal SG begins at time t52. At this time, the overcurrent protection circuit 510 performs the soft-start operation described above. Therefore, the power supply voltage VCC2 (=output voltage VOUT) generated by the power supply circuit 500 gradually increases.

[0335] At time t53, when the power supply voltage VCC2 (=output voltage VOUT) exceeds the low voltage release threshold Vuv2H, the ready signal RDY rises from low level to high level (=the ready terminal RDY is in a high impedance state). Note that the ready signal RDY may also fall from high level to low level at time t56 after a predetermined time Tb (e.g., 10 μs) has elapsed.

[0336] At time t53, the rising edge of the ready signal RDY triggers the BIST execution signal (UV1 / OV1_BIST) of the UVLO / OVLO circuit 412 to rise from low to high. This causes the self-diagnosis circuit B to perform a self-diagnosis of the UVLO / OVLO circuit 412, among the multiple diagnostic targets. The self-diagnosis operation of the UVLO / OVLO circuit 412 may be performed over a predetermined time Tc (e.g., 70 μs).

[0337] Furthermore, at time t53, the rising edge of the ready signal RDY is used as a trigger to pulse-drive a self-diagnosis command (BIST_CMD) from the controller chip 410 to the driver chip 420 at a predetermined frequency (e.g., 1 MHz). Note that the self-diagnosis command (BIST_CMD) to the driver chip 420 may not be transmitted from the controller chip 410 unless the self-diagnosis result of the overcurrent protection circuit 510 is OK. The self-diagnosis command (BIST_CMD) in this figure corresponds to the previously mentioned pulse signal S411c ( FIG. 12 ).

[0338] At time t54, the BIST execution signal (UV2 / OV2_BIST) of the UVLO / OVLO circuit 422 rises from low to high based on a self-diagnosis command (BIST_CMD) from the controller chip 410 to the driver chip 420. This causes the self-diagnosis circuit B to perform a self-diagnosis of the UVLO / OVLO circuit 422, among multiple diagnostic targets. The self-diagnosis operation of the UVLO / OVLO circuit 422 may be performed over a predetermined time Td (e.g., 30 μs).

[0339] Also, at time t54, the BIST execution signal (SC_BIST) of the short-circuit detection comparator 424 rises from low to high based on a self-diagnosis command (BIST_CMD) from the controller chip 410 to the driver chip 420. This causes the self-diagnosis circuit B to perform a self-diagnosis of the comparator 424, among multiple diagnostic targets. The self-diagnosis operation of the short-circuit detection comparator 424 may be performed over a predetermined time Te (e.g., 30 μs).

[0340] When a predetermined time Tf (for example, 0.5 μs) has elapsed since the self-diagnosis operation of the short-circuit detection comparator 424 started, a BIST result signal (SC_result) is transmitted from the driver chip 420 to the controller chip 410 at time t55.

[0341] At this time, if the fault signal FLT falls to a low level (=the logical level when an abnormality is detected) as expected, the signal transmission path (transformers TR1, TR2, and TR4) that transmits the abnormality detection result of the driver chip 420 to the controller chip 410 is diagnosed as normal. Note that the fault signal FLT may rise from a low level to a high level at time t56 when the ready signal RDY falls to a low level.

[0342] Furthermore, when a predetermined time Tg has elapsed since the self-diagnostic operation of the UVLO / OVLO circuit 422 started, a BIST result signal (UV2 / OV2_result) is transmitted from the driver chip 420 to the controller chip 410 at time t57.

[0343] When a predetermined time Th (e.g., 100 μs) has elapsed since the start of self-diagnosis operation for circuits other than the overcurrent protection circuit 510, at time t58, the self-diagnosis results obtained up to that point are stored in the BIST result signal BIST_result. Furthermore, the inputs of the multiple comparators targeted for diagnosis are switched so that the voltage to be monitored (such as the sense voltage Vsns) is applied instead of the test voltage. The rising edge of the ready signal RDY is ignored so that the self-diagnosis operation is not restarted.

[0344] After a predetermined time Ti (e.g., 100 μs) has elapsed since time t58, the above series of self-diagnostic operations ends at time t59. When the self-diagnostic on signal BISTON is raised to high level at any timing, the self-diagnostic result at that time is latched and output as the self-diagnostic output signal BISTOUT. At this time, if the self-diagnostic result is NG, BISTOUT becomes L, and if the self-diagnostic result is OK, BISTOUT becomes HiZ.

[0345] To summarize the above, in the self-diagnosis sequence of the second embodiment, the self-diagnosis of the overcurrent protection circuit 510 is performed first. Then, if the diagnosis result of the overcurrent protection circuit 510 is OK, components other than the overcurrent protection circuit 510 (UVLO / OVLO circuit 412, UVLO / OVLO circuit 422, short-circuit detection comparator 424, and the signal transmission path from the driver chip 420 to the controller chip 410) are diagnosed in sequence, and the respective diagnosis results are stored.

[0346] In this way, the self-diagnosis circuit B may diagnose the overcurrent protection circuit 510 as normal before permitting the operation of the power supply circuit 500 and starting the diagnosis of circuits other than the overcurrent protection circuit 510 .

[0347] During the self-diagnosis operation, the function of forcibly stopping the output transistor M1 due to UV1 detection may be masked. Also, during the self-diagnosis operation, the function of forcibly stopping the soft-start clock due to UV1 detection may be masked.

[0348] 20 is a diagram (flowchart) showing an example of the self-diagnosis operation in the second embodiment. After the power supply voltage VCC1 is started in step #1, when the power supply voltage VCC1 exceeds the low voltage release threshold Vuv1H in step #2, the self-diagnosis operation of the overcurrent protection circuit 510 is started in step #3.

[0349] In step #4, it is determined whether the diagnosis result of the overcurrent protection circuit 510 is OK. If the result is YES, the flow proceeds to step #5. On the other hand, if the result is NO, the flow proceeds to step #8.

[0350] If the determination in step #4 is YES, switching control of the gate drive signal SG is started in step #5. As a result, the power supply voltage VCC2 begins to rise gradually. Thereafter, when the power supply voltage VCC2 exceeds the low voltage release threshold Vuv2H in step #6, the ready signal RDY is raised to a high level in step #7.

[0351] On the other hand, if a negative determination is made in step #4, then in step #8, switching control of the gate drive signal SG is not permitted, the ready signal RDY is also maintained at a low level, and in step #9, the self-diagnosis output signal BISTOUT is set to a low level (= the logic level when the diagnosis result is NG), completing the series of self-diagnosis operations.

[0352] When the ready signal RDY is raised to a high level in step #7, the flow advances to step #10, where the self-diagnosis operation of the UVLO / OVLO circuit 412 is started.

[0353] In the following step #11, it is determined whether the diagnosis result of the UVLO / OVLO circuit 412 is OK. If the result is YES, a BIST result signal indicating that the diagnosis is OK (UV1_BIST = OV1_BIST = H) is acquired. On the other hand, if the result is NO, a BIST result signal indicating that the diagnosis is NG (UV1_BIST = L or OV1_BIST = L) is acquired. After step #11 is completed, the flow proceeds to step #22.

[0354] Furthermore, when the ready signal RDY is raised to a high level in the above-mentioned step #7, the flow proceeds to step #12. In step #12, a self-diagnosis command (BIST_CMD) is transmitted from the controller chip 410 to the driver chip 420. In the following step #13, the self-diagnosis command (BIST_CMD) transmitted from the controller chip 410 is received by the driver chip 420.

[0355] When the driver chip 420 receives a self-diagnosis command (BIST_CMD) in step #13, the self-diagnosis operations of the UVLO / OVLO circuit 422 and the short-circuit detection comparator 424 are started in step #14.

[0356] In the following step #15, it is determined whether the diagnostic results of the UVLO / OVLO circuit 422 and the short-circuit detection comparator 424 are OK. If the result is YES, a BIST result signal indicating OK (DRV_BIST=H) is obtained. On the other hand, if the result is NO, a BIST result signal indicating NG (DRV_BIST=L) is obtained. After step #15 is completed, the flow proceeds to step #22.

[0357] Furthermore, when the driver chip 420 receives a self-diagnosis command (BIST_CMD) in step #13, a self-diagnosis operation of the OSFB signal transmission path is started in step #16. The OSFB signal transmission path is a signal transmission path for transmitting the abnormality detection result of the UVLO / OVLO circuit 422 from the driver chip 420 to the controller chip 410. In the self-diagnosis operation of the OSFB signal transmission path, the OSFB pulse is stopped in step #17.

[0358] In the following step #18, it is determined whether the diagnosis result of the OSFB signal transmission path is OK. If the result is YES, a BIST result signal indicating OK (OSFB_BIST=H) is obtained. On the other hand, if the result is NO, a BIST result signal indicating NG (OSFB_BIST=L) is obtained. After step #18 is completed, the flow proceeds to step #22.

[0359] Furthermore, when the driver chip 420 receives a self-diagnosis command (BIST_CMD) in step #13, a self-diagnosis operation of the FLT signal transmission path is started in step #19. The FLT signal transmission path is a signal transmission path for transmitting the abnormality detection result of the short-circuit detection comparator 424 from the driver chip 420 to the controller chip 410. In the self-diagnosis operation of the FLT signal transmission path, in step #20, the comparator 424 is intentionally set to a short-circuit detection state (= a state in which the fault signal FLT should be lowered to a low level).

[0360] In the following step #21, it is determined whether the diagnosis result of the FLT signal transmission path is OK. If the result is YES, a BIST result signal indicating that the diagnosis is OK (FLT_BIST=H) is obtained. On the other hand, if the result is NO, a BIST result signal indicating that the diagnosis is NG (FLT_BIST=L) is obtained. After step #21 is completed, the flow proceeds to step #22.

[0361] In this way, the self-diagnosis operations (steps #10, #14, #15 and #19) for circuits other than the overcurrent protection circuit 510 are not performed unless the diagnosis result for the overcurrent protection circuit 510 is OK.

[0362] After the above series of self-diagnostic operations are performed, in step #22, it is determined whether all the self-diagnostic results are OK. If the result is YES, the flow proceeds to step #23. On the other hand, if the result is NO, the flow proceeds to step #25.

[0363] If the determination in step #22 is YES, the self-diagnosis results (diagnosis OK) obtained up to that point are latched in step #23. Then, in the following step #24, a self-diagnosis output signal BISTOUT is output in response to the pulse input of the self-diagnosis ON signal BISTON, completing a series of self-diagnosis operations. Note that in step #24, since the self-diagnosis result is OK, BISTOUT=HiZ.

[0364] On the other hand, if a negative determination is made in step #22, the self-diagnosis results (NG) obtained up to that point are latched in step #25. Then, in the following step #26, a self-diagnosis output signal BISTOUT is output in response to the pulse input of the self-diagnosis ON signal BISTON, completing the series of self-diagnosis operations. In step #26, since the self-diagnosis result is NG, BISTOUT=L.

[0365] <Application to Vehicles> Fig. 21 is a diagram showing the exterior of a vehicle. The vehicle X of this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0366] Vehicle X includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0367] The signal transmission device 200 or 400 described above can be incorporated into any of the electronic devices mounted on the vehicle X.

[0368] <Supplementary Notes> The various embodiments described above will be summarized below.

[0369] For example, a signal transmission device disclosed in this specification includes a signal transmission circuit configured to transmit a pulse signal from a primary circuit system to a secondary circuit system while insulating the primary circuit system from the secondary circuit system; a power supply circuit configured to generate an output voltage of the secondary circuit system from an input voltage of the primary circuit system while insulating the primary circuit system from the secondary circuit system; a first abnormality detection circuit configured to detect an abnormality in the primary circuit system; a second abnormality detection circuit configured to detect an abnormality in the secondary circuit system; a signal transmission path configured to transmit a detection result of the second abnormality detection circuit from the secondary circuit system to the primary circuit system while insulating the primary circuit system from the secondary circuit system; and a self-diagnosis circuit configured to self-diagnose each of the first abnormality detection circuit, the second abnormality detection circuit, and the signal transmission path, wherein the first abnormality detection circuit includes a power supply abnormality detection unit configured to detect an abnormality in the power supply circuit as a diagnosis target of the self-diagnosis circuit, and the self-diagnosis circuit is configured to perform self-diagnosis of the power supply abnormality detection unit first (first configuration).

[0370] In addition, in the signal transmission device having the above-mentioned first configuration, the self-diagnosis circuit may be configured (second configuration) to diagnose the power supply abnormality detection unit as normal, and then allow the power supply circuit to operate and start diagnosing components other than the power supply abnormality detection unit.

[0371] Furthermore, in the signal transmission device having the above-mentioned first or second configuration, the power supply circuit may be configured (third configuration) to drive a primary current flowing through a primary coil of a transformer and generate the output voltage from a secondary voltage induced in a secondary coil of the transformer.

[0372] Furthermore, in the signal transmission device according to the third configuration, the power supply abnormality detection unit may be configured (fourth configuration) to include an overcurrent protection circuit configured to limit the primary current to an overcurrent detection value or less.

[0373] Furthermore, in the signal transmission device of the fourth configuration, the overcurrent protection circuit may include a comparator configured to generate an overcurrent detection signal by comparing a sense voltage corresponding to the primary current with a predetermined threshold voltage, and the self-diagnosis circuit may be configured to diagnose whether the comparator is normal or not by monitoring the overcurrent detection signal while a predetermined test voltage is input instead of the sense voltage (fifth configuration).

[0374] Furthermore, in the signal transmission device having the fourth or fifth configuration, the overcurrent protection circuit may be configured (sixth configuration) to increase the overcurrent detection value over a predetermined soft start period when the output voltage is started or restarted.

[0375] Furthermore, in the signal transmission device having any of the above first to sixth configurations, the first abnormality detection circuit may include, as diagnostic targets of the self-diagnosis circuit, a first comparator configured to detect an undervoltage abnormality in the first power supply voltage of the primary circuit system, and a second comparator configured to detect an overvoltage abnormality in the first power supply voltage, and the second abnormality detection circuit may include, as diagnostic targets of the self-diagnosis circuit, a third comparator configured to detect an undervoltage abnormality in the second power supply voltage of the secondary circuit system, a fourth comparator configured to detect an overvoltage abnormality in the second power supply voltage, a fifth comparator configured to detect an overheat abnormality, and a sixth comparator configured to detect a short-circuit abnormality (seventh configuration).

[0376] Furthermore, the signal transmission device according to any one of the first to seventh configurations may be configured (eighth configuration) in which a first chip on which circuit elements of the primary circuit system are integrated, a second chip on which circuit elements of the secondary circuit system are integrated, and a third chip on which insulating elements that provide insulation between the primary circuit system and the secondary circuit system are integrated are sealed in a single package.

[0377] Furthermore, for example, the electronic device disclosed in this specification may have a power transistor and a gate driver IC that drives the gate of the power transistor, and the gate driver IC may be configured as a signal transmission device having any one of the first to eighth configurations (ninth configuration).

[0378] Furthermore, for example, the vehicle disclosed in this specification may have a configuration (tenth configuration) including the electronic device according to the ninth configuration.

[0379] Furthermore, for example, the power supply circuit disclosed in this specification includes a feedback control circuit configured to control a switch output stage for generating an output voltage for a secondary circuit system from an input voltage for the primary circuit system while isolating the primary circuit system from a secondary circuit system, and an overcurrent protection circuit configured to limit the primary current of the switch output stage to a predetermined overcurrent detection value or less, and the overcurrent protection circuit is configured to gradually increase the overcurrent detection value over a soft start period when starting or restarting the output voltage (eleventh configuration).

[0380] In addition, in the power supply circuit according to the eleventh configuration, the switch output stage may be configured (twelfth configuration) to drive the primary current flowing in the primary coil of a transformer and generate the output voltage from a secondary voltage induced in the secondary coil of the transformer.

[0381] In the power supply circuit according to the eleventh or twelfth configuration, the overcurrent protection circuit may include a comparator configured to compare a sense voltage corresponding to the primary current with a predetermined threshold voltage to generate an overcurrent detection signal, and may be configured (a thirteenth configuration) to gradually increase the threshold voltage over the soft start period when starting or restarting the output voltage.

[0382] Furthermore, in the power supply circuit according to any one of the above-mentioned 11th to 13th configurations, the overcurrent protection circuit may be configured (14th configuration) to perform a hiccup-type overcurrent protection operation so as to forcibly turn off the primary current until the next on timing in the switching period of the primary current when the primary current exceeds the overcurrent detection value during start-up or restart of the output voltage.

[0383] In the power supply circuit according to the fourteenth configuration, the overcurrent protection circuit may be configured (fifteenth configuration) to perform an off-latch type overcurrent protection operation so as to forcibly turn off the primary current until a waiting time longer than the switching period of the primary current has elapsed when the primary current exceeds the overcurrent detection value after starting or restarting the output voltage.

[0384] Furthermore, the power supply circuit according to any one of the eleventh to fifteenth configurations may include a feedback signal generating circuit configured to generate a feedback signal having pulse information corresponding to the output voltage and output the feedback signal from the secondary circuit system to the primary circuit system, and the feedback control circuit may be configured to drive the primary current according to the feedback signal (sixteenth configuration).

[0385] Furthermore, for example, the signal transmission device disclosed in this specification is configured (configuration 17) to include a power supply circuit having any of the configurations 11 to 16 above, and a signal transmission circuit configured to transmit a pulse signal from the primary circuit system to the secondary circuit system while insulating the primary circuit system from the secondary circuit system.

[0386] In addition, the signal transmission device according to the seventeenth configuration may also be configured (eighteenth configuration) in which a first chip on which circuit elements of the primary circuit system are integrated, a second chip on which circuit elements of the secondary circuit system are integrated, and a third chip on which insulating elements that provide insulation between the primary circuit system and the secondary circuit system are integrated are sealed in a single package.

[0387] Furthermore, for example, the electronic device disclosed in this specification may have a configuration (19th configuration) in which the electronic device has a power transistor and a gate driver IC that drives the gate of the power transistor, and the gate driver IC is a signal transmission device having the 18th configuration described above.

[0388] Furthermore, for example, the vehicle disclosed in this specification may have a configuration (20th configuration) including an electronic device according to the 19th configuration.

[0389] <Other Modifications> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0390] 1H (u / v / w) Upper gate driver IC 1L (u / v / w) Lower gate driver IC 2H (u / v / w) Upper power transistor 2L (u / v / w) Lower power transistor 3 ECU 4 Motor 5 Semiconductor device 11, 11A to 11F Low potential terminal 12, 12A to 12F High potential terminal 21, 21A to 21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 First inner end 25 First outer end 26 First spiral portion 27 Second inner end 28 Second outer end 29 Second spiral portion 31 First low potential wiring 32 Second low potential wiring 33 First high potential wiring 34 Second high potential wiring 41 Semiconductor chip 42 First main surface 43 Second main surface 44A to 44D Chip side wall 45 First functional device 51 Insulating layer 52 Insulating principal surface 53A to 53D Insulating side wall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulating layer 58 First insulating layer 59 Second insulating layer 60 Second functional device 61 Seal conductor 62 Device region 63 Outer region 64 Seal plug conductor 65 Seal via conductor 66 First inner region 67 Second inner region 71 Through wiring 72 Low-potential connecting wiring 73 Lead-out wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 Substrate plug electrode 78 First electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connecting wiring 82 Pad plug electrode 85 Dummy pattern 86 High-potential dummy pattern 87 First high-potential dummy pattern 88 Second high potential dummy pattern 89 First region 90 Second region 91 Third region 92 First connection portion 93 First pattern94 Second pattern 95 Third pattern 96 First outer peripheral line 97 Second outer peripheral line 98 First intermediate line 99 First connecting line 100 Slit 130 Isolation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 First portion 147 Second portion 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p Primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 Buffer 220 Driver chip (second chip) 221, 222 Buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer chip (third chip) 230a First wiring layer (lower layer) 230b Second wiring layer (upper layer) 231, 232 Transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Transformer chip 301 First transformer 302 Second transformer 303 Third transformer 304 Fourth transformer 305 First guard ring 306 Second guard ring 400 Signal transmission device (insulated gate driver IC) 400p Primary circuit system 400s Secondary circuit system 410 Controller chip 411 Logic circuit 411a Logic unit 411b Edge detection unit 411c Pulse transmission unit 411d Logic unit 411e, 411f Latch 411g NAND gate 411h Latch 411i Edge detection unit 411j Flip-flop 412 UVLO / OVLO circuit 412a, 412b Comparators 413, 414, 415 NMOSFETs420 Driver chip 421 Logic circuit 421a Logic unit 421b Pulse receiving unit 421c Logic unit 421d AND gate 421e Oscillator 422 UVLO / OVLO circuit 422a, 422b Comparator 423, 424 Comparator 425 PMOSFET 426 NMOSFET 427 NMOSFET (discharge switch) 430 Transformer chip 500 Power supply circuit 510 Overcurrent protection circuit (power supply abnormality detection unit) 511 Comparator 512, 513 Counter 514 OR gate 515 NAND gate 516, 517 Inverter 520 Feedback signal generation circuit 521 Oscillator 522 Comparator 530 Feedback control circuit 531 Charge pump 532 Current detection unit 533 Comparator 534 Oscillator 535 OR gate 536 RS flip-flop a1 to a8 Pads (corresponding to first current supply pads) b1 to b8 Pads (corresponding to first voltage measurement pads) c1 to c4 Pads (corresponding to second current supply pads) d1 to d4 Pads (corresponding to second voltage measurement pads) e1, e2 Pads A Electronic device B Self-diagnosis circuit B1 Logic B2, B3 Switch C1 Capacitor D1 Diode L1p, L2p, Lp Primary coil L1s, L2s, L3s, L4s, Ls Secondary coil M1 Output transistor (NMOSFET) R1 to R3 Resistor Rs Sense resistor SW11 to SW14, SW21 to SW28 Switches SWO Switch output stage T21, T22, T23, T24, T25, T26 External terminals TR1 to TR5, TR Transformer X First direction X21, X22, X23 Internal terminals Y Second direction Y21, Y22, Y23 Wiring Z Normal directionZ21, Z22, Z23 Via X vehicles

Claims

1. a signal transmission circuit configured to transmit a pulse signal from the primary circuit system to the secondary circuit system while insulating the primary circuit system from the secondary circuit system; a power supply circuit configured to generate an output voltage of the secondary circuit system from an input voltage of the primary circuit system while isolating the primary circuit system from the secondary circuit system; a first abnormality detection circuit configured to detect an abnormality in the primary circuit system; a second abnormality detection circuit configured to detect an abnormality in the secondary circuit system; a signal transmission path configured to transmit a detection result of the second abnormality detection circuit from the secondary circuit system to the primary circuit system while isolating the primary circuit system from the secondary circuit system; a self-diagnosis circuit configured to perform self-diagnosis on each of the first abnormality detection circuit, the second abnormality detection circuit, and the signal transmission path; Equipped with a power supply abnormality detection unit configured to detect an abnormality in the power supply circuit as a diagnostic target of the self-diagnosis circuit, and the self-diagnosis circuit performs self-diagnosis of the power supply abnormality detection unit first.

2. 2. The signal transmission device according to claim 1, wherein the self-diagnosis circuit diagnoses the power supply abnormality detection unit as normal, then permits operation of the power supply circuit, and starts diagnosis of components other than the power supply abnormality detection unit.

3. 2. The signal transmission device according to claim 1, wherein the power supply circuit generates the output voltage from a secondary voltage induced in a secondary coil of the transformer by driving a primary current flowing in a primary coil of the transformer.

4. 4. The signal transmission device according to claim 3, wherein the power supply abnormality detection unit includes an overcurrent protection circuit configured to limit the primary current to an overcurrent detection value or less.

5. the overcurrent protection circuit includes a comparator configured to compare a sense voltage according to the primary current with a predetermined threshold voltage to generate an overcurrent detection signal; 5. The signal transmission device according to claim 4, wherein the self-diagnosis circuit diagnoses whether the comparator is normal by monitoring the overcurrent detection signal while a predetermined test voltage is input instead of the sense voltage.

6. 5. The signal transmission device according to claim 4, wherein the overcurrent protection circuit increases the overcurrent detection value over a predetermined soft start period when the output voltage is started or restarted.

7. the first abnormality detection circuit includes, as a diagnosis target of the self-diagnosis circuit, a first comparator configured to detect an undervoltage abnormality in a first power supply voltage of the primary circuit system, and a second comparator configured to detect an overvoltage abnormality in the first power supply voltage; 2. The signal transmission device according to claim 1, wherein the second abnormality detection circuit includes, as diagnostic targets of the self-diagnosis circuit, a third comparator configured to detect an undervoltage abnormality in the second power supply voltage of the secondary circuit system, a fourth comparator configured to detect an overvoltage abnormality in the second power supply voltage, a fifth comparator configured to detect an overheat abnormality, and a sixth comparator configured to detect a short-circuit abnormality.

8. a first chip on which circuit elements of the primary circuit system are integrated; a second chip on which circuit elements of the secondary circuit system are integrated; a third chip on which an insulating element for insulating between the primary circuit system and the secondary circuit system is integrated; 2. The signal transmission device according to claim 1, wherein the signal transmission device is sealed in a single package.

9. 9. An electronic device comprising: a power transistor; and a gate driver IC that drives a gate of the power transistor, wherein the gate driver IC is the signal transmission device according to claim 1.

10. A vehicle comprising the electronic device according to claim 9.