Semiconductor device

Abstract

A semiconductor device (1) comprises: a semiconductor layer (40); a first vertical MOS transistor (10) and a second vertical MOS transistor (20) that are formed in the semiconductor layer (40); a metal layer (30) that is in contact with and connected to the entire back side surface of the semiconductor layer (40); and a support (42) that is bonded to the back side of the metal layer (30) with an adhesive (41) therebetween. In a plan view, the support (42) has a larger area than the semiconductor layer (40) and encompasses the semiconductor layer (40); the thickness of the support (42) is greater than the thickness of the semiconductor layer (40); the height of the adhesive (41) along a side surface of the semiconductor layer (40) is less than that of a top surface of the semiconductor layer (40) in a cross-sectional view of the semiconductor device (1), the cross-sectional view including the center of the semiconductor layer (40) and the outer circumference of the semiconductor layer (40) in a plan view; and in the cross-sectional view, a semiconductor chip (2), which is the portion of the semiconductor device (1) excluding the support (42) and the adhesive (41), has a curved shape that is convex in the direction toward the support (42).

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device, and more particularly to a chip-size package type semiconductor device.

[0002] In order to protect lithium ion batteries from overcharging and / or over-discharging, dual-configuration vertical MOS transistors capable of controlling bidirectional conduction with a single chip are used.

[0003] U.S. Pat. No. 4,616,413

[0004] In order to reduce the on-resistance of a dual-configuration vertical MOS transistor, it is preferable that the dual-configuration vertical MOS transistor (hereinafter, the dual-configuration vertical MOS transistor is also referred to as a "semiconductor chip") has a large area in a plan view and a thin semiconductor substrate. However, such a structure increases the warping of the semiconductor chip and reduces the strength of the semiconductor chip. Patent Document 1 discloses a structure in which a printed circuit board is attached to a rigid metal plate via a conductive adhesive.

[0005] Therefore, an object of the present disclosure is to provide a semiconductor device including a dual-configuration vertical MOS transistor that can minimize the area of ​​the rigid metal plate in a planar view in a structure in which a rigid metal plate is attached via a conductive adhesive.

[0006] In order to solve the above-mentioned problems, there is provided a chip-size package type semiconductor device capable of face-down mounting, comprising: a semiconductor substrate; a low-concentration impurity layer formed on a front surface of the semiconductor substrate; when the semiconductor substrate and the low-concentration impurity layer are collectively defined as a semiconductor layer, a first vertical MOS transistor formed in a first region of the semiconductor layer; a second vertical MOS transistor formed in a second region adjacent to the first region in a plan view of the semiconductor layer; a metal layer in contact with the entire back surface side of the semiconductor substrate; and a support body bonded to the back surface side of the metal layer via an adhesive, wherein, in the plan view, the support body has an area larger than that of the semiconductor layer and encloses the semiconductor layer, the thickness of the support body is larger than that of the semiconductor layer and includes the center and the outer periphery of the semiconductor layer in the plan view; in a cross-sectional view of the semiconductor device, the height of the adhesive along the side surface of the semiconductor layer is less than the top surface of the semiconductor layer; and when the semiconductor chip of the semiconductor device is viewed in the cross-section excluding the support body and the adhesive, the semiconductor chip has a curved shape that is convex in a direction approaching the support body.

[0007] According to the above configuration, in a dual-configuration vertical MOS transistor, it is possible to reduce the on-resistance, reduce the warpage of the semiconductor chip, and improve the strength of the semiconductor chip.

[0008] An object of the present disclosure is to provide a semiconductor device including a dual-configuration vertical MOS transistor, which reduces the on-resistance of the semiconductor chip, reduces warpage of the semiconductor chip, and improves the strength of the semiconductor chip.

[0009] FIG. 1 is a cross-sectional view schematically illustrating an example of the structure of a semiconductor device according to embodiment 1. FIG. 2A is a plan view schematically illustrating an example of the structure of a semiconductor device according to embodiment 1. FIG. 2B is a cross-sectional view schematically illustrating a main current flowing through the semiconductor device according to embodiment 1. FIG. 3A is a plan view schematically illustrating an example of the structure of a semiconductor device according to embodiment 1. FIG. 3B is a perspective view schematically illustrating an example of the structure of a semiconductor device according to embodiment 1. FIG. 4A is a flow chart illustrating a part of a manufacturing process of a semiconductor device according to embodiment 1. FIG. 4B is a cross-sectional view schematically illustrating a process of face-down mounting the semiconductor device according to embodiment 1. FIG. 5A is a cross-sectional SEM image illustrating an example of the structure of a semiconductor device according to embodiment 1. FIG. 5B is a cross-sectional SEM image illustrating an example of the structure of a semiconductor device according to embodiment 1. FIG. 5C is a cross-sectional SEM image illustrating an example of the structure of a semiconductor device according to embodiment 1. FIG. 6A is a cross-sectional SEM image illustrating an example of the structure of a semiconductor device according to comparative example 1 of embodiment 1. FIG. 6B is a cross-sectional SEM image illustrating an example of the structure of a semiconductor device according to comparative example 1 of embodiment 1. FIG. 7 is a graph showing the relationship between the amount of warpage of the semiconductor chip according to embodiment 1 and the length of the base of the fillet of the conductive adhesive. FIG. 8A is a cross-sectional SEM image showing an example of the structure of a semiconductor device according to comparative example 2 of embodiment 1. FIG. 8B is a cross-sectional SEM image showing an example of the structure of a semiconductor device according to comparative example 2 of embodiment 1. FIG. 9 is a cross-sectional SEM image showing an example of the structure of a semiconductor device according to embodiment 1. FIG. 10A is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device according to modified example 1 of embodiment 1. FIG. 10B is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device according to modified example 2 of embodiment 1. FIG. 11 is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device according to embodiment 2. FIG. 12 is a flow chart showing a part of a manufacturing process of the semiconductor device according to embodiment 2.

[0010] Specific examples of semiconductor devices according to one aspect of the present disclosure will be described below with reference to the drawings. Each embodiment shown here represents a specific example of the present disclosure. Therefore, the numerical values, shapes, components, arrangements of components, and connection forms shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. In each figure, substantially identical components are assigned the same reference numerals, and redundant explanations will be omitted or simplified.

[0011] (Embodiment 1) [1. Structure of a Semiconductor Device] Fig. 1 is a cross-sectional view showing an example of the structure of a semiconductor device. Fig. 2A is a plan view thereof, and the size and shape of the semiconductor device are examples except that the semiconductor device is rectangular (square or oblong). The size, shape, and arrangement of the pads are also examples. Fig. 2B is a cross-sectional view schematically showing the main current flowing through the semiconductor device. Figs. 1 and 2B are cross sections taken along I-I in Fig. 2A.

[0012] 1 and 2B , the semiconductor device 1 includes a semiconductor substrate 32, a metal layer 30, and a low-concentration impurity layer 33 formed on the semiconductor substrate 32. In the present disclosure, the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as a semiconductor layer 40.

[0013] The semiconductor substrate 32 is disposed on the back surface side of the semiconductor layer 40 and is made of silicon of the first conductivity type containing impurities of the first conductivity type. The low-concentration impurity layer 33 is disposed on the front surface side of the semiconductor layer 40 and is formed in contact with the semiconductor substrate 32. The low-concentration impurity layer 33 is of the first conductivity type and contains impurities of the first conductivity type at a concentration lower than the concentration of the impurities of the first conductivity type in the semiconductor substrate 32. The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0014] As shown in FIGS. 1 and 2A, the semiconductor device 1 has a first vertical MOS transistor 10 (hereinafter also referred to as “transistor 10”) formed in a first region A1 in the semiconductor layer 40, and a second vertical MOS transistor 20 (hereinafter also referred to as “transistor 20”) formed in a second region A2 in the semiconductor layer 40.

[0015] 2A , the first region A1 and the second region A2 are adjacent to each other in a plan view of the semiconductor layer 40 and are one and the other of two halves of the semiconductor layer 40 in terms of area. In FIG. 2A , a virtual boundary line 90 between the first region A1 and the second region A2 is indicated by a dashed line (for ease of understanding, the dashed line indicating the boundary line 90 is shown extending to the outside of the semiconductor layer 40 and the semiconductor device 1). Note that in FIG. 2A , the dashed lines indicating the first region A1 and the second region A2 do not strictly coincide with the semiconductor layer 40 and the boundary line 90 for ease of understanding, but are shown inside with a slight margin. However, the periphery of the first region A1 and the periphery of the second region A2 substantially coincide with the periphery of the semiconductor layer 40 and the boundary line 90.

[0016] The metal layer 30 is formed in contact with the back surface of the semiconductor layer 40 (semiconductor substrate 32) and is made of, for example, silver (Ag) or copper (Cu). Note that the metal layer 30 may contain trace amounts of elements other than metals that are mixed in as impurities during the manufacturing process of the metal material. The metal layer 30 is formed over the entire back surface of the semiconductor layer 40 (semiconductor substrate 32), and the thickness of the metal layer 30 is preferably 10 μm or more.

[0017] The support 42 is formed in indirect contact with the rear surface of the metal layer 30 via an adhesive 41. The support 42 is typically at least twice as thick as the semiconductor layer 40, and is a flat metal plate with a uniform thickness of, for example, 200 μm in its plane. Hereinafter, the support 42 may also be referred to as a thick film metal plate 42. The thick film metal plate 42 preferably has a conductivity similar to that of the metal layer 30, and for example, a conductivity of 30×10 at 20° C. ６ [S / m] or more, and is typically made of a metal material mainly made of copper (Cu). The adhesive 41 is conductive, and is typically a silver paste, and hereinafter the adhesive 41 may also be referred to as a conductive adhesive 41.

[0018] As shown in FIG. 1 , in this disclosure, the structure of the semiconductor device 1 excluding the support 42 and the adhesive 41 is referred to as the semiconductor chip 2. As shown in FIG. 1 , the semiconductor chip 2 has a curved shape that is convex toward the support 42. The curved shape refers to, for example, a shape that occurs due to warping. The amount of warping of the semiconductor chip 2 is the difference between the highest and lowest positions in the Z direction on the upper or lower surface of the semiconductor layer 40 or on the lower surface of the metal layer 30 when the semiconductor chip 2 is viewed cross-sectionally. When the warping that occurs in the semiconductor chip 2 is convex toward the support 42, the highest position is the outer periphery, particularly the corners, of the semiconductor layer 40 in a planar view, and the lowest position is the center of the semiconductor layer 40 in a planar view.

[0019] The center of the semiconductor layer 40 in a planar view refers to the intersection of diagonal lines of the semiconductor layer 40 in a planar view. Furthermore, the cross-sectional view of the semiconductor device 1 in this disclosure refers to the cross section of the semiconductor device 1 viewed from a plane that includes both the center of the semiconductor layer 40 in the semiconductor chip 2 in a planar view and the outer periphery of the semiconductor layer 40 in the semiconductor chip 2 in a planar view. In this case, the outer periphery of the semiconductor layer 40 may be any position on the outer periphery of the semiconductor layer 40.

[0020] 1 and 2A, a first body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed in a first region A1 of the semiconductor layer 40 (low-concentration impurity layer 33). A first source region 14 containing impurities of the first conductivity type, a first gate conductor 15, and a first gate insulating film 16 are formed in the first body region 18.

[0021] The first gate insulating film 16 is formed inside a plurality of first gate trenches 17 that are formed from the upper surface of the semiconductor layer 40, penetrating the first source region 14 and the first body region 18, to a depth reaching a part of the low-concentration impurity layer 33, and the first gate conductor 15 is formed inside the first gate trench 17 on the first gate insulating film 16. The first gate conductor 15 is a buried gate electrode buried inside the semiconductor layer 40, and is electrically connected to the first gate pad 119.

[0022] The first source electrode 11 is composed of a portion 12 and a portion 13, and the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13. The portion 12 of the first source electrode 11 is a layer that is joined with solder during reflow in face-down mounting, and may be made of a metal material including, but not limited to, one or more of nickel, titanium, tungsten, and palladium. The surface of the portion 12 may be plated with gold or the like.

[0023] Portion 13 of first source electrode 11 is a layer that connects portion 12 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0024] The thickness of the first source electrode 11 including the portions 12 and 13 is, for example, 2 μm or more and 8 μm or less.

[0025] A second body region 28 containing impurities of the second conductivity type is formed in the second region A2 of the low-concentration impurity layer 33. A second source region 24 containing impurities of the first conductivity type, a second gate conductor 25, and a second gate insulating film 26 are formed in the second body region 28.

[0026] The second gate insulating film 26 is formed inside a plurality of second gate trenches 27 that are formed from the upper surface of the semiconductor layer 40, penetrating the second source region 24 and the second body region 28, to a depth reaching a part of the low-concentration impurity layer 33, and the second gate conductor 25 is formed inside the second gate trench 27 on the second gate insulating film 26. The second gate conductor 25 is a buried gate electrode buried inside the semiconductor layer 40, and is electrically connected to the second gate pad 129.

[0027] The second source electrode 21 is composed of a portion 22 and a portion 23, and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23. The portion 22 of the second source electrode 21 is a layer that is joined with solder during reflow in face-down mounting, and may be made of a metal material including, but not limited to, one or more of nickel, titanium, tungsten, and palladium. The surface of the portion 22 may be plated with gold or the like.

[0028] Portion 23 of second source electrode 21 is a layer that connects portion 22 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0029] The thickness of the second source electrode 21 including the portions 22 and 23 is, for example, 2 μm or more and 8 μm or less.

[0030] With the above configuration of transistor 10 and transistor 20, semiconductor substrate 32 functions as a common drain region in which the first drain region of transistor 10 and the second drain region of transistor 20 are shared. A part of the low-concentration impurity layer 33 on the side in contact with semiconductor substrate 32 may also function as a common drain region. Note that low-concentration impurity layer 33 also serves as a drift layer common to transistor 10 and transistor 20, and may be referred to as drift layer 33 in this specification.

[0031] Furthermore, the metal layer 30 functions as a common drain electrode that is a common drain electrode for the drain electrode of the transistor 10 and the drain electrode of the transistor 20. When the adhesive 41 is a silver paste and the support 42 is a thick film metal plate, not only the metal layer 30 but also the conductive adhesive 41 and the thick film metal plate 42 function as a common drain electrode.

[0032] 1 , the first body region 18 is covered with an interlayer insulating layer 34 having an opening, and is connected to a portion 13 of the first source electrode 11 connected to the first source region 14 through the opening in the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 13 of the first source electrode are covered with a passivation layer 35 having an opening, and are connected to a portion 12 connected to the portion 13 of the first source electrode through the opening in the passivation layer 35.

[0033] The second body region 28 is covered with an interlayer insulating layer 34 having an opening, and is connected through the opening in the interlayer insulating layer 34 to a portion 23 of the second source electrode 21 that is connected to the second source region 24. The interlayer insulating layer 34 and the portion 23 of the second source electrode are covered with a passivation layer 35 having an opening, and are connected through the opening in the passivation layer 35 to a portion 22 that is connected to the portion 23 of the second source electrode.

[0034] Therefore, the plurality of first source pads 111 and the plurality of second source pads 121 refer to regions, so-called terminal portions, where the first source electrodes 11 and the second source electrodes 21, respectively, are partially exposed on the surface of the semiconductor device 1. Similarly, the one or more first gate pads 119 and the one or more second gate pads 129 refer to regions, so-called terminal portions, where the first gate electrode 19 (not shown in FIGS. 1, 2A, and 2B) and the second gate electrode 29 (not shown in FIGS. 1, 2A, and 2B), respectively, are partially exposed on the surface of the semiconductor device 1.

[0035] In the present disclosure, it is assumed that, in a plan view, the first region A1 includes only components constituting the first vertical MOS transistor 10, and the second region A2 includes only components constituting the second vertical MOS transistor 20. The boundary line 90 may be considered to be an imaginary line that traces the center position of the gap between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. It may also be considered to be the gap itself, although it has a finite width (even in the case of the gap, it can be recognized as a line with the naked eye or when viewed at low magnification).

[0036] In the semiconductor device 1, for example, the first conductivity type may be N-type and the second conductivity type may be P-type, with the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 being N-type semiconductors, and the first body region 18 and the second body region 28 being P-type semiconductors.

[0037] Furthermore, in the semiconductor device 1, for example, the first conductivity type may be P-type and the second conductivity type may be N-type, with the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 being P-type semiconductors, and the first body region 18 and the second body region 28 being N-type semiconductors.

[0038] 2. Operation of Dual-Configuration Vertical MOS Transistor In the following explanation, the conduction operation of the semiconductor device 1 will be described assuming that the transistor 10 and the transistor 20 are so-called N-channel transistors, in which the first conductivity type is N-type and the second conductivity type is P-type.

[0039] 3A and 3B are a plan view and a perspective view, respectively, of a general unit configuration of transistor 10 (or transistor 20) repeatedly formed in the X direction and the Y direction of semiconductor device 1. For ease of understanding, semiconductor substrate 32, metal layer 30, conductive adhesive 41, thick film metal plate 42, passivation layer 35, first source electrode 11 (or second source electrode 21), and interlayer insulating layer 34 are not shown in FIGS.

[0040] The structure of the transistor 10 is similar to that of the transistor 20. Therefore, the reference numerals of the transistor 10 will be used below to describe the approximate unit configuration.

[0041] The Y direction is parallel to the upper surface of the semiconductor layer 40 and is the direction in which the first gate trench 17 extends. The X direction is parallel to the upper surface of the semiconductor layer 40 and is perpendicular to the Y direction. The Z direction is perpendicular to both the X direction and the Y direction and is the direction indicating the height direction of the semiconductor device. In the present disclosure, the Y direction may be referred to as the first direction, the X direction as the second direction, and the Z direction as the third direction.

[0042] 3A and 3B , the transistor 10 includes a first connection portion 18a that electrically connects the first body region 18 and the first source electrode 11. The first connection portion 18a is a region of the first body region 18 in which the first source region 14 is not formed, and contains the same second conductivity type impurity as the first body region 18. The first source regions 14 and the first connection portion 18a are alternately and periodically arranged in the Y direction. The same applies to the transistor 20.

[0043] In the semiconductor device 1, when a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21, and a voltage equal to or greater than the threshold is applied to the second gate electrode 29 (second gate conductor 25) with the second source electrode 21 as the reference, a conductive channel is formed near the second gate insulating film 26 in the second body region 28. As a result, a main current flows through the path of the first source electrode 11 - the first connection portion 18a - the first body region 18 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 30 - the conductive adhesive 41 - the thick film metal plate 42 - the conductive adhesive 41 - the metal layer 30 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the conductive channel formed in the second body region 28 - the second source region 24 - the second source electrode 21, bringing the semiconductor device 1 into a conductive state. In this conductive path, a PN junction is present at the contact surface between the second body region 28 and the low-concentration impurity layer 33, functioning as a body diode.

[0044] Similarly, in the semiconductor device 1, when a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first source electrode 11, and a voltage equal to or greater than the threshold voltage is applied to the first gate electrode 19 (first gate conductor 15) with the first source electrode 11 as the reference, a conductive channel is formed near the first gate insulating film 16 in the first body region 18. As a result, a main current flows through the path of the second source electrode 21 - the second connection portion 28a - the second body region 28 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 30 - the conductive adhesive 41 - the thick film metal plate 42 - the conductive adhesive 41 - the metal layer 30 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the conductive channel formed in the first body region 18 - the first source region 14 - and the first source electrode 11, bringing the semiconductor device 1 into a conductive state. A PN junction is present at the contact surface between the first body region 18 and the low-concentration impurity layer 33 along this conductive path, and functions as a body diode.

[0045] 2B shows the bidirectional flow of the main current diagrammatically with arrows. The flow of the main current in the horizontal direction (X direction) occurs in each of the metal layer 30, the conductive adhesive 41, the thick-film metal plate 42, and the semiconductor substrate 32. Because the resistivity of the metal layer 30 and the thick-film metal plate 42 is lower than that of the other layers, increasing the thickness of the metal layer 30 or the thick-film metal plate 42 increases the cross-sectional area of ​​the main current path, thereby reducing the on-resistance of the semiconductor device 1.

[0046] 3. Method for Manufacturing Semiconductor Device A method for manufacturing the semiconductor device 1 will now be described.

[0047] 4A is a simplified diagram showing part of the manufacturing process of the semiconductor device 1 according to the present embodiment 1. The structure of each dual-configuration vertical MOS transistor, which will be separated later, is formed in a grid shape on a silicon wafer up to step 501.

[0048] Next, in step 502, the back side of the silicon wafer (corresponding to the semiconductor substrate 32 in terms of each dual-configuration vertical MOS transistor to be subsequently separated) is thinned. In the thinning process in step 502, the thickness of the semiconductor layer 40 is preferably controlled to be 15 μm or more and 100 μm or less, and more preferably 15 μm or more and 75 μm or less.

[0049] Next, in step 503, a metal layer 30 is formed on the entire back surface of the thinned silicon wafer. The metal layer 30 may be a multilayer structure including, for example, multiple metal layers. However, the surface that comes into contact with the conductive adhesive 41 in the next step 504 is preferably made primarily of silver (Ag) or copper (Cu). The multiple metal layers may be individually formed by any method, such as vapor deposition, sputtering, or plating. In the metal layer formation step 503, the thickness of the metal layer 30 is preferably 10 μm or greater.

[0050] Next, in step 504, the silicon wafer is diced using a blade to separate each dual-configuration vertical MOS transistor. The separated dual-configuration vertical MOS transistors are in a state that can be called the semiconductor chip 2 described above, since the thick film metal plate 42 has not yet been bonded to them.

[0051] In step 504, the metal layer 30 formed on the back surface of the silicon wafer in step 503 is also cut together with the silicon wafer, but the metal layer 30 that is physically pushed out by the blade extends along the side surfaces of the semiconductor chips 2. As a result, protrusions (so-called burrs) that extend downward (in the −Z direction) on the back surface side of the semiconductor chips 2 are formed on the periphery of the metal layer 30 of the individual semiconductor chips 2.

[0052] Note that dicing with a blade is just one example, and the dual-configuration vertical MOS transistors may be separated into individual pieces by a method other than blade dicing, such as dicing with a laser, although protrusions are less likely to be formed when dicing with a laser.

[0053] Next, in step 505, a thick film metal plate 42 to which a conductive adhesive 41 such as silver paste has been applied is prepared, and the back side of the metal layer 30 of the semiconductor chip 2 is bonded to the thick film metal plate 42. Typically, the amount of conductive adhesive 41 pressed into the plate is set to, for example, 5 μm to 10 μm, and the conductive adhesive 41 is applied to the surface of the thick film metal plate 42 after hardening and bonding, with the thickness calculated to be a target value (for example, 20 μm to 60 μm).

[0054] The conductive adhesive 41 is an adhesive for joining the back surface of the metal layer 30 to the thick film metal plate 42. When viewed after the conductive adhesive 41 has hardened and the thick film metal plate 42 has been joined, it is desirable that the entire back surface of the metal layer 30 is evenly covered with the conductive adhesive 41.

[0055] The thick-film metal plate 42 is selected to have an area larger than the area of ​​the semiconductor substrate 32 in a plan view, and during bonding, the plates are aligned so that a margin of approximately equal width is provided from the outer periphery of the metal layer 30 to the outer periphery of the closest thick-film metal plate 42 in a plan view. As an example, as shown in FIG. 2A , the thick-film metal plate 42 has a similar shape to the semiconductor layer 40. The semiconductor layer 40 and the thick-film metal plate 42 having similar shapes means that the semiconductor layer 40 and the thick-film metal plate 42 have the same shape in a plan view and differ only in area.

[0056] Furthermore, if the thick metal plate 42 is a so-called flat plate that has a uniform thickness macroscopically and does not have any steps or irregularities, it is convenient for bonding the semiconductor layer 40. In the first embodiment, the thick metal plate 42 will be described as being a flat plate.

[0057] During bonding, it is common to align the relatively small-area semiconductor chip 2 with the relatively large-area thick-film metal plate 42 as the receiving side. In plan view, the conductive adhesive 41 may protrude from the back surface of the metal layer 30. The amount of protruding conductive adhesive 41 may or may not be uniform along the periphery of the semiconductor layer 40 in plan view. FIG. 2A shows, as an example, a case where the protruding conductive adhesive 41 is uniform. Alternatively, as shown in FIG. 1, the protruding conductive adhesive 41 may partially creep up along the side surface of the semiconductor chip 2, forming a roughly triangular fillet.

[0058] In step 505, the thick film metal plate 42 is heat-treated at a high temperature while the semiconductor chip 2 is attached to it in order to harden the conductive adhesive 41, such as silver paste. The heat treatment temperature is preferably 200°C or less, for example, 170°C. The conductive adhesive 41 hardens at around 170°C, bonding the metal layer 30 and the thick film metal plate 42 together to form the semiconductor device 1.

[0059] During the heat treatment at a high temperature of 170°C, the semiconductor chip 2 warps. As described above, the thickness of the semiconductor layer 40 is preferably 15 μm or more and 75 μm or less, and the thickness of the first source electrode 11 and the second source electrode 21 is preferably 2 μm or more and 8 μm or less. The thickness of the metal layer 30 is preferably 10 μm or more. With this thickness configuration, the semiconductor chip 2 at 170°C warps in a convex shape in the direction approaching the thick film metal plate 42 (the −Z direction in the cross-sectional view of FIG. 1 ).

[0060] FIG. 4B is a schematic diagram showing the semiconductor device 1 when it is mounted face down.

[0061] [4. Discussion] The following describes the effects achieved by the semiconductor device 1 according to the first embodiment.

[0062] In a dual-configuration vertical MOS transistor, in order to reduce the on-resistance when conductive, it is necessary to thin the semiconductor substrate 32 (semiconductor layer 40) and thicken the metal layer 30. A semiconductor chip 2 with such a configuration is prone to warping in the -Z direction at high temperatures. The thinner the semiconductor layer 40 and the thicker the metal layer 30, the greater the warping that occurs at high temperatures.

[0063] In particular, when a dual-configuration vertical MOS transistor with low on-resistance is required, it is effective to increase the area in a plan view of the semiconductor chip 2 in order to increase the total gate width of the channel. However, if the area is large, the warpage that occurs in the semiconductor chip 2 increases significantly.

[0064] When mounting the semiconductor chip 2 face-down on the mounting substrate, a reflow process using a solder joint material is required, in which the temperature is raised to approximately 240° C. It is known that if the amount of warping of the semiconductor chip 2 at 240° C. exceeds 40 μm, mounting problems are likely to occur regardless of the direction of the warping, and therefore it is necessary to keep the amount of warping of the semiconductor chip 2 below 40 μm.

[0065] In the semiconductor device 1 according to the first embodiment, the semiconductor chip 2 is bonded to the thick film metal plate 42 at approximately 170° C., which is lower than 240° C., and therefore the amount of warping of the semiconductor chip 2 can be fixed to the same level as that which occurs at approximately 170° C. If a material that does not remelt, such as silver paste, is selected as the conductive adhesive 41, the reflow process (240° C.) performed when mounting the semiconductor device 1 face-down on a mounting substrate will not increase the warping of the semiconductor chip 2 already bonded to the thick film metal plate 42, as shown in FIG.

[0066] Therefore, the configuration of the semiconductor device 1 according to the first embodiment is particularly effective for a semiconductor chip 2 having a structure in which the amount of warpage of the semiconductor chip 2 is large, that is, a semiconductor chip 2 having a thin semiconductor layer 40, a large area in a plan view of the semiconductor chip 2, and a thick metal layer 30. Furthermore, if the thick film metal plate 42 is sufficiently thick, the thick film metal plate 42 serves as a support for the semiconductor chip 2, and can compensate for the decrease in strength of the semiconductor chip 2 caused by making the semiconductor layer 40 thinner.

[0067] 1, when the semiconductor chip 2 is bonded to the thick film metal plate 42 via the conductive adhesive 41, the conductive adhesive 41 that protrudes from the semiconductor chip 2 partially creeps up onto the side surfaces of the semiconductor chip 2, forming a fillet that is roughly triangular in cross section. Therefore, if the area of ​​the thick film metal plate 42 is not sufficiently larger than the area of ​​the semiconductor layer 40 in plan view, there is a concern that the protruding conductive adhesive 41 will not be contained within the thick film metal plate 42.

[0068] Furthermore, when viewed in cross section, if the overflowing conductive adhesive 41 creeps up to the top surface of the semiconductor chip 2, there is a possibility that the semiconductor device 1 may short-circuit, so the height to which the conductive adhesive 41 creeps up from the surface of the thick film metal plate 42 along the side of the semiconductor chip 2 (the height of the fillet of the conductive adhesive 41) must be less than the top surface of the semiconductor layer 40.

[0069] Therefore, in the semiconductor device 1 according to this embodiment 1, (1) the area of ​​the thick metal plate 42 in plan view must be prepared taking into account that the conductive adhesive 41 will protrude by the length of the bottom edge of the fillet of the conductive adhesive 41, and (2) the thickness of the semiconductor chip 2 must be adjusted taking into account that the conductive adhesive 41 will creep up by the height of the fillet of the conductive adhesive 41.

[0070] The semiconductor device 1 of this embodiment 1 controls the curvature of the semiconductor chip 2, thereby determining the appropriate size of the thick film metal plate 42 in a planar view to address (1) above, and preventing short circuits in the semiconductor chip 2 caused by the overflow (fillet) of the conductive adhesive 41 to address (2) above.

[0071] First, the above (1) will be explained.

[0072] As described above, in the semiconductor device 1 according to the first embodiment, the thick film metal plate 42 needs to be large enough to contain, in a plan view, the semiconductor chip 2 and the conductive adhesive 41 that protrudes from the semiconductor chip 2. Therefore, by joining the semiconductor chip 2 to the thick film metal plate 42, the area of ​​the semiconductor device 1 is inevitably larger than the area of ​​the semiconductor chip 2 in a plan view.

[0073] In order to keep the area of ​​the semiconductor device 1 as small as possible from the area of ​​the semiconductor chip 2 when viewed in a plane, it is necessary to make the area of ​​the thick film metal plate 42 as small as possible, and to do this, it is important to reduce the length by which the conductive adhesive 41 protrudes.

[0074] Therefore, in the semiconductor device 1 of this embodiment 1, the thickness of the metal layer 30 is set to be 10 μm or more, and the warp of the semiconductor chip 2 at 170°C is controlled to be convex in the direction approaching the support 42 (-Z direction).

[0075] 1, when the back surface of the metal layer 30 warps so as to be convex in the direction approaching the thick film metal plate 42 (-Z direction), the outer periphery of the semiconductor chip 2 warps in the direction relatively away from the support 42 (+Z direction). When the semiconductor chip 2 assumes such a curved shape, the pressure of the conductive adhesive 41 on the outer periphery of the semiconductor chip 2 is reduced, which has the effect of suppressing the length by which the conductive adhesive 41 protrudes from the semiconductor chip 2.

[0076] Therefore, in a cross-sectional view of the semiconductor device 1, when the semiconductor chip 2 of the semiconductor device 1 is viewed excluding the thick film metal plate 42 and the conductive adhesive 41, it is desirable that the semiconductor chip 2 has a curved shape that is convex in the direction approaching the thick film metal plate 42. In other words, it is desirable that the thickness of the conductive adhesive 41 immediately below the semiconductor layer 40 at the periphery of the semiconductor layer 40 in a plan view is thicker than the thickness of the conductive adhesive 41 immediately below the semiconductor layer 40 at the center of the semiconductor layer 40 in a plan view.

[0077] 5A, 5B, and 5C show cross-sectional SEM images of the semiconductor device 1 according to the first embodiment mounted face-down on a mounting substrate. Fig. 5B is an enlarged cross-sectional SEM image of the portion surrounded by the dashed line in Fig. 5A, and Fig. 5C is an enlarged cross-sectional SEM image of the portion surrounded by the dashed line in Fig. 5B. In the semiconductor device 1 shown in Fig. 5A, 5B, and 5C, the semiconductor layer 40 has a thickness of 53 μm, the first source electrode 11 and the second source electrode 21 have a thickness of 4 μm, the metal layer 30 has a thickness of 10 μm, and the thick-film metal plate 42 has a thickness of 200 μm.

[0078] 5B and 5C indicates the position of the interface between the semiconductor layer 40 and the metal layer 30 at the center of the semiconductor layer 40 in a plan view, extended to the outer periphery of the semiconductor layer 40 in a plan view. Also, horizontal line B in Fig. 5C indicates the position of the interface between the semiconductor layer 40 and the metal layer 30 at the outer periphery of the semiconductor layer 40 in a plan view.

[0079] 5C, horizontal line A is closer to thick film metal plate 42 (in the -Z direction) than horizontal line B, and the distance in the Z direction between horizontal line A and horizontal line B is 10 μm. Therefore, semiconductor chip 2 has a warped shape that is convex in the direction approaching thick film metal plate 42 (in the -Z direction), and the amount of warping is 10 μm.

[0080] As shown in Figure 5C, when the amount of warping of the semiconductor chip 2 is 10 [μm], the protruding length of the conductive adhesive 41 (the length of the bottom edge of the fillet of the conductive adhesive 41) is 128 [μm], and the thick film metal plate 42 must have a margin of 128 [μm] or more from the outer periphery of the semiconductor chip 2.

[0081] 6A and 6B show cross-sectional SEM images of Comparative Example 1 according to the first embodiment. FIG. 6B is an enlarged cross-sectional SEM image of the portion surrounded by the dashed line in FIG. 6A . In the semiconductor device 1 shown in FIGS. 6A and 6B , the semiconductor layer 40 has a thickness of 53 μm, the first source electrode 11 and the second source electrode 21 have a thickness of 4 μm, the metal layer 30 has a thickness of 3 μm, and the thick-film metal plate 42 has a thickness of 200 μm. In this thickness configuration, the semiconductor chip 2 has a warped shape that is convex in the direction away from the thick-film metal plate 42 (the +Z direction), and the amount of warping is 2 μm.

[0082] As shown in Figure 6B, when the semiconductor chip 2 warps by 2 μm in the +Z direction, the length that the conductive adhesive 41 protrudes (the length of the base of the fillet of the conductive adhesive 41) is 150 μm, which is longer than the length of the base of the fillet of the conductive adhesive 41, 128 μm, that is formed when the semiconductor chip 2 warps by 10 μm in the -Z direction in the semiconductor device 1 of this embodiment 1.

[0083] That is, by warping the semiconductor chip 2 so as to be convex in the −Z direction, the pressure exerted by the conductive adhesive 41 on the outer periphery of the semiconductor chip 2 is reduced, and the length of the conductive adhesive 41 that protrudes from the semiconductor chip 2 in a plan view is reduced. Therefore, with the aim of specifying an appropriate size for the thick film metal plate 42, the inventors have studied the relationship between the amount of warping of the semiconductor chip 2 and the protruding length of the conductive adhesive 41 (the length of the base of the fillet of the conductive adhesive 41) in the semiconductor device 1 according to the first embodiment.

[0084] 7 shows a graph illustrating the relationship between the length of the base of the fillet of the conductive adhesive 41 and the amount of warpage of the semiconductor chip 2. The horizontal axis represents the amount of warpage w [μm] of the semiconductor chip 2, and the vertical axis represents the length b [μm] of the base of the fillet formed by the protruding conductive adhesive 41. The thickness of the semiconductor layer 40 was set to 53 [μm], and semiconductor chips 2 with different amounts of warpage were fabricated by adjusting the thickness of the metal layer 30, and the length of the base of the fillet of the conductive adhesive 41 for each amount of warpage was plotted.

[0085] The plots marked with circles represent the relationship between the length b of the base of the fillet of the conductive adhesive 41 and the amount of warping w of the semiconductor chip 2 when the amount of pressing of the conductive adhesive 41 is 5 μm, where b and w have the relationship b = -0.75 × w + 135.3. The plots marked with squares represent the relationship between the length b of the base of the fillet of the conductive adhesive 41 and the amount of warping w of the semiconductor chip 2 when the amount of pressing of the conductive adhesive 41 is 10 μm, where b and w have the relationship b = -1.5 × w + 270.6.

[0086] The pushing amount of the conductive adhesive 41 refers to the amount by which the semiconductor chip 2 is further pushed toward the thick film metal plate 42 after the entire back side of the metal layer 30 is evenly covered with the conductive adhesive 41 in order to ensure adhesion between the metal layer 30 and the conductive adhesive 41 during bonding in step 505.

[0087] The area of ​​the semiconductor layer 40 in plan view is S [μm ２ ], and the amount of conductive adhesive 41 pushed in is P [μm], the amount of conductive adhesive 41 that protrudes is S × P [μm] ３], the greater the amount of conductive adhesive 41 pressed in, the greater the amount of conductive adhesive 41 that protrudes. In order to minimize the amount of conductive adhesive 41 that protrudes and to ensure stable adhesion between metal layer 30 and conductive adhesive 41, it is desirable that the amount of conductive adhesive 41 pressed in be in the range of 5 μm to 10 μm.

[0088] In the semiconductor device 1 according to the first embodiment, in order for the thick-film metal plate 42 to contain the protruding portion of the conductive adhesive 41 in a planar view, a margin equal to the length of the bottom edge of the fillet of the conductive adhesive 41 is required when the conductive adhesive 41 is pressed in a range of 5 μm to 10 μm. Therefore, if the shortest distance from the outer periphery of the semiconductor layer 40 to the outer periphery of the thick-film metal plate 42 in a planar view is M μm, then it is sufficient to satisfy the relationship -0.75 × w - 135.3 (plotted line with circles) ≦ M ≦ -1.5 × w + 270.6 (plotted line with squares). It is not necessary to expand the area of ​​the thick-film metal plate 42 beyond this range. By adjusting the direction and amount of warpage w of the semiconductor chip 2, it is possible to reduce the area of ​​the thick-film metal plate 42.

[0089] Note that, in a plan view, the minimum length M of the closest distance from the outer periphery of the semiconductor layer 40 to the outer periphery of the thick film metal plate 42 refers to the margin mentioned in the explanation of step 504. That is, as an example, it refers to the minimum length of the margin provided with approximately the same width from the outer periphery of the metal layer 30 to the outer periphery of the thick film metal plate 42 closest to it in a plan view.

[0090] However, as a result of the inventors' investigations, if the amount of warping of the semiconductor chip 2 at 170°C exceeds 30 μm, the physical adhesion between the metal layer 30 and the conductive adhesive 41 at the outer periphery of the semiconductor chip 2 deteriorates, and the conductive adhesive 41 and the metal layer 30 may peel off.

[0091] 8A and 8B show cross-sectional SEM images of Comparative Example 2 according to the first embodiment. FIG. 8B is an enlarged cross-sectional SEM image of the portion surrounded by the dashed line in FIG. 8A . In the semiconductor device 1 shown in FIGS. 8A and 8B , the semiconductor layer 40 has a thickness of 40 μm, the first source electrode 11 and the second source electrode 21 have a thickness of 4 μm, the metal layer 30 has a thickness of 25 μm, and the thick-film metal plate 42 has a thickness of 200 μm. In this thickness configuration, the semiconductor chip 2 has a warped shape that is convex in the direction approaching the thick-film metal plate 42 (the −Z direction), and the amount of warpage is 35 μm.

[0092] 8B , when the warpage of the semiconductor chip 2 is 35 μm, a space is created between the metal layer 30 and the conductive adhesive 41 at the periphery of the semiconductor chip 2, and it can be seen that the metal layer 30 and the conductive adhesive 41 are not in close contact with each other. If the warpage is too large, there is a concern that the conductive adhesive 41 may peel off near the periphery of the metal layer 30 in a planar view. Therefore, in order to reduce the amount of protrusion of the conductive adhesive 41 while stably ensuring the adhesion of the bond between the metal layer 30 and the thick-film metal plate 42, it is preferable that the warpage of the semiconductor chip 2 at 170° C. be 30 μm or less.

[0093] The direction of warping (also called the direction of curvature) and the amount of warping (also called the amount of curvature) of the semiconductor chip 2 at high temperatures are determined by the relationship between the physical properties of the semiconductor layer 40, the first source electrode 11, the second source electrode 21, and the metal layer 30, such as the linear expansion coefficient and Young's modulus, and their respective thicknesses.

[0094] Since the metal species constituting the first source electrode 11 and the second source electrode 21 and the metal species constituting the metal layer 30 often have similar linear expansion coefficients, the direction of warping of the semiconductor chip 2 is often determined solely by the relationship between the metal layer 30 and the thickness of the first source electrode 11 and the second source electrode 21.

[0095] Since the thickness of the first source electrode 11 and the thickness of the second source electrode 21 are typically 2 μm or more and 8 μm or less, the thickness of the metal layer 30 is desirably 10 μm or more in order to control the warpage to be convex in the −Z direction. This is because, by making the thickness of the metal layer 30 thicker than the thickness of the first source electrode 11 and the thickness of the second source electrode 21, greater thermal stress is generated in the metal layer 30 at high temperatures, and the semiconductor chip 2 takes on a curved shape that is convex in the direction in which the metal layer 30 is provided (−Z direction).

[0096] The amount of warpage is determined by the relative relationship between the thickness of the semiconductor layer 40 and the metal layer 30, and increases as the semiconductor layer 40 becomes thinner and as the metal layer 30 becomes thicker. Therefore, by adjusting the thickness of the semiconductor layer 40 and the metal layer 30, it is possible to control the amount of warpage of the semiconductor chip 2 at 170°C to 30 μm or less.

[0097] In the semiconductor device 1 according to the first embodiment, when the amount of conductive adhesive 41 applied to the surface of the thick-film metal plate 42 and the amount of pressing of the conductive adhesive 41 are constant, and when stable adhesion between the metal layer 30 and the thick-film metal plate 42 via the conductive adhesive 41 is ensured, the volume of the conductive adhesive 41 that protrudes from the semiconductor chip 2 (the volume of the fillet of the conductive adhesive 41) is constant. While the volume of the fillet of the conductive adhesive 41 is constant, the height of the fillet of the conductive adhesive 41 (the amount by which the conductive adhesive 41 creeps up from the surface of the thick-film metal plate 42 along the side of the semiconductor chip 2) varies depending on the length of the base of the fillet of the conductive adhesive 41.

[0098] Next, the above (2) will be explained.

[0099] In the semiconductor device 1 according to the first embodiment, when the length of the long side of the semiconductor layer 40 in plan view is L1 [μm] and the length of the short side is L2 [μm] (when the semiconductor layer 40 is a square, L1=L2), the amount of the conductive adhesive 41 that protrudes from the semiconductor chip 2 is L1×L2×P [μm ３Furthermore, the conductive adhesive 41 that protrudes from the semiconductor chip 2 forms a fillet that is roughly triangular in cross section, so if the height of the fillet of the conductive adhesive 41 is ht [μm], the volume of the fillet of the conductive adhesive 41 is (b×ht / 2)×2×(L1+L2) [μm ３ However, it is assumed that the amount of the conductive adhesive 41 that protrudes in plan view is uniform along the periphery of the semiconductor layer 40.

[0100] The amount of conductive adhesive 41 that protrudes from the semiconductor chip 2 is L1×L2×P [μm ３ ] and the volume of the fillet of the conductive adhesive 41 b × ht × (L1 + L2) [μm ３ ], the height of the fillet of the conductive adhesive 41 is ht = P × L1 × L2 / {b × (L1 + L2)}. Note that this is based on the assumption that the amount of warping of the semiconductor chip 2 is 30 μm or less and that the conductive adhesive 41 is not peeled off between the metal layer 30 and the thick film metal plate 42.

[0101] If the conductive adhesive 41 creeps up to the top surface of the semiconductor chip 2, the semiconductor device 1 may be short-circuited, so the amount by which the conductive adhesive 41 creeps up from the surface of the thick film metal plate 42 along the side of the semiconductor chip 2 (the height of the fillet of the conductive adhesive 41) must be less than the top surface of the semiconductor layer 40.

[0102] In the semiconductor device 1 according to the first embodiment, the semiconductor chip 2 is controlled to be convex in the direction approaching the support 42 (-Z direction), and the outer periphery of the semiconductor chip 2 is curved due to warping in the direction relatively away from the support 42 (+Z direction). When the semiconductor chip 2 has such a curved shape, the distance from the surface of the thick metal plate 42 to the top surface of the semiconductor chip 2 becomes longer on the outer periphery of the semiconductor chip 2 in a plan view, and therefore, the effect of preventing the conductive adhesive 41 that protrudes from the semiconductor chip 2 from creeping up to the top surface of the semiconductor chip 2 can be enjoyed.

[0103] In the semiconductor device 1 of this embodiment 1, when the thickness of the semiconductor chip 2 at the center of the semiconductor chip 2 in a planar view is H [μm] and the thickness of the conductive adhesive 41 is T [μm], if the relationship ht < H + T + w holds, the conductive adhesive 41 will not creep up to the top surface of the semiconductor layer 40.

[0104] In other words, by controlling the direction and amount of warping of the semiconductor chip 2, it is possible to reduce the length of the conductive adhesive 41 that protrudes from the semiconductor chip 2 in a planar view, and also to prevent the conductive adhesive 41 that protrudes from the semiconductor chip 2 in a cross-sectional view from creeping up onto the top surface of the semiconductor chip 2.

[0105] 9 is a cross-sectional SEM image of the outer periphery of the semiconductor device 1 according to the first embodiment. As shown in FIG. 9, the metal layer 30 may have protrusions in the direction toward the thick-film metal plate 42 (-Z direction) on the surface that is bonded to the conductive adhesive 41. As an example, these protrusions are burrs that are formed when the metal layer 30 is physically stretched when the semiconductor chips 2 are separated from the wafer state using a blade. In the case of burrs, they are often formed continuously along the outer periphery of the metal layer 30 in a plan view.

[0106] In the semiconductor device 1 of this embodiment 1, if there are even partial areas on the outer periphery of the semiconductor chip 2 where the burr height is 5 μm or more from the back surface of the metal layer 30, this acts as an anchor effect for the bonding between the metal layer 30 and the conductive adhesive 41, and has the effect of improving adhesion with the conductive adhesive 41.

[0107] Furthermore, as a result of further investigations by the inventors, it was found that, in terms of adhesion between the metal layer 30 and the conductive adhesive 41, it is desirable that the surface of the metal layer 30 that is bonded to the conductive adhesive 41 is made of a metal species other than nickel (Ni), and that typically, if silver (Ag) or copper (Cu) is used as the main material, adhesion between the metal layer 30 and the conductive adhesive 41 can be stably ensured.

[0108] A modification of the semiconductor device 1 according to the first embodiment will be described below.

[0109] 10A shows a schematic cross-sectional view of Modification 1 of the semiconductor device 1 according to Embodiment 1. In the semiconductor device 1 according to Modification 1, the support 42 has a curved shape that is convex toward the semiconductor chip 2. The curved shape of the support 42 refers to a shape that occurs due to warping of the support 42 during heat treatment when bonding the metal layer 30 and the support 42 via the conductive adhesive 41, for example. The amount of warping of the support 42 is the difference between the highest and lowest positions in the Z direction on the upper or lower surface of the support 42 when viewed cross-sectionally. When the warping of the support 42 is convex toward the semiconductor chip 2, the highest position is the center of the support 42 in a planar view, and the lowest position is the outer periphery of the support 42 in a planar view, particularly a corner on the outer periphery.

[0110] The direction and amount of warping of the support 42 can be controlled by adjusting the amount of warping of the semiconductor chip 2 generated at 170°C, the thickness and / or material of the support 42, the thickness and / or material of the conductive adhesive 41, or the bonding conditions. The easiest way to adjust the thickness is to reduce the thickness of the support 42. Reducing the thickness of the support 42 can increase the amount of warping of the support 42 when the semiconductor device 1 is completed, but this reduces the rigidity of the semiconductor device 1. Therefore, as a guideline, it is preferable to design the thickness of the support 42 so that the amount of warping of the support 42 is smaller than the amount of warping of the semiconductor chip 2.

[0111] As shown in Figure 10A, in semiconductor device 1, when the amount of curvature of support 42 is smaller than the amount of curvature of semiconductor chip 2 and support 42 has a curved shape that is convex in the direction toward semiconductor chip 2, the pressure applied to conductive adhesive 41 is reduced compared to when support 42 is not curved, and the length by which conductive adhesive 41 protrudes from semiconductor layer 40 in a planar view can be reduced.

[0112] 10B shows a schematic cross-sectional view of Modification 2 of the semiconductor device 1 according to Embodiment 1. In the semiconductor device 1 according to Modification 2, the support 42 has a curved shape that is convex in a direction away from the semiconductor chip 2. As shown in FIG. 10B , in the semiconductor device 1, when the amount of curvature of the support 42 is smaller than the amount of curvature of the semiconductor chip 2 and the support 42 has a curved shape that is convex in a direction away from the semiconductor chip 2, it is possible to prevent voids from occurring between the semiconductor chip 2 and the conductive adhesive 41 near the center of the semiconductor layer 40 in a planar view, compared to when the support 42 is not curved.

[0113] Second Embodiment Hereinafter, a semiconductor device 100 according to a second embodiment, which is configured by partially modifying the configuration of the semiconductor device 1 according to the first embodiment, will be described.

[0114] The semiconductor device 100 according to the second embodiment is an example in which the support 42 , which is a thick metal plate according to the first embodiment, is changed to an insulating support 420 .

[0115] Here, for the semiconductor device 100 of embodiment 2, the components similar to those of the semiconductor device 1 of embodiment 1 have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from the semiconductor device 1.

[0116] 11 is a schematic cross-sectional view of a semiconductor device 100 according to embodiment 2. This semiconductor device 100 differs from the semiconductor device 1 according to embodiment 1 in that the support 42 is replaced with an insulating support 420.

[0117] 12 shows a simplified diagram of part of the manufacturing process of the semiconductor device 100 according to the second embodiment. Steps 501 to 504 are the same as the manufacturing process of the semiconductor device 1 according to the first embodiment. Step 506 corresponds to step 505 in the first embodiment.

[0118] In the second embodiment, the semiconductor chip 2 is bonded to the insulating support 420 in step 506. In step 506, a conductive adhesive 41 is applied in advance to the upper surface of the insulating support 420. The adhesive 41 is, for example, a silver paste, and hardens at a high temperature of 170° C., bonding the semiconductor chip 2 and the insulating support 420 together.

[0119] [3. Discussion] In the semiconductor device 100 according to this embodiment, the insulating support 420 is used, and therefore rigidity can be improved compared to the thick film metal plate according to embodiment 1. An example of a material with good rigidity is a silicon substrate. When a silicon substrate is used as the insulating support 420, the same effect as when a thick film metal plate is used in the semiconductor device 1 according to embodiment 1 can be achieved with thinner dimensions.

[0120] Furthermore, since the semiconductor device according to the present disclosure includes the metal layer 30, the metal layer 30 can be used as a conduction path to achieve a sufficiently low on-resistance. Therefore, the semiconductor device 100 according to the second embodiment is useful in the case of a semiconductor chip 2 including the metal layer 30 on the back surface side of the semiconductor layer 40.

[0121] As with the semiconductor device 1 of embodiment 1, in the semiconductor device 100 of embodiment 2, the presence of the metal layer 30 in the semiconductor chip 2 makes it possible to make the direction of warping that occurs in the semiconductor chip 2 at 170°C convex in the direction approaching the support 42.

[0122] Although the semiconductor device according to one aspect of the present disclosure has been described above based on Embodiments 1 and 2 and Modifications 1 and 2, the present disclosure is not limited to these embodiments and modifications. As long as they do not deviate from the spirit of the present disclosure, various modifications that would occur to a person skilled in the art to these embodiments and configurations constructed by combining components of different embodiments and modifications may also be included within the scope of one or more aspects of the present disclosure.

[0123] A semiconductor device including a vertical MOS transistor according to the present invention can be widely used as a device for controlling the conduction state of a current path.

[0124] REFERENCE SIGNS LIST 1, 100 Semiconductor device 2 Semiconductor chip 10 Transistor (first vertical MOS transistor) 11 First source electrode 12, 13 Portion 14 First source region 15 First gate conductor 16 First gate insulating film 17 First gate trench 18 First body region 18a First connection region 19 First gate electrode 20 Transistor (second vertical MOS transistor) 21 Second source electrode 22, 23 Portion 24 Second source region 25 Second gate conductor 26 Second gate insulating film 27 Second gate trench 28 Second body region 28a Second connection region 29 Second gate electrode 30 Metal layer 32 Semiconductor substrate 33 Low concentration impurity layer (drift layer) 34 Interlayer insulating layer 35 Passivation layer 40 Semiconductor layer 41 Adhesive (conductive adhesive) 42 Support (thick film metal plate) 90 Boundary line 111 First source pad 119 First gate pad 121 Second source pad 129 Second gate pad 420 Insulating support A1 First region A2 Second region

Claims

1. A semiconductor device capable of face-down mounting, A semiconductor substrate; a low concentration impurity layer formed on a front surface side of the semiconductor substrate; When the semiconductor substrate and the low-concentration impurity layer are combined to form a semiconductor layer, a first vertical MOS transistor formed in a first region of the semiconductor layer; a second vertical MOS transistor formed in a second region adjacent to the first region in a plan view of the semiconductor layer; a metal layer in contact with the entire back surface of the semiconductor substrate; A support body is bonded to a back surface side of the metal layer via an adhesive, In the plan view, the support has an area larger than that of the semiconductor layer and contains the semiconductor layer; the thickness of the support is greater than the thickness of the semiconductor layer; In a cross-sectional view of the semiconductor device including a center of the semiconductor layer and an outer periphery of the semiconductor layer in the plan view, a height of the adhesive along a side surface of the semiconductor layer is less than a top surface of the semiconductor layer; When the semiconductor chip of the semiconductor device is viewed in cross section without the support and the adhesive, the semiconductor chip has a curved shape that is convex toward the support. Semiconductor device.

2. In the plan view, the semiconductor layer has a rectangular shape, At the outer periphery of the semiconductor layer in the plan view, the thickness of the adhesive directly below the semiconductor layer is greater than the thickness of the adhesive directly below the semiconductor layer at the center of the semiconductor layer in the plan view. The semiconductor device according to claim 1 .

3. When the amount of curvature of the semiconductor chip is w [μm] and the shortest distance from the outer periphery of the semiconductor layer to the outer periphery of the support in the plan view is M [μm], The relationship -0.75 x w + 135.3 ≤ M ≤ -1.5 x w + 270.6 is established. The semiconductor device according to claim 1 .

4. In the plan view, a length of a side of the semiconductor layer along a first direction is L1 [μm], a length of a side of the semiconductor layer along a second direction perpendicular to the first direction is L2 [μm], and a length of the adhesive sticking out from the outer periphery of the semiconductor chip is b [μm]; When the thickness of the semiconductor chip is H [μm] and the thickness of the adhesive is T [μm] at the center of the semiconductor chip in the plan view, The relationship P×L1×L2 / {b×(L1+L2)}<H+T+w(5[μm]≦P≦10[μm]) is established. The semiconductor device according to claim 3 .

5. In the cross-sectional view, the support has a curved shape that is convex in a direction toward the semiconductor chip, The amount of curvature of the support is smaller than the amount of curvature of the semiconductor chip. The semiconductor device according to claim 3 .

6. In the cross-sectional view, the support has a curved shape that is convex in a direction away from the semiconductor chip, The amount of curvature of the support is smaller than the amount of curvature of the semiconductor chip. The semiconductor device according to claim 3 .

7. In the plan view, the metal layer has an outer periphery provided with a protrusion protruding toward the adhesive, In the cross-sectional view of the protrusion, the protrusion has a height of 5 μm or more. The semiconductor device according to claim 3 .

8. The metal layer has a multi-layer structure, and the surface that is bonded to the adhesive does not contain nickel. The semiconductor device according to claim 3 .

9. The adhesive is a conductive adhesive containing conductive particles and made of a resin that is thermally cured at 200° C. or less. The semiconductor device according to claim 3 .

10. The support is made of a metal, The electrical conductivity of the support is equal to that of the metal layer. The semiconductor device according to claim 3 .

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