Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor that has excellent mechanical strength while enabling miniaturization yet ensuring high capacity.　A multilayer ceramic capacitor 1 including: a laminate 2 comprising an inner layer part 6, in which a dielectric layer 4 and an inner electrode layer 5 are alternately laminated, and two outer layer parts 7 forming two main surfaces A at mutually opposing positions in a layering direction T; and outer electrodes 3 that are respectively disposed on end faces C on two sides in a length direction L of the laminate 2, and that are connected to the inner electrode layer 5. When one of the two outer layer parts 7 is divided into three equal portions in the layering direction T, the porosity S1 of an outermost layer 7o positioned on the main surface A side, the porosity S2 of a middle layer 7m, and the porosity S3 of an innermost layer 7i positioned on the inner layer part 6 side satisfy the following relational expression.　(1): S1>S2>S3

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] As electronic devices such as mobile phones and digital devices have become smaller and more powerful, there has been a demand for smaller electronic components, including multilayer ceramic capacitors, with higher capacitance. Multilayer ceramic capacitors used in mobile devices such as mobile phones and portable music players must be able to withstand shocks such as being dropped without falling off the mounting board and without cracking. Furthermore, multilayer ceramic capacitors used in in-vehicle devices such as ECUs must be able to withstand bending stresses caused by linear expansion and contraction of the mounting board during thermal cycles and tensile stresses applied to the external electrodes.

[0003] A multilayer ceramic capacitor generally comprises a laminate in which dielectric layers and internal electrode layers are alternately stacked, with dielectric layers further stacked on the top and bottom surfaces of the laminate, and a pair of external electrodes formed on both end surfaces of the laminate. In order to increase the mechanical strength of the multilayer ceramic capacitor, a technique is known in which a conductive resin layer is formed by using a paste containing a thermoplastic resin containing a metal element and a glass component between the base electrode layer and the plating layer that constitute the external electrodes, thereby mitigating the mechanical and thermal stress that the laminate receives from the wiring board when mounted on the wiring board (e.g., Patent Document 1).

[0004] However, the arrangement of conductive resin layers increases the thickness of the external electrodes, which tends to lead to an increase in the size of the multilayer ceramic capacitor, and therefore cannot be said to be a sufficient technology for multilayer ceramic capacitors, which are expected to become increasingly smaller and have larger capacitances in the future.

[0005] Therefore, there is a need to develop multilayer ceramic capacitors that are compact, have high capacitance, and have excellent mechanical strength.

[0006] JP 2019-16781 A

[0007] An object of the present invention is to provide a multilayer ceramic capacitor that is excellent in mechanical strength while enabling miniaturization and large capacitance.

[0008] The inventors discovered that, in the outer layer portions sandwiching the inner layer portion in the stacking direction, in which dielectric layers and internal electrode layers are alternately stacked, by setting the porosity S1 of the outermost layer located on the main surface side, the porosity S2 of the intermediate layer, and the porosity S3 of the innermost layer located on the inner layer portion side to a predetermined relationship, it is possible to alleviate the mechanical and thermal stresses received from the wiring board when mounted, and thus completed the present invention.

[0009] That is, the present invention provides a multilayer ceramic capacitor having a laminate including an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, and two outer layer portions arranged to sandwich the inner layer portion in the stacking direction and forming two main surfaces at opposite positions in the stacking direction, and external electrodes arranged on both end surfaces of the laminate in a length direction intersecting the stacking direction and connected to the internal electrode layers, wherein when one of the two outer layer portions sandwiching the inner layer portion is divided into thirds in the stacking direction, the porosity S1 of the outermost layer located on the main surface side, the porosity S2 of the intermediate layer, and the porosity S3 of the innermost layer located on the inner layer portion side satisfy the following relational expression (1): S1>S2>S3 (1)

[0010] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can be made smaller and have a higher capacitance, while also being able to alleviate the mechanical and thermal stresses that it receives from a wiring board when mounted.

[0011] 1 is an external perspective view of a multilayer ceramic capacitor 1 (first embodiment); FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor 1 shown in FIG. 1; FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor 1 shown in FIG. 1; FIG. 4 is a schematic diagram showing the structure of an inner layer portion 6 of the multilayer ceramic capacitor 1; FIG. 5 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor 1 shown in FIG. 1, showing another form of a side gap portion; FIG. 6 is an external perspective view of a multilayer ceramic capacitor 100 (second embodiment); FIG. 7 is a cross-sectional view taken along line VII-VII of the multilayer ceramic capacitor 100 shown in FIG. 6; FIG. 8 is a schematic diagram showing the structure of an inner layer portion 6 of the multilayer ceramic capacitor 100; FIG. 9 is an external perspective view of a multilayer ceramic capacitor 200 (third embodiment); FIG. 10 is a cross-sectional view taken along line X-X of the multilayer ceramic capacitor 200 shown in FIG. 11; FIG. 12 is a schematic diagram showing the structure of an inner layer portion 6 of the multilayer ceramic capacitor 200;

[0012] Hereinafter, embodiments of the multilayer ceramic capacitor of the present invention will be described.

[0013] It should be noted that the embodiments are merely illustrative of the embodiments of the present invention, and the present invention is not limited to the contents of the embodiments. Furthermore, it is possible to combine the contents described in different embodiments, and such implementations are also included in the present invention. Furthermore, the drawings are intended to facilitate understanding of the specification and may be drawn schematically, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0014] First Embodiment (Multilayer Ceramic Capacitor) FIGS. 1 to 5 show the shape and structure of a multilayer ceramic capacitor 1. FIG. 1 is a schematic perspective view of the multilayer ceramic capacitor 1. FIG. 2 is a cross-sectional view (LT cross-sectional view) of the multilayer ceramic capacitor 1 taken along line II-II at the center in the width direction W shown in FIG. 1. FIG. 3 is a cross-sectional view (WT cross-sectional view) of the multilayer ceramic capacitor 1 taken along line III-III at the center in the length direction L shown in FIG. 1. FIG. 4 is a schematic diagram showing the structure of an inner layer portion 6 of the multilayer ceramic capacitor 1. FIG. 5 is a cross-sectional view (WT cross-sectional view) of the multilayer ceramic capacitor 1 taken along line III-III at the center in the length direction L shown in FIG. 1, showing a side gap portion having a different form from the side gap portion shown in FIG. 3. The direction in which the dielectric layers 4 and the internal electrode layers 5 are stacked is defined as the stacking direction T. The structure of the multilayer ceramic capacitor 1 will be described using the length direction L perpendicular to the stacking direction T and the width direction W perpendicular to the stacking direction T and the length direction L. In the embodiment, the stacking direction T, the width direction W, and the length direction L are perpendicular to one another, but they are not necessarily perpendicular to one another and may intersect one another.

[0015] The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a laminate 2 and a pair of external electrodes 3 provided on both ends of the laminate 2. The laminate 2 includes an inner layer portion 6 including a plurality of pairs of dielectric layers 4 and internal electrode layers 5.

[0016] Furthermore, of the six outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the stacking direction T are designated as the first main surface A1 and the second main surface A2, a pair of outer surfaces facing each other in the width direction W are designated as the first side surface B1 and the second side surface B2, and a pair of outer surfaces facing each other in the length direction L are designated as the first end surface C1 and the second end surface C2.

[0017] In addition, when there is no need to particularly distinguish between the first main surface A1 and the second main surface A2, they will be collectively referred to as the main surface A; when there is no need to particularly distinguish between the first side surface B1 and the second side surface B2, they will be collectively referred to as the side surface B; and when there is no need to particularly distinguish between the first end surface C1 and the second end surface C2, they will be collectively referred to as the end surface C.

[0018] The dimensions of the multilayer ceramic capacitor 1 are not particularly limited, but for example, the dimension in the stacking direction T can be 0.1 mm or more and 6.5 mm or less, the dimension in the length direction L can be 0.2 mm or more and 6.5 mm or less, and the dimension in the width direction W can be 0.1 mm or more and 5.5 mm or less.

[0019] (Laminate) The laminate 2 includes an inner layer portion 6, an outer layer portion 7 disposed on the main surface A side of the inner layer portion 6, and a side gap portion 8 disposed on the side surface B side of the inner layer portion 6. The laminate 2 preferably has rounded ridge portions E. The ridge portions E are portions where two surfaces of the laminate 2, i.e., the main surface A and the side surface B, the main surface A and the end surface C, or the side surface B and the end surface C, intersect, and also include corners where the main surface A, the side surface B, and the end surface C intersect.

[0020] (Inner layer portion) The inner layer portion 6 is located between the internal electrode layer 5 closest to the first main surface A1 and the internal electrode layer 5 closest to the second main surface A2, and is a portion where multiple internal electrode layers 5 face each other via the dielectric layer 4, forming electrostatic capacitance.

[0021] 4 is a schematic diagram showing the structure of the inner layer portion 6. In an actual multilayer ceramic capacitor, the dielectric layers 4 are integrated to such an extent that the boundaries between the dielectric layers 4 are not visible.

[0022] (Internal electrode layers) The internal electrode layers 5 are preferably rectangular, although not particularly limited thereto. The corners of the rectangle may be rounded or may be formed at an angle. The first internal electrode layer 5a extends to the first end face C1 of the laminate 2, and the second internal electrode layer 5b extends to the second end face C2 of the laminate 2.

[0023] The internal electrode layers 5 are formed by sintering a conductive paste containing a metal powder serving as a conductor, an organic solvent, a binder, and a dispersant on the dielectric layers 4. The internal electrode layers 5 and the dielectric layers 4 are alternately stacked to form an internal layer portion 6. The internal electrode layers 5 are composed of a first internal electrode layer 5a and a second internal electrode layer 5b, and the first internal electrode layer 5a and the second internal electrode layer 5b are disposed on the dielectric layers 4a and 4b, respectively. Note that, unless it is necessary to particularly distinguish between the first internal electrode layer 5a and the second internal electrode layer 5b, they will be collectively referred to as the internal electrode layer 5.

[0024] The internal electrode layers 5 can be made of a conductive material such as, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys, but are not limited to these.

[0025] The thickness of the internal electrode layer 5 is not particularly limited, but may be, for example, about 0.3 μm to 1.5 μm.

[0026] The internal electrode layers 5 include opposing electrode portions 52 where the first internal electrode layer 5a and the second internal electrode layer 5b face each other, and extraction electrode portions 51 where the first internal electrode layer 5a and the second internal electrode layer 5b do not face each other and are drawn from the opposing electrode portions 52 toward one end face C. An end of the extraction electrode portion 51 is exposed at the end face C and electrically connected to the external electrode 3. The extending direction of the extraction electrode portions 51 differs between the first internal electrode layer 5a and the second internal electrode layer 5b, and the extraction electrode portions 51 are drawn alternately toward the first end face C1 and the second end face C2. An electric charge is accumulated between the opposing electrode portions 52 of the first internal electrode layer 5a and the second internal electrode layer 5b adjacent to each other in the stacking direction T, and the first internal electrode layer 5a and the second internal electrode layer 5b function as a capacitor.

[0027] The thickness of each of the first internal electrode layers 5a and the second internal electrode layers 5b is preferably, for example, about 0.2 μm or more and 2.0 μm or less, and the total number of the first internal electrode layers 5a and the second internal electrode layers 5b is preferably 2 layers or more and 2000 layers or less.

[0028] (Dielectric Layer) The dielectric layer 4 can be formed of a dielectric material such as a ceramic material. Examples of such ceramic materials include BaTiO ３ , CaTiO ３ , SrTiO ３ , and CaZrO ３ When the above-mentioned dielectric material is used as the main component, a secondary component such as a Si compound, an Mg compound, an Al compound, a Mn compound, an Sn compound, a Cu compound, an Ni compound, or a rare earth compound can be added depending on the desired properties of the laminate.

[0029] The main component of the dielectric layer 4 is BaTiO ３ When using the above, crystal grains with a perovskite structure are formed in the dielectric layer 4. In order to increase the capacitance of the multilayer ceramic capacitor, it is preferable that the grain size of the crystals is 1 μm or less and the thickness of the dielectric layer is thin.

[0030] The dielectric layer 4 is made of, for example, a sintered ceramic green sheet containing a ceramic material.

[0031] The thickness of the dielectric layer 4 is not particularly limited, but can be, for example, about 0.2 μm to 10.0 μm in the effective region for forming capacitance formed by the first internal electrode layer 5 a and the second internal electrode layer 5 b.

[0032] The number of dielectric layers 4 is not particularly limited, but may be, for example, 2 to 2000 layers in the effective capacitance formation area formed by the first internal electrode layers 5a and the second internal electrode layers 5b.

[0033] (Outer Layer Portion) On both the top and bottom of the inner layer portion 6, outer layer portions 7 are provided, which are composed only of dielectric layers and do not have internal electrode layers 5. The thickness of the outer layer portions 7 is not limited, but may be, for example, 15 μm to 150 μm. The outer layer portions 7 are formed of a ceramic material, and may be formed of the same material as the dielectric layer 4 of the inner layer portion 6. The thickness of the dielectric layer in the outer layer portion 7 may be greater than the thickness of the dielectric layer in the effective region of capacitance formation where the internal electrode layers 5 are formed. The material of the dielectric layer in the outer layer portion 7 may also be different from the material of the dielectric layer 4 of the inner layer portion 6.

[0034] (Side Gap Portion) The side gap portion 8 is provided on both side surfaces B of the inner layer portion 6 in the laminate 2. The dimension of the side gap portion 8 in the width direction W is preferably 5 μm or more and 40 μm or less, and particularly preferably 5 μm or more and 20 μm or less.

[0035] The side gap portion 8 can be formed integrally with the inner layer portion 6 using the same material as the dielectric layer 4, or may be formed by attaching the same ceramic material as the dielectric layer 4 to both sides of the inner layer portion 6 in the width direction W. The side gap portion 8 is also called a W gap portion.

[0036] 5 shows an example in which ceramic material is attached to both sides of the inner layer portion 6 in the width direction W to form side gap portions 81, 82. The side gap portions 81, 82 can have a two-layer structure with inner layers 81a, 82a on the inside in the width direction W and outer layers 81b, 82b on the outside in the width direction.

[0037] The boundaries between the inner layers 81 a, 82 a and the outer layers 81 b, 82 b can be easily confirmed by observing them with an optical microscope due to the difference in sinterability. Furthermore, the side gap portion 8 is not limited to a two-layer structure consisting of the inner layers 81 a, 82 a and the outer layers 81 b, 82 b, but may have a three-layer or more layer structure.

[0038] (Porosity of Outer Layer Portions) By providing voids P in the outer layer portions 7, the multilayer ceramic capacitor 1 can alleviate the mechanical and thermal stresses that it receives from the wiring board when mounted. However, providing voids P allows moisture to penetrate into the inner layer portions 6 from the outside, which reduces the moisture resistance of the laminate 2, so it is necessary to adjust the void ratio.

[0039] The LT cross section at the center in the width direction W of the multilayer ceramic capacitor 1 is observed at 6000x magnification using a scanning electron microscope (SEM). Five areas with a field of view of 19.5 μm × 10.5 μm are photographed so that no overlapping areas exist, and the ratio of the area occupied by voids P to the entire field of view is calculated as the porosity from each of the obtained SEM images by image analysis, and the average value for the five fields of view can be obtained.

[0040] When one of the two outer layer portions 7a, 7b sandwiching the inner layer portion 6 is divided into three equal parts in the stacking direction T, the porosity S1 of the outermost layer 7o located on the main surface A side, the porosity S2 of the intermediate layer 7m, and the porosity S3 of the innermost layer 7i located on the inner layer portion 6 side satisfy the following relational expression (1), it becomes possible to alleviate mechanical and thermal stresses while maintaining moisture resistance: S1>S2>S3 (1)

[0041] For example, as shown in Figure 2, when the outer layer portion 7b is divided into three equal parts in the stacking direction T, the voids P in the outermost layer 7bo located on the main surface A side contribute to stress relaxation, so it is preferable to make the void ratio S1 relatively large, and the voids P in the innermost layer 7bi located on the inner layer portion 6 side contribute to moisture resistance, so it is preferable to make the void ratio S3 relatively small.When the void ratio S1 of the outermost layer 7bo located on the main surface A side, the void ratio S2 of the intermediate layer 7bm, and the void ratio S3 of the innermost layer 7bi located on the inner layer portion 6 side satisfy the above-mentioned relational expression (1), it is possible to achieve both stress relaxation and maintenance of moisture resistance.

[0042] Furthermore, by ensuring that both of the two outer layer portions 7a, 7b sandwiching the inner layer portion 6 satisfy the relational expression (1), it becomes possible to reliably obtain the effect of alleviating stress.

[0043] The porosity S1 of the outermost layer 7bo is preferably 10% or less, the porosity S2 of the intermediate layer 7bm is preferably 5% or less, and the porosity S3 of the innermost layer 7bi is preferably 4% or less.

[0044] (Components in the Outer Layer Portion) By incorporating Si into the outer layer portion 7, the sinterability of the ceramic material is improved and the difference in shrinkage rate between the inner layer portion 6 and the outer layer portion 7 can be reduced. This prevents the outer layer portion 7 from peeling off from the inner layer portion 6. Furthermore, by segregating Si at the interface between the inner layer portion 6 and the outer layer portion 7, the adhesive strength between the inner layer portion 6 and the outer layer portion 7 can be increased. This reliably prevents moisture from penetrating from the outside. Furthermore, incorporating Mg can suppress the grain growth of ceramic grains, making it possible to form a dense layer structure.

[0045] The composition of each component can be determined by cutting the multilayer ceramic capacitor to expose the dielectric ceramic layers and performing elemental analysis on the cut surface using wavelength dispersive X-ray analysis (WDX) or transmission electron microscope-energy dispersive X-ray analysis (TEM-EDX). At this time, the composition of each dielectric ceramic layer is measured at five points and the average value is calculated.

[0046] The content of Si segregated at the boundary between the outer layer portion 7 and the inner layer portion 6 is preferably higher than the content of Si in the intermediate layer 7m of the outer layer portion 7. By increasing the content of Si at the boundary in this manner, peeling of the outer layer portion 7 from the inner layer portion 6 can be prevented.

[0047] Furthermore, the content of Mg segregated at the boundary between the outer layer portion 7 and the inner layer portion 6 is preferably higher than the content of Mg in the intermediate layer 7m of the outer layer portion 7. This increases the density of the innermost layer 7bi and improves moisture resistance.

[0048] (Thickness of Outer Layer Portion) In the two outer layer portions 7a, 7b, when the thickness of one in the stacking direction T is t1 and the thickness of the other in the stacking direction T is t2, by making t1 larger than t2 and arranging the outer layer portion 7 having the thickness t1 so as to face the wiring board, it is possible to reduce the vibration noise (ringing noise) of the wiring board that is generated due to the electrostrictive effect of the multilayer ceramic capacitor.

[0049] (External Electrodes) The external electrodes 3 are electrically connected to the internal electrode layers 5 and function as external input / output terminals. On the surface of the laminate 2, a first external electrode 3a and a second external electrode 3b are formed.

[0050] The first external electrode 3a is formed on the first end face C1 of the laminate 2. The first external electrode 3a is formed in a cap shape, and its edge portion extends from the first end face C1 of the laminate 2 to the first main face A1, the second main face A2, the first side face B1, and the second side face B2.

[0051] The second external electrode 3b is formed on the second end face C2 of the laminate 2. The second external electrode 3b is formed in a cap shape, and its edge portion extends from the second end face C2 of the laminate 2 to the first main face A1, the second main face A2, the first side face B1, and the second side face B2.

[0052] In the multilayer ceramic capacitor 1, the first internal electrode layer 5a extended to the first end face C1 of the laminate 2 is connected to the first external electrode 3a, and the second internal electrode layer 5b extended to the second end face C2 of the laminate 2 is connected to the second external electrode 3b.

[0053] The external electrode 3 may have a structure including, for example, a base electrode layer 30 and a plating layer 31 disposed on the base electrode layer 30 .

[0054] The base electrode layer 30 includes at least one layer selected from a baked layer, a conductive resin layer, a direct plating layer, and the like, as will be described below.

[0055] (Baked Layer) The baked layer is formed by applying a conductive paste containing glass and metal to the laminate 2 and baking it, and may be baked simultaneously with the internal electrode layers 5, or may be baked after baking the internal electrode layers 5. The temperature for the baking treatment is preferably 700 to 900°C.

[0056] The glass component includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal includes at least one selected from Cu, Ni, Ag, Pd, Ag—Pd alloy, Au, etc.

[0057] The thickness of the baking layer is preferably, for example, 0.1 μm or more and 200 μm or less. The baking layer may be a multi-layered layer.

[0058] (Conductive Resin Layer) The conductive resin layer is formed on the surface of the baked layer, or is formed directly on the surface of the laminate 2. The conductive resin layer may be a multi-layered layer.

[0059] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate 2, and then performing a heat treatment at a temperature of 250 to 550°C or higher to thermally cure the resin and form a conductive resin layer. The atmosphere during this heat treatment is N ２ In order to prevent the resin from scattering and the various metal components from being oxidized, it is preferable to keep the oxygen concentration at 100 ppm or less.

[0060] The thickness of the conductive resin layer at the center of the first end face C1 and the second end face C2 is preferably, for example, about 10 μm to 200 μm, and the thickness of the conductive resin layer on the first principal face A1 and the second principal face A2 and the first side face B1 and the second side face B2 at the center in the longitudinal direction L is preferably, for example, about 5 μm to 50 μm.

[0061] The resin for the conductive resin layer can be any of various known thermosetting resins, such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin is one of the most suitable resins, as it has excellent heat resistance, moisture resistance, and adhesion. The amount of resin contained in the conductive resin layer is preferably 25 vol% or more and 65 vol% or less of the total volume of the conductive resin.

[0062] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, and imidazole-based curing agents can be used as the curing agent.

[0063] Because the conductive resin layer contains a thermosetting resin, it is more flexible than, for example, a conductive layer formed by firing a plating film or a conductive paste. Therefore, even if the ceramic electronic component is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the ceramic electronic component.

[0064] The metal powder contained in the conductive resin layer may be Ag, Cu, Ni, or an alloy thereof. The Cu and Ni metal powders may be coated with Ag. The Cu metal powders may be treated with an anti-oxidation treatment.

[0065] The reason for using Ag metal powder as the conductive metal is that Ag has the lowest resistivity of all metals, making it suitable for electrode materials, and because Ag is a noble metal, it does not oxidize and has high resistance.The reason for using Ag-coated metal is that it allows the base metal to be made inexpensive while maintaining the above-mentioned properties of Ag.

[0066] The metal powder contained in the conductive resin layer is preferably contained in an amount of 35 vol % to 75 vol % based on the volume of the entire conductive resin.

[0067] The shape of the metal powder contained in the conductive resin layer is not particularly limited. The metal powder may be spherical, flat, etc. The average particle size of the metal powder contained in the conductive resin layer is not particularly limited, but can be, for example, about 0.3 μm or more and 10 μm or less.

[0068] The metal powder contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, when the metal powder particles come into contact with each other, a conductive path is formed inside the conductive resin layer.

[0069] (Plating Layer) A plating layer may be provided directly on the end surface C of the laminate 2 where the internal electrode layers 5 are exposed. That is, the multilayer ceramic capacitor 1 may have a structure including a plating layer that is electrically connected directly to the internal electrode layers 5 and the surface electrodes 32. In such a case, a catalyst may be provided on the surface of the laminate 2 as a pretreatment, and then the plating layer may be formed directly.

[0070] The plating layer preferably contains at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, etc., or an alloy containing these metals. For example, when the first internal electrode layer 5a and the second internal electrode layer 5b are formed using Ni, the direct plating layer is preferably formed using Cu, which has good bonding properties with Ni.

[0071] The thickness of each plating layer is preferably 1.0 μm or more and 15 μm or less. The plating layer preferably does not contain glass. The proportion of metal contained in the plating layer per unit volume is preferably 99 volume % or more.

[0072] When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which makes the process more complicated. Therefore, electrolytic plating is usually preferred. As a plating method, barrel plating is preferably used. If necessary, an upper layer plating electrode may be formed on the surface of the lower layer plating electrode in the same manner.

[0073] The plating layer 31 disposed on the base electrode layer 30 contains at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0074] The plating layer can be formed of multiple layers, and for example, a two-layer structure consisting of Ni plating and Sn plating is preferred. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component, and the Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, allowing for easier mounting. The thickness of each plating layer is preferably 1.0 μm or more and 15 μm or less.

[0075] (Surface Electrode) A surface electrode 32 can be provided on the main surface A of the laminate 2 with a predetermined length, extending from an end surface C of the laminate 2 in the longitudinal direction L toward the center of the laminate 2. The surface electrode 32 can be formed integrally with the external electrode 3 by extending onto the main surface A. However, as shown in Figure 2, the surface electrode 32 can also be formed on the main surface A of the laminate 2 in advance, and the surface electrode 32 can be covered by the portion of the external electrode 3 that extends onto the main surface A. By providing a gap P in the outermost layer 7o located on the main surface A side of the outer layer portion 7, unevenness is formed on the main surface A, increasing the contact area and thereby increasing the adhesion of the surface electrode 32.

[0076] Although FIG. 2 shows a configuration in which the surface electrode 32 is completely covered by the external electrode 3, it may also be a configuration in which at least a portion of the surface electrode 32 is covered by a portion of the external electrode 3 that extends onto the main surface A.

[0077] (Method for Manufacturing Multilayer Ceramic Capacitor) Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment will be described.

[0078] (Laminate Manufacturing Process) In the laminate manufacturing process, first, a ceramic slurry for the inner layer is prepared by adding a solvent or the like to a ceramic material for forming the dielectric layer for the inner layer. Then, the ceramic slurry for the inner layer is molded into a sheet to prepare a ceramic green sheet for the inner layer for lamination. A pattern of the internal electrode layer is printed on the surface of the ceramic green sheet for the inner layer for lamination using a conductive paste. Next, the ceramic green sheets for the inner layer for lamination are stacked and isostatically pressed to prepare an inner layer block.

[0079] A ceramic slurry for the outer layer is prepared by adding a solvent or the like to a ceramic material for forming the outer dielectric layer. The ceramic slurry for the outer layer is then molded into a sheet to create a ceramic green sheet for lamination. The ceramic green sheets for the outer layer for lamination are then stacked and isostatically pressed to create a first outer layer block and a second outer layer block. Because the first outer layer block and the second outer layer block are pressed separately, the density is improved compared to conventional integral pressing. Furthermore, because more pressure is applied to the region at the beginning of lamination, the density is improved, while the region at the end of lamination is less dense than the region at the beginning of lamination.

[0080] Because the first and second outer layer blocks are isostatically pressed, the denser portions of the laminated sheets are brought to the inner layer side, making it possible to form a denser region on the inner layer side. By forming the surface electrodes before isostatically pressing the first and second outer layer blocks, it is no longer necessary to remove a single dielectric sheet to expose the surface electrodes as in the conventional method, and the surface shapes of the surface electrodes can be made similar on the first and second main surface sides.

[0081] The first outer layer block, inner layer block, and second outer layer block are then stacked together and pressed at a pressure of 1 to 50 MPa at a temperature of 70 to 90°C for a maximum press pressure holding time of 180 seconds or less, thereby completing a mother block member.

[0082] The mother block member is divided along cutting lines corresponding to the dimensions of the laminate to produce multiple laminated chips, which are then barrel polished to round the corners and ridges, and then fired.

[0083] According to the above process, the outer layer portion 7 and the side gap portion 8 can be formed simultaneously with the formation of the laminate 2, but it is also possible to first form the inner layer portion 6 in which the ends of the internal electrode layers 5 in the width direction W are exposed on both sides by cutting out from a mother block member, and then form the laminate 2 by attaching a ceramic material to both sides of the inner layer portion 6 so as to cover the exposed ends of the internal electrode layers 5. The laminate 2 formed in this manner can have side gap portions 81, 82 as shown in Fig. 5 .

[0084] (Firing process) In the firing process, the laminated chip is subjected to a binder removal process and a firing process to form an element part. The firing process co-sinters the conductive paste layer and the green sheet for the dielectric layer, forming the internal electrode layer 5 and the dielectric layer 4, respectively. The conditions for the binder removal process can be determined depending on the type of organic binder contained in the green sheet and the conductive paste layer. The firing process can be carried out at a temperature at which the laminated chip is sufficiently densified. The firing temperature depends on the materials of the dielectric and the internal electrode layer, but is preferably 900°C to 1400°C.

[0085] (External Electrode Forming Process) In the external electrode forming process, external electrodes 3 are formed on the laminate 2 to form the multilayer ceramic capacitor 1. The external electrodes 3 may be formed by a known method. For example, a base electrode layer, a conductive resin layer, or a direct plating layer is formed on the end surface C where the internal electrode layers 5 of the laminate 2 are drawn out and exposed, and further plating layers are provided as necessary. In this embodiment, a Ni plating layer and a Sn plating layer are formed on the baked layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating. In this manner, a multilayer ceramic capacitor can be obtained.

[0086] Second Embodiment A multilayer ceramic capacitor 100 will be described as a second embodiment. FIGS. 6 to 8 show the shape and structure of the multilayer ceramic capacitor 100. FIG. 6 is a schematic perspective view of the multilayer ceramic capacitor 100. FIG. 7 is a cross-sectional view of the multilayer ceramic capacitor 100 taken along line VII-VII shown in FIG. 6. FIG. 8 is a schematic diagram showing the structure of an inner layer 6 of the multilayer ceramic capacitor 100. The multilayer ceramic capacitor 100 will be described, focusing on the configuration that differs from the multilayer ceramic capacitor 1 of the first embodiment.

[0087] 6 , the multilayer ceramic capacitor 100 of this embodiment includes a laminate 2 and four external electrodes 3. The external electrodes 3 are arranged at each of the four corners of the laminate 2 when viewed along the stacking direction T. The external electrodes 3 are arranged to cover a portion of the first main surface A1, a portion of the second main surface A2, a portion of either the first side surface B1 or the second side surface B2, and a portion of either the first end surface C1 or the second end surface C2 of the laminate 2. However, this is not limited thereto, and the external electrodes may be arranged so as not to cover a portion of the first main surface A1 or the second main surface A2 in order to further reduce the dimension in the stacking direction T. In this case, the external electrodes are generally L-shaped.

[0088] The ratio Y / X of the length Y in the width direction W to the length X in the length direction L of the multilayer ceramic capacitor 100 of this embodiment is, but is not limited to, 0.85 or more and 1.0 or less. For example, if the ratio Y / X of the length Y to the length X is less than 0.85, the shape will be closer to a substantially rectangular shape rather than a substantially square shape. In this case, the height of the multilayer ceramic capacitor 100, i.e., the dimension in the stacking direction T, is preferably 120 μm or less.

[0089] 7 and 8 , the first internal electrode layer 5a of this embodiment has a counter electrode portion 52 and two lead electrode portions 51. Each lead electrode portion 51 is exposed to either the first side surface B1 or the second side surface B2 and either the first end face C1 or the second end face C2. The lead electrode portions 51 of two first internal electrode layers 5a facing each other in the stacking direction T are led out to two different surfaces. Specifically, when one first internal electrode layer 5a has a lead electrode portion 51 led out to the first side surface B1 and the first end face C1 and a lead electrode portion 51 led out to the second side surface B2 and the second end face C2, the other first internal electrode layer 5a has a lead electrode portion 51 led out to the first side surface B1 and the second end face C2 and a lead electrode portion 51 led out to the second side surface B2 and the first end face C1. 8, the lead electrode portion 51 is exposed continuously from the end face to the side face, but is not limited to this and may be exposed discontinuously from the end face to the side face. A dielectric layer 114a is formed around the opposing electrode portion 52 of the first internal electrode layer 5a, except for the portion from which the lead electrode portion 51 extends.

[0090] The second internal electrode layer 5b is disposed at a position shifted from the lead electrode portion 51 of the first internal electrode layer 5a in the stacking direction T. In other words, the second internal electrode layer 5b is disposed at a position overlapping the lead electrode portion 51 of the first internal electrode layer 5a when viewed along the stacking direction T. Alternatively, two second internal electrode layers 5b may be disposed on the same plane. Two second internal electrode layers 5b disposed on the same plane are disposed without overlapping each other when viewed along the stacking direction T, and a dielectric layer 114b is disposed between the two second internal electrode layers 5b. By disposing the second internal electrode layer 5b on each of the two outer layer portions 7a, 7b, it is possible to ensure electrical connectivity between the first surface electrode 132a and the second surface electrode 132b (described later) and the first internal electrode layer 5a via the base electrode layer 30. Furthermore, the second internal electrode layer 5b is fixed to the conductive component in the external electrode 3, thereby improving the fixing strength between the laminate 2 and the external electrode 3.

[0091] 7 , in this embodiment, four first surface electrodes 132a (only two are shown in FIG. 7 ) are arranged on the first main surface A1 of the laminate 2. Furthermore, four second surface electrodes 132b (only two are shown in FIG. 7 ) are arranged on the second main surface A2 of the laminate 2. The first surface electrodes 132a are arranged at each of the four corners of the first main surface A1. The second surface electrodes 132b are arranged at each of the four corners of the second main surface A2. The first surface electrodes 132a and the second surface electrodes 132b are arranged at positions shifted in the stacking direction T from the lead electrode portions 51 of the first internal electrode layers 5a. In other words, the first surface electrodes 132a and the second surface electrodes 132b are arranged at positions overlapping the lead electrode portions 51 of the first internal electrode layers 5a when viewed along the stacking direction T. The first surface electrode 132a and the second surface electrode 132b are electrodes that do not form capacitance.

[0092] The first surface electrode 132a and the second surface electrode 132b may have the same shape and dimensions as the second internal electrode layer 5b. In this case, the first surface electrode 132a and the second surface electrode 132b are preferably made of the same material as the second internal electrode layer 5b.

[0093] The first surface electrode 132a and the second surface electrode 132b may be formed by sputtering. When the first surface electrode 132a and the second surface electrode 132b are formed by sputtering, the first surface electrode 132a and the second surface electrode 132b preferably contain at least one selected from Ni, Cr, Cu, and Ti. The thickness of the first surface electrode 132a and the second surface electrode 132b formed by sputtering is preferably 50 nm to 400 nm. This allows the thickness of the first surface electrode 132a and the second surface electrode 132b in the stacking direction T to be sufficiently thin, thereby allowing the thickness of the multilayer ceramic capacitor 100 in the stacking direction T to be sufficiently thin. The thickness of the first surface electrode 132a and the second surface electrode 132b in the stacking direction T can be adjusted by changing the distance between the target and the area to be sputtered. Furthermore, the thickness of the first surface electrode 132a and the second surface electrode 132b may be measured using an actual observation image, or may be measured using fluorescent X-rays to convert the thickness from a specified element using a calibration curve method for metal species.

[0094] The first surface electrode 132a and the second surface electrode 132b may be sintered electrodes. A sintered electrode is an electrode containing the same dielectric component as the dielectric layer 4. In other words, when the dielectric layer 4 is made of CaZrO ３ In this case, the first surface electrode 132a and the second surface electrode 132b may be made of, for example, Ca or Zr, or CaZrO ３ When the dielectric layer 4a and the dielectric layer 4b have different components, the first surface electrode 132a and the second surface electrode 132b preferably contain the same type of component as the dielectric layer 4b. This can further strengthen the adhesion between the dielectric layer 4b and the first surface electrode 132a and the second surface electrode 132b.

[0095] The metal components in the fired electrodes preferably contain Ni. In this case, the first internal electrode layers 5a preferably contain Ni. By containing the same type of metal component as the first internal electrode layers 5a in the fired electrodes, the laminate 2, the first surface electrode 132a, and the second surface electrode 132b can be fired simultaneously when the laminate 2 is fired.

[0096] The fired electrode is formed by printing a conductive paste for Ni fired electrodes onto a dielectric sheet using screen printing or the like, followed by firing. At this time, by applying a thin layer of the conductive paste for Ni fired electrodes or reducing the dielectric component contained in the conductive paste for Ni fired electrodes, Ni particles bond together during firing, resulting in a discontinuous fired electrode. The discontinuous formation of the fired electrode means that the fired electrode is arranged discontinuously when viewed along the width direction W.

[0097] As shown in Fig. 7 , the external electrode 3 includes a base electrode layer 30 containing a conductive metal that is disposed on the laminate 2, a base plating layer 31a that is disposed so as to cover the surface of the base electrode layer 30, and a top plating layer 31b that is disposed so as to cover the surface of the base plating layer 31a. In this embodiment, the base plating layer 31a is a Ni plating layer, and the top plating layer 31b is a Sn plating layer. While Fig. 7 shows the base electrode layer 30, the base plating layer 31a, and the top plating layer 31b arranged in this order, they may also be arranged in the order of base electrode layer, top plating layer, base plating layer, and top plating layer.

[0098] The base electrode layer 30 is preferably formed by a direct plating layer. A direct plating layer is a plating layer that directly covers the surface of the laminate 2. When the base electrode layer 30 is a direct plating layer, the thickness of the external electrode 3 can be reduced in each direction, thereby making it possible to miniaturize the multilayer ceramic capacitor. The metal ratio per unit volume of the direct plating layer is preferably 99 volume percent or more. The direct plating may have two plating layers with different metal particle sizes. In this case, it is preferable that the plating layer with the larger metal particle size is arranged closer to the laminate 2 and the plating layer with the smaller metal particle size is arranged farther from the laminate 2.

[0099] The multilayer ceramic capacitor 100 according to the second embodiment can also achieve the same effects as the multilayer ceramic capacitor 1 according to the first embodiment.

[0100] Third Embodiment A multilayer ceramic capacitor 200 will be described as a third embodiment. The multilayer ceramic capacitor 200 will be described, focusing on the configuration that differs from the multilayer ceramic capacitor 1 of the first embodiment and the multilayer ceramic capacitor 100 of the second embodiment.

[0101] The multilayer ceramic capacitor 200 according to the third embodiment has the same configuration as the multilayer ceramic capacitor 100 according to the second embodiment, except for its overall shape. In the third embodiment, configurations that are the same as or similar to those in the second embodiment are denoted by the same or similar reference numerals, and detailed descriptions thereof will be omitted.

[0102] Fig. 9 is a perspective view of the multilayer ceramic capacitor 200 according to this embodiment. Fig. 10 is a cross-sectional view taken along line XX in Fig. 9. Fig. 11 is an exploded perspective view of the inner layer portion 6 according to this embodiment.

[0103] Referring to FIG. 9, in this embodiment, the length in the length direction L of the multilayer ceramic capacitor 200 is shorter than the length in the width direction W.

[0104] Referring to Figures 10 and 11, each first internal electrode layer 5a is exposed to either the first end face C1 or the second end face C2, but this is not limited to this, and each first internal electrode layer 5a may be exposed to either the first end face C1 or the second end face C2, the first side face B1, and the second side face B2.

[0105] Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments and can be embodied in various forms without departing from the spirit of the present invention. The present invention includes the following combinations.

[0106] <1> A multilayer ceramic capacitor having a laminate including inner layer portions in which dielectric layers and internal electrode layers are alternately stacked, and two outer layer portions arranged to sandwich the inner layer portions in the stacking direction and forming two main surfaces at opposite positions in the stacking direction, and external electrodes arranged on both end surfaces of the laminate in a length direction intersecting the stacking direction and connected to the internal electrode layers, wherein, when one of the two outer layer portions sandwiching the inner layer portions is divided into thirds in the stacking direction, the porosity S1 of the outermost layer located on the main surface side, the porosity S2 of an intermediate layer, and the porosity S3 of the innermost layer located on the inner layer portion side satisfy the following relational expression (1): S1>S2>S3 (1)

[0107] <2> The multilayer ceramic capacitor according to <1>, wherein both of the two outer layer portions sandwiching the inner layer portion satisfy the relational expression (1).

[0108] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the porosity S1 of the outermost layer is 1% or more and 10% or less.

[0109] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the porosity S2 of the intermediate layer is 1% or more and 5% or less.

[0110] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the porosity S3 of the innermost layer is 1% or more and 4% or less.

[0111] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the Si content in the boundary between the outer layer portion and the inner layer portion is higher than the Si content in the intermediate layer of the outer layer portion.

[0112] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein the Mg content in the boundary between the outer layer portion and the inner layer portion is higher than the Mg content in the intermediate layer of the outer layer portion.

[0113] <8> The multilayer ceramic capacitor according to any one of <1> to <7>, wherein a surface electrode is disposed on the main surface.

[0114] <9> The multilayer ceramic capacitor according to <8>, wherein at least a portion of the surface electrode is covered by a portion of the external electrode extending onto the main surface.

[0115] <10> The multilayer ceramic capacitor according to <8> or <9>, further comprising a plating layer directly connected to the internal electrode layer and the surface electrode.

[0116] 1, 100, 200 Multilayer ceramic capacitor 2 Laminate 3 External electrode 3a First external electrode 3b Second external electrode 4 Dielectric layer 4a Dielectric layer 4b Dielectric layer 5 Internal electrode layer 5a First internal electrode layer 5b Second internal electrode layer 6 Internal layer portion 7 External layer portion 7a External layer portion 7b External layer portion 7i Innermost layer 7m Intermediate layer 7o Outermost layer 8 Side gap portion 30 Base electrode layer 31 Plating layer 31a Base plating layer 31b Surface plating layer 32 Surface electrode 52 Counter electrode portion 51 Lead electrode portion 81 Side gap portion 81a Inner layer 81b Outer layer 82 Side gap portion 82a Inner layer 82b Outer layer 114a Dielectric layer 114b Dielectric layer 132a First surface electrode 132b Second surface electrode P Gap A Main surface A1 First main surface A2 Second main surface B Side surface B1 First side surface B2 Second side surface C End surface C1 First end surface C2 Second end surface E Ridge portion

Claims

1. a laminate including an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, and two outer layer portions that are arranged to sandwich the inner layer portion in the stacking direction and form two main surfaces at positions opposite to each other in the stacking direction; external electrodes disposed on both end surfaces of the laminate in a longitudinal direction intersecting the lamination direction and connected to the internal electrode layers; A multilayer ceramic capacitor having A multilayer ceramic capacitor in which, when one of the two outer layer portions sandwiching the inner layer portion is divided into three equal parts in the stacking direction, the porosity S1 of the outermost layer located on the main surface side, the porosity S2 of the intermediate layer, and the porosity S3 of the innermost layer located on the inner layer portion side satisfy the following relational expression (1): S1>S2>S3...(1)

2. 2. The multilayer ceramic capacitor according to claim 1, wherein both of the two outer layer portions sandwiching the inner layer portion satisfy the relational expression (1).

3. 3. The multilayer ceramic capacitor according to claim 1, wherein the porosity S1 of the outermost layer is 10% or less.

4. 3. The multilayer ceramic capacitor according to claim 1, wherein the intermediate layer has a porosity S2 of 5% or less.

5. 3. The multilayer ceramic capacitor according to claim 1, wherein the porosity S3 of the innermost layer is 4% or less.

6. 3. The multilayer ceramic capacitor according to claim 1, wherein a Si content in the boundary between said outer layer portion and said inner layer portion is higher than a Si content in said intermediate layer in said outer layer portion.

7. 3. The multilayer ceramic capacitor according to claim 1, wherein the Mg content in the boundary between the outer layer portion and the inner layer portion is higher than the Mg content in the intermediate layer of the outer layer portion.

8. 3. The multilayer ceramic capacitor according to claim 1, wherein a surface electrode is disposed on said main surface.

9. 9. The multilayer ceramic capacitor according to claim 8, wherein at least a portion of said surface electrodes is covered by portions of said external electrodes extending onto said main surfaces.

10. 10. The multilayer ceramic capacitor according to claim 9, further comprising a plating layer directly connecting the internal electrode layer and the surface electrode.