Semiconductor substrate manufacturing method, semiconductor substrate, and semiconductor substrate manufacturing apparatus

Abstract

A method for manufacturing a semiconductor substrate, comprising the steps of: forming, on a first surface of a first substrate, a plurality of terrace portions aligned in a first direction parallel to a horizontal surface of the first substrate, and a step portion of a predetermined height between two adjacent portions in the first direction; forming a first semiconductor layer so that a portion of the step portion is exposed; and heat-treating the first substrate on which the first semiconductor layer has been formed, thereby evaporating Si from a portion of the first substrate from a portion of the step portion exposed from the first semiconductor layer, thereby forming a buffer layer having at least one graphene layer in at least a portion between the first semiconductor layer and the first substrate.

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing a semiconductor substrate, a semiconductor substrate, and an apparatus for manufacturing a semiconductor substrate. [Background technology]

[0002] A conventional method for manufacturing semiconductor layers is known, which involves reducing the dislocation density of a III-V group nitride compound semiconductor on a buffer layer on a base substrate (see, for example, Patent Document 1).

[0003] According to the manufacturing method in Patent Document 1, an AlN layer with a thickness below the critical film thickness is formed on a SiC substrate, which is the base material substrate, then graphene is formed on the SiC substrate by heat treatment, and a GaN layer is grown on the AlN layer. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-38968 [Overview of the project] [Problems that the invention aims to solve]

[0005] According to the semiconductor layer manufacturing method of Patent Document 1, an AlN layer with a low dislocation density can be formed by forming an AlN layer with a thickness below the critical thickness on a SiC substrate. However, it is difficult to uniformly form an AlN layer with a thickness below the critical thickness on a SiC substrate, and it has been difficult to reproducibly form a uniform graphene layer over a large area of ​​1 square centimeter or more on a SiC substrate. Therefore, it has been difficult to form a GaN layer with a low dislocation density over a large area necessary for forming high-quality semiconductor devices.

[0006] Therefore, the present invention has been made in view of these points, and aims to enable the formation of high-quality semiconductor layers with a large area and low dislocation density, which was difficult with the prior art. [Means for solving the problem]

[0007] A first embodiment of the present invention provides a method for manufacturing a semiconductor substrate, comprising the steps of: forming a plurality of terrace portions on a first surface of a first substrate, which is a surface along a first direction parallel to the horizontal plane of the first substrate, and a step portion of a predetermined height located between two adjacent terrace portions in the first direction, on a first surface of a first substrate formed by cutting out a semiconductor crystal containing at least Si and C along a surface inclined with respect to a horizontal plane perpendicular to the crystal growth direction of the semiconductor crystal; forming a first semiconductor layer on the first surface of the first substrate such that a part of the step portion is exposed after the terrace portions and the step portion have been formed on the first surface of the first substrate; and heat-treating the first substrate on which the first semiconductor layer has been formed, thereby evaporating a part of the Si of the first substrate from a part of the step portion exposed from the first semiconductor layer, to form a buffer layer having at least one graphene layer in at least a part between the first semiconductor layer and the first substrate.

[0008] The semiconductor crystal is a SiC single crystal, the horizontal plane perpendicular to the crystal growth direction of the semiconductor crystal is the (0001) plane, and the first surface of the first substrate may be inclined with respect to the horizontal plane at an angle greater than 0° and less than 10°.

[0009] In the process of forming the first semiconductor layer, the first semiconductor layer may be formed by depositing a semiconductor with a thickness less than or equal to the height of the step portion on the first surface of the first substrate.

[0010] The height of the step portion may be greater than or equal to the critical film thickness of the first semiconductor layer obtained by crystal growth on the first surface of the first substrate. The height of the step portion may be between 5 nm and 200 nm.

[0011] The difference between the lattice constant of the first substrate and the lattice constant of the first semiconductor layer may be 4% or less. The process may further include forming a second semiconductor layer on the upper surface of the first semiconductor layer after the step of forming the buffer layer.

[0012] The second semiconductor layer may include at least one material selected from a single-element semiconductor material, a III-V group nitride semiconductor material, and a II-VI group compound semiconductor material.

[0013] In the process of forming the buffer layer, the first substrate may be heat-treated to evaporate at least a portion of the first semiconductor layer, thereby forming a region where the buffer layer and the second semiconductor layer are in contact, or a region where the first substrate and the second semiconductor layer are in contact.

[0014] The process may further include a step of separating at least a portion of the region including the second semiconductor layer from the first substrate after forming the second semiconductor layer, thereby forming a second substrate including the second semiconductor layer.

[0015] The step of forming the second substrate may further include the step of forming a predetermined device on the second semiconductor layer after forming the second semiconductor layer. The process may further include a step of bonding the second substrate to the third substrate after the second substrate has been formed.

[0016] In the step of forming the first semiconductor layer, the first semiconductor layer may be formed within a predetermined first temperature range higher than room temperature; in the step of forming the buffer layer, the buffer layer may be formed by heat treatment at a temperature higher than the predetermined first temperature range without returning to room temperature after forming the first semiconductor layer; and in the step of forming the second semiconductor layer, the second semiconductor layer may be formed within a predetermined second temperature range higher than room temperature without returning to room temperature after forming the buffer layer.

[0017] In a second aspect of the present invention, there is provided a semiconductor substrate including: a first substrate formed of a semiconductor crystal containing at least Si and C, the first substrate including a plurality of terrace portions which are surfaces along a first direction parallel to a horizontal plane perpendicular to a crystal growth direction of the semiconductor crystal, and step portions having a predetermined height provided between two adjacent terrace portions in the first direction; a first semiconductor layer formed with a thickness less than the height of the step portions on the plurality of terrace portions at least in a part of a surface of the first substrate where the plurality of terrace portions are formed; and a buffer layer having at least one graphene layer formed at least in a part between the first semiconductor layer and the first substrate.

[0018] The semiconductor substrate may further include a second semiconductor layer formed on a surface of the first semiconductor layer opposite to the first substrate. A region where the buffer layer and the second semiconductor layer are in contact with each other, or a region where the first substrate and the second semiconductor layer are in contact with each other may be formed.

[0019] In a third aspect of the present invention, a first surface of a first substrate formed by cutting out the semiconductor crystal along a surface inclined with respect to a horizontal plane perpendicular to the crystal growth direction of the semiconductor crystal containing at least Si and C is exposed, and a first fixing stage for fixing a second surface on the opposite side of the first surface is provided. An etching device for etching the first surface of the first substrate fixed to the first fixing stage to form a plurality of terrace portions which are surfaces along a first direction parallel to the horizontal plane of the first substrate and a step portion having a predetermined height located between two adjacent terrace portions in the first direction. A first semiconductor layer forming device for forming a first semiconductor layer on the first surface of the first substrate, an annealing device for heating the first substrate on which the first semiconductor layer is formed to evaporate a part of Si of the first substrate from a part of the step portion exposed from the first semiconductor layer to form a buffer layer having at least one graphene layer in at least a part between the first semiconductor layer and the first substrate, a first transfer path connecting a chamber for accommodating the first substrate of the first semiconductor layer forming device and a chamber for accommodating the first substrate of the annealing device, and a control unit for controlling the first fixing stage, the etching device, the first semiconductor layer forming device, and the annealing device. A substrate transfer mechanism is provided in the chamber for accommodating the first substrate of the first semiconductor layer forming device, the chamber for accommodating the first substrate of the annealing device, and the first transfer path. The substrate transfer mechanism enables the first substrate fixed to the first fixing stage to move between the chamber of the first semiconductor layer forming device and the chamber of the annealing device. The etching device is provided inside the first semiconductor layer forming device. The control unit has at least a function of controlling a step of moving the first substrate from the first fixing stage fixing the first substrate, a step of forming the plurality of terrace portions and the step portion on the first substrate, a step of forming the first semiconductor layer so that a part of the step portion is exposed, and a step of forming the buffer layer after the step of forming the first semiconductor layer. A manufacturing apparatus for a semiconductor substrate is provided.

[0020] The first semiconductor layer forming apparatus is capable of forming a second semiconductor layer on the first surface side of the first substrate after forming the buffer layer, and the control unit may further include a function to control the process of forming the second semiconductor layer on the first surface side of the first substrate after forming the buffer layer.

[0021] The apparatus comprises a second semiconductor layer forming apparatus for forming a second semiconductor layer on the first surface of the first substrate, a chamber for housing the first substrate in the second semiconductor layer forming apparatus, and a second transport path connecting the chamber for housing the first substrate in the annealing apparatus, wherein a transport mechanism is provided in the chamber for housing the first substrate in the second semiconductor layer forming apparatus, the chamber for housing the first substrate in the annealing apparatus, and the second transport path, the transport mechanism making the first substrate, which is fixed to the first fixed stage, movable between the chamber of the second semiconductor layer forming apparatus and the chamber of the annealing apparatus, and the control unit may further include a function to control the second semiconductor layer forming apparatus after the buffer layer has been formed to control the process of forming the second semiconductor layer on the first surface side of the first substrate.

[0022] The control unit further comprises a second fixing stage for fixing the side of the second semiconductor layer formed on the first substrate that is opposite to the first substrate, and the control unit may further include a function to control the process of separating at least a portion of the formed second semiconductor layer from the first substrate by controlling the first fixing stage and the second fixing stage after the second semiconductor layer has been formed on the first substrate.

[0023] The control unit may further include a function for controlling the following steps: forming the first semiconductor layer within a predetermined first temperature range higher than room temperature; forming the buffer layer by heat treatment at a temperature higher than the predetermined first temperature range without returning to room temperature after forming the first semiconductor layer; and forming the second semiconductor layer within a predetermined second temperature range higher than room temperature without returning to room temperature after forming the buffer layer. [Effects of the Invention]

[0024] The present invention offers the advantage of being able to form a high-quality semiconductor crystal layer with a large area and low dislocation density on a semiconductor base material substrate. [Brief explanation of the drawing]

[0025] [Figure 1] An example of the manufacturing flow of a semiconductor substrate according to this embodiment is shown. [Figure 2] An example of the first substrate 100 according to this embodiment is shown. [Figure 3] An example of the first substrate 100 according to this embodiment being subjected to etching is shown. [Figure 4] This example shows a first semiconductor layer 120 formed on the surface of the first substrate 100 in which the terrace portion 102 and step portion 110 are formed. [Figure 5] Figure 4 is a schematic diagram of an enlarged cross-section of the surface of the first substrate 100 on which the first semiconductor layer 120 is formed. [Figure 6] This example shows a seed layer growth substrate 140 according to this embodiment subjected to high-temperature heat treatment in a high-temperature heating furnace 416. [Figure 7] This example shows a case in which the thickness of the first semiconductor layer 120 is grown with respect to the height h of the step portion 110 according to this embodiment. [Figure 8] This figure schematically shows the state of the seed layer growth substrate 140 after high-temperature heat treatment according to this embodiment. [Figure 9] Figure 8 schematically shows the surface condition of the seed layer growth substrate 140 after high-temperature heat treatment. [Figure 10] This example shows a case in which a second semiconductor layer 160 is crystallized on the upper surface of the intermediate layer 150 according to this embodiment. [Figure 11] The first example of a high-speed electron diffraction pattern of the formed first semiconductor layer 120 is shown. [Figure 12] A second example of the high-speed electron diffraction pattern of the formed first semiconductor layer 120 is shown. [Figure 13] An example of the Raman scattering spectrum of the surface of the formed intermediate layer 150 is shown. [Figure 14]An example of a surface image obtained by observing the surface of the formed intermediate layer 150 with an atomic force microscope is shown. [Figure 15] An example of the symmetrical reflection X-ray rocking curve of the formed second semiconductor layer 160 is shown. [Figure 16] An example of an asymmetric reflection X-ray rocking curve from the formed second semiconductor layer 160 to another surface is shown. [Figure 17] The Raman scattering spectrum of the formed second semiconductor layer 160 is shown. [Figure 18] An example of the configuration of the composite material substrate 200 according to this embodiment is shown. [Figure 19] The configuration examples of the first substrate 202 and the second substrate 204 according to this embodiment are shown. [Figure 20(a)] This example shows a configuration in which the second semiconductor layer 160 according to this embodiment is separated from the first substrate 100. [Figure 20(b)] This diagram shows an example of the configuration after the second semiconductor layer 160 according to this embodiment has been separated from the first substrate 100. [Figure 21(a)] This example shows a reinforcing substrate 350 bonded to the upper surface of the second semiconductor layer 160 according to this embodiment. [Figure 21(b)] A first example of the second semiconductor substrate 360 ​​according to this embodiment is shown. [Figure 22] A second example of the second semiconductor substrate 360 ​​according to this embodiment is shown. [Figure 23] An example configuration of the first manufacturing apparatus 400 according to this embodiment is shown. [Figure 24] This shows an example of the configuration of the second manufacturing apparatus 450 according to this embodiment. [Modes for carrying out the invention]

[0026] <An example of a semiconductor substrate manufacturing flow> Figure 1 shows an example of the semiconductor substrate manufacturing flow according to this embodiment. Figures 2 to 10 show the process by which the semiconductor substrate is formed according to this manufacturing flow.

[0027] First, a first substrate 100, which will serve as the base material, is prepared (S10). Figure 2 shows an example of the first substrate 100 according to this embodiment. The first substrate 100 is a substrate formed from a semiconductor crystal containing at least Si and C. The semiconductor crystal is preferably a single crystal of SiC. In this embodiment, an example in which a SiC single crystal substrate is used as an example of the first substrate 100 will be described.

[0028] The first substrate 100 can be a 4H-SiC single crystal substrate or a 6H-SiC single crystal substrate. The first substrate 100 is a substrate formed by cutting out a semiconductor crystal from a plane inclined with respect to a horizontal plane perpendicular to the crystal growth direction of the semiconductor crystal. Here, the horizontal plane perpendicular to the crystal growth direction of the semiconductor crystal is the (0001) plane. Thus, the first surface 101 of the first substrate 100 has an orientation (sometimes called an off-angle) that is inclined with respect to the exact (0001) plane. Here, the inclination angle with respect to the (0001) plane is θ. The first surface 101 of the first substrate 100 is, for example, the Si plane. The first surface 101 can also be the C plane opposite to the Si plane.

[0029] Next, a plurality of flat portions (referred to as terrace portions in this embodiment) and one or more wall portions (referred to as step portions in this embodiment) are formed on the first substrate 100 (S11). For example, the first substrate 100 is placed in a furnace capable of heating the substrate to a high temperature in a hydrogen gas atmosphere, and the first surface 101 of the first substrate 100 is etched under a hydrogen (H2) atmosphere. For etching the first surface 101, it is desirable to use an etching apparatus that can set the substrate temperature to a temperature suitable for substrate surface treatment. The etching apparatus may be the same apparatus as the furnace capable of heating the substrate.

[0030] The etching apparatus can, for example, raise the temperature of the first substrate 100 to 1000°C or higher. Furthermore, the etching apparatus can adjust the hydrogen gas pressure to a pressure suitable for substrate surface treatment; for example, the hydrogen gas atmosphere can be set to 1 atmosphere. In addition to a hydrogen gas atmosphere, a mixed gas atmosphere of hydrogen gas and another gas (e.g., argon (Ar) gas, ammonia (NH3) gas, etc.) may be used for etching the first surface 101 of the first substrate 100.

[0031] Figure 3 shows an example of the first substrate 100 according to this embodiment after etching. Figure 3 is a schematic diagram of a substrate cross-section, which is an enlarged view of the surface of the first substrate 100 after etching.

[0032] Since the first substrate 100 is formed by crystal growth with the (0001) plane as the horizontal plane of the crystal, etching the first surface 101, which is inclined with respect to the (0001) plane, processes the surface of the first substrate 100 to form a plane parallel to the (0001) plane. Because the first surface 101 of the first substrate 100 is inclined with respect to the (0001) plane before etching, such etching forms steps on the surface of the first substrate 100 that are height-controlled to a predetermined height.

[0033] Figure 3 shows an example in which a plurality of terrace portions 102 are formed along a first direction parallel to the (0001) plane of the first substrate 100, and a step portion 110 of a predetermined height h is formed between two adjacent terrace portions 102 in the first direction. In Figure 3, the width of the terrace portion 102 is w. The step height h can be controlled using the off-angle of the first substrate 100, off-direction, etching temperature, hydrogen gas flow rate, etching temperature, etching pressure, heating rate, and etching time as control parameters.

[0034] The step height h is thought to be determined by the minimum surface free energy of the first substrate 100, which depends on these parameters. In general terms, the surface morphology of the step portion 110 with step height h and the terrace portion 102 with width w that surrounds the step portion 110 is determined by minimizing the step formation energy and the surface free energy due to the interaction between steps.

[0035] In the etching process of the first substrate 100, for example, the etching process is controlled so that the step height h is an integer multiple of the lattice constant in the c-axis direction (the direction perpendicular to the substrate surface (0001) plane) of the SiC single crystal substrate. The lattice constants in the c-axis direction of the 4H-SiC substrate and the 6H-SiC substrate are 1.0 nm and 1.5 nm, respectively. The specific value of the step height h will be described later.

[0036] From the viewpoint of forming a uniform, high-quality semiconductor layer on a large-area substrate, it is desirable to control the in-plane variation of the first substrate 100 in terms of step height h to approximately ±10-20% of the center value of the step height h. As an example, by controlling the etching operation of the first substrate 100, the center value of the in-plane step height h of the first substrate 100 can be set to 60 nm, and the in-plane variation to ±10 nm.

[0037] The terrace width w is determined by the off-angle θ of the first substrate 100. The off-angle θ can be appropriately determined depending on the growth conditions of the first substrate 100. For the off-angle θ of the first surface 101 of the first substrate 100, an angle range greater than 0° and less than 10° is practical. The off-angle θ may also be in the range of 2° < θ < 6°. For example, the off-angle θ is 4°.

[0038] After forming terraces 102 and steps 110 on the first surface 101 of the first substrate 100, a first semiconductor layer 120 is formed so that a part of the steps 110 is exposed (S12). Figure 4 shows an example in which the first semiconductor layer 120 is formed on the surface of the first substrate 100 on which the terraces 102 and steps 110 are formed according to this embodiment. Figure 5 is a schematic diagram of a substrate cross-section, which is an enlarged view of the surface of the first substrate 100 on which the first semiconductor layer 120 of Figure 4 is formed. The substrate on which the first semiconductor layer 120 is formed is called a seed layer growth substrate 140.

[0039] The first semiconductor layer 120 is grown, for example, by the MOCVD method. In order to suppress the generation of misfit dislocations and form a high-quality semiconductor layer (semiconductor single crystal layer), it is desirable to select a semiconductor material for the first semiconductor layer 120 that has a small difference in lattice constant from that of the first substrate 100. For example, the difference between the lattice constant of the first substrate 100 and the lattice constant of the first semiconductor layer 120 can be 4% or less. It is even more desirable for the difference in lattice constants to be 2% or less.

[0040] When the first substrate 100 is a SiC single crystal substrate, aluminum nitride (AlN) is a preferred material for the first semiconductor layer 120. The difference in lattice constants (lattice mismatch rate) between SiC and AlN is small, at 1.27%, which helps to suppress the generation of misfit dislocations as much as possible. In this embodiment, an example using AlN as an example of the first semiconductor layer 120 will be described.

[0041] The thickness d of the first semiconductor layer 120 is preferably less than or equal to the step height h of the first substrate 100. More preferably, as shown in Figure 5, the thickness d of the first semiconductor layer 120 is smaller than the step height h. By making the thickness d of the first semiconductor layer 120 smaller than the step height h, a part of the step portion 110 can be exposed after the formation of the first semiconductor layer 120.

[0042] For example, the first semiconductor layer 120 is formed by depositing the material for the first semiconductor layer 120, with a thickness of less than or equal to the height h of the step portion 110, onto the surface of the first substrate 100 where the terrace portion 102 and the step portion 110 are formed. In this case, nuclei of the semiconductor material are formed at the edges or on the plane of the terrace portion 102, and crystal growth proceeds in two or three dimensions so that the entire surface of the terrace portion 102 is covered with the semiconductor material.

[0043] Here, misfit dislocations due to lattice mismatch may form parallel to the growth interface. However, because the lattice constant mismatch between SiC and AlN is small, the stress applied to the AlN crystal growth layer is small, and the growth of dislocations that penetrate the upper surface of the crystal growth layer is suppressed. As a result, a good first semiconductor layer 120 with few defects can be formed.

[0044] In reality, the step height h and the thickness d of the first semiconductor layer 120 may vary within the plane of the first substrate 100. Therefore, taking such variations into consideration, the growth conditions for the first semiconductor layer 120 can be determined so that the thickness d of the first semiconductor layer 120 is less than or equal to the step height h.

[0045] Even when the lattice constant mismatch rate is several percent, the dislocations associated with the lattice mismatch at the growth temperature of the first semiconductor layer 120 are mostly misfit dislocations present at the interface between the first substrate 100 and the first semiconductor layer 120. Such dislocations are not through-dislocations that degrade the crystallinity of the grown layer, such as crystal defects reaching the upper part of the first semiconductor layer 120. Therefore, even when the thickness of the first semiconductor layer 120 is grown to a thickness greater than the critical film thickness, the c-axis orientation and a-axis orientation of the first semiconductor layer 120 are appropriately controlled, and the dislocation density is 10 2 cm -2 It can be formed as a single crystal with the following extremely low dislocation density.

[0046] Here, the step height h of the first semiconductor layer 120 can be designed based on the growth conditions of the first semiconductor layer 120 formed on the first substrate 100. When forming the first semiconductor layer 120 by an MOCVD method suitable for practical production, the height of the step portion 110 is set to be, for example, greater than or equal to the critical film thickness of the first semiconductor layer 120 obtained by crystal growth on the first substrate 100, taking into consideration conditions such as the growth rate of the semiconductor layer by the MOCVD method.

[0047] Here, when growing AlN on a SiC single crystal substrate, where the lattice constant difference with SiC is small, the critical film thickness is approximately 3 nm. Therefore, the height h of the step portion 110 is set to a value greater than approximately 3 nm, in the range of 5 nm to 200 nm. More preferably, the height h of the step portion 110 may be set to a range of 30 nm to 100 nm, which facilitates the growth control of the first semiconductor layer 120.

[0048] Next, the first substrate 100 on which the first semiconductor layer 120 is formed is heat-treated to form a buffer layer 130 (S13). Figure 6 shows an example in which the seed layer growth substrate 140 according to this embodiment is subjected to high-temperature heat treatment in a high-temperature heating furnace 416. The high-temperature heating furnace 416 performs high-temperature heat treatment on the seed layer growth substrate 140 in an inert gas atmosphere such as nitrogen (N2) gas or argon (Ar) gas. The high-temperature heating furnace 416 may be a different furnace from the furnace on which the first semiconductor layer 120 is grown, or it may be the same furnace on which the first semiconductor layer 120 is grown, provided that it is equipped with a heating device that can raise the temperature to a predetermined high-temperature region.

[0049] The temperature of the high-temperature heat treatment can be higher than the temperature at which the first semiconductor layer 120 is grown. For example, if the first semiconductor layer 120 is AlN, the growth temperature of AlN can be 1000°C to 1200°C, so the temperature of the high-temperature heat treatment can be in the range of 1300°C to 2000°C.

[0050] Such high-temperature heat treatment thermally decomposes SiC on the surface of the SiC single-crystal substrate to desorb Si. For example, when a SiC single-crystal substrate is used as the first substrate 100, Si evaporates from the step portion 110 exposed from the first semiconductor layer 120 on the surface of the first substrate 100. After SiC is thermally decomposed and Si is desorbed, C remains between the first semiconductor layer 120 and the surface of the first substrate 100. The C remaining between the first semiconductor layer 120 and the surface of the first substrate 100 forms two-dimensional bonds with each other and becomes at least one layer of graphene, for example, several layers of graphene layers.

[0051] As described above, the high-temperature heat treatment evaporates a part of Si of the first substrate 100 from a part of the step portion 110 exposed from the first semiconductor layer 120, and forms a buffer layer 130 having at least one layer of graphene in at least a part between the first semiconductor layer 120 and the first substrate 100. In other words, by exposing a part of the step portion 110 from the first semiconductor layer 120, the thermal decomposition elements of the first substrate 100 can be efficiently evaporated from the exposed step portion 110. When the first substrate 100 is a SiC single-crystal substrate, the element that is thermally decomposed and evaporated is Si.

[0052] Note that since the heating temperature of the above-described high-temperature heat treatment is higher than the temperature at which the first semiconductor layer 120 grows, the surface of the first semiconductor layer 120 may also be thermally decomposed during the high-temperature heat treatment process, reducing the thickness of the first semiconductor layer 120. FIG. 7 shows an example in which the first semiconductor layer 120 is grown while changing the thickness of the first semiconductor layer 120 with respect to the height h of the step portion 110 according to the present embodiment. FIG. 7 shows three examples in which the thickness of the first semiconductor layer 120 is small (the thickness of the first semiconductor layer 120 = d1 < h), the thickness of the first semiconductor layer 120 is equal (the thickness of the first semiconductor layer 120 = d2 = h), and the thickness of the first semiconductor layer 120 is large (the thickness of the first semiconductor layer 120 = d3 > h) with respect to the height h of the step portion 110.

[0053] In the plane of the first substrate 100, when the thickness of the first semiconductor layer 120 is smaller than the step height h (h > d1), as described above, a graphene layer can be formed between the first substrate 100 and the first semiconductor layer 120 by high-temperature heat treatment. Further, when the thickness of the first semiconductor layer 120 is equal to the step height h (h = d2), while evaporating the surface of the first semiconductor layer 120 by high-temperature heat treatment, Si is evaporated to form a graphene layer between the first substrate 100 and the first semiconductor layer 120.

[0054] On the other hand, when the thickness of the first semiconductor layer 120 is larger than the step height h (h < d3), since the step portion 110 is covered with the first semiconductor layer 120, at the initial stage of the high-temperature heat treatment process, Si does not evaporate from the step portion 110 and a graphene layer is not formed. However, since the thickness of the first semiconductor layer 120 decreases by high-temperature heat treatment, the high-temperature heat treatment is performed so that the step portion 110 is exposed, and by further continuing the high-temperature heat treatment, Si can be evaporated from the exposed step portion 110.

[0055] Therefore, even if there is a region of the first semiconductor layer 120 with h < d3 in the plane of the first substrate 100 before the high-temperature heat treatment, a graphene layer can be formed between the first substrate 100 and the first semiconductor layer 120 by setting the conditions of the high-temperature heat treatment. In other words, in S12, the first semiconductor layer 120 may be formed so as to cover the step portion 110 on the surface of the first substrate 100 where the terrace portion 102 and the step portion 110 are formed. In this case, in S13, the high-temperature heat treatment is performed so that a part of the step portion 110 is exposed, and by further continuing the high-temperature heat treatment, a graphene layer can be formed.

[0056] FIG. 8 is a diagram schematically showing a state after performing high-temperature heat treatment on the seed layer growth substrate 140 according to the present embodiment. Note that the seed layer growth substrate 140 after the high-temperature heat treatment may be referred to as a crystal growth substrate 142. The first semiconductor layer 120 may have a reduced layer thickness by being heated at a temperature higher than the growth temperature of the first semiconductor layer 120.

[0057] In this embodiment, the first semiconductor layer 120 with reduced thickness may be referred to as the residual seed layer 122. In other words, the residual seed layer 122 refers to the first semiconductor layer 120 formed on the first substrate 100. Furthermore, a buffer layer 130 is formed at the interface between the first substrate 100 and the first semiconductor layer 120 by the breaking of bonds between the constituent atoms of the substrate on the surface of the first substrate 100, causing some of the constituent atoms to evaporate.

[0058] For example, if the first substrate 100 is a SiC single crystal substrate and the first semiconductor layer 120 is AlN, the above high-temperature heat treatment reduces the thickness of the AlN first semiconductor layer 120, resulting in a residual AlN seed layer 122. At the interface between the AlN first semiconductor layer 120 and the first substrate 100, which is a SiC single crystal substrate, the SiC is thermally decomposed and the Si evaporates, forming a buffer layer 130 (graphene layer) having graphene in which C is bonded two-dimensionally. Here, the thickness of the buffer layer 130 is the thickness of one layer of graphene (0.67 nm) or the thickness of multiple layers of graphene (0.67 nm × n, where n is an integer).

[0059] Figure 9 schematically shows the surface state of the seed layer growth substrate 140 after the high-temperature heat treatment shown in Figure 8. In Figure 9, the first semiconductor layer 120, which is thinner than the step height h, has its layer thickness reduced by the high-temperature heat treatment, becoming a residual seed layer 122.

[0060] Furthermore, a buffer layer 130 is formed at the interface between the first substrate 100 and the first semiconductor layer 120. The buffer layer 130 may be, for example, epitaxial graphene or turbo stacked graphene. In this embodiment, the residual seed layer 122 formed by high-temperature heat treatment and the buffer layer 130 may be referred to as an intermediate layer 150 for growing a high-quality semiconductor layer (semiconductor single crystal layer) on the residual seed layer 122.

[0061] Next, a second semiconductor layer 160 is formed on the upper surface of the first semiconductor layer 120 (S14). FIG. 10 shows an example in which the second semiconductor layer 160 is crystal-grown on the upper surface of the intermediate layer 150 according to the present embodiment. The second semiconductor layer 160 is preferably a single-crystal semiconductor layer.

[0062] For the crystal growth of the second semiconductor layer 160, from the viewpoints of increasing the wafer size and efficient production, it is desirable to use a method such as metalorganic chemical vapor deposition (MOCVD) or sputtering. When the residual seed layer 122 is AlN, the material of the second semiconductor layer 160 includes at least one material among single-element semiconductor materials, III-V nitride semiconductor materials, and II-VI compound semiconductor materials. The second semiconductor layer 160 includes, for example, Si, Al x Ga 1-x N, In x Ga 1-x N, and Al x Ga y In 1-x-y N (0 ≤ x, y ≤ 1). The thickness of the second semiconductor layer 160 can be grown to a thickness according to the purpose as long as it is equal to or greater than the thickness of the basic lattice of the crystal of the material.

[0063] In the crystal growth of the second semiconductor layer 160, it is desirable to perform crystal growth with an extremely low dislocation density by performing orientation control in the c-axis direction and the a-axis direction. Here, the extremely low dislocation density refers to a dislocation density of 10 2 cm -2 or less as evaluated by an evaluation method such as potassium hydroxide (KOH) etching or a transmission electron microscope.

[0064] When the residual seed layer 122 is AlN (when the first substrate 100 is SiC and the intermediate layer 150 is an AlN layer / graphene layer), Si is a preferred example of the second semiconductor layer 160 as a single-element semiconductor. Further, as the III-V compound semiconductor, the second semiconductor layer 160 preferably includes III-V nitride semiconductors such as hexagonal compound semiconductors, for example, GaN, InN, and mixed crystals of AlGaN, InGaN, and InAlN.

[0065] Si allows for an atomic arrangement that approximately matches the lattice of the hexagonal c-plane, and its orientation can be controlled in both the c-axis and a-axis directions. However, even when using such a second semiconductor layer 160, a difference in the lattice constant and / or the coefficient of thermal expansion may occur between the second semiconductor layer 160 and the residual seed layer 122. Such a difference in the lattice constant and / or the coefficient of thermal expansion can generate stress and cause crystal strain.

[0066] However, the thickness of the residual seed layer 122 is thinner than the height h of the step portion 110 on the surface of the first substrate 100, for example, at most about 100 nm. Therefore, even if a difference in lattice constant and / or thermal expansion coefficient occurs between the second semiconductor layer 160 and the residual seed layer 122, the stress-induced crystal strain is absorbed by the buffer layer 130 or the intermediate layer 150, and dislocation generation in the second semiconductor layer 160 can be suppressed.

[0067] As a result, a second semiconductor layer 160 with an extremely low dislocation density can be grown. In other words, a first semiconductor substrate 300 having a second semiconductor layer 160 with an extremely low dislocation density can be fabricated. The second semiconductor layer 160 of such a first semiconductor substrate 300 can be used as a semiconductor layer for fabricating a predetermined device.

[0068] Furthermore, the second semiconductor layer 160 may be grown after a portion of the residual seed layer 122 on the first substrate 100 has been evaporated or removed. In this case, a region where the buffer layer 130 and the second semiconductor layer are in contact, or a region where the first substrate 100 and the second semiconductor layer 160 are in contact, may be formed in the region where a portion of the residual seed layer 122 has been evaporated or removed.

[0069] As described above, according to the semiconductor substrate manufacturing flow of this embodiment, 1 cm 2 Dislocation density is 10 in an area exceeding 4 cm -2A smaller, higher-quality second semiconductor layer 160 can be formed on the first substrate 100. While the fabricated first semiconductor substrate 300 can be provided, it can also be provided as a substrate for fabricating a high-quality second semiconductor layer 160 at the seed layer growth substrate 140 stage.

[0070] Furthermore, a substrate with predetermined devices formed on the second semiconductor layer 160 can be provided after further forming predetermined devices within and on the second semiconductor layer 160. Street lines may be formed on the substrate with predetermined devices to separate the predetermined device regions. In the regions of the street lines, the second semiconductor layer 160 and the intermediate layer 150 may be removed to expose the surface of the first substrate 100.

[0071] <Verification Experiment 1> The manufacturing flow of the semiconductor substrate according to the present embodiment described above was actually carried out and experimentally verified that a high-quality second semiconductor layer 160 with an extremely low transition density could be obtained. The first substrate 100 was a SiC single crystal substrate. The substrate size of the first substrate 100 was 10 mm × 10 mm × 350 μm. The off-angle of the first surface 101 of the first substrate 100 was 4° in the (11-20) direction.

[0072] Next, the step height h on the surface of the first substrate 100 was controlled from 50 nm to 60 nm by hydrogen etching to form terrace portions 102 and step portions 110. Then, single-crystal AlN was grown on the surface of the first substrate 100 as a single-domain first semiconductor layer 120. The thickness of the first semiconductor layer 120 was set to 40 nm. Here, the thickness of the first semiconductor layer 120 is greater than or equal to the critical film thickness.

[0073] Next, a high-temperature heat treatment was performed in a nitrogen atmosphere at 1650°C, 500 Torr, and for 20 minutes using a high-temperature heat treatment apparatus. This high-temperature heat treatment confirmed the formation of an AlN layer / graphene layer on the first substrate 100. Here, the AlN layer corresponds to the residual seed layer 122, and the graphene layer corresponds to the buffer layer 130. In other words, an intermediate layer 150 (AlN layer / graphene layer) is formed on the SiC single crystal substrate.

[0074] Figure 11 shows a first example of a high-speed electron diffraction pattern of the first semiconductor layer 120 formed in this manner. Figure 11(a) shows an example of a high-speed electron diffraction (RHEED) pattern of the first semiconductor layer 120 before high-temperature heat treatment. Figure 11(b) shows an example of a high-speed electron diffraction pattern of the surface of the intermediate layer 150 after high-temperature heat treatment.

[0075] Figures 11(a) and (b) show the diffraction patterns when the electron beam direction is parallel to [10-10]. In the high-speed electron diffraction pattern of Figure 11(a), streak lines with spacing corresponding to the lattice constant of AlN were observed, as shown in the figure. From this, it was confirmed that a single-crystal AlN layer was formed as the first semiconductor layer 120 on the SiC single-crystal substrate.

[0076] The high-speed electron diffraction pattern in Figure 11(b) shows streak lines with spacings corresponding to the lattice constants of AlN and graphene, as shown in the figure. This confirms that a single-crystal AlN layer remains on the SiC single-crystal substrate as a residual seed layer 122, and that a graphene layer has been formed as a buffer layer 130.

[0077] Figure 12 shows a second example of the high-speed electron diffraction pattern of the formed first semiconductor layer 120. Figure 12(a) shows a second example of the high-speed electron diffraction pattern of the first semiconductor layer 120 before high-temperature heat treatment, and Figure 12(b) shows a second example of the high-speed electron diffraction pattern of the surface of the intermediate layer 150 formed after high-temperature heat treatment. Note that Figures 12(a) and 12(b) are diffraction patterns when the direction of the electron beam is parallel to [11-20].

[0078] The high-speed electron diffraction pattern in Figure 12(a) shows streak lines at intervals corresponding to the lattice constant of AlN, as shown in the figure. This confirms that a single-crystal AlN layer has been formed as the first semiconductor layer 120 on the SiC single-crystal substrate. The high-speed electron diffraction pattern in Figure 12(b) shows streak lines at intervals corresponding to the lattice constants of AlN and graphene, as shown in the figure. This confirms that a single-crystal AlN layer remains on the SiC single-crystal substrate as a residual seed layer 122, and that a graphene layer has been formed as a buffer layer 130.

[0079] Figure 13 shows an example of the Raman scattering spectrum of the surface of the intermediate layer 150 formed by high-temperature heat treatment. As shown in Figure 13, the G band was observed in the left peak of the Raman scattering spectrum, and the G' band was observed in the right peak. From the intensity ratio of the G band and the G' band, it was confirmed that a buffer layer 130 composed of a 2-atom layer of graphene was formed between the first substrate 100 and the residual seed layer 122.

[0080] Figure 14 shows an example of a surface image of the formed intermediate layer 150 observed with an atomic force microscope (AFM). Figure 14 shows the results of observing the surface of the intermediate layer 150 formed after high-temperature heat treatment. The scan area of ​​the atomic force microscope is 1000 nm × 1000 nm.

[0081] As shown in Figure 14, the peak-to-valley difference (peak-to-valley value) of the surface image obtained by atomic force microscopy was confirmed to be 3.8 nm. In other words, it was confirmed that the surface of the residual seed layer 122, which forms the surface of the intermediate layer 150, is atomically flat. Furthermore, it was confirmed that no anomalies indicating the presence of dislocations or domains were observed in the AFM image.

[0082] A GaN layer was grown on the upper surface of the intermediate layer 150 fabricated as described above, as the second semiconductor layer 160, by the MOCVD method. The thickness of the GaN layer is 1.0 μm. Figure 15 shows an example of the symmetric reflection X-ray rocking curve of the second semiconductor layer 160 formed in this way. Figure 15 is the symmetric reflection X-ray rocking curve of the second semiconductor layer 160 with respect to the

[0002] plane.

[0083] Figure 16 also shows an example of the asymmetric reflection X-ray rocking curve from the formed second semiconductor layer 160 to other planes. Figures 16(a) to (d) are the asymmetric reflection X-ray rocking curves for the [10-11] plane, the [10-12] plane, the [10-13] plane, and the [30-32] plane, respectively.

[0084] The formed second semiconductor layer 160 is a thin GaN layer of 1 μm, which is susceptible to the influence of the substrate. However, the symmetric reflection X-ray rocking curve shown in Figure 15 and the asymmetric reflection X-ray rocking curve shown in Figure 16 were obtained. Furthermore, a small FWHM value of 350 arcsec (350 / 3600 = 0.0972 [deg]) was obtained for both the rocking curves shown in Figures 15 and 16. Note that the FWHM value of the rocking curve decreases as the crystal quality of the sample increases.

[0085] The FWHM value of 350 arcsec for the symmetric and asymmetric X-ray rocking curves obtained in the verification experiment is smaller than the FWHM value of rocking curves of GaN single-crystal grown films known to date. Therefore, it can be said that a higher quality second semiconductor layer 160 has been formed than conventionally. Furthermore, with conventional techniques, it was difficult to obtain small FWHM values ​​for both symmetric and asymmetric X-ray rocking curves. In contrast, the formed second semiconductor layer 160 was able to obtain small FWHM values ​​for both symmetric and asymmetric X-ray rocking curves, thus verifying that the crystal quality of the second semiconductor layer 160 can be significantly improved compared to conventional techniques.

[0086] Figure 17 shows the Raman scattering spectrum of the formed second semiconductor layer 160. As shown in Figure 17, the peak position of the GaN-LO phonon mode in the Raman scattering spectrum indicates that there is almost no interfacial stress acting on the crystal-grown second semiconductor layer 160.

[0087] Furthermore, a sample was prepared by growing a 1.0 μm thick AlN layer, identical to the residual seed layer 122 used in the verification experiment, on the surface of the intermediate layer 150. The crystallinity of the prepared sample was measured in the same way by analyzing its Raman scattering spectrum. As a result, no peak shift of AlN due to interfacial stress was observed in the Raman scattering spectrum. Therefore, it can be concluded that there is almost no interfacial stress acting on the residual seed layer 122.

[0088] <Verification Experiment 2> In addition to the verification experiment 1 described above, verification experiment 2 was conducted with the step height h reduced to 1 / 3. In verification experiment 2, a SiC single crystal substrate was prepared as the first substrate 100, and its surface was treated by etching to form a step height h of 20 nm. Two samples were then prepared, in which single crystal AlN layers with thicknesses of 5 nm and 10 nm were formed on the surface of the first substrate 100 as the first semiconductor layer 120. In both samples, the thickness of the first semiconductor layer 120 was set to a value smaller than the step height h of the first substrate 100.

[0089] After forming the first semiconductor layer 120, high-temperature heat treatment was performed (1650°C, nitrogen atmosphere, the same as in Verification Experiment 1). Then, as described in Verification Experiment 1, it was confirmed that a stacked structure of residual AlN layer / graphene layer formed as an intermediate layer 150 on the upper surface of the first semiconductor layer 120 by the high-temperature heat treatment.

[0090] Next, a GaN layer was formed as the second semiconductor layer 160 on the upper surface of the intermediate layer 150 with a thickness of 560 nm using the MOCVD method. The crystal quality of the second semiconductor layer 160 of the fabricated sample was then evaluated using the same method as in verification experiment 1.

[0091] The FWHM values ​​of the X-ray rocking curves for symmetric and asymmetric reflections were small, both below 350 arcsec, similar to verification experiment 1. This verified that a high-quality second semiconductor layer 160 can be formed even when the step height h of the first substrate 100 is controlled within a relatively small range. Furthermore, it was confirmed that, similar to verification experiment 1, no peak shift due to interfacial stress was observed in the Raman scattering spectrum of the second semiconductor layer 160.

[0092] The results of Verification Experiments 1 and 2 demonstrate that a second semiconductor layer 160 of higher quality than that of the conventional technology can be formed on the upper surface of the first substrate 100. Furthermore, the results of the above verification experiments show that even when considering the crystal orientation of the SiC single crystal substrate after crystal growth of the second semiconductor layer 160 and fluctuations in the crystal axis of the second semiconductor layer 160 which depend on the thickness of the second semiconductor layer 160, the crystal orientation is controlled and the dislocation density is extremely low (dislocation density 10 2 cm -2 This demonstrates that a second semiconductor layer 160 can be formed on the upper surface of the first substrate 100 as a high-quality single-crystal semiconductor layer (as described below).

[0093] According to the semiconductor substrate manufacturing flow of this embodiment described above, a buffer layer 130 can be formed between the first substrate 100 and the first semiconductor layer 120 by forming a first semiconductor layer 120 that covers the upper surface of the first substrate 100 and then performing a high-temperature heat treatment. Here, by exposing the end of the step portion 110 formed on the first substrate 100 from the first semiconductor layer 120, some of the material atoms forming the first substrate 100 can be efficiently evaporated (sublimated) from the end of the step portion 110. As a result, a uniform buffer layer 130 can be formed over the entire surface of the first substrate 100, without covalent bonds with the surface of the first substrate 100.

[0094] Furthermore, the intermediate layer 150 has a laminated structure of the buffer layer 130 and the residual seed layer 122 of the thin film, and is a layer for crystal growth of the second semiconductor layer 160 on its upper surface. With this intermediate layer 150, even if there is a difference in lattice constant and / or thermal expansion coefficient between the first substrate 100 and the second semiconductor layer 160, the buffer layer 130 can mitigate the difference in lattice constant and / or thermal expansion coefficient.

[0095] Therefore, a high-quality second semiconductor layer 160 with an extremely low dislocation density can be formed over the entire upper surface of the first substrate 100. In other words, a high-quality second semiconductor layer 160 with an extremely low dislocation density and a predetermined composition, in which the c-axis orientation and a-axis orientation are appropriately controlled, can be obtained on the upper surface of the first substrate 100.

[0096] Furthermore, the step formed on the surface of the first substrate 100 and the first semiconductor layer 120 only need to be formed to the extent that the edge of the step portion 110 is exposed from the first semiconductor layer 120. For example, a step of average height h is formed on the surface of the first substrate 100, and the first semiconductor layer 120 is formed with a layer thickness of less than or equal to the average height h. In this way, the first semiconductor layer 120 does not require precise crystal growth control at the atomic layer level, and highly efficient crystal growth by the MOCVD method, which has the high productivity required for practical application, can be used. This also makes it possible to increase the diameter of the first substrate 100.

[0097] Furthermore, generally, the cause of reduced crystal quality in semiconductor layers is the interfacial stress generated due to mismatches in lattice constants and thermal expansion coefficients between the crystal growth surface and the semiconductor layer in which the crystal is grown. According to the semiconductor substrate manufacturing flow of this embodiment, the buffer layer 130 mitigates the mismatches in lattice constants and thermal expansion coefficients between the second semiconductor layer 160 growing on the upper surface of the residual seed layer 122 and the residual seed layer 122, thereby suppressing the generation of interfacial stress. Therefore, by using the buffer layer 130 instead of the low-temperature buffer layer in conventional two-stage growth methods, a higher quality second semiconductor layer 160 can be obtained.

[0098] As described above, by using the high-quality second semiconductor layer 160 formed in this embodiment, it is possible to form a semiconductor device with significantly improved characteristics and quality compared to conventional semiconductor devices. Furthermore, the range of semiconductors that can be used as the second semiconductor layer 160 is limited to single-element semiconductors, III-V compound semiconductors, II-IV compound semiconductors, etc., and it can be widely applied as a material for forming semiconductor devices.

[0099] In particular, III-V nitride semiconductor mixed crystals generally have high-density edge dislocations and through dislocations due to mismatches in lattice constants and thermal expansion coefficients. Since these dislocations (lattice defects) act as donors, III-V nitride semiconductor mixed crystals exhibit n-type electrical properties with a high residual electron concentration. For this reason, it has been difficult to control the p-type conductivity of III-V nitride semiconductor mixed crystals even by adding acceptor impurities. However, in this embodiment, the second semiconductor layer 160 can control the density of crystal defects to a low level, so even when formed as a III-V nitride semiconductor mixed crystal, the p-type conductivity can be controlled.

[0100] <Variation> In the above embodiment, the single-crystal SiC may be doped with impurity elements other than Si and C. Furthermore, although the area of ​​a high-quality semiconductor layer is considered to be limited, the first substrate may be polycrystalline SiC. In this case, elements other than Si and C, such as O, may be included.

[0101] In the above embodiment, an example using the MOCVD method as a means for growing the first semiconductor layer 120 has been described, but the invention is not limited to this. Other methods such as molecular beam epitaxy (MBE) and laser ablation may be used to grow the first semiconductor layer 120. Even if the first semiconductor layer 120 is grown by such a method, a high-quality second semiconductor layer 160 can be formed on the upper surface of the intermediate layer 150.

[0102] Furthermore, although the first substrate 100 has been described as a single-crystal substrate formed from a single material in this embodiment, it is not limited to this. The first substrate 100 may be formed from a composite material. Such a first substrate 100 made of a composite material will be described next as a composite material substrate 200.

[0103] Figure 18 shows an example of the configuration of a composite material substrate 200 according to this embodiment. The composite material substrate 200 has a first substrate 202 of a first material and a second substrate 204 of a second material. The first substrate 202 is a single crystal material. The first substrate 202 is, for example, a SiC single crystal substrate. When the first substrate 202 is a SiC single crystal substrate, the first surface 201 of the first substrate 202 opposite to the second substrate 204 can be, for example, a Si surface of the SiC crystal structure. Alternatively, the first surface 201 can be a C surface opposite to Si.

[0104] Since the first substrate 202 is reinforced by the second substrate 204, its thickness can be reduced compared to the first substrate 100 which is formed from a single material. The first substrate 202 can be made, for example, about 0.5 μm or thicker. It is desirable that the thickness of the first substrate 202 be such that it can be bonded to the upper surface of the second substrate 204, as will be described later.

[0105] Furthermore, the thickness of the first substrate 202 may be adjusted by polishing the first surface 201 of the first substrate 202 after it has been bonded to the second substrate 204. In this case, the thickness of the first substrate 202 can be made thinner than 0.5 μm.

[0106] The second substrate 204 can be, for example, a SiC sintered substrate. The second material of the second substrate 204 may be other single crystal materials or sintered materials, such as SiN, AlN, C, etc.

[0107] The composite material substrate 200 shown in Figure 18 can be manufactured, for example, as follows. First, a third substrate 206 of the first material and a second substrate 204 of the second material are prepared. Figure 19 shows an example of a composite material substrate composed of the first substrate 202 and the second substrate 204 according to this embodiment. Figure 19(a) shows an example of the configuration of the prepared third substrate 206 and second substrate 204. The third substrate 206 and the second substrate 204 each have flat surfaces, for example, a second surface 203 and a third surface 205 that are flat on the order of nanometers.

[0108] As shown in Figure 19(a), the third substrate 206 has a separation region 208. The separation region 208 is located at a predetermined distance from the second surface 203 of the third substrate 206. The separation region 208 can be formed, for example, as a modified layer formed by implanting ions such as oxygen ions. Such a separation region 208 makes the third substrate 206 separable mechanically or chemically.

[0109] Then, when the third substrate 206 is separated by the separation region 208, a portion of the third substrate 206 becomes the first substrate 202, and the remaining portion becomes the first material substrate portion 207. In other words, the separation region 208 is provided at a distance from the second surface 203 of the third substrate 206, such that the thickness of the first substrate 202 to be separated from the third substrate 206 is a predetermined distance.

[0110] The second surface 203 of the third substrate 206 and the third surface 205 of the second substrate 204 are joined by pressure pressing and heating after undergoing surface treatment such as chemical surface treatment or plasma treatment. The joining can be performed in air or vacuum. After joining the third substrate 206 and the second substrate 204, they are separated chemically or mechanically in the separation region 208.

[0111] Figure 18(b) shows an example in which the second substrate 204 is bonded to the third substrate 206 and then separated at the separation region 208. Then, the surface of the first substrate 202 bonded to the upper surface of the second substrate 204 is finished to a first surface 201 with a predetermined off-angle by surface treatment including polishing such as mechanical polishing and chemical polishing, and cleaning. This results in a composite material substrate 200 in which the first substrate 202 of the first material and the second substrate 204 of the second material are bonded together.

[0112] By using the composite material substrate 200 described above instead of the first substrate 100 and executing the operation flow from S10 to S14 shown in Figure 1, an intermediate layer 150 and a second semiconductor layer 160 can be formed on the upper surface of the composite material substrate 200. Compared to the first substrate 100 made of a single material, such a composite material substrate 200 can reduce the amount of the first material that makes up the substrate. Therefore, the second material of the second substrate 204 can be made of a lower-cost material compared to the first material, and the cost can be reduced by reducing the amount of the first material, which is a high-quality single-crystal material.

[0113] <Formation of self-supporting semiconductor substrates> In the semiconductor substrate manufacturing flow according to this embodiment described above, an example has been given in which an intermediate layer 150 and a second semiconductor layer 160 are formed on the upper surface of a first substrate 100 or a composite material substrate 200, but the invention is not limited to this. The second semiconductor layer 160 may be formed as a self-supporting semiconductor substrate using the manufacturing flow shown in Figure 1.

[0114] For example, in S14, it was explained that the first semiconductor substrate 300 shown in Figure 10 can be fabricated by growing the second semiconductor layer 160 on the upper surface of the intermediate layer 150. Here, the thickness of the second semiconductor layer 160 can be grown to a greater extent so that it can be handled by the second semiconductor layer 160 alone. For example, the thickness of the second semiconductor layer 160 can be in the range of 5 μm to 1 mm. From the perspective of handling the second semiconductor layer 160 alone without support, the thickness of the second semiconductor layer 160 may be 1 mm or more.

[0115] For crystal growth of the second semiconductor layer 160, methods such as MOCVD and HVPE can be used. Furthermore, multiple crystal growth methods can be used in combination. For example, MOCVD and HVPE can be used in combination. In this case, for instance, the layer may be grown to a predetermined thickness using the MOCVD method, and then further grown to the same predetermined thickness using the HVPE method.

[0116] Even in this case, the intermediate layer 150 mitigates the stress on the second semiconductor layer 160 caused by the difference in lattice constants and thermal expansion coefficients between the first substrate 100, the residual seed layer 122, and the second semiconductor layer 160. For example, a high-quality second semiconductor layer 160 of a predetermined thickness that can stand on its own can be grown as a crystal.

[0117] After growing the second semiconductor layer 160 to a predetermined thickness, the second semiconductor layer 160 may be separated from the first substrate 100. The second semiconductor layer 160 is connected to the first substrate 100 by an intermediate layer 150, and the buffer layer 130 constituting the intermediate layer 150 has a laminated structure comprising a single layer or multiple layers having two-dimensional bonding.

[0118] The bonds between each layer having two-dimensional bonding in the buffer layer 130, between the buffer layer 130 and the first surface 101 of the first substrate 100, and between the buffer layer 130 and the residual seed layer 122 are weak forces such as van der Waals forces. Therefore, the second semiconductor layer 160 can be easily separated from the first substrate 100 without etching off the buffer layer 130, for example by a chemical etching method, as described below.

[0119] Figure 20(a) shows an example of a configuration for separating the second semiconductor layer 160 from the first substrate 100 according to this embodiment. One side of the first semiconductor substrate 300, on which the second semiconductor layer 160 has been crystal-grown on the first substrate 100, is placed in a separation apparatus equipped with a first fixed stage 310 and a second fixed stage 312. Figure 20(a) shows an example in which the bottom surface of the first substrate 100 is fixed with the first fixed stage 310. Note that the apparatus configuration in Figure 20 is just an example and does not limit the method of separating the second semiconductor layer 160 from the first substrate 100. As long as the second semiconductor layer 160 can be mechanically separated from the first substrate 100, the separation method and apparatus are not limited to the example in Figure 20.

[0120] The first fixed stage 310 and the second fixed stage 312 can each be adsorption stages. In this case, the adsorption method for the first fixed stage 310 and the second fixed stage 312 can be vacuum adsorption, electromagnetic adsorption, Bernoulli method, or cyclone method non-contact adsorption. It is desirable to select an adsorption method that is suitable for the substrate material, thickness, size, etc.

[0121] Furthermore, the method of adsorption for the first fixing stage 310 and the second fixing stage 312 may involve adsorbing an adhesive sheet that can be temporarily fixed, a substrate to which an adhesive has been attached or coated, etc., onto the fixing stage, and then fixing the first semiconductor substrate 300 via the adhesive sheet or the substrate. The adhesive sheet is, for example, an adhesive sheet that can be peeled off by heat or UV.

[0122] Instead of the adsorption stage described above, a fixing stage may be used that includes a heating device for heating the stage or a UV irradiation device for irradiating the stage with UV light, and an adhesive sheet that can be peeled off by heat or UV light. When fixing the first semiconductor substrate 300, the first fixing stage 310 and the second fixing stage 312 may have the same fixing method or different fixing methods, and it is desirable that the fixing method can be changed as appropriate.

[0123] Next, the second fixing stage 312 fixes the other side of the first semiconductor substrate 300, for example, the surface of the second semiconductor layer 160. Then, with the first semiconductor substrate 300 fixed to the first fixing stage 310, the second fixing stage 312 is moved to a position where the second semiconductor layer 160 can be separated from the first substrate 100. It is desirable that the second fixing stage 312 includes a mechanism for moving perpendicular to the surface of the first semiconductor substrate 300, as well as a mechanism for moving in a direction different from perpendicular to the surface of the first semiconductor substrate 300 from the first substrate 100.

[0124] Figure 20(b) shows an example of the configuration after the second semiconductor layer 160 according to this embodiment has been separated from the first substrate 100. As shown in Figure 20(b), it is desirable that the movement mechanism of the second fixed stage 312 be configured such that the trajectory of the center of the second fixed stage 312 traces an arc with the vicinity of the substrate edge of the first semiconductor substrate 300 as the pivot point. In Figure 20(b), an example is shown in which the size of the second fixed stage 312 is larger than the size of the second semiconductor layer 160 to be separated, but this is not the only option. The size of the second fixed stage 312 may be the same as or smaller than the size of the second semiconductor layer 160 to be separated.

[0125] With this moving mechanism of the second fixed stage 312, even if the first semiconductor substrate 300 to be moved is a large-diameter wafer with a large surface area, the second semiconductor layer 160 can be stably and safely separated from the first semiconductor substrate 100 without placing a large load on the entire first semiconductor substrate 300, the first substrate 100, and the second semiconductor layer 160.

[0126] Furthermore, if the size of the second semiconductor layer 160 to be separated is small, for example, if the surface area is approximately 100 mm² 2In the following cases (for example, when the size is a square with sides of 10 mm or less), separation can be easily and safely performed even by moving vertically, without causing damage such as cracks to the second semiconductor layer 160. When separating multiple second semiconductor layers 160, if the size of the area to be separated is small, for example, if the area of ​​the target area is approximately 100 mm² 2 In the following cases (for example, when the size is a square with sides of 10 mm or less), separation can be easily and safely achieved even by moving in a vertical direction, without causing damage such as cracks to the second semiconductor layer 160.

[0127] Furthermore, the roles of the first fixed stage 310 and the second fixed stage 312 when separating the second semiconductor layer 160 from the first substrate 100 can be swapped. In this case, the first fixed stage 310 is equipped with a moving mechanism and may move the first substrate 100. Alternatively, both the first fixed stage 310 and the second fixed stage 312 are equipped with a moving mechanism and may move both the first fixed stage 310 and the second fixed stage 312 together.

[0128] Next, by removing the second semiconductor layer 160 from the second fixed stage 312, a self-supporting semiconductor substrate containing a high-quality second semiconductor layer 160 of a predetermined thickness is obtained. The self-supporting semiconductor substrate has a thickness that allows it to stand on its own. The self-supporting semiconductor substrate may have a configuration comprising a second semiconductor layer 160 and an intermediate layer 150, or the intermediate layer 150 may be removed. The intermediate layer 150 can be removed, for example, by dry etching using oxygen or chlorine-based gases. Alternatively, the intermediate layer 150 may be removed by chemical mechanical polishing (CMP).

[0129] After separating the second semiconductor layer 160 from the first substrate 100, the first substrate 100 can be reused by removing the buffer layer 130 remaining on the surface of the first substrate 100 on the side where the intermediate layer 150 is formed. The buffer layer 130 remaining on the surface of the first substrate 100 can be removed, for example, by dry etching using oxygen gas or chlorine gas. When reusing the first substrate 100, polishing treatments such as chemical mechanical polishing (CMP) may be performed on the surface of the first substrate 100 as appropriate.

[0130] As described above, after forming a second semiconductor layer 160 on the first substrate 100, a self-supporting semiconductor substrate formed by the second semiconductor layer 160 can be formed by separating a portion of the region containing the formed second semiconductor layer 160 from the first substrate 100. This makes it possible to obtain a self-supporting semiconductor substrate of significantly higher quality compared to conventional techniques for semiconductor substrates such as III-V compound semiconductors, II-VI compound semiconductors, and Si having a predetermined mixed crystal ratio of constituent elements.

[0131] Furthermore, a high-quality self-supporting semiconductor substrate of a predetermined thickness can be obtained without undergoing processing steps such as cutting and polishing of the substrate material or chemical etching steps as in conventional technologies. Moreover, since the high-quality self-supporting semiconductor substrate of a predetermined thickness separates from the first substrate 100 at the position of the buffer layer 130 without damaging the first substrate 100, the first substrate 100 can be easily reused.

[0132] In the semiconductor substrate manufacturing flow according to this embodiment described above, an example was described in which an intermediate layer 150 and a second semiconductor layer 160 are formed on the upper surface of a first substrate 100 or a composite material substrate 200, and then the second semiconductor layer 160 is separated from the first substrate 100. However, the method is not limited to this. For example, after forming the second semiconductor layer 160 on the first substrate 100 by executing the semiconductor substrate manufacturing flow shown in Figure 1, a reinforcing substrate 350 may be further bonded to the upper surface of the second semiconductor layer 160, and then the second semiconductor layer 160 may be separated from the first substrate 100.

[0133] Figure 21(a) shows an example in which a reinforcing substrate 350 is bonded to the upper surface of the second semiconductor layer 160 according to this embodiment. For example, after appropriately cleaning and performing surface treatment such as plasma treatment on the bonding surface of the second semiconductor layer 160 and the bonding surface of the reinforcing substrate 350, the second semiconductor layer 160 and the reinforcing substrate 350 are bonded by bringing the bonding surfaces into close contact and applying pressure.

[0134] The bonding process, which involves bringing the surfaces to be joined together into close contact and applying pressure, may be carried out in air or in a vacuum. Furthermore, this bonding process may be carried out at room temperature or under heating. It is desirable that the bonding strength between the second semiconductor layer 160 and the reinforcing substrate 350 is greater than at least the force acting between the layers of the two-dimensional layered material constituting the buffer layer 130 (the magnitude of the interlayer interaction or the interlayer bonding force).

[0135] After bonding the reinforcing substrate 350 to the second semiconductor layer 160, the first substrate 100 and the second semiconductor layer 160 bonded to the reinforcing substrate 350 are separated. For example, similar to the method described in Figures 20(a) and 20(b), the surface of the first substrate 100 and the surface of the reinforcing substrate 350 are fixed by a first fixing stage 310 and a second fixing stage 312, respectively, and the first fixing stage 310 and / or the second fixing stage 312 are moved to separate the first substrate 100 and the second semiconductor layer 160.

[0136] After separating the first substrate 100 and the second semiconductor layer 160, the side of the second semiconductor layer 160 opposite to the reinforcing substrate 350 is etched. This removes the residual seed layer 122, or a portion of the residual seed layer 122 and buffer layer 130, that is present on the side of the second semiconductor layer 160 opposite to the reinforcing substrate 350. In this etching process, the remaining buffer layer 130 may be removed, leaving the residual seed layer 122 on the surface of the second semiconductor layer 160.

[0137] As described above, a second semiconductor substrate in which a second semiconductor layer 160 is bonded to a reinforcing substrate 350 can be fabricated. Figure 21(b) shows a first example of the second semiconductor substrate 360 ​​according to this embodiment. The above procedure for fabricating the second semiconductor substrate 360 ​​is an example and is not limited thereto.

[0138] For example, similar to the method described in Figures 20(a) and 20(b), after separating the first substrate 100 and the second semiconductor layer 160, the side of the separated second semiconductor layer 160 that was attached to the first substrate 100 may be joined to the reinforcing substrate 350. In this case, a support capable of supporting the second semiconductor layer 160 may be provided on the side of the second semiconductor layer 160 opposite to the first substrate 100, and then the second semiconductor layer 160 may be separated from the first substrate 100. The support can support the second semiconductor layer 160 after it has been separated from the first substrate 100, and makes it possible to easily handle the separated second semiconductor layer 160.

[0139] After separating the second semiconductor layer 160 from the first substrate 100, part or all of the buffer layer 130 remaining on the residual seed layer 122 is etched off. Then, the reinforcing substrate 350 is pressed against the side of the residual seed layer 122 opposite to the second semiconductor layer 160. The pressing process may be carried out in air, or alternatively, in a vacuum. Then, the support that supports the second semiconductor layer 160 is separated or removed from the second semiconductor layer 160.

[0140] As described above, the second semiconductor substrate 360 ​​can be fabricated. Figure 22 shows a second example of the second semiconductor substrate 360 ​​according to this embodiment, fabricated in this manner. In addition, the second semiconductor substrate 360 ​​may be formed by separating the first substrate 100 after forming a predetermined semiconductor device on the second semiconductor layer 160 and then bonding the second semiconductor layer 160 to the reinforcing substrate 350.

[0141] Furthermore, the reinforcing substrate 350 may have device structures such as circuit elements and wiring, or optical component structures such as optical waveguides formed in some areas. In addition, the reinforcing substrate 350 may have devices, apparatus, etc. that have other functions such as heat dissipation, in addition to the function of supporting and reinforcing the second semiconductor layer 160.

[0142] The above example of the second semiconductor substrate 360 ​​illustrates a configuration in which a single-layer second semiconductor layer 160 is bonded to the upper surface of a reinforcing substrate 350, but the invention is not limited to this configuration. The region to which the second semiconductor layer 160 is bonded may be the entire surface of the second semiconductor substrate 360 ​​or only a portion of it.

[0143] The second semiconductor substrate 360 ​​may have a structure in which multiple second semiconductor layers 160 of the same or different materials are bonded to at least a portion of the upper surface of the reinforcing substrate 350 by repeating the above process multiple times. In this case, the second semiconductor substrate 360 ​​may be formed by stacking multiple second semiconductor layers 160 of the same or different materials in a two-dimensional or three-dimensional manner.

[0144] Furthermore, multiple second semiconductor layers 160 may be bonded to at least a portion of the upper surface of the reinforcing substrate 350. In this case, the multiple second semiconductor layers 160 may be bonded to the reinforcing substrate 350 in a two-dimensional or three-dimensional manner, forming separate islands. The bonding of the second semiconductor layers on the second semiconductor substrate 360 ​​may be done without adhesive, or with adhesive. For example, bonding may be done using a thermosetting adhesive or a UV-curing adhesive. The reinforcing substrate 350 may be a semiconductor substrate, a dielectric substrate, a glass substrate, a metal substrate, a resin substrate, etc.

[0145] Circuit elements, wiring, etc., may be formed on the reinforcing substrate 350 and / or the second semiconductor substrate 360 ​​before bonding. In this case, the circuit elements and wiring of the reinforcing substrate 350 and the second semiconductor substrate 360 ​​may be connected to each other after bonding. Alternatively, circuit elements and wiring may be formed on the second semiconductor substrate 360 ​​after the reinforcing substrate 350 and the second semiconductor substrate 360 ​​have been bonded together.

[0146] As described above, a second semiconductor substrate 360 ​​can be easily fabricated by separating a high-quality second semiconductor layer 160 from the first substrate 100 at the location of the buffer layer 130 and bonding it to the upper surface of the reinforcing substrate 350. The fabrication of the second semiconductor substrate 360 ​​can be carried out without etching the buffer layer 130, and a high-quality second semiconductor layer 160 can be bonded to the upper surface of the reinforcing substrate 350, which is made of a different material than the first substrate 100, in fewer steps. Furthermore, since the second semiconductor layer 160 is separated from the first substrate 100 at the location of the buffer layer 130, the first substrate 100 can be easily reused.

[0147] <Manufacturing equipment> The first semiconductor substrate 300 and the second semiconductor substrate 360 ​​according to this embodiment can be manufactured using separate and independent semiconductor manufacturing equipment. However, since they can be manufactured using a simple manufacturing process, they can also be manufactured using dedicated semiconductor manufacturing equipment. Therefore, the manufacturing equipment for producing the first semiconductor substrate 300 and the second semiconductor substrate 360 ​​will be described below.

[0148] Figure 23 shows an example of the configuration of the first manufacturing apparatus 400 according to this embodiment. The first manufacturing apparatus 400 comprises a first semiconductor layer forming apparatus 410, a first transport path 412, a gate valve 414, and a high-temperature heating furnace 416. The high-temperature heating furnace 416 is sometimes called an annealing apparatus. Although not shown in Figure 23, the first manufacturing apparatus 400 may further include a first fixed stage 310, a second fixed stage 312, an etching apparatus, and a control unit. Also, Figure 23 omits detailed configurations such as a preparation room for setting substrates, gas introduction equipment, and heating stages, and only shows the key points of the configuration of the first manufacturing apparatus 400.

[0149] The first semiconductor layer formation apparatus 410 has a chamber for housing the first substrate 100, and forms a first semiconductor layer 120 of a predetermined thickness on the first substrate 100 within the chamber. The first semiconductor layer formation apparatus 410 also forms a second semiconductor layer 160 on the first substrate 100. The first semiconductor layer formation apparatus 410 is a semiconductor crystal growth furnace for growing the semiconductor layer crystals. The first semiconductor layer formation apparatus 410 can be, for example, an MOCVD furnace.

[0150] Furthermore, the first semiconductor layer formation apparatus 410 is equipped with an etching apparatus inside. The etching apparatus etches the first surface 101 of the first substrate 100 fixed to the first fixed stage 310 to form a plurality of terrace portions 102 aligned in a first direction parallel to the horizontal plane of the first substrate 100, and a step portion 110 of a predetermined height between two adjacent terrace portions 102 in the first direction.

[0151] The high-temperature heating furnace 416 has a chamber for housing the first substrate 100. The high-temperature heating furnace 416 heats the first substrate 100, on which the first semiconductor layer 120 has been formed, in the chamber to evaporate some of the Si from a portion of the first substrate 100 from a portion of the step portion 110 exposed from the first semiconductor layer 120, thereby forming a buffer layer 130 having graphene in at least a portion between the first semiconductor layer 120 and the first substrate 100. The high-temperature heating furnace 416 is a furnace for performing a high-temperature heating treatment at a temperature of 1300°C or higher in an inert gas atmosphere after the first semiconductor layer 120 has been formed on the surface of the first substrate 100. The high-temperature heating furnace 416 can be, for example, an RF heating furnace.

[0152] The first transport path 412 connects the first semiconductor layer forming apparatus 410 and the high-temperature heating furnace 416. A substrate transport mechanism is provided in the chamber of the first semiconductor layer forming apparatus 410, the chamber of the high-temperature heating furnace 416, and the first transport path 412. The substrate transport mechanism makes it possible to move the first substrate 100, which is fixed to the first fixed stage 310, between the chamber of the first semiconductor layer forming apparatus 410 and the chamber of the high-temperature heating furnace 416. Such a first transport path 412 is a transport path that can transport the first substrate 100 between the first semiconductor layer forming apparatus 410 and the high-temperature heating furnace 416 without exposing it to the atmosphere.

[0153] The gate valve 414 is a valve that can shut off the flow of gas between the first semiconductor layer formation apparatus 410 and the high-temperature heating furnace 416 during each process, depending on the semiconductor crystal growth and high-temperature heat treatment processes.

[0154] The first fixing stage 310 fixes the first substrate 100. The first fixing stage 310, for example, exposes the first surface 101 of the first substrate 100 and fixes the second surface opposite to the first surface 101. The first fixing stage 310 is configured to move between the chamber of the first semiconductor layer forming apparatus 410 and the chamber of the high-temperature heating furnace 416 by passing through the first transport path 412 while fixing the first substrate 100. The first fixing stage 310 may be the same stage as the fixing stage described in Figures 20(a) and 20(b), or it may be a different stage.

[0155] The control unit controls the first fixed stage 310, the etching apparatus, the first semiconductor layer forming apparatus 410, and the high-temperature heating furnace 416. The control unit executes the operation flow shown in Figure 1. The control unit has, for example, a function to move the first fixed stage 310 on which the first substrate 100 is fixed, a function to form a plurality of terrace portions 102 and step portions 110 on the first substrate 100, a function to form the first semiconductor layer 120 such that a part of the step portions 110 is exposed, and a function to form a buffer layer 130 after the first semiconductor layer 120 has been formed. The control unit may also have a function to form a second semiconductor layer 160 on the upper surface of the first semiconductor layer 120 which is formed on the upper surface of the formed buffer layer 130.

[0156] The control unit includes, for example, a CPU (Central Processing Unit) and a memory unit. The CPU functions as a control unit that controls the first fixed stage 310, the etching apparatus, the first semiconductor layer forming apparatus 410, and the high-temperature heating furnace 416 by executing a program stored in the memory unit.

[0157] The first manufacturing apparatus 400 described above can perform the steps from forming a step on the first substrate 100 to forming the second semiconductor layer 160 on the first substrate 100 without exposing the first substrate 100 to the atmosphere. Therefore, the first manufacturing apparatus 400 can maintain the cleanliness of the surface of the first substrate 100, and thus grow a higher quality second semiconductor layer 160.

[0158] Figure 24 shows an example of the configuration of the second manufacturing apparatus 450 according to this embodiment. In the second manufacturing apparatus 450, components that are substantially the same as those in the operation of the first manufacturing apparatus 400 according to this embodiment shown in Figure 23 are denoted by the same reference numerals, and redundant explanations are omitted. The second manufacturing apparatus 450 further comprises a second semiconductor layer forming apparatus 418 and a second transport path 420.

[0159] The first semiconductor layer forming apparatus 410 of the second manufacturing apparatus 450 causes a first semiconductor layer 120 of a predetermined thickness to form on the first substrate 100. Then, the second semiconductor layer forming apparatus 418 causes a second semiconductor layer 160 of a predetermined thickness to form on the first substrate 100. The second semiconductor layer forming apparatus 418 may form the second semiconductor layer 160 in a different manner than the first semiconductor layer forming apparatus 410. The second semiconductor layer forming apparatus 418 can be, for example, an HVPE furnace.

[0160] The second transport path 420 connects the chamber of the second semiconductor layer forming apparatus 418 that houses the first substrate 100 with the chamber of the high-temperature heating furnace 416 that houses the first substrate 100. The first fixed stage 310 is also provided to be able to move between the chamber of the second semiconductor layer forming apparatus 418 and the chamber of the high-temperature heating furnace 416 while the first substrate 100 remains fixed. The second transport path 420 may also include a transport mechanism for moving and fixing the first substrate 100, which is fixed in the high-temperature heating furnace 416, into the second semiconductor layer forming apparatus 418.

[0161] As a result, the control unit has the function of controlling the second semiconductor layer forming apparatus 418 after forming a buffer layer 130 on the first substrate 100 to form a second semiconductor layer 160 on the upper surface of the first semiconductor layer 120 which is formed on the upper surface of the formed buffer layer 130.

[0162] The second manufacturing apparatus 450, like the first manufacturing apparatus 400, can perform the steps from forming a step on the first substrate 100 to forming the second semiconductor layer 160 on the first substrate 100 without exposing the first substrate 100 to the atmosphere. Therefore, the first manufacturing apparatus 400 can maintain the cleanliness of the surface of the first substrate 100, and thus grow a higher quality second semiconductor layer 160.

[0163] The first manufacturing apparatus 400 and the second manufacturing apparatus 450 described above may further include a second fixing stage 312 for fixing the side of the second semiconductor layer 160 formed on the first substrate 100 that is opposite to the first substrate 100. In this case, the control unit may have a function to control the first fixing stage 310 and the second fixing stage 312 after the second semiconductor layer 160 has been formed on the first substrate 100, as described in Figures 20(a) and 20(b), to separate a portion of the area including the formed second semiconductor layer 160 from the first substrate 100. As a result, the first manufacturing apparatus 400 and the second manufacturing apparatus 450 can perform the process up to the step of separating the first substrate 100.

[0164] In the first manufacturing apparatus 400 and the second manufacturing apparatus 450 according to the above embodiment, the control unit causes the first semiconductor layer 120 to be formed within a predetermined first temperature range higher than room temperature. The first temperature range is, for example, 1000°C to 1200°C. The control unit may also have a function to form a buffer layer 130 by performing heat treatment at a predetermined temperature higher than the predetermined first temperature range without returning the first semiconductor layer 120 to room temperature after it has been formed. The predetermined temperature is, for example, a predetermined temperature of 1300°C or higher.

[0165] Furthermore, the control unit may have a function to form the second semiconductor layer 160 at a predetermined second temperature range higher than room temperature without returning the substrate temperature of the first substrate 100 to room temperature after forming the buffer layer 130. The second temperature range is, for example, a predetermined range from 1000°C to 1300°C or higher. This allows the first manufacturing apparatus 400 and the second manufacturing apparatus 450 to form the second semiconductor layer 160 on the first substrate 100 without lowering the substrate temperature of the first substrate 100 to room temperature after forming the first semiconductor layer 120 on the first substrate 100.

[0166] When the substrate temperature is lowered, stress is generated within the substrate due to the difference in thermal expansion coefficients. Misfit transitions caused by lattice mismatch in the region near the epitaxial growth interface between the first semiconductor layer 120 and the second semiconductor layer 160 may react with each other within the second semiconductor layer 160 due to the stress generated by the difference in thermal expansion coefficients when the substrate temperature is lowered, causing a through transition that reaches the surface of the second semiconductor layer 160 (the surface opposite to the side of the first substrate 100). The first manufacturing apparatus 400 and the second manufacturing apparatus 450 can form the second semiconductor layer 160 on the first substrate 100 without lowering the substrate temperature of the first substrate 100 to room temperature, thereby suppressing the occurrence of such through transitions in the second semiconductor layer 160 and enabling the formation of a higher quality second semiconductor layer 160 with fewer defects.

[0167] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments, and various modifications and changes are possible within the scope of its gist. For example, all or part of the apparatus can be configured by functionally or physically distributing and integrating in any unit. Furthermore, new embodiments resulting from any combination of multiple embodiments are also included in the embodiments of the present invention. The effects of the new embodiments resulting from the combinations are combined with the effects of the original embodiments. [Explanation of Symbols]

[0168] 100 First board 101 Page 1 102 Terrace section 110 Step section 120 First Semiconductor Layer 122 Remaining Seed Layer 130 Buffer layer 140 Seed layer growth substrate 142 Crystal growth substrate 150 Middle Class 160 Second Semiconductor Layer 200 Composite Material Substrates 201 Page 1 202 First substrate 203 2nd page 204 Second board 205 Page 3 206 Third board 207 First material substrate part 300 First Semiconductor Substrate 310 First Fixed Stage 312 Second Fixed Stage 350 Reinforcement board 360 Second Semiconductor Substrate

Claims

1. a step of forming, on a first surface of a first substrate formed by cutting out a semiconductor crystal containing at least Si and C along a surface inclined with respect to a horizontal plane perpendicular to a crystal growth direction of the semiconductor crystal, a plurality of terrace portions, which are surfaces along a first direction parallel to the horizontal plane of the first substrate, and a step portion of a predetermined height located between two of the terrace portions adjacent to each other in the first direction; forming the terrace portion and the step portion on the first surface of the first substrate, and then depositing a first semiconductor layer having a critical film thickness or more to form the first semiconductor layer such that a portion of the step portion is exposed; a step of evaporating a part of Si of the first substrate from a part of the step portion exposed from the first semiconductor layer by heat-treating the first substrate on which the first semiconductor layer is formed, thereby forming a buffer layer having at least one graphene layer at least in a part between the first semiconductor layer and the first substrate; having the predetermined height of the step portion is greater than a critical film thickness of the first semiconductor layer obtained by crystal growth on the first surface of the first substrate; A method for manufacturing a semiconductor substrate.

2. In the process of forming the plurality of terrace portions and step portions, the first surface of the first substrate is etched in a hydrogen gas atmosphere to form the terrace portions and step portions on the first surface of the first substrate. The method for manufacturing a semiconductor substrate according to claim 1 .

3. the semiconductor crystal is a SiC single crystal, the horizontal plane perpendicular to the crystal growth direction of the semiconductor crystal is a (0001) plane, the first surface of the first substrate is inclined with respect to the horizontal plane at an angle in the range of greater than 0° and smaller than 10°; The method for manufacturing a semiconductor substrate according to claim 1 .

4. 2 . The method for manufacturing a semiconductor substrate according to claim 1 , wherein in the step of forming the first semiconductor layer, the first semiconductor layer is formed by depositing a semiconductor on the first surface of the first substrate to a thickness equal to or less than the height of the step portion.

5. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the step portion has a height of 5 nm or more and 200 nm or less.

6. The method for manufacturing a semiconductor substrate according to claim 1 , wherein a difference between a lattice constant of the first substrate and a lattice constant of the first semiconductor layer is 4% or less.

7. The method for manufacturing a semiconductor substrate according to claim 1 , further comprising the step of forming a second semiconductor layer on an upper surface of the first semiconductor layer after the step of forming the buffer layer.

8. 8. The method for producing a semiconductor substrate according to claim 7, wherein the second semiconductor layer includes at least one of a single element semiconductor material, a III-V nitride semiconductor material, and a II-VI compound semiconductor material.

9. 8. The method for manufacturing a semiconductor substrate according to claim 7, wherein in the step of forming the buffer layer, the first substrate is heat-treated to evaporate at least a portion of the first semiconductor layer, thereby forming a region where the buffer layer and the second semiconductor layer contact each other, or a region where the first substrate and the second semiconductor layer contact each other.

10. 8. The method for manufacturing a semiconductor substrate according to claim 7, further comprising the step of: after forming the second semiconductor layer, separating at least a portion of a region including the second semiconductor layer from the first substrate to form a second substrate including the second semiconductor layer.

11. The method for manufacturing a semiconductor substrate according to claim 10 , wherein the step of forming the second substrate further comprises the step of forming a predetermined device in the second semiconductor layer after forming the second semiconductor layer.

12. The method for manufacturing a semiconductor substrate according to claim 10, further comprising the step of bonding the second substrate to a third substrate after forming the second substrate.

13. In the step of forming the first semiconductor layer, the first semiconductor layer is formed within a first predetermined temperature range that is higher than room temperature; In the step of forming the buffer layer, after the first semiconductor layer is formed, a heat treatment is performed at a temperature higher than the first temperature range without returning the temperature to the room temperature, and the buffer layer is formed; In the step of forming the second semiconductor layer, the second semiconductor layer is formed within a second predetermined temperature range higher than room temperature without returning the temperature to room temperature after the buffer layer is formed. The method for manufacturing a semiconductor substrate according to claim 7 .

14. a first substrate formed of a semiconductor crystal containing at least Si and C, the first substrate including a plurality of terrace portions on a first surface of the first substrate, the terrace portions being surfaces along a first direction parallel to a horizontal plane perpendicular to a crystal growth direction of the semiconductor crystal, and a step portion of a predetermined height provided between two of the terrace portions adjacent to each other in the first direction; a first semiconductor layer formed on the plurality of terrace portions in at least a portion of a surface of the first substrate on which the plurality of terrace portions are formed, the first semiconductor layer having a thickness less than a height of the step portion and equal to or greater than a critical film thickness; a buffer layer having at least one graphene layer formed at least partially between the first semiconductor layer and the first substrate; Equipped with the predetermined height of the step portion is greater than a critical film thickness of the first semiconductor layer obtained by crystal growth on the first surface of the first substrate; Semiconductor substrate.

15. The semiconductor substrate according to claim 14 , further comprising a second semiconductor layer formed on a surface of the first semiconductor layer opposite to the first substrate.

16. The semiconductor substrate according to claim 15 , further comprising a region where the buffer layer and the second semiconductor layer contact each other, or a region where the first substrate and the second semiconductor layer contact each other.

17. a first fixing stage for exposing a first surface of a first substrate formed by cutting out a semiconductor crystal containing at least Si and C along a surface that is inclined with respect to a horizontal plane perpendicular to a crystal growth direction of the semiconductor crystal, and fixing a second surface opposite to the first surface; an etching device for etching the first surface of the first substrate fixed to the first fixed stage to form a plurality of terrace portions that are surfaces along a first direction parallel to the horizontal plane of the first substrate, and a step portion of a predetermined height located between two of the terrace portions adjacent to each other in the first direction; a first semiconductor layer forming device for forming a first semiconductor layer having a critical thickness or more on the first surface of the first substrate; an annealing device for heating the first substrate on which the first semiconductor layer is formed, to evaporate a part of Si of the first substrate from a part of the step portion exposed from the first semiconductor layer, and forming a buffer layer having at least one graphene layer at least in a part between the first semiconductor layer and the first substrate; a first transfer path connecting a chamber of the first semiconductor layer forming apparatus that accommodates the first substrate and a chamber of the annealing apparatus that accommodates the first substrate; a control unit that controls the first fixing stage, the etching device, the first semiconductor layer forming device, and the annealing device; Equipped with a substrate transport mechanism is provided between a chamber of the first semiconductor layer forming apparatus that accommodates the first substrate, a chamber of the annealing apparatus that accommodates the first substrate, and the first transport path, and the substrate transport mechanism is capable of moving the first substrate fixed to the first fixed stage between the chamber of the first semiconductor layer forming apparatus and the chamber of the annealing apparatus; the etching apparatus is provided inside the first semiconductor layer forming apparatus, the control unit has a function of controlling at least a step of moving the first substrate from the first fixed stage to which the first substrate is fixed, a step of forming the plurality of terrace portions and the step portion on the first substrate, a step of forming the first semiconductor layer so that a part of the step portion is exposed, and a step of forming the buffer layer after the step of forming the first semiconductor layer, the predetermined height of the step portion is greater than a critical film thickness of the first semiconductor layer obtained by crystal growth on the first surface of the first substrate; Semiconductor substrate manufacturing equipment.

18. the first semiconductor layer forming apparatus is capable of forming a second semiconductor layer on the first surface side of the first substrate after forming the buffer layer; the control unit further has a function of controlling a step of forming the second semiconductor layer on the first surface side of the first substrate after forming the buffer layer. The semiconductor substrate manufacturing apparatus according to claim 17.

19. a second semiconductor layer forming device for forming a second semiconductor layer on the first surface of the first substrate; a second transfer path connecting a chamber of the second semiconductor layer forming apparatus that accommodates the first substrate and a chamber of the annealing apparatus that accommodates the first substrate; Equipped with a transport mechanism is provided between a chamber of the second semiconductor layer forming apparatus that accommodates the first substrate, a chamber of the annealing apparatus that accommodates the first substrate, and the second transport path, and the transport mechanism is capable of moving the first substrate fixed to the first fixed stage between the chamber of the second semiconductor layer forming apparatus and the chamber of the annealing apparatus; The control unit further has a function of controlling the second semiconductor layer forming device after forming the buffer layer, to control a step of forming the second semiconductor layer on the first surface side of the first substrate. The semiconductor substrate manufacturing apparatus according to claim 17.

20. a second fixing stage that fixes a surface of the second semiconductor layer formed on the first substrate opposite to the first substrate, the control unit further has a function of controlling the first fixing stage and the second fixing stage after forming the second semiconductor layer on the first substrate, to control a process of separating at least a portion of a region including the formed second semiconductor layer from the first substrate.

20. The semiconductor substrate manufacturing apparatus according to claim 18 or 19.

21. The control unit is forming the first semiconductor layer within a first predetermined temperature range above room temperature; forming the buffer layer by performing a heat treatment at a temperature higher than the first temperature range without returning the temperature to room temperature after forming the first semiconductor layer; and forming the second semiconductor layer at a predetermined second temperature range higher than the room temperature without returning the temperature to the room temperature after forming the buffer layer.

20. The semiconductor substrate manufacturing apparatus according to claim 18 or 19.

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