Learning device, inference device, and semiconductor device

Abstract

A learning device (13) comprises: a data acquisition unit (21) for acquiring training data including a bus master transfer request, and a bus-occupied interval that lasts until the bus master receives a transfer response from a bus slave in response to the bus master transfer request; and a model generation unit (22) for generating a trained model for inferring the bus-occupied interval from the bus master transfer request by using the training data.

Description

Learning device, inference device, and semiconductor device

[0001] The present disclosure relates to a learning device, an inference device, and a semiconductor device.

[0002] There are known devices that arbitrate transfer requests from multiple bus masters. For example, in a device described in Patent Document 1, when an interconnect receives transfer requests from multiple bus masters, it outputs the transfer request issued by the bus master with the highest priority to a memory controller according to the priorities set for each bus master. When the interconnect receives a response to the transfer request output to the memory controller, it selects the transfer request of the bus master with the next highest priority and outputs it to the memory controller.

[0003] Japanese Patent Application Laid-Open No. 2019-220060

[0004] In a conventional bus control device such as that described in Patent Document 1, it is not possible to assign bus access priority to each transfer request.

[0005] Therefore, an object of the present disclosure is to provide a learning device, an inference device, and a semiconductor device that can assign bus access priorities on a transfer request basis.

[0006] The learning device of the present disclosure includes a data acquisition unit that acquires learning data including a transfer request from a bus master and a bus occupation time until the bus master receives a transfer response from a bus slave in response to the transfer request from the bus master, and a model generation unit that uses the learning data to generate a trained model for inferring the bus occupation time from the transfer request from the bus master.

[0007] The inference device disclosed herein includes a data acquisition unit that acquires transfer requests from bus masters, and an inference unit that outputs bus occupation time from the transfer requests from the bus masters acquired by the data acquisition unit using a trained model for inferring bus occupation time from the transfer requests from the bus masters.

[0008] The semiconductor device of the present disclosure includes a plurality of bus masters, a plurality of bus slaves, a bus interconnecting the plurality of bus masters and the plurality of bus slaves and performing address transfers and data transfers between the plurality of bus masters and the plurality of bus slaves, and a bus control device controlling the address transfers and data transfers via the bus.

[0009] The bus control device includes a memory device that stores past transfer requests output by multiple bus masters, priorities set for the transfer requests, and bus occupation times for data transfers based on the transfer requests, and a learning device. The learning device includes a data acquisition unit that acquires, from the memory device, attributes of transfer requests whose bus occupation times are shorter than a first occupation time and the priorities of the transfer requests as learning data, and a model generation unit that uses the learning data to generate a learned model that estimates priorities that will result in bus occupation times shorter than the first occupation time from the attributes of the transfer requests.

[0010] The learning device of the present disclosure includes a data acquisition unit that acquires learning data including competing transfer requests from multiple bus masters and transfer requests that grant bus access rights among the competing transfer requests from the multiple bus masters, and a model generation unit that uses the learning data to generate a learned model that determines, from the competing transfer requests from the multiple bus masters, a transfer request that grants bus access rights among the competing transfer requests from the multiple bus masters.

[0011] The inference device disclosed herein includes a data acquisition unit that acquires competing transfer requests from a plurality of bus masters, and an inference unit that determines, from the competing transfer requests from the plurality of bus masters acquired by the data acquisition unit, a transfer request that will be granted bus access rights from the competing transfer requests from the plurality of bus masters, using a learned model that determines, from the competing transfer requests from the plurality of bus masters, a transfer request that will be granted bus access rights from the competing transfer requests from the plurality of bus masters.

[0012] According to the present disclosure, bus access priority can be assigned to each transfer request.

[0013] FIG. 1 is a diagram showing the configuration of a semiconductor device according to a first embodiment. FIG. 2 is a diagram showing the configuration of a bus control device 10. FIG. 3 is a diagram showing the configuration of a learning device 13. FIG. 4 is a flowchart showing the learning process of the learning device 13 according to the first embodiment. FIG. 5 is a diagram showing the configuration of an inference device 14. FIG. 6 is a flowchart showing the inference process of the inference device 14 according to the first embodiment. FIG. 7 is a flowchart showing the learning process of the learning device 13 according to the second embodiment. FIG. 8 is a diagram for explaining an example of transitions between states and actions during learning. FIG. 9 is a flowchart showing the inference process of the inference device 14 according to the second embodiment. FIG. 10 is a diagram showing a configuration when the functions of the bus control device 10 are realized using software.

[0014] Hereinafter, embodiments will be described with reference to the drawings. First Embodiment <Description of Semiconductor Device> Fig. 1 is a diagram showing the configuration of a semiconductor device according to a first embodiment.

[0015] The semiconductor device includes a plurality of bus masters M1 to MN, a plurality of bus slaves S1 to SN, a bus control device 10, and a bus 100. In the following description, the bus masters M1 to MN may be collectively referred to as bus master M, and the bus slaves S1 to SN may be collectively referred to as bus slave S.

[0016] The bus masters M1 to MN output transfer requests. The bus slaves S1 to SN respond to the transfer requests. In response to the transfer request from the bus master Mj, the bus slave Si transmits data to the bus master Mj via the bus 100.

[0017] A bus control device 10 controls address transfers and data transfers. Addresses and data are transferred over a bus 100. A plurality of bus masters M1 to MN and a plurality of bus slaves S1 to SN are interconnected by the bus 100.

[0018] The bus control device 10 determines the priority of the transfer requests and determines the order in which the transfer requests are processed based on the assigned priority.

[0019] 2 is a diagram showing the configuration of the bus control device 10. The bus control device 10 includes a transfer request storage device 11, a transfer time storage device 12, a learning device 13, an inference device 14, a transfer request arbitration device 15, and a learned model storage device 16.

[0020] The transfer request storage device 11 stores past transfer requests from the bus master M. The transfer time storage device 12 stores bus occupation time, which is the response time of the bus slave S to the past transfer request. The bus occupation time may be the time it takes for the bus slave S to transfer data to another bus slave via the bus in response to the transfer request.

[0021] The learning device 13 acquires information from the transfer request storage device 11 and the transfer time storage device 12, performs learning processing, and generates a trained model. The generated trained model is stored in the trained model storage device 16.

[0022] The inference device 14 uses the learned model stored in the learned model storage device 16 to perform an inference process to estimate a priority for a transfer request that will result in a bus occupation time that is shorter than the first occupation time.

[0023] The transfer request arbitration device 15 rearranges the processing order of transfer requests output by a plurality of bus masters M.

[0024] 3 is a configuration diagram of the learning device 13. The learning device 13 includes a data acquisition unit 21 and a model generation unit 22.

[0025] The data acquisition unit 21 acquires data relating to past transfer requests from the transfer request storage device 11 and the transfer time storage device 12 as learning data.

[0026] The model generation unit 22 classifies the training data by attributes of past transfer requests. Based on the training data, which includes the burst size, burst length, and single-shot size included in the attributes of the transfer requests, address information of the bus slave S, and priorities based on the arbitration results of the transfer request arbitration device 15, the model generation unit 22 learns attributes having a priority that results in a bus occupation time shorter than the first occupation time and attributes having a priority that results in a bus occupation time longer than the second occupation time. That is, the model generation unit 22 generates a trained model that infers priorities that result in a shorter bus occupation time from data related to past transfer requests stored in the transfer request storage device 11 and the transfer time storage device 12. The burst size represents the size of unit data during burst transmission (e.g., 32 bytes), and the burst length represents the number of unit data during burst transmission. The single-shot size represents the size of data during normal transmission (e.g., 32 bytes).

[0027] The learning algorithm used by the model generation unit 22 may be a known algorithm such as supervised learning, unsupervised learning, or reinforcement learning. As an example, a case where reinforcement learning is applied will be described. In reinforcement learning, an agent (acting subject) in a certain environment observes the current state (environmental parameters) and determines the action to be taken. The environment changes dynamically depending on the agent's actions, and the agent is given a reward according to the environmental changes. The agent repeats this process and learns the course of action that will obtain the most reward through a series of actions. Q-learning and TD-learning are known as representative reinforcement learning methods. For example, in the case of Q-learning, a general update formula for the action value function Q(s, a) is expressed as Equation (1).

[0028]

[0029] In equation (1), st represents the state of the environment at time t, and at represents the action at time t. Action at changes the state to st+1. rt+1 represents the reward obtained due to the change in state, γ represents the discount rate, and α represents the learning coefficient. Note that γ is in the range of 0<γ≦1, and α is in the range of 0<α≦1. The bus occupation time becomes action at, the transfer request becomes state st, and the best action at in state st at time t is learned.

[0030] The update formula expressed by equation (1) increases the action value function Q(s, a) if the action value function Q of the action a with the highest Q value at time t+1 is greater than the action value function Q of the action a executed at time t, and decreases the action value function Q if the opposite is true. In other words, the action value function Q(s, a) is updated so that the action value function Q of the action a at time t approaches the best action value at time t+1. This allows the best action value in a certain environment to be propagated sequentially to the action value in the previous environment.

[0031] As described above, when generating a trained model by reinforcement learning, the model generation unit 22 includes a reward calculation unit 23 and a function update unit 24.

[0032] The reward calculation unit 23 calculates a reward based on data relating to past transfer requests acquired from the transfer request storage device 11 and the transfer time storage device 12. The reward calculation unit 23 calculates a reward r based on transfer requests classified by attribute. For example, the reward calculation unit 23 increases the reward r (for example, gives a reward of "1") in the case of an attribute having a priority such that the bus occupation time is shorter than the first occupation time, and on the other hand, decreases the reward r (for example, gives a reward of "-1") in the case of an attribute having a priority such that the bus occupation time is longer than the second occupation time.

[0033] The function update unit 24 updates the function for determining the priority for making the bus occupation time shorter than the first occupation time in accordance with the reward calculated by the reward calculation unit 23, and outputs the updated function to the trained model storage device 16. For example, in the case of Q-learning, the action value function Q(st, at) expressed by equation (1) is used as the function for calculating the priority for making the bus occupation time shorter than the first occupation time.

[0034] The learning process described above is repeated. The learned model storage device 16 stores the action-value function Q(st,at) updated by the function update unit 24, i.e., the learned model.

[0035] Next, the learning process performed by the learning device 13 will be described with reference to Fig. 4. Fig. 4 is a flowchart showing the learning process performed by the learning device 13 according to the first embodiment.

[0036] In step b1, the data acquisition unit 21 acquires data relating to past transfer requests from the transfer request storage device 11 and the transfer time storage device 12 as learning data.

[0037] In step b2, the model generation unit 22 classifies the learning data by attributes of past transfer requests. The model generation unit 22 calculates a reward based on the response time of the bus slave S. Specifically, the reward calculation unit 23 classifies the learning data by attributes of the transfer requests, obtains the response time of the bus slave S for the classified attributes, and determines whether to increase or decrease the reward based on a predetermined bus occupation time.

[0038] If the remuneration calculation unit 23 determines that the remuneration should be increased, it increases the remuneration in step b3. On the other hand, if the remuneration calculation unit 23 determines that the remuneration should be decreased, it decreases the remuneration in step b4.

[0039] In step b5, the function update unit 24 updates the action value function Q(st, at) represented by equation (1) stored in the trained model storage device 16 based on the reward calculated by the reward calculation unit 23.

[0040] The learning device 13 repeatedly executes the above steps b1 to b5. The generated action-value function Q(st, at) is stored in the learned model storage device 16 as a learned model.

[0041] The learning device 13 in this embodiment stores the learned model in a learned model storage device 16 provided outside the learning device 13, but the learned model storage device 16 may also be provided inside the learning device 13.

[0042] 5 is a configuration diagram of the inference device 14. The inference device 14 includes a data acquisition unit 31 and an inference unit 32.

[0043] The data acquisition unit 31 acquires a transfer request from the bus master M. The inference unit 32 uses the learned model to infer a priority that will result in a bus occupation time that is shorter than the first occupation time. That is, by inputting the transfer request acquired by the data acquisition unit 31 into this learned model, it is possible to infer a priority that will result in a bus occupation time that is shorter than the first occupation time that is suitable for the transfer request of the bus master M during a predetermined period.

[0044] In this embodiment, it has been described that a learned model learned by the model generation unit 22 of the bus control device 10 is used to output a priority that will make the bus occupation time of the transfer request arbitration device 15 shorter than the first occupation time, but it is also possible to obtain a learned model from another bus control device 10 and output a priority that will make the bus occupation time of the transfer request arbitration device 15 shorter than the first occupation time based on this learned model.

[0045] Next, a process for obtaining a priority that makes the bus occupation time of the transfer request arbitration device 15 shorter than the first occupation time using a trained model will be described with reference to Fig. 6. Fig. 6 is a flowchart showing the inference process of the inference device 14 according to the first embodiment.

[0046] In step c1, the data acquisition unit 31 acquires a transfer request from the bus master M.

[0047] In step c2, the inference unit 32 inputs the transfer request obtained in step c1 into the learned model stored in the learned model storage device 16, and obtains a priority that results in a bus occupancy time that is shorter than the first occupancy time.

[0048] In step c3, the inference unit 32 outputs to the transfer request arbitration unit 15 the priority that will result in the obtained bus occupation time being shorter than the first occupation time.

[0049] In step c4, the transfer request arbitration device 15 arbitrates bus access using a priority that results in the output bus occupation time being shorter than the first occupation time, thereby enabling priority to be assigned to each transfer request, thereby improving transmission efficiency.

[0050] In this embodiment, a case where reinforcement learning is applied to the learning algorithm used by the inference unit 32 has been described, but the present invention is not limited to this. As for the learning algorithm, other than reinforcement learning, supervised learning, unsupervised learning, semi-supervised learning, or the like can also be applied.

[0051] Furthermore, the learning algorithm used in the model generation unit 22 may be deep learning, which learns to extract the features themselves, or machine learning may be performed according to other known methods, such as neural networks, genetic programming, functional logic programming, and support vector machines.

[0052] The learning device 13 and the inference device 14 may be connected to the bus control device 10 via a network, for example, and may be separate devices from the bus control device 10. Alternatively, the learning device 13 and the inference device 14 may be built into the bus control device 10. Furthermore, the learning device 13 and the inference device 14 may exist on a cloud server.

[0053] The model generation unit 22 may also learn the response time information of the bus slave S using learning data acquired from multiple bus control devices 10. The model generation unit 22 may acquire learning data from multiple bus control devices 10 used in the same area, or may learn the response time information of the bus slave S using learning data collected from multiple bus control devices 10 operating independently in different areas. It is also possible to add or remove bus control devices 10 that collect learning data from the target devices during the learning process. Furthermore, the learning device 13 that learned the response time information of the bus slave S for a certain bus control device 10 may be applied to another bus control device 10, and the response time information of the bus slave S for the other bus control device 10 may be re-learned and updated.

[0054] Variation 1 of Embodiment 1 In the above embodiment, the learning device 13 generates the trained model using reinforcement learning, but the learning device 13 may also generate the trained model using supervised learning.

[0055] The transfer request storage device 11 and the transfer time storage device 12 store past transfer requests output by a plurality of bus masters M, priorities set for the transfer requests, and bus occupation times for data transfers based on the transfer requests.

[0056] The data acquisition unit 21 of the learning device 13 acquires, as learning data, the attributes (input data) and the set priority (teacher data) of past transfer requests for which the bus occupation time is shorter than the first occupation time.

[0057] The model generation unit 22 of the learning device 13 generates a trained model that estimates a priority that results in a bus occupation time that is shorter than the first occupation time from the attributes of the transfer request through supervised learning using the training data. The generated trained model is stored in the trained model storage device 16.

[0058] The data acquisition unit 31 of the inference device 14 acquires attributes of a transfer request from the bus master M. The inference unit 32 of the inference device 14 estimates a priority for making the bus occupation time shorter than the first occupation time from the attributes of the transfer request acquired by the data acquisition unit 31, using a learned model that estimates a priority for making the bus occupation time shorter than the first occupation time from the attributes of the transfer request.

[0059] The transfer request arbitration device 15 rearranges the processing order of transfer requests output by the multiple bus masters M according to the priority inferred by the inference unit 32 .

[0060] Modification 2 of Embodiment 1 The trained model storage device 16 stores trained models that match three access request patterns.

[0061] The learning device 13 uses as learning data a pattern in which the proportion of transfer requests whose bus occupation time is shorter than the first occupation time is equal to or greater than a first threshold (e.g., 80%), to create a learned model 1. The learning device 13 uses as learning data a pattern in which the proportion of transfer requests whose bus occupation time is longer than the second occupation time is equal to or greater than a first threshold (e.g., 80%), to create a learned model 2. The learning device 13 uses as learning data a pattern in which the proportion of transactions whose bus occupation time is shorter than the first occupation time is 50% and the proportion of transactions whose bus occupation time is longer than the second occupation time is 50%, to create a learned model 3.

[0062] The inference device 14 holds a predetermined number of transfer requests and calculates the ratio of transfer requests whose bus occupation time is shorter than the first occupation time and transfer requests whose bus occupation time is longer than the second occupation time, thereby selecting one of the learned models 1, 2, and 3. The inference device 14 performs inference using the selected learned model. The transfer request arbitration device 15 arbitrates the transfer requests based on the inference result.

[0063] For example, when the inference device 14 is performing inference using learned model 1, if the pattern of the arbitration result by the transfer request arbitration device 15 matches learned model 2, the inference device 14 switches the learned model to be used to learned model 2 and performs inference, and the transfer request arbitration device 15 arbitrates the transfer request based on the inference result.

[0064] Modification 3 of Embodiment 1. A semiconductor device includes a plurality of bus masters, a plurality of bus slaves, a bus interconnecting the plurality of bus masters and the plurality of bus slaves and performing address transfer and data transfer between the plurality of bus masters and the plurality of bus slaves, and a bus control device controlling the address transfer and data transfer via the bus. The bus control device includes: a transfer request storage device that stores transfer request information output by a plurality of bus masters; a transfer time storage device that stores times at which bus slaves respond to transfer requests output by the plurality of bus masters; a learning unit that acquires past information from the transfer request storage device and the transfer time storage device, classifies the past transfer requests by attribute, and selects an attribute having a priority such that the bus occupation time is shorter than a first occupation time from information on the response times of bus slaves belonging to that attribute, and performs true learning of that attribute, and also classifies the past transfer requests by attribute, and selects an attribute having a bus occupation time longer than a predetermined time from information on the response times of bus slaves belonging to that attribute, and performs false learning of that attribute, thereby executing a learning process to infer a priority such that the bus occupation time is shorter than the first occupation time; an inference unit that performs inference processing to infer a priority such that the bus occupation time is shorter than the first occupation time from the past information from the transfer request storage device and the transfer time storage device and the transfer request information output by the bus masters; and a transfer request arbitration device that rearranges the processing order of transfer requests output by the plurality of bus masters according to the priority inferred by the inference unit.

[0065] The learning unit may include a data acquisition unit that acquires learning data including the priority to be given to the transfer request arbitration device and the response time of the bus slave, and the priority of the transfer request arbitration device and the response time of the bus slave obtained by accumulating access requests of the bus master over a predetermined period, and a model generation unit that uses the learning data to generate a learned model for inferring the priority and the response time of the bus slave from the accumulation of access requests of the bus master over a predetermined period of the semiconductor device.

[0066] The learning unit may increase the learning reward according to the degree of shortening of the average bus occupation time, the degree of reduction in the transfer request acceptance time of the bus slave, or the degree of reduction in the transfer request acceptance time of the bus master, as a criterion for increasing the reward in learning.

[0067] The transfer request acceptance time of a bus master is the time from when the bus master transmits a transfer request to when the bus master receives bus access rights. The transfer request acceptance time of a bus slave is the time from when the bus master transmits a transfer request to when the bus master is granted bus access rights, transmits a transfer request to the bus slave, and the bus slave receives the transfer request.

[0068] The learning unit may reduce the learning reward according to the degree of increase in the average bus occupation time, the degree of increase in the transfer request acceptance time of the bus slave, or the degree of increase in the transfer request acceptance time of the bus master, as a criterion for reducing the learning reward.

[0069] The inference unit may include a data acquisition unit that acquires access requests from bus masters over a predetermined period of time, and an inference unit that outputs the priority and the response time of the bus slave from the access requests from the bus masters over the predetermined period of time acquired by the data acquisition unit using a trained model for inferring the priority of the semiconductor device and the response time of the bus slave from the access requests from the bus masters over the predetermined period of time.

[0070] The inference device may be provided with a trained model memory unit that holds multiple trained models so that the trained model to be used in accordance with the pattern of the access request can be selected to arbitrate the access request.

[0071] Second Embodiment <Learning Phase> The transfer request arbitration device 15 acquires transfer requests from the bus master M. When transfer requests from multiple bus masters M conflict, the transfer request arbitration device 15 outputs the conflicting transfer requests to the learning device 13.

[0072] The data acquisition unit 21 acquires learning data including competing transfer requests from multiple bus masters M and transfer requests that grant bus access rights among the competing transfer requests from multiple bus masters M. The transfer requests include the address of the bus master M, the address of the bus slave S, the size of the data to be transferred, and the time when the transfer requests were received.

[0073] The model generation unit 22 uses the learning data to generate a learned model (behavior) that determines, from competing transfer requests (states) from multiple bus masters M, which transfer request will be granted bus access rights among the competing transfer requests from multiple bus masters M.

[0074] The transfer request arbitration device 15 grants bus access rights to transfer requests to which bus access rights are to be granted, among a plurality of transfer requests.

[0075] The learning algorithm used by the model generation unit 22 may be a known algorithm such as supervised learning, unsupervised learning, or reinforcement learning. As an example, a case where reinforcement learning is applied will be described. In reinforcement learning, an agent (acting subject) in a certain environment observes the current state (environmental parameters) and determines the action to be taken. The environment changes dynamically depending on the agent's actions, and the agent is given a reward according to the environmental changes. The agent repeats this process and learns the course of action that will obtain the most reward through a series of actions. Q-learning and TD-learning are known as representative reinforcement learning methods. For example, in the case of Q-learning, a general update formula for the action value function Q(s, a) is expressed as Equation (1).

[0076] In equation (1), st represents the state of the environment at time t, and at represents the action at time t. The action at changes the state to st+1. rt+1 represents the reward obtained due to the change in state, γ represents the discount rate, and α represents the learning coefficient. Note that γ is in the range of 0<γ≦1, and α is in the range of 0<α≦1. Multiple competing transfer requests become the state st, and the decision on which of the multiple competing transfer requests to grant bus access rights becomes the action at, and the best action at in the state st at time t is learned.

[0077] The update formula expressed by equation (1) increases the action value function Q(s, a) if the action value function Q of the highest action a at time t+1 is greater than the action value function Q of the action a executed at time t, and decreases the action value function Q if the opposite is true. In other words, the action value function Q(s, a) is updated so that the action value function Q of the action a at time t approaches the best action value at time t+1. This allows the best action value in a certain environment to be propagated sequentially to the action value in the previous environment.

[0078] The reward calculation unit 23 calculates the transaction time of a transfer request as the difference between the time when the transfer request with granted bus access rights is received and the time when data transmission based on that transfer request is completed. The reward calculation unit 23 calculates the average transaction time based on the time of one or more past transactions and the calculated transaction time. If the average transaction time decreases, the reward calculation unit 23 increases the reward r (for example, gives a reward of "1"), and if the average transaction time increases, the reward calculation unit 23 decreases the reward r (for example, gives a reward of "-1").

[0079] The function update unit 24 updates a function for determining which of a plurality of competing transfer requests is to be granted the bus access right, in accordance with the calculated reward, and outputs the updated function to the learned model storage device 16. In the case of Q-learning, for example, the function update unit 24 uses the action value function Q(st, at) expressed by equation (1) as a function for determining which of a plurality of competing transfer requests is to be granted the bus access right.

[0080] The learning process described above is repeated. The learned model storage device 16 stores the action-value function Q(st,at) updated by the function update unit 24, i.e., the learned model.

[0081] Next, the learning process performed by the learning device 13 will be described with reference to Fig. 7. Fig. 7 is a flowchart showing the learning process performed by the learning device 13 according to the second embodiment.

[0082] In step d1, if the transfer request arbitration device 15 determines that transfer requests from a plurality of bus masters M conflict, the process proceeds to step d2.

[0083] In step d2, the transfer request arbitration device 15 outputs the attributes of the conflicting transfer requests to the learning device 13. The data acquisition unit 21 acquires the conflicting transfer requests from the bus master M.

[0084] In step d3, the model generation unit 22 determines, based on the action value function Q(st, at), which of the competing transfer requests to which the bus access right is to be granted. The model generation unit 22 outputs the transfer request for which it has been determined that the bus access right is to be granted to the transfer request arbitration device 15. The transfer request arbitration device 15 transmits a signal granting the bus access right to the bus master M that has transmitted the transfer request for which it has been determined that the bus access right is to be granted. Data is transferred between the bus master M and the bus slave S.

[0085] In step d4, the remuneration calculation unit 23 calculates the transaction time of the transfer request to which the bus access right has been granted. The remuneration calculation unit 23 calculates the average transaction time MT based on the time of one or more past transactions and the calculated transaction time.

[0086] In steps d5 and d7, if the average transaction time MT decreases, the process proceeds to step d6, and if the average transaction time MT increases, the process proceeds to step d8.

[0087] In step d6, the remuneration calculation unit 23 increases the remuneration. In step d8, the remuneration calculation unit 23 decreases the remuneration.

[0088] In step d9, the function update unit 24 updates the action value function Q(st, at) stored in the trained model storage unit based on the reward.

[0089] The learning device 13 repeatedly executes the above steps d1 to d9 and stores the generated action value function Q(st, at) as a learned model in the learned model storage device 16.

[0090] <Utilization Phase> The transfer request arbitration device 15 acquires transfer requests from the bus masters M. When transfer requests from multiple bus masters M conflict, the transfer request arbitration device 15 outputs the conflicting transfer requests to the inference device 14.

[0091] The inference device 14 uses the action value function Q(st, at) that is a learned model to infer which transfer request among a plurality of competing transfer requests should be granted the bus access right.

[0092] The data acquisition unit 31 acquires competing transfer requests from multiple bus masters M. The transfer request includes the address of the bus master M, the address of the bus slave S, the size of the data to be transferred, and the time when the transfer request was received.

[0093] The inference unit 32 determines, from the competing transfer requests from the multiple bus masters M acquired by the data acquisition unit 31, a transfer request to which bus access rights will be granted, using a learned model that determines, from the competing transfer requests from the multiple bus masters M, a transfer request to which bus access rights will be granted, from the competing transfer requests from the multiple bus masters M.

[0094] 8 is a diagram illustrating an example of state and behavior transitions during learning. BUSREQ1, BUSREQ2, and BUSREQ3 represent transfer requests from bus masters M1, M2, and M3, respectively. BUSACK1, BUSACK2, and BUSACK3 represent granting of access rights to bus masters M1, M2, and M3, respectively. BUSIF represents data transmitted to bus 100. M1 represents data transfer from a bus slave to bus master M1, M2 represents data transfer from the bus slave to bus master M2, and M3 represents data transfer from the bus slave to bus master M3.

[0095] At time t1, BUSREQ1, BUSREQ2, and BUSREQ3 compete with each other. At time t2, the access right BUSACK1 is granted to bus master M1 based on the action value function Q, and data transfer to bus master M1 begins.

[0096] At time t3, BUSREQ1 ends. At time t4, the access right BUSACK1 of bus master M1 ends, and data transfer to bus master M1 ends. The average transaction time MT is updated, and as a result, the action value function Q is updated.

[0097] Immediately after time t4, BUSREQ2 and BUSREQ3 compete with each other. At time t5, the access right BUSACK2 is granted to bus master M2 based on the action value function Q, and data transfer to bus master M2 begins.

[0098] At time t6, BUSREQ2 ends. At time t7, the access right BUSACK2 of bus master M2 ends, and the data transfer to bus master M2 ends. The average transaction time MT is updated, and as a result, the behavior value function Q is updated.

[0099] Immediately after time t7, BUSREQ1 and BUSREQ3 compete with each other. At time t8, the access right BUSACK3 is granted to bus master M3 based on the action value function Q, and data transfer to bus master M3 begins.

[0100] At time t9, BUSREQ3 ends. At time t10, the access right BUSACK3 of bus master M3 ends, and data transfer to bus master M3 ends. The average transaction time MT is updated, and as a result, the action value function Q is updated.

[0101] Immediately after time t10, only BUSREQ1 is activated. At time t11, the access right BUSACK1 is granted to the bus master M1, and data transfer to the bus master M1 begins.

[0102] At time t12, BUSREQ1 ends. At time t13, the access right BUSACK1 of the bus master M1 ends, and the data transfer to the bus master M1 ends.

[0103] Immediately after time t13, BUSREQ2 and BUSREQ3 compete with each other. At time t14, the access right BUSACK2 is granted to bus master M2 based on the action value function Q, and data transfer to bus master M2 begins.

[0104] At time t15, BUSREQ2 ends. At time t16, the access right BUSACK2 of bus master M2 ends, and the data transfer to bus master M2 ends. The average transaction time MT is updated, and as a result, the behavior value function Q is updated.

[0105] Immediately after time t16, BUSREQ1 and BUSREQ3 compete with each other. At time t17, the access right BUSACK3 is granted to bus master M3 based on the action value function Q, and data transfer to bus master M3 begins.

[0106] At time t8, BUSREQ3 ends. At time t19, the access right BUSACK3 of bus master M3 ends, and data transfer to bus master M3 ends. The average transaction time MT is updated, and as a result, the behavior value function Q is updated.

[0107] Immediately after time t19, BUSREQ1 and BUSREQ2 compete with each other. At time t20, the access right BUSACK1 is granted to bus master M1 based on the action value function Q, and data transfer to bus master M1 begins.

[0108] At time t21, BUSREQ1 ends. At time t22, the access right BUSACK1 of bus master M3 ends, and the data transfer to bus master M1 ends. The average transaction time MT is updated, and as a result, the action value function Q is updated.

[0109] Next, the processing of the inference device 14 will be described with reference to Fig. 9. Fig. 9 is a flowchart showing the inference processing of the inference device 14 according to the second embodiment.

[0110] In step e1 , when transfer requests from a plurality of bus masters M conflict, the data acquisition unit 31 acquires the conflicting transfer requests from the transfer request arbitration device 15 .

[0111] In step e2, the inference unit 32 determines, from among the multiple competing transfer requests, a transfer request to which the bus access right is to be granted, using the action value function Q(st, at), which is a learned model. The inference unit 32 outputs the transfer request to which the bus access right has been granted to the transfer request arbitration device 15.

[0112] In step e3, the transfer request arbitration device 15 transmits a signal granting the bus access right to the bus master M that transmitted the transfer request for which it was determined that the bus access right should be granted. Data is transferred between the bus master M and the bus slave S.

[0113] Variation 1 of Embodiment 2: The model generation unit 22 may increase the reward when the average bus waiting time decreases as a result of the granting of bus access rights, and may decrease the reward when the average bus waiting time increases as a result of the granting of bus access rights. The average bus waiting time is the average waiting time during which no data is transmitted to the bus within a predetermined period of time.

[0114] Modification 2 of Embodiment 2: The model generation unit 22 may increase the reward when the average waiting time of the bus master M decreases as a result of the bus access right being granted, and may decrease the reward when the average waiting time of the bus master M increases as a result of the bus access right being granted. The average waiting time of the bus master M is the average time from when the bus master M transmits a transfer request until when it receives the bus access right.

[0115] In the first and second embodiments, the bus control device 10 may perform the corresponding operations using digital circuit hardware or software.

[0116] 10 is a diagram showing a configuration in which the functions of the bus control device 10 are realized using software. The bus control device 10 includes a processor 1001 and a memory 1002 connected to a bus 100. The processor 1001 executes a program stored in the memory 1002.

[0117] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0118] 1 semiconductor device, 10 bus control device, 11 transfer request storage device, 12 transfer time storage device, 13 learning device, 14 inference device, 15 transfer request arbitration device, 16 learned model storage device, 21, 31 data acquisition unit (data acquisition device), 22 model generation unit (model generator), 23 reward calculation unit (reward calculator), 24 function update unit (function updater), 32 inference unit (inference device), 100 bus, 1001 processor, 1002 memory, M1 to MN bus masters, S1 to SN bus slaves.

Claims

1. a plurality of bus masters; A plurality of bus slaves; a bus interconnecting the plurality of bus masters and the plurality of bus slaves and for performing address transfer and data transfer between the plurality of bus masters and the plurality of bus slaves; a bus control device for controlling the address transfer and the data transfer via the bus; The bus control device a storage device that stores past transfer requests output by the plurality of bus masters, priorities set for the transfer requests, and bus occupation times for data transfers based on the transfer requests; A learning device is provided. The learning device a data acquisition unit that acquires, from the storage device, attributes of transfer requests whose bus occupation time is shorter than a first occupation time and priorities of the transfer requests as learning data; a model generation unit that uses the learning data to generate a trained model that estimates a priority that will result in a bus occupation time that is shorter than a first occupation time, based on attributes of a transfer request.

2. 2. The learning device according to claim 1, wherein the model generation unit increases a reward when the bus occupation time is shorter than a first occupation time, and decreases the reward when the bus occupation time is longer than a second occupation time that is longer than the first occupation time.

3. the bus control device further comprises an inference device; a data acquisition unit that acquires attributes of a transfer request from a bus master; 2. The semiconductor device according to claim 1, further comprising: an inference unit that uses a learned model that infers a priority that will result in a bus occupation time that is shorter than a first occupation time from attributes of the transfer request acquired by the data acquisition unit, and that infers a priority that will result in a bus occupation time that is shorter than a first occupation time from attributes of the transfer request.

4. The bus control device further comprises:

4. The semiconductor device according to claim 3, further comprising a transfer request arbitration unit that rearranges the processing order of transfer requests output by said plurality of bus masters in accordance with the priorities inferred by said inference unit.

5. The bus control device further comprises:

2. The semiconductor device according to claim 1, further comprising: a trained model storage device that stores a plurality of the trained models, so as to enable selection of the trained model to be used in accordance with a pattern of the transfer requests in order to arbitrate the transfer requests.

6. a data acquisition unit that acquires learning data including competing transfer requests from a plurality of bus masters and transfer requests that grant bus access rights among the competing transfer requests from the plurality of bus masters; a model generation unit that generates a trained model that determines, from competing transfer requests from a plurality of bus masters, a transfer request to which a bus access right is to be granted, using the training data; The model generation unit increases a reward when the average transaction time decreases as a result of the granting of the bus access right, and decreases the reward when the average transaction time increases as a result of the granting of the bus access right.

7. 7. The learning device according to claim 6, wherein the model generation unit increases a reward when the average bus waiting time decreases as a result of the granting of the bus access right, and decreases a reward when the average bus waiting time increases as a result of the granting of the bus access right.

8. 7. The learning device according to claim 6, wherein the model generation unit increases a reward when the average waiting time of the bus master decreases as a result of the bus access right being granted, and decreases a reward when the average waiting time of the bus master increases as a result of the bus access right being granted.