Semiconductor device, power conversion device and method for manufacturing semiconductor device

Abstract

This semiconductor device is provided with: a semiconductor layer (3) having a first conductivity type; a back gate region (4) which is a diffusion layer provided in a surface layer part of the semiconductor layer (3) and having a second conductivity type; a trench (6) which is provided in the semiconductor layer (3) and penetrates through the back gate region (4); a gate insulating film (10) which is provided on the inner surface of the trench (6); a gate electrode (11) which is provided on the gate insulating film (10) and is embedded in the trench (6); and an electric field attenuated layer (7) which is a diffusion layer provided in the semiconductor layer (3) below the trench (6) so as to cover the bottom of the trench (6) and having the second conductivity type. The width of the bottom of the electric field attenuated layer (7) is smaller than the width of the entire electric field attenuated layer (7), and is smaller than the width of the bottom of the trench (6).

Description

Semiconductor device, power conversion device, and method of manufacturing the semiconductor device

[0001] The present disclosure relates to a semiconductor device, and more particularly to a trench gate type semiconductor device.

[0002] A trench-gate MOSFET (hereinafter referred to as a "trench MOSFET") is known, in which a gate electrode is disposed in a trench formed in a semiconductor layer. In a trench MOSFET, a channel region is formed in the depth direction of a semiconductor substrate, allowing a large current to flow per unit area.

[0003] Furthermore, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed using a silicon carbide (SiC) substrate has a high critical electric field and a high off-state breakdown voltage because the band gap of SiC is larger than that of Si. However, the critical electric field of a trench MOSFET formed using a SiC substrate (hereinafter referred to as an "SiC trench MOSFET") is high at the bottom of the trench in which the gate electrode is embedded. Therefore, a high electric field is applied to the gate insulating film at the bottom of the trench, raising concerns that the gate insulating film may be destroyed at the bottom of the trench.

[0004] For example, Patent Document 1 discloses a technology for alleviating the electric field acting on the gate insulating film at the bottom of a trench by providing a P-type electric field relaxation region to cover the bottom of the trench in which the gate electrode is buried, and providing a P-type diffusion layer on the side of the trench that electrically connects the electric field relaxation region and the P-type well.

[0005] International Publication No. 2018 / 225600

[0006] As in the technology of Patent Document 1, if a P-type electric field relaxation region is provided to cover the bottom of the trench and a P-type diffusion layer that electrically connects the electric field relaxation region and the P-type well is provided on the side of the trench, the resistance of the JFET region (hereinafter referred to as "JFET resistance"), which is the region between the trenches, becomes high, resulting in the problem of an increase in the on-resistance of the MOSFET.

[0007] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that can prevent breakdown of the gate insulating film at the bottom of the trench while suppressing an increase in on-resistance.

[0008] The semiconductor device according to the present disclosure comprises a semiconductor layer of a first conductivity type, a back gate region which is a diffusion layer of a second conductivity type provided in a surface layer portion of the semiconductor layer, a trench provided in the semiconductor layer and penetrating the back gate region, a gate insulating film provided on an inner surface of the trench, a gate electrode provided on the gate insulating film and embedded in the trench, and an electric field relaxation layer which is a diffusion layer of the second conductivity type provided in the semiconductor layer below the trench and covers a bottom of the trench, wherein the width of the bottom of the electric field relaxation layer is smaller than the overall width of the electric field relaxation layer and is also smaller than the width of the bottom of the trench, and the angle formed by the side surface and the bottom surface of the bottom of the electric field relaxation layer is greater than or equal to 60° and less than 90°.

[0009] According to the semiconductor device according to the present disclosure, it is possible to prevent breakdown of the gate insulating film at the bottom of the trench while suppressing an increase in on-resistance.

[0010] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment. FIG. 3 is a diagram showing a current flow when the semiconductor device according to the first embodiment is on. FIG. 4 is a diagram showing a current flow when the semiconductor device of the comparative example is on. FIG. 5 is a diagram for explaining a manufacturing method of the semiconductor device according to the first embodiment. FIG. 6 is a diagram for explaining a manufacturing method of the semiconductor device according to the first embodiment. FIG. 7 is a diagram for explaining a manufacturing method of the semiconductor device according to the first embodiment. FIG. 8 is a diagram for explaining a manufacturing method of the semiconductor device according to the first embodiment. FIG. 9 is a diagram for explaining a manufacturing method of the semiconductor device according to the first embodiment. FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment. FIG. 12 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a fourth embodiment is applied.

[0011] In the following embodiments, the first conductivity type will be described as N-type and the second conductivity type as P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. ＋ ", and P-type with a relatively high impurity concentration is called "P ＋ Here, the impurity concentration of each region is defined by the peak concentration. That is, a region with a high (or low) impurity concentration means a region with a high (or low) peak impurity concentration.

[0012] 1 and 2 are diagrams showing the configuration of a SiC trench MOSFET, which is a semiconductor device according to embodiment 1. Fig. 1 is a plan view of the semiconductor device, and Fig. 2 is a cross-sectional view of a region 101 taken along line A1-A2 and a region 102 taken along line B1-B2 shown in Fig. 1.

[0013] 2 , the semiconductor device according to the first embodiment is formed using a semiconductor substrate 1 made of N-type (first conductivity type) SiC. An N-type buffer layer 2 having a lower impurity concentration than the semiconductor substrate 1 is formed on the semiconductor substrate 1. An epitaxial layer 3, which is an N-type semiconductor layer having a lower impurity concentration than the buffer layer 2, is formed on the buffer layer 2.

[0014] A back gate region 4, which is a P-type diffusion layer into which P-type (second conductivity type) ion species (e.g., aluminum, boron, etc.) are implanted, is formed in the surface layer of the epitaxial layer 3. The surface layer of the back gate region 4 contains N ＋ A source region 5, which is a type diffusion layer, is formed.

[0015] A trench 6 having a depth of several μm is formed on the upper surface of the epitaxial layer 3. At the bottom of the trench 6, an electric field relaxation layer 7, which is a P-type diffusion layer into which P-type ion species (e.g., aluminum, boron, etc.) have been implanted, is formed.

[0016] In a cross-sectional view, the overall width of the electric field relaxation layer 7 is the same as the width of the bottom of the trench 6, but the width of the bottom of the electric field relaxation layer 7 is smaller than the overall width and is also smaller than the width of the bottom of the trench 6. An angle 7a formed by the side surface and the bottom surface of the bottom of the electric field relaxation layer 7 is 60° or more and less than 90°. In addition, the width of the bottom of the electric field relaxation layer 7 is 40% or more and 90% or less of the width of the bottom of the trench 6.

[0017] In the region 102 along the line B1-B2, a connection layer 8, which is a P-type diffusion layer, is formed to connect the back gate region 4 and the electric field relaxation layer 7.

[0018] The inside of the source region 5 is formed with a P ＋ A contact layer 9, which is a type diffusion layer, is selectively formed on the source region 5. The contact layer 9 penetrates the source region 5 and is connected to the back gate region 4 below the source region 5.

[0019] In the epitaxial layer 3 , the N-type region remaining without the back gate region 4 , source region 5 , field relaxation layer 7 , connection layer 8 and contact layer 9 becomes a drift layer 31 .

[0020] A gate insulating film 10 is formed on the inner surfaces (bottom and side surfaces) of the trench 6. A gate electrode 11 is formed on the gate insulating film 10 so as to fill the trench 6.

[0021] An interlayer insulating film 12 is formed so as to cover the gate electrode 11. A contact hole 13 is formed in the interlayer insulating film 12, reaching the source region 5 and the contact layer 9. That is, the width of the contact hole 13 is P ＋ 1 shows the structure of the upper surface of the epitaxial layer 3, and elements formed above the epitaxial layer 3 are not shown, but the position of the contact hole 13 is indicated by a dotted line.

[0022] A source electrode 16 is formed on the interlayer insulating film 12. The source electrode 16 is electrically connected to the source region 5 and the contact layer 9 through the contact hole 13. The contact layer 9 realizes an ohmic connection between the source electrode 16 and the back gate region 4.

[0023] In this embodiment, the source electrode 16 is made of aluminum or AlSi, and a barrier metal 15 made of Ti or TiN is provided below the source electrode 16. Therefore, the source electrode 16 is connected to the source region 5 and the contact layer 9 via the barrier metal 15 and the silicide 14.

[0024] Fig. 3 is a cross-sectional view showing the current flow when the SiC trench MOSFET of the first embodiment is on. Fig. 4 is a diagram showing the current flow when the SiC trench MOSFET, which is a semiconductor device of a comparative example, is on. In Fig. 4, elements that are the same as or correspond to those shown in Figs. 1 and 2 are given the same reference numerals.

[0025] In the semiconductor device of the comparative example, in a cross-sectional view, the overall width of the electric field relaxation layer 7 is the same as the width of the bottom of the trench 6, and the width of the bottom of the electric field relaxation layer 7 is also the same as the width of the bottom of the trench 6. The other configurations are the same as those of the semiconductor device of the first embodiment.

[0026] 3 and 4 , the flow of current in the SiC trench MOSFET in the on state will be described. When a potential of 0.0 V is applied to the source electrode 16 and a potential of several volts is applied to the gate electrode 11 and the back surface of the semiconductor substrate 1, an N-type inversion layer 23 (channel layer) is formed in the portion of the back gate region 4 that contacts the trench 6, and an N-type accumulation layer 24 is formed in the portion of the drift layer 31 that contacts the trench 6. That is, the inversion layer 23 is formed in the back gate region 4 on the sidewall of the trench 6, and the accumulation layer 24 is formed in the drift layer 31 on the sidewall of the trench 6.

[0027] When inversion layer 23 and accumulation layer 24 are formed on the sidewall of trench 6, current 201 flows from the back surface of semiconductor substrate 1 toward source electrode 16. When current 201 flows through drift layer 31 and reaches the vicinity of trench 6, it generates current 203, which collides with electric field relaxation layer 7 at the bottom of trench 6 and then flows into inversion layer 23 and accumulation layer 24, and current 202, which flows directly into inversion layer 23 and accumulation layer 24 without colliding with electric field relaxation layer 7.

[0028] In region 101 along line A1-A2 where connection layer 8 is not present, currents 202 and 203 flow to source electrode 16 through drift layer 31 between electric field relaxation layers 7, and accumulation layer 24 and inversion layer 23 formed on the sidewall of trench 6. On the other hand, in region 102 along line B1-B2 where connection layer 8 is present, currents 202 and 204 flow to source electrode 16 through drift layer 31 between electric field relaxation layer 7 and connection layer 801, and accumulation layer 24 and inversion layer 23 formed on the sidewall of trench 6.

[0029] In this way, currents 202 and 203 generated from current 201 flowing from the back surface of semiconductor substrate 1 toward source electrode 16 flow into a region of drift layer 31 where field relaxation layer 7 and connection layer 8 are not formed. Therefore, the amount of current 202 and current 203 is limited by field relaxation layer 7 and connection layer 8. The degree of this limitation is defined as JFET resistance. In region 102 where connection layer 8 is present, the path through which the current flows (current path) is narrowed by the width of connection layer 8, so JFET resistance 222 in region 102 where connection layer 8 is present is higher than JFET resistance 221 in region 101 where connection layer 8 is not present.

[0030] The on-resistance of a MOSFET is an index representing the performance of the MOSFET when it is on, and corresponds to the sum of the channel resistance, which is the resistance of the inversion layer 23, the JFET resistance, and the drain resistance, which is the resistance of the drift layer 31. Therefore, as the areas of the field relaxation layer 7 and the connection layer 8 become larger, the JFET resistance increases, and the on-resistance also increases, resulting in a decrease in the performance of the MOSFET when it is on.

[0031] As can be seen by comparing the current flow in the semiconductor device according to the first embodiment shown in Figure 3 with the semiconductor device of the comparative example shown in Figure 4, in the semiconductor device according to the first embodiment, the width of the bottom of the electric field relaxation layer 7 is smaller than the width of the bottom of the trench 6, and therefore the width of the region of the drift layer 31 where the electric field relaxation layer 7 and the connection layer 8 are not formed, which is the entrance of the current path, is wider. Therefore, in the semiconductor device according to the first embodiment, the amount of current 202 that flows without hitting the electric field relaxation layer 7 increases (the amount of current 203 that hits the electric field relaxation layer 7 decreases) compared to the semiconductor device of the comparative example, and the limit on the amount of current, i.e., the JFET resistances 221 and 222, are reduced. Therefore, the semiconductor device according to the first embodiment has a small on-resistance and a small loss.

[0032] Furthermore, in the semiconductor device according to the first embodiment, the bottom of the trench 6 is covered with the electric field relaxation layer 7, which also provides the effect of relaxing the electric field applied to the gate insulating film 10 at the bottom of the trench 6, thereby preventing breakdown of the gate insulating film 10.

[0033] As described above, the semiconductor device according to the first embodiment can prevent breakdown of the gate insulating film 10 at the bottom of the trench 6 while suppressing an increase in the on-resistance of the MOSFET.

[0034] 5 to 11 are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment. Hereinafter, the method for manufacturing the semiconductor device according to the first embodiment will be explained with reference to these diagrams.

[0035] First, a semiconductor substrate 1 made of N-type SiC is prepared, an N-type buffer layer 2 is grown on the semiconductor substrate 1, and an N-type epitaxial layer 3 is grown on the buffer layer 2. Then, P-type ion species (e.g., aluminum, boron) are implanted several times into the entire surface of the epitaxial layer 3 to form a P-type back gate region 4. Furthermore, N-type ion species (nitrogen, phosphorus) are implanted several times into the surface layer of the back gate region 4 by selective ion implantation using photolithography, to form an N-type source region 5. Through these steps, the configuration shown in FIG. 5 is obtained.

[0036] Next, a TEOS oxide film 17 is deposited on the surface of the source region 5 to a thickness of 2.0 μm to 3.0 μm, and the TEOS oxide film 17 is etched by selective dry etching using photolithography to form an opening in the TEOS oxide film 17 corresponding to the region where the trench 6 will be formed. Then, by selective etching using the TEOS oxide film 17 as a mask, the trench 6 is formed, penetrating the source region 5 and the back gate region 4 and reaching the underlying drift layer 31. Through these steps, the configuration shown in FIG. 6 is obtained.

[0037] The width of trench 6 is wider than the width of the opening of TEOS oxide film 17. The width of the top of trench 6 may be wider than the width of the bottom. In other words, the width of the top of the mesa-shaped semiconductor layer between trenches 6 may be narrower than the width of the bottom. In this case, the angle formed between the sidewall of trench 6 and the top surface of source region 5 is an obtuse angle several degrees larger than a right angle.

[0038] Next, P-type ion species (e.g., aluminum, boron) are implanted several times by selective ion implantation using the TEOS oxide film 17 used to form the trench 6 as a mask, thereby forming a P-type field relaxation layer 7 at the bottom of the trench 6. At this time, because the width of the opening of the TEOS oxide film 17 is narrower than the width of the trench 6, the P-type ion species are implanted mainly into the center of the trench 6. Therefore, the field relaxation layer 7 formed at the bottom of the trench 6 is formed deeper in the center than in the peripheral portion. As a result, the width of the bottom of the field relaxation layer 7 is smaller than the width of the bottom of the trench 6. Through these steps, the configuration shown in FIG. 7 is obtained.

[0039] Next, photolithography is used to cover region 101 where connection layer 8 is not to be provided with resist 18. Then, by selective ion implantation using TEOS oxide film 17 and resist 18 as a mask, P-type ion species (e.g., aluminum, boron) are implanted several times from an oblique direction to form P-type connection layer 8 that connects field relaxation layer 7 and back gate region 4 on the side wall of trench 6 in region 102, as shown in Figure 8. The implantation angle in the oblique ion implantation is, for example, in the range of 20 to 40 degrees.

[0040] After removing the resist 18 and removing the TEOS oxide film 17 by wet etching, a TEOS oxide film 19 is deposited to a thickness of 1.0 μm to 2.0 μm on the epitaxial layer 3 including the inside of the trench 6. Then, the TEOS oxide film 19 is etched by selective dry etching using photolithography to form an opening in the TEOS oxide film 19 corresponding to the region where the contact layer 9 is to be formed. Then, by selective ion implantation using the TEOS oxide film 19 as a mask, a P-type ion species (e.g., aluminum, boron, BF ２ ) is implanted once or several times to form a P-type contact layer 9 as shown in FIG.

[0041] After removing the TEOS oxide film 19 by wet etching, annealing is performed at a temperature of 1700°C or higher to activate the N-type or P-type diffusion layers formed in the above steps. To prevent Si sublimation, a carbon-based film (such as a graphite film) may be deposited before annealing. The carbon-based film is removed after annealing.

[0042] Next, a TEOS oxide film is deposited on the epitaxial layer 3 to a thickness of about 800 nm to 1500 nm, and the TEOS oxide film is patterned by selective etching using photolithography to form a field oxide film (not shown).

[0043] Next, an oxide film having a thickness of approximately 30 nm to 70 nm is deposited on the upper surface of the epitaxial layer 3, including the inside of the trench 6, and is then nitrided at 1100° C. to form a gate insulating film 10. Subsequently, polysilicon containing N-type impurities is deposited on the epitaxial layer 3 to fill the trench 6, and the polysilicon is etched by selective dry etching using photolithography to form a gate electrode 11 in the trench 6. Through these steps, the structure shown in FIG. 10 is obtained.

[0044] Thereafter, a TEOS oxide film is deposited on the epitaxial layer 3, then a BPSG film is deposited to a thickness of about 300 nm to 1000 nm, and a TEOS oxide film is deposited again thereon to form the interlayer insulating film 12. Then, by selective dry etching using photolithography, contact holes 13 are formed in the interlayer insulating film 12. The etching of the interlayer insulating film 12 consisting of the TEOS oxide film, BPSG film, and TEOS oxide film may be performed by wet etching alone or by a combination of dry etching and wet etching (dry etching followed by wet etching).

[0045] Next, Ni is sputtered onto the source region 5 and contact layer 9 exposed in the contact hole 13, followed by heat treatment to remove unreacted Ni, and another heat treatment to form silicide 14 made of NiSi. Furthermore, Ti or TiN is sputtered onto the interlayer insulating film 12, including the inside of the contact hole 13, to form barrier metal 15. Aluminum or AlSi is then sputtered onto the barrier metal 15, and patterned by selective dry etching or wet etching using photolithography to form source electrode 16. Thereafter, a SiN film or a conductive nitride film is deposited, and polyimide is deposited thereon to form a protective film (not shown).

[0046] Through the above steps, the structure shown in FIG. 11 is obtained, completing the semiconductor device according to the first embodiment.

[0047] <Second Embodiment> Fig. 12 is a diagram showing the configuration of a SiC trench MOSFET which is a semiconductor device according to a second embodiment. In Fig. 12, elements that are the same as or correspond to those shown in Figs. 1 and 2 are given the same reference numerals.

[0048] In the configuration of the semiconductor device according to the second embodiment, the cross section of the electric field relaxation layer 7 provided at the bottom of the trench 6 is octagonal. The other configurations are the same as those of the first embodiment.

[0049] In a cross-sectional view, the overall width of the electric field relaxation layer 7 is the same as the width of the bottom of the trench 6, but because the shape of the electric field relaxation layer 7 is octagonal, the widths of the top and bottom of the electric field relaxation layer 7 are smaller than the width of the bottom of the trench 6. An angle 7b formed by the side surface and top surface of the top of the electric field relaxation layer 7 is 30° or more and less than 90°. In addition, the width of the top of the electric field relaxation layer 7 is 40% or more and 90% or less of the width of the bottom of the trench 6.

[0050] In the semiconductor device according to the second embodiment, the cross-sectional shape of the electric field relaxation layer 7 is octagonal, and therefore the region of the drift layer 31 in contact with the trench 6 is larger than that in the first embodiment. This increases the size of the accumulation layer 24 that forms part of the current path, and further reduces the JFET resistance.

[0051] <Embodiment 3> Fig. 13 is a diagram showing the configuration of a SiC trench MOSFET which is a semiconductor device according to embodiment 2. In Fig. 13, elements that are the same as or correspond to those shown in Figs. 1 and 2 are given the same reference numerals.

[0052] In the configuration of the semiconductor device according to the third embodiment, the depth (distance from the upper surface of the epitaxial layer 3) of the bottom of the connection layer 8 that connects the electric field relaxation layer 7 and the back gate region 4 is shallower than the bottom of the electric field relaxation layer 7. The other configurations are the same as those of the first or second embodiment. Note that FIG. 13 shows a trench 6 having an octagonal cross section as in the second embodiment.

[0053] In the semiconductor device according to the third embodiment, the depth of the bottom of the connection layer 8 is shallower than the bottom of the electric field relaxation layer 7, and therefore the entrance of the current path (the region of the drift layer 31 where the electric field relaxation layer 7 and the connection layer 8 are not formed) is larger than in the first or second embodiment, and therefore the JFET resistance can be further reduced.

[0054] Fourth Embodiment In this embodiment, the semiconductor device according to any one of the above-described first to third embodiments is applied to a power conversion device. Although the application of the semiconductor device according to any one of the first to third embodiments is not limited to a specific power conversion device, the following will describe a case in which the semiconductor device according to any one of the first to third embodiments is applied to a three-phase inverter as the fourth embodiment.

[0055] FIG. 14 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0056] The power conversion system shown in Fig. 14 is composed of a power supply 1100, a power conversion device 1200, and a load 1300. The power supply 1100 is a DC power supply and supplies DC power to the power conversion device 1200. The power supply 1100 can be composed of various components, such as a DC system, a solar cell, or a storage battery, or it can be composed of a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 1100 can also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0057] The power conversion device 1200 is a three-phase inverter connected between the power supply 1100 and the load 1300, and converts DC power supplied from the power supply 1100 into AC power and supplies the AC power to the load 1300. As shown in Fig. 14 , the power conversion device 1200 includes a main conversion circuit 1201 that converts DC power into AC power and outputs it, a drive circuit 1202 that outputs drive signals that drive each switching element of the main conversion circuit 1201, and a control circuit 1203 that outputs control signals to the drive circuit 1202.

[0058] The load 1300 is a three-phase electric motor driven by AC power supplied from the power conversion device 1200. The load 1300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0059] The power conversion device 1200 will be described in detail below. The main conversion circuit 1201 includes switching elements and freewheel diodes (not shown). The switching elements convert DC power supplied from the power supply 1100 into AC power, which is supplied to the load 1300. The main conversion circuit 1201 can have a variety of specific circuit configurations. The main conversion circuit 1201 according to this embodiment is a two-level, three-phase full-bridge circuit, and can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. Each switching element of the main conversion circuit 1201 is a semiconductor device according to any one of the first to third embodiments. Two of the six switching elements are connected in series to form upper and lower arms, each of which constitutes a phase (U phase, V phase, and W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 1201, are connected to the load 1300.

[0060] Drive circuit 1202 generates drive signals for driving the switching elements of main conversion circuit 1201 and supplies them to the control electrodes of the switching elements of main conversion circuit 1201. Specifically, in accordance with control signals from control circuit 1203 (described later), drive signals for turning the switching elements on and off are output to the control electrodes of each switching element. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0061] The control circuit 1203 controls the switching elements of the main conversion circuit 1201 so that the desired power is supplied to the load 1300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 1201 should be in the on state based on the power to be supplied to the load 1300. For example, the main conversion circuit 1201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 1203 then outputs a control command (control signal) to the drive circuit 1202 so that an on signal is output to the switching element that should be in the on state at each point in time, and an off signal is output to the switching element that should be in the off state at each point in time. In accordance with this control signal, the drive circuit 1202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0062] In the power conversion device according to the present embodiment, the semiconductor devices according to the first to third embodiments are applied as switching elements of the main conversion circuit 1201, and therefore, an improvement in conversion efficiency can be realized.

[0063] In the present embodiment, an example has been described in which the semiconductor device according to the first to third embodiments is applied to a two-level three-phase inverter, but the application of the semiconductor device according to the first to third embodiments is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used. In addition, when power is supplied to a single-phase load, the semiconductor device according to the first to third embodiments may also be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the semiconductor device according to the first to third embodiments can also be applied to a DC / DC converter or an AC / DC converter.

[0064] Furthermore, the power conversion device to which the semiconductor device according to any one of the first to third embodiments is applied is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, or the like.

[0065] In the above description, a MOSFET has been shown as the semiconductor device, but the semiconductor device may be of a trench gate type, and may be other than a MOSFET, such as an IGBT (Insulated Gate Bipolar Transistor) or an RC-IGBT (Reverse Conducting IGBT). Furthermore, the materials of the semiconductor layers, such as the semiconductor substrate 1, buffer layer 2, and epitaxial layer 3, are not limited to SiC, and may be, for example, silicon (Si), or a wide bandgap semiconductor other than SiC, such as gallium nitride (GaN) or diamond.

[0066] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0067] <Supplementary Notes> Various aspects of the present disclosure will be summarized below as supplementary notes.

[0068] a gate insulating film provided on an inner surface of the trench; a gate electrode provided on the gate insulating film and embedded in the trench; and an electric field relaxation layer which is the second conductivity type diffusion layer provided in the semiconductor layer below the trench and covers a bottom of the trench, wherein the width of the bottom of the electric field relaxation layer is smaller than the overall width of the electric field relaxation layer and is also smaller than the width of the bottom of the trench.

[0069] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the width of the upper portion of the electric field buffer layer is smaller than the entire width of the electric field buffer layer and smaller than the width of the bottom portion of the trench.

[0070] (Supplementary Note 3) The semiconductor device described in Supplementary Note 1 or Supplementary Note 2 further includes a connection layer, which is a diffusion layer of the second conductivity type, provided in the semiconductor layer on a side wall of the trench and connects the electric field relaxation layer and the back gate region, and the depth of the bottom of the connection layer is shallower than the depth of the bottom of the electric field relaxation layer.

[0071] (Supplementary Note 4) A power conversion device comprising: a main conversion circuit having the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 3, which converts input power and outputs the converted power; a drive circuit which outputs a drive signal to the semiconductor device for driving the semiconductor device; and a control circuit which outputs a control signal to the drive circuit for controlling the drive circuit.

[0072] (Supplementary Note 5) A method for manufacturing a semiconductor device, comprising: (a) forming a back gate region, which is a diffusion layer of a second conductivity type, in a surface layer portion of a semiconductor layer of a first conductivity type; (b) forming a trench in the semiconductor layer that penetrates the back gate region by selective etching using a mask; and (c) forming an electric field relaxation layer, which is a diffusion layer of the second conductivity type and covers a bottom of the trench, in the semiconductor layer below the trench by selective ion implantation using the mask used in step (b), wherein the width of the trench formed in step (b) is wider than the width of the opening of the mask, and the width of a bottom of the electric field relaxation layer formed in step (c) is smaller than the overall width of the electric field relaxation layer and is also smaller than the width of the bottom of the trench.

[0073] 1 semiconductor substrate, 2 buffer layer, 3 epitaxial layer, 4 back gate region, 5 source region, 6 trench, 7 field relaxation layer, 8 connection layer, 9 contact layer, 10 gate insulating film, 11 gate electrode, 12 interlayer insulating film, 13 contact hole, 14 silicide, 15 barrier metal, 16 source electrode, 17 TEOS oxide film, 18 resist, 19 TEOS oxide film, 23 inversion layer, 24 accumulation layer, 31 drift layer, 1100 power supply, 1200 power conversion device, 1201 main conversion circuit, 1202 drive circuit, 1203 control circuit, 1300 load.

Claims

1. A semiconductor layer of a first conductivity type, a back gate region which is a diffusion layer of a second conductivity type provided in a surface layer portion of the semiconductor layer, a trench provided in the semiconductor layer and penetrating the back gate region, a gate insulating film provided on an inner surface of the trench, a gate electrode provided on the gate insulating film and formed so as to be embedded in the trench, an electric field relaxation layer which is a diffusion layer of the second conductivity type provided in the semiconductor layer under the trench and covering a bottom portion of the trench, comprising: a width of a bottom portion of the electric field relaxation layer is smaller than a width of an entire portion of the electric field relaxation layer and smaller than a width of a bottom portion of the trench, an angle formed by a side surface and a bottom surface of the bottom portion of the electric field relaxation layer is 60° or more and less than 90°, a semiconductor device.

2. The inner surface of the trench has a side surface and a bottom surface, and the gate electrode is formed on the gate insulating film provided on the side surface and the bottom surface of the trench, The semiconductor device according to Claim 1.

3. a width of an upper portion of the electric field relaxation layer is smaller than a width of an entire portion of the electric field relaxation layer and smaller than a width of a bottom portion of the trench, The semiconductor device according to Claim 1 or Claim 2.

4. further comprising a connection layer which is a diffusion layer of the second conductivity type provided in the semiconductor layer on a side wall of the trench and connecting the electric field relaxation layer and the back gate region, a depth of a bottom portion of the connection layer is shallower than a depth of a bottom portion of the electric field relaxation layer, The semiconductor device according to Claim 1 or Claim 2.

5. having the semiconductor device according to Claim 1 or Claim 2, a main conversion circuit which converts input power and outputs the converted power, a drive circuit which outputs a drive signal for driving the semiconductor device to the semiconductor device, a control circuit which outputs a control signal for controlling the drive circuit to the drive circuit, a power conversion device comprising the above.

6. (a) a step of forming a back gate region which is a diffusion layer of a second conductivity type in a surface layer portion of a semiconductor layer of a first conductivity type, (b) a step of forming a trench penetrating the back gate region in the semiconductor layer by selective etching using a mask, (c) a step of forming an electric field relaxation layer which is a diffusion layer of the second conductivity type covering a bottom portion of the trench in the semiconductor layer under the trench by selective ion implantation using the mask used in the step (b), comprising: a width of the trench formed in the step (b) is wider than a width of an opening of the mask, The width of the bottom of the electric field relaxation layer formed in the step (c) is smaller than the overall width of the electric field relaxation layer and smaller than the width of the bottom of the trench. Method for manufacturing a semiconductor device.