IC-mounted substrate

Abstract

This IC-mounted substrate includes a mounting substrate and a high-frequency IC. The high-frequency IC is mounted on a first surface of the mounting substrate via a plurality of power supply bumps. A power supply via for supplying power to the high-frequency IC, a power supply pattern for supplying power to the high-frequency IC, and a high-frequency transmission path for transmitting a high-frequency signal are formed on the mounting substrate 1. The plurality of power supply bumps and the power supply via are connected via a pad. The power supply pattern is electrically connected to the power supply via. The high-frequency transmission path has a signal line for transmitting the high-frequency signal, and a ground pattern formed so as to be adjacent to both side edges of the signal line in plan view. The power supply via is formed so as not to overlap with the high-frequency transmission path in plan view.

Description

IC mounting board

[0001] The present invention relates to an IC mounting substrate. This application claims priority to Japanese Patent Application No. 2023-109956, filed on July 4, 2023, the contents of which are incorporated herein by reference.

[0002] Patent Document 1 discloses a multilayer printed circuit board including an IC and a substrate. The substrate has power supply vias and wiring layers formed therein. The IC is mounted on the substrate by solder balls. This multilayer printed circuit board is an IC-mounted board in which the IC is mounted on the substrate.

[0003] Japanese Patent No. 6671551

[0004] In an IC mounting substrate, the position where wiring can be formed may be restricted by power supply vias formed in the substrate, which may reduce the degree of freedom in wiring layout.

[0005] An object of one aspect of the present invention is to provide an IC mounting board that allows a high degree of freedom in wiring layout.

[0006] An IC mounting board according to a first aspect of the present invention comprises a mounting board having a first surface and a second surface opposite to the first surface, and a radio frequency IC mounted on the first surface of the mounting board by a plurality of power bumps, wherein the mounting board is formed with power supply vias that supply power to the radio frequency IC, a power supply pattern that supplies power to the radio frequency IC, and a radio frequency transmission line that transmits a radio frequency signal, the plurality of power bumps and the power supply vias are connected via pads, the power supply pattern is electrically connected to the power supply vias, the radio frequency transmission line has a signal line that transmits the radio frequency signal, and ground patterns that are formed adjacent to both side edges of the signal line in a planar view, and the power supply vias are formed so as not to overlap the radio frequency transmission line in a planar view.

[0007] According to the first aspect of the present invention, the power supply via does not overlap the high frequency transmission line in a plan view, so that the degree of freedom in the layout of wiring is increased.

[0008] A second aspect of the present invention is the IC mounting board of the first aspect, wherein the number of the power supply bumps connected to the pads may be greater than the number of the power supply vias connected to the pads.

[0009] A third aspect of the present invention is the IC mounting board of the first or second aspect, further comprising an antenna that performs at least one of transmitting and receiving a high-frequency wireless signal, and the signal line may function as a power feed line that feeds power to the antenna.

[0010] A fourth aspect of the present invention is the IC mounting board according to any one of the first to third aspects, wherein a plurality of ground vias electrically connected to the ground pattern are formed in the mounting board, and the plurality of ground vias may be arranged along the signal line.

[0011] A fifth aspect of the present invention is the fourth aspect, wherein the plurality of ground vias may be formed so as to surround the signal line in an annular shape with intervals therebetween.

[0012] A sixth aspect of the present invention is the IC mounting board of the fifth aspect, wherein the pitch between the plurality of ground vias may be λ / 4 or less, where λ is the wavelength of the high frequency signal.

[0013] A seventh aspect of the present invention is the IC mounting board according to any one of the first to sixth aspects, wherein the high frequency IC may be mounted on the first surface of the mounting board by wafer level packaging.

[0014] One aspect of the present invention provides an IC mounting substrate that allows a high degree of freedom in wiring layout.

[0015] 1 is a configuration diagram of an IC mounting substrate according to an embodiment of the present invention;

[0016] Hereinafter, an IC mounting board according to an embodiment of the present invention will be described with reference to the drawings.

[0017] [IC Mounting Board] Fig. 1 is a configuration diagram of an IC mounting board 100 according to an embodiment. As shown in Fig. 1, the IC mounting board 100 includes a mounting board 1, a high-frequency IC 2, a plurality of power bumps 3, a plurality of signal bumps 4, a plurality of ground bumps 5, and a plurality of antennas 6. The IC mounting board 100 is an antenna board. The IC mounting board 100 is, for example, a phased array antenna board.

[0018] The mounting substrate 1 includes an inner layer 10, a first outer layer 20 laminated on one surface 10a of the inner layer 10, and a second outer layer 30 laminated on the other surface 10b of the inner layer 10. The inner layer 10 is, for example, a core layer. The first outer layer 20 and the second outer layer 30 are, for example, build-up layers.

[0019] The positional relationship of each component of the mounting substrate 1 is tentatively determined based on Fig. 1. For example, the first outer layer 20 is above the inner layer 10. The second outer layer 30 is below the inner layer 10. The positional relationship determined here does not limit the orientation of the IC mounting substrate 100 during use. Viewing the mounting substrate 1 from above and below is called a plan view.

[0020] The inner layer 10 has a plurality of wiring layers 11. The plurality of wiring layers 11 includes three wiring layers 11A to 11C. The wiring layers 11A to 11C are a first wiring layer 11A, a second wiring layer 11B, and a third wiring layer 11C, respectively. The number of wiring layers 11 is not particularly limited. The number of wiring layers 11 may be one or more. Each of the first wiring layer 11A to the third wiring layer 11C has a power supply pattern. The power supply pattern is made of a conductive material such as metal (e.g., copper). The power supply pattern supplies power to the high-frequency IC 2.

[0021] The power supply patterns formed on the first wiring layer 11A to the third wiring layer 11C are a first power supply pattern, a second power supply pattern, and a third power supply pattern, respectively. Note that the number of power supply patterns formed on each of the first wiring layer 11A to the third wiring layer 11C is not particularly limited. The number of power supply patterns formed on each of the first wiring layer 11A to the third wiring layer 11C may be one or more. That is, the number of power supply patterns formed on each of the first wiring layer 11A to the third wiring layer 11C may be one or more (any number equal to or greater than two).

[0022] The first to third power supply patterns are connected to different power supplies (not shown), for example. Therefore, the voltages applied to the high frequency IC 2 by the first to third power supply patterns can be determined independently. The voltages applied to the high frequency IC 2 by the first to third power supply patterns C may be different from each other or may be the same as each other.

[0023] A dielectric layer 12 is formed between adjacent wiring layers 11. A dielectric layer 12 is also formed between wiring layer 11A and a third wiring layer 21C (described later). A dielectric layer 12 is also formed between wiring layer 11C and a first wiring layer 31A (described later). The inner layer 10 is formed by alternately stacking wiring layers 11 and dielectric layers 12.

[0024] The first outer layer 20 has a plurality of wiring layers 21. The wiring layers 21 are conductor layers formed of a conductive material such as metal (e.g., copper). In this embodiment, the plurality of wiring layers 21 include three wiring layers 21A to 21C. The wiring layers 21A to 21C are a first wiring layer 21A, a second wiring layer 21B, and a third wiring layer 21C, respectively. The number of wiring layers 21 is not particularly limited. The number of wiring layers 21 may be one or more.

[0025] A dielectric layer 22 is formed between adjacent wiring layers 21. The first outer layer 20 is formed by alternately laminating the dielectric layers 22 and the wiring layers 21 on the surface 10a (upper surface) of the inner layer 10.

[0026] The second outer layer 30 has a plurality of wiring layers 31. The wiring layers 31 are conductor layers formed of a conductive material such as metal (e.g., copper, etc.). In this embodiment, the plurality of wiring layers 31 include three wiring layers 31A to 31C. The wiring layers 31A to 31C are a first wiring layer 31A, a second wiring layer 31B, and a third wiring layer 31C, respectively. The number of wiring layers 31 is not particularly limited. The number of wiring layers 31 may be one or more.

[0027] A dielectric layer 32 is formed between adjacent wiring layers 31. The second outer layer 30 is formed by alternately laminating wiring layers 31 and dielectric layers 32 on the surface 10b (lower surface) of the inner layer 10.

[0028] At least one of the wiring layers 21 and 31 is a high-frequency transmission line. The high-frequency transmission line transmits high-frequency signals. In this embodiment, the second wiring layer 21B has a high-frequency transmission line.

[0029] A plurality of power supply vias 13 are formed in the mounting substrate 1. The plurality of power supply vias 13 include three power supply vias 13A to 13C. The power supply vias 13A to 13C are a first power supply via 13A, a second power supply via 13B, and a third power supply via 13C, respectively. Note that the number of power supply vias 13 is not particularly limited. The number of power supply vias 13 may be one or more. The number of power supply vias 13 is determined according to the required current.

[0030] The power supply via 13 is made of a conductive material. The power supply via 13 can be made of a conductive pin, a conductive wire, metal plating, a conductive paste, etc. Examples of conductive materials used for the power supply via 13 include metals such as copper, silver, gold, and alloys, and carbon.

[0031] The upper end of the first power supply via 13A reaches the first surface 1a (top surface) of the mounting substrate 1. The upper end of the first power supply via 13A is electrically connected to the power supply bump 3 (first power supply bump 3A) via a pad 16A provided on the first surface 1a. The first power supply via 13A extends from the first surface 1a (top surface) to the second surface 1b (bottom surface) of the mounting substrate 1. The lower end of the first power supply via 13A is electrically connected to the first power supply pattern.

[0032] The upper end of the second power supply via 13B reaches the first surface 1a (top surface) of the mounting substrate 1. The upper end of the second power supply via 13B is electrically connected to the plurality of power supply bumps 3 (second and third power supply bumps 3B, 3C) via pads 16B provided on the first surface 1a. The pads 16B are connected to the plurality of power supply bumps 3 (3B, 3C). The second power supply via 13B extends from the first surface 1a (top surface) toward the second surface 1b (bottom surface) of the mounting substrate 1. The lower end of the second power supply via 13B is electrically connected to the second power supply pattern.

[0033] The number of power supply bumps 3 (3B, 3C) connected to pad 16B (i.e., two) is greater than the number of second power supply vias 13B connected to pad 16B (i.e., one). The number of power supply bumps 3 connected to pad 16B may be greater than the number of second power supply vias 13B connected to pad 16B, and for example, the number of power supply bumps 3 may be three and the number of second power supply vias 13B may be two. By making the number of first power supply vias 13A smaller than the number of power supply bumps 3 connected to the first power supply vias 13A, the degree of freedom in the layout of the wiring layer 21 (high-frequency transmission path) can be increased.

[0034] The upper end of the third power supply via 13C reaches the first surface 1a (top surface) of the mounting substrate 1. The upper end of the third power supply via 13C is electrically connected to the plurality of power supply bumps 3 (fourth and fifth power supply bumps 3D, 3E) via pads 16C provided on the first surface 1a. The pads 16C are connected to the plurality of power supply bumps 3 (3D, 3E). The third power supply via 13C extends from the first surface 1a (top surface) toward the second surface 1b (bottom surface) of the mounting substrate 1. The lower end of the third power supply via 13C is electrically connected to the third power supply pattern.

[0035] The number of power supply bumps 3 (3D, 3E) connected to pad 16C (i.e., two) is greater than the number of third power supply vias 13C connected to pad 16C (i.e., one). The number of power supply bumps 3 connected to pad 16C may be greater than the number of third power supply vias 13C connected to pad 16C, and for example, the number of power supply bumps 3 (3D, 3E) may be three and the number of third power supply vias 13C may be two. By making the number of third power supply vias 13C less than the number of power supply bumps 3 connected to the third power supply vias 13C, the degree of freedom in layout of the wiring layer 21 (high frequency transmission path) can be increased.

[0036] It is desirable that the number of power supply vias 13A to 13C be smaller than the number (total number) of power supply bumps 3 (3A to 3E) connected to the power supply vias 13A to 13C. This increases the degree of freedom in the layout of the wiring layer 21 (high frequency transmission path).

[0037] A plurality of signal vias 14 are formed in the mounting substrate 1. The plurality of signal vias 14 include two signal vias 14A and 14B. The signal vias 14A and 14B are the first signal via 14A and the second signal via 14B, respectively. Note that the number of signal vias 14 is not particularly limited. The number of signal vias 14 may be one or more.

[0038] The signal via 14 is formed of a conductive material. The signal via 14 can be formed of a conductive pin, a conductive wire, metal plating, a conductive paste, etc. Examples of conductive materials used for the signal via 14 include metals such as copper, silver, gold, and alloys, and carbon.

[0039] The upper end of the first signal via 14A is electrically connected to a first signal line 24A that is part of the second wiring layer 21B (i.e., formed in the second wiring layer 21B) via a buried via 15G. The first signal line 24A is electrically connected to a signal bump 4 (first signal bump 4A) via the first buried via 15A and a pad 16D. The lower end of the first signal via 14A is part of the first wiring layer 31A. The first signal via 14A is electrically connected to the antenna 6 (first antenna 6A) via two buried vias 15C and 15D. The first signal via 14A may, for example, penetrate the inner layer 10.

[0040] The upper end of the second signal via 14B is electrically connected to a second signal line 24B that is part of the second wiring layer 21B (i.e., formed in the second wiring layer 21B) via a buried via 15H. The second signal line 24B is electrically connected to the signal bump 4 (second signal bump 4B) via the second buried via 15B and a pad 16E. The lower end of the second signal via 14B is part of the first wiring layer 31A. The second signal via 14B is electrically connected to the antenna 6 (second antenna 6B) via two buried vias 15E and 15F. The second signal via 14B may, for example, penetrate the inner layer 10.

[0041] The pads 16A to 16E are provided on the first surface 1a and are made of a conductive material such as metal (e.g., copper). The pads 16A to 16E are part of the first wiring layer 21A.

[0042] The high frequency IC 2 is an integrated circuit that processes high frequency signals. The high frequency IC 2 is mounted on the first surface 1a of the mounting substrate 1 by bumps 3, 4, and 5. The IC package used for the high frequency IC 2 may be, for example, a BGA (Ball Grid Alley), a CSP (Chip Size Package), or a FOWLP (Fan Out Wafer Level Package).

[0043] The high frequency IC 2 is electrically connected to the antenna 6 (first antenna 6A) via the signal bump 4 (first signal bump 4A), pad 16D, first buried via 15A, first signal line 24A, buried via 15G, first signal via 14A, and buried vias 15C and 15D. The high frequency IC 2 is electrically connected to the antenna 6 (second antenna 6B) via the signal bump 4 (second signal bump 4B), pad 16E, second buried via 15B, second signal line 24B, buried via 15H, second signal via 14B, and buried vias 15E and 15F.

[0044] The high frequency IC 2, for example, controls transmission and reception of high frequency signals by an antenna 6. The high frequency IC 2 may be mounted on the first surface 1a of the mounting substrate 1 by wafer level packaging (WLP). By employing a wafer level package, the pitch of the power supply bumps 3 can be increased.

[0045] The multiple power bumps 3 include power bumps 3A to 3E. The power bumps 3A to 3E are a first power bump 3A, a second power bump 3B, a third power bump 3C, a fourth power bump 3D, and a fifth power bump 3E, respectively. The power bumps 3 are electrically connected to the high frequency IC 2. Therefore, the high frequency IC 2 is electrically connected to the pads 16A to 16E via the power bumps 3.

[0046] The signal bumps 4 are electrically connected to the high frequency IC 2. The ground bumps 5 are electrically connected to the high frequency IC 2. Materials for the power supply bumps 3, signal bumps 4, and ground bumps 5 include metals such as solder (SnAgCu solder, etc.), gold, silver, and copper.

[0047] The antenna 6 is formed on the second surface 1b of the mounting substrate 1. The multiple antennas 6 include a first antenna 6A and a second antenna 6B. The antenna 6 transmits and receives, for example, high-frequency radio signals (for example, in the 28 GHz band). The antenna 6 may be configured to only transmit or only receive high-frequency radio signals. In other words, it is sufficient for the antenna 6 to be capable of at least one of transmission and reception.

[0048] The antenna 6 may be, for example, an array antenna in which a plurality of radiating elements are formed two-dimensionally. The antenna 6 may be a linear antenna, a planar antenna, a microstrip antenna, a patch antenna, or the like. The antenna 6 may also constitute a phased array antenna. The antenna 6 is formed of a conductive material such as metal (e.g., copper). The antenna 6 is not limited to being formed on the second surface 1b of the mounting substrate 1, and may also be formed inside the mounting substrate 1.

[0049] 2 is a plan view of the wiring layer 21, which is a high-frequency transmission line. In this embodiment, a high-frequency transmission line that is part of the second wiring layer 21B (see FIG. 1) (i.e., formed in the second wiring layer 21B) is used as an example. The high-frequency transmission line is preferably located on the opposite side of the power supply pattern from the antenna 6 (i.e., above the power supply pattern in FIG. 1).

[0050] As shown in FIG. 2, the high-frequency transmission line includes a first signal line 24A (signal line), a second signal line 24B (signal line), and a ground pattern 25.

[0051] The first signal line 24A transmits high-frequency signals. One end of the first signal line 24A is electrically connected to the signal bump 4 (first signal bump 4A) via the first buried via 15A and the pad 16D (see FIG. 1). The other end of the first signal line 24A is electrically connected to the antenna 6 (first antenna 6A) via one buried via 15G, the first signal via 14A, and two buried vias 15C and 15D (see FIG. 1). The first signal line 24A functions as a power feed line that feeds power to the antenna 6 (first antenna 6A). The first signal line 24A functions as high-frequency wiring that transmits high-frequency signals.

[0052] The second signal line 24B transmits high-frequency signals. One end of the second signal line 24B is electrically connected to the signal bump 4 (second signal bump 4B) via the second buried via 15B and the pad 16E (see FIG. 1). The other end of the second signal line 24B is electrically connected to the antenna 6 (second antenna 6B) via one buried via 15H, the second signal via 14B, and two buried vias 15E and 15F (see FIG. 1). The second signal line 24B functions as a power feed line that feeds power to the antenna 6 (second antenna 6B). The second signal line 24B functions as high-frequency wiring that transmits high-frequency signals.

[0053] The ground pattern 25 is formed with a first opening 25A surrounding the first signal line 24A, a second opening 25B surrounding the second signal line 24B, and a plurality of third openings 25C surrounding the power supply vias 13.

[0054] The first opening 25A is formed linearly along the first signal line 24A. The inner periphery of the first opening 25A is spaced apart from the first signal line 24A. In other words, the first signal line 24A is formed inside the first opening 25A and spaced apart from the inner periphery of the first opening 25A. The ground pattern 25 and the first signal line 24A are electrically insulated from each other.

[0055] One side edge 24a of the first signal line 24A is close to the opposite side edge 25a of the first opening 25A. The distance between the side edges 24a and 25a is approximately constant. The other side edge 24b of the first signal line 24A is close to the opposite side edge 25b of the first opening 25A. The distance between the side edges 24b and 25b is approximately constant. Therefore, the ground pattern 25 is formed adjacent to both side edges of the first signal line 24A. The first signal line 24A and the ground pattern 25 form a coplanar line, which is a type of high-frequency transmission line.

[0056] The second opening 25B is formed linearly along the second signal line 24B. The inner periphery of the second opening 25B is spaced apart from the second signal line 24B. In other words, the second signal line 24B is formed inside the second opening 25B and spaced apart from the inner periphery of the second opening 25B. The ground pattern 25 and the second signal line 24B are electrically insulated from each other.

[0057] One side edge 24c of the second signal line 24B is close to the opposing side edge 25c of the second opening 25B. The distance between the side edges 24c and 25c is approximately constant. The other side edge 24d of the second signal line 24B is close to the opposing side edge 25d of the second opening 25B. The distance between the side edges 24d and 25d is approximately constant. Therefore, the ground pattern 25 is formed adjacent to both side edges of the second signal line 24B. The second signal line 24B and the ground pattern 25 form a coplanar line, which is a type of high-frequency transmission line.

[0058] A plurality of ground vias 26, which are set to a ground potential, are formed on the mounting substrate 1. The ground vias 26 are formed at positions overlapping the ground pattern 25 in a plan view. The ground vias 26 have, for example, a circular shape in a plan view. The ground vias 26 are electrically connected to the ground pattern 25.

[0059] The multiple ground vias 26 form a first ground via group 27A and a second ground via group 27B. The first ground via group 27A includes multiple ground vias 26 arranged along the first signal line 24A (the inner periphery of the first opening 25A). Specifically, the multiple ground vias 26 are formed in a ring shape surrounding the first signal line 24A with intervals between them. The multiple ground vias 26 that make up the first ground via group 27A are, for example, arranged at equal intervals along the inner periphery of the first opening 25A. Some of the multiple ground vias 26 are arranged at intervals along the first signal line 24A. This improves the transmission quality of the coplanar line formed by the first signal line 24A and the ground pattern 25.

[0060] The second ground via group 27B has a plurality of ground vias 26 arranged along the second signal line 24B (the inner peripheral edge of the second opening 25B). Specifically, the plurality of ground vias 26 are formed in a ring shape surrounding the second signal line 24B at intervals. The plurality of ground vias 26 constituting the second ground via group 27B are, for example, arranged at equal intervals along the inner peripheral edge of the second opening 25B. Some of the plurality of ground vias 26 are arranged at intervals along the second signal line 24B. This can improve the transmission quality of the coplanar line formed by the second signal line 24B and the ground pattern 25.

[0061] The pitch p1 of the ground vias 26 in the first ground via group 27A (e.g., the distance between the centers of adjacent ground vias 26) is preferably λ / 4 or less, where λ is the wavelength of a high-frequency signal. If the pitch p1 is λ / 4 or less, the transmission quality of the coplanar line formed by the first signal line 24A and the ground pattern 25 can be further improved.

[0062] The pitch p2 of the ground vias 26 in the second ground via group 27B (e.g., the distance between the centers of adjacent ground vias 26) is preferably λ / 4 or less, where λ is the wavelength of a high-frequency signal. If the pitch p2 is λ / 4 or less, the transmission quality of the coplanar line formed by the second signal line 24B and the ground pattern 25 can be further improved.

[0063] The third opening 25C has a shape corresponding to the power supply via 13. In this embodiment, the shapes of the power supply via 13 and the third opening 25C are circular in plan view. The inner diameter of the third opening 25C is larger than the outer diameter of the power supply via 13. The third opening 25C is concentric with the power supply via 13. An inner peripheral edge 25e of the third opening 25C is spaced apart from the power supply via 13. In other words, the power supply via 13 is formed inside the third opening 25C and spaced apart from the inner peripheral edge 25e of the third opening 25C. The ground pattern 25 and the power supply via 13 are electrically insulated.

[0064] In this way, the power supply vias 13 are formed so as not to overlap with the ground pattern 25 in a plan view. That is, in a plan view, the positions of the power supply vias 13 and the ground pattern 25 are different. In other words, the power supply vias 13 are formed at a different position from the ground pattern 25 in a plan view.

[0065] [Advantages of the IC Mounting Board of the Embodiment] In the IC mounting board 100, the power supply vias 13 are formed so as not to overlap the high-frequency transmission lines (in this embodiment, the coplanar lines formed by the signal lines 24A and 24B and the ground pattern 25) in a planar view. Specifically, the power supply vias 13 are formed in an area outside the range that functions as a coplanar line (outside the ground vias 26 relative to the signal lines 24A and 24B) (see FIG. 2). This increases the degree of freedom in the layout of the wiring layer 21, particularly the wiring layer 21B (high-frequency transmission line) that has the high-frequency transmission line (see FIG. 1). Therefore, for example, by forming the ground vias 26 at a narrow pitch, the transmission quality of the high-frequency transmission line can be stabilized.

[0066] The IC mounting board 100 has a high degree of freedom in the layout of the wiring layer 21 (high-frequency transmission path), allowing the length of the wiring to be determined freely. For example, when a phased array antenna is used, it is easy to align the lengths of the first signal line 24A and the second signal line 24B (see FIG. 2).

[0067] In the IC mounting board 100, the first signal line 24A and the second signal line 24B function as feeder lines, thereby improving the performance of the antenna 6.

[0068] The technical scope of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the IC mounting substrate 100 shown in FIG. 1, the second power supply via 13B and the third power supply via 13C are each electrically connected to multiple power supply bumps 3. In the IC mounting substrate, there is no particular limit to the number of power supply vias electrically connected to multiple power supply bumps. In the IC mounting substrate, it is sufficient that at least one power supply via is electrically connected to multiple power supply bumps.

[0069] Although IC mounting board 100 of this embodiment includes antenna 6, the IC mounting board does not necessarily have to include an antenna. In that case, the antenna may be provided on an antenna board mounted on second surface 1b of mounting board 1.

[0070] In addition, it is possible to replace the components in the above-described embodiments with well-known components as appropriate, and the above-described embodiments and variations may be combined as appropriate, without departing from the spirit of the present invention.

[0071] REFERENCE SIGNS LIST 1...Mounting substrate 1a...First surface 1b...Second surface 2...High frequency IC 3...Power supply bump 6...Antenna 11...Wiring layer 13...Power supply via 16A, 16B, 16C...Pad 21B...Second wiring layer (having high frequency transmission path) 24A...First signal line (signal line) 24B...Second signal line (signal line) 25...Ground pattern 26...Ground via 100...IC mounting substrate

Claims

1. a mounting substrate having a first surface and a second surface opposite to the first surface; a high frequency IC mounted on the first surface of the mounting substrate by a plurality of power supply bumps; Equipped with The mounting board is a power supply via for supplying power to the high frequency IC; a power supply pattern for supplying power to the high frequency IC; a high-frequency transmission path for transmitting a high-frequency signal is formed, the plurality of power supply bumps and the power supply vias are connected via pads; the power supply pattern is electrically connected to the power supply via; the high-frequency transmission line includes a signal line that transmits the high-frequency signal, and ground patterns that are formed adjacent to both side edges of the signal line in a plan view; The power supply via is formed so as not to overlap the high-frequency transmission line in a plan view. IC mounting board.

2. the number of the power supply bumps connected to the pad is greater than the number of the power supply vias connected to the pad; The IC mounting board according to claim 1.

3. further comprising an antenna for at least one of transmitting and receiving high-frequency radio signals; the signal line functions as a feed line for feeding power to the antenna.

3. The IC mounting board according to claim 1.

4. a plurality of ground vias electrically connected to the ground pattern are formed on the mounting board; the plurality of ground vias are arranged along the signal line; 3. The IC mounting board according to claim 1.

5. the plurality of ground vias are formed so as to surround the signal line in an annular shape at intervals; The IC mounting board according to claim 4 .

6. The pitch of the plurality of ground vias is λ / 4 or less, where λ is the wavelength of the high-frequency signal.

6. The IC mounting board according to claim 5.

7. the high-frequency IC is mounted on the first surface of the mounting substrate by wafer-level packaging; 3. The IC mounting board according to claim 1.