Multilayer ceramic capacitor

Abstract

In the present invention, in order to provide a multilayer ceramic capacitor with which it is possible to reduce manufacturing costs while increasing the effective area of an internal electrode that contributes to capacitance expression: first internal electrode layers (16a) and second internal electrode layers (16b) of a multilayer ceramic capacitor are exposed at a first side surface (12c) and a second side surface (12d) of a laminate (12); the first internal electrode layers (16a) have a first region (23a) along the edge on the first side surface (12c) side of the laminate (12), and a second region (25a) along the edge on the second side surface (12d) side of the laminate (12); the second internal electrode layers (16b) have a third region (23b) along the edge on the first side surface (12c) side of the laminate (12), and a fourth region (25b) along the edge on the second side surface (12d) side of the laminate (12); and a Ni-Mg-O phase is formed from the first region (23a) to the fourth region (25b).

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In recent years, there has been a demand for small, high-capacity multilayer ceramic capacitors. Such multilayer ceramic capacitors have, for example, a rectangular parallelepiped laminate formed by alternately laminating dielectric layers on which internal electrodes are printed and internal electrodes, and then laminating external ceramic layers on the top and bottom surfaces of the laminate, and external electrodes formed on both end surfaces of the laminate.

[0003] Some of these multilayer ceramic capacitors have dielectric layers called side margins formed on the side surfaces of the laminate to prevent the internal electrodes from connecting to the external electrodes on the side surfaces of the laminate.

[0004] Patent Document 1 discloses a method for manufacturing a multilayer ceramic capacitor having the above-mentioned side margins. In this manufacturing method, a mother laminate is formed by stacking ceramic green sheets, each having a conductive film formed on its surface to form an internal electrode. Next, the mother laminate is cut so that the conductive film is exposed on the side where no external electrodes are formed, thereby obtaining a laminate chip. Then, a ceramic slurry that will form the side margins is applied to the internal electrodes exposed on both sides of the cut laminate chip.

[0005] Japanese Unexamined Patent Publication No. 61-248413

[0006] However, the structure of Patent Document 1, in which side margins are formed by applying ceramic slurry to the internal electrodes exposed on both sides of the cut laminate chip, has the following problems: Since no internal electrodes are disposed in the side margins, the effective area of ​​the internal electrodes is reduced. Furthermore, the additional step of forming the side margins increases manufacturing costs.

[0007] Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor that can reduce manufacturing costs while increasing the effective area of ​​the internal electrodes that contribute to the generation of capacitance.

[0008] A multilayer ceramic capacitor according to the present invention comprises: a laminate including a plurality of dielectric layers stacked together, the laminate having first and second main surfaces opposing each other in a stacking direction of the dielectric layers, first and second side surfaces opposing each other in a width direction perpendicular to the stacking direction, and first and second end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; first internal electrode layers arranged on the plurality of dielectric layers and exposed at the first end surfaces; second internal electrode layers arranged on the plurality of dielectric layers and exposed at the second end surfaces; first external electrodes having a base electrode layer arranged on the first end surfaces and a plating layer arranged on the base electrode layer; and second external electrodes having a base electrode layer arranged on the second end surfaces and a plating layer arranged on the base electrode layer, in which the first internal electrode layer is exposed on the first side surfaces and the second side surfaces, and the second internal electrode layer is exposed on the first side surfaces and the second side surfaces.

[0009] In the multilayer ceramic capacitor according to the present invention, the first internal electrode layers are exposed on the first and second side faces, so that the effective area of ​​the internal electrode layers that contribute to the development of the capacitance of the capacitor can be increased. In addition, the process of forming dielectric layers on the widthwise ends can be eliminated, so that the manufacturing cost of the multilayer ceramic capacitor can be reduced.

[0010] According to the present invention, in a multilayer ceramic capacitor, it is possible to reduce manufacturing costs while increasing the effective area of ​​the internal electrodes that contribute to capacitance generation.

[0011] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0012] 1 is a perspective view showing an external appearance of a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to an embodiment of the present invention; 2 is a front view showing a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to an embodiment of the present invention; 3 is a plan view showing a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to an embodiment of the present invention; 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 1; 5 is a schematic cross-sectional view taken along line V-V in FIG. 1; 6 is a schematic cross-sectional view taken along line VI-VI in FIG. 4; and 7 is a schematic cross-sectional view taken along line VII-VII in FIG. 4. (a) is a cross-sectional view taken along line II-II in FIG. 1 showing a structure in which opposing electrode portions of internal electrode layers of a multilayer ceramic capacitor according to an embodiment of the present invention are divided into two; (b) is a cross-sectional view taken along line II-II in FIG. 1 showing a structure in which opposing electrode portions of internal electrode layers of a multilayer ceramic capacitor according to an embodiment of the present invention are divided into three; and (c) is a cross-sectional view taken along line II-II in FIG. 1 showing a structure in which opposing electrode portions of internal electrode layers of a multilayer ceramic capacitor according to an embodiment of the present invention are divided into four.

[0013] As an example of the present invention, a multilayer ceramic capacitor will be described below in this embodiment.

[0014] 1. Multilayer Ceramic Capacitor A multilayer ceramic capacitor 10, which is an example of a multilayer ceramic capacitor according to an embodiment of the present invention, will be described. FIG. 1 is an external perspective view showing a multilayer ceramic capacitor, which is an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a front view showing a multilayer ceramic capacitor, which is an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 3 is a plan view showing a multilayer ceramic capacitor, which is an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 4 is a cross-sectional view taken along line VI-VII in FIG. 1.

[0015] The multilayer ceramic capacitor 10 includes a laminate 12 and external electrodes 30. The laminate 12 is formed by alternately stacking a plurality of dielectric layers 14 and a plurality of internal electrode layers 16, and is composed of an internal layer portion 15a that exhibits capacitance, and a first external layer portion 15b1 and a second external layer portion 15b2 that are arranged to sandwich the internal layer portion 15a from the upper and lower main surfaces.

[0016] Hereinafter, the configuration of each of the laminate 12, the internal electrode layer 16, and the external electrode 30 will be described in that order.

[0017] (Laminate) The laminate 12 includes a plurality of stacked dielectric layers 14 and a plurality of internal electrode layers 16. The laminate 12 further includes a first main surface 12a and a second main surface 12b that face in a height direction x, which is the stacking direction of the plurality of dielectric layers 14; a first side surface 12c and a second side surface 12d that face in a width direction y that is perpendicular to the height direction x; and a first end surface 12e and a second end surface 12f that face in a length direction z that is perpendicular to the height direction x and the width direction y. The length direction z is also defined as the L direction, which is the direction connecting the first end surface 12e and the second end surface 12f. The width direction y is also defined as the W direction, which is the direction connecting the first side surface 12c and the second side surface 12d. The height direction x is also defined as the T direction, which is the direction connecting the first main surface 12a and the second main surface 12b.

[0018] The laminate 12 has a rectangular parallelepiped shape. The "rectangular parallelepiped shape" includes a rectangular parallelepiped with rounded corners and ridges. Note that a corner refers to a portion where three adjacent faces of the laminate 12 intersect, and a ridge refers to a portion where two adjacent faces of the laminate 12 intersect. In other words, a "rectangular parallelepiped" member refers to any member having a first main surface 12a and a second main surface 12b, a first side surface 12c and a second side surface 12d, and a first end surface 12e and a second end surface 12f.

[0019] The first and second main surfaces 12a and 12b, the first and second side surfaces 12c and 12d, and the first and second end surfaces 12e and 12f may have irregularities or the like formed on some or all of them.

[0020] As shown in Figures 4 and 5, the laminate 12 has, in the height direction x connecting the first main surface 12a and the second main surface 12b, an inner layer portion 15a in which a plurality of internal electrode layers 16 face each other, a first outer layer portion 15b1 formed from a plurality of dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 located closest to the first main surface 12a, and a second outer layer portion 15b2 formed from a plurality of dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 located closest to the second main surface 12b.

[0021] The first outer layer portion 15b1 is located on the first main surface 12a side of the laminate 12 and is an aggregate of multiple dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a.

[0022] The second outer layer portion 15b2 is located on the second main surface 12b side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b.

[0023] The region sandwiched between the first outer layer portion 15b1 and the second outer layer portion 15b2 is the inner layer portion 15a.

[0024] The laminate 12 includes an end 22b (L gap) of the laminate 12 that is located between the inner layer portion 15a and the first end face 12e, and between the inner layer portion 15a and the second end face 12f, and that includes an extraction electrode portion of either the first internal electrode layer 16a or the second internal electrode layer 16b described below.

[0025] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 50 to 1000, including the first outer layer portion 15b1 and the second outer layer portion 15b2. The thickness of the dielectric layers 14 is preferably, for example, approximately 0.5 μm to 10 μm.

[0026] The dielectric layer 14 may be formed from, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics composed primarily of BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Depending on the desired properties of the laminate, a material containing a minor component in a smaller amount than the major component, such as a manganese compound, an iron compound, a chromium compound, a cobalt compound, or a nickel compound, may also be used. In particular, in this embodiment, it is preferable for the dielectric layer 14 to contain magnesium as an additive, either as a simple substance or as a compound. Here, MgO is used.

[0027] (Internal Electrode Layers) As shown in Figures 4 and 5, the internal electrode layers 16 include first internal electrode layers 16a and second internal electrode layers 16b. The first internal electrode layers 16a and the second internal electrode layers 16b are alternately stacked with the dielectric layers 14 interposed therebetween.

[0028] The first internal electrode layer 16a is disposed on the surface of the dielectric layer 14. The first internal electrode layer 16a has a first opposing electrode portion 18a that faces the second internal electrode layer 16b, and a first lead electrode portion 20a that is located on one end side of the first internal electrode layer 16a and extends from the first opposing electrode portion 18a to the first end face 12e of the laminate 12. The end of the first lead electrode portion 20a is led out to the first end face 12e and exposed. Specifically, the end of the first lead electrode portion 20a is slightly recessed from the second end face 12f.

[0029] The shape of the first opposing electrode portion 18a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view, although the corners in plan view may be rounded or may be formed obliquely (tapered) in plan view.

[0030] The shape of the first lead electrode portion 20a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first lead electrode portion 20a may be tapered in plan view, with a slope increasing in either direction.

[0031] The second internal electrode layer 16b is disposed on a surface of a dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode layer 16a is disposed. The second internal electrode layer 16b has a second opposing electrode portion 18b that faces the first internal electrode layer 16a, and a second extraction electrode portion 20b that is located on one end side of the second internal electrode layer 16b and extends from the second opposing electrode portion 18b to the second end face 12f of the laminate 12. The end of the second extraction electrode portion 20b is extended to and exposed at the second end face 12f. Specifically, the end of the second extraction electrode portion 20b is slightly recessed from the first end face 12e.

[0032] The shape of the second opposing electrode portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view, although the corners in plan view may be rounded or may be formed obliquely (tapered) in plan view.

[0033] The shape of the second extraction electrode portion 20b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second extraction electrode portion 20b may be tapered in plan view, with a slope increasing in either direction.

[0034] In this embodiment, the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b face each other via the dielectric layer 14, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0035] The number of stacked internal electrode layers 16 is not particularly limited, but is preferably 50 to 1000. The thickness of the internal electrode layers 16 is preferably about 0.2 μm to 2.0 μm.

[0036] Furthermore, in this embodiment, the first internal electrode layer 16 a and the second internal electrode layer 16 b of the internal electrode layer 16 are exposed to the first side surface 12 c and the second side surface 12 d of the laminate 12 .

[0037] 5 and 6, the first internal electrode layer 16a has a first edge 16a1, one of both edges along the width direction y, drawn to and exposed on the first side surface 12c, and a second edge 16a2, the other of both edges along the width direction y, drawn to and exposed on the second side surface 12d.

[0038] 5 and 7, the second internal electrode layer 16b has a third edge 16b1, one of both edges along the width direction y, drawn to and exposed on the first side surface 12c, and a fourth edge 16b2, the other of both edges along the width direction y, drawn to and exposed on the second side surface 12d.

[0039] In this way, the first internal electrode layer 16a and the second internal electrode layer 16b are exposed on the first side surface 12c and the second side surface 12d in the laminate 12. This makes it possible to increase the effective area of ​​the internal electrodes that contribute to capacitance generation. In addition, it is possible to omit the step of forming a dielectric layer on the side end sides in the width direction y where the first side surface 12c and the second side surface 12d are located, thereby reducing manufacturing costs.

[0040] The internal electrode layers 16 can be made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy. In particular, in this embodiment, it is preferable that the material contains at least Ni.

[0041] Furthermore, in this embodiment, it is preferable that an insulating Ni—Mg—O phase is formed in the regions along the exposed portions of the first side surface 12 c and the second side surface 12 d of the laminate 12 of the internal electrode layer 16.

[0042] 5 and 6, the first internal electrode layer 16a has a first region 23a along a first edge 16a1 on the first side surface 12c side and a second region 25a along a second edge 16a2 on the second side surface 12d side. The Ni—Mg—O phase is disposed in the first region 23a and the second region 25a.

[0043] 5 and 7, the second internal electrode layer 16b has a third region 23b along a third edge 16b1 on the first side face 12c side and a fourth region 25b along a fourth edge 16b2 on the second side face 12d side. The Ni-Mg-O phase is disposed in the third region 23b and the fourth region 25b.

[0044] This ensures insulation of the exposed portions of the first and second side faces 12c, 12d of the first internal electrode layer 16a, and also ensures insulation of the exposed portions of the first and second side faces 12c, 12d of the second internal electrode layer 16b.

[0045] Since Mg is contained as an additive in the ceramics that are the raw material of the dielectric layers 14 and Ni is contained as a raw material of the internal electrode layers 16, when the laminate 12 is fired, NiO generated on the internal electrode layer 16 side and MgO contained in the dielectric layers 14 form a solid solution in the first region 23 a and the second region 25 a of the first internal electrode layer 16 a. Similarly, NiO and MgO form a solid solution in the third region 23 b and the fourth region 25 b of the second internal electrode layer 16 b. As a result, a Ni—Mg—O phase is arranged in the first region 23 a, the second region 25 a, the third region 23 b, and the fourth region 25 b.

[0046] Although the oxide NiO produced during firing of the laminate 12 also has insulating properties, the inclusion of the Ni—Mg—O phase has the following advantages. The Ni—Mg—O phase is a solid solution, and once formed, it cannot be restored by an oxidation-reduction reaction. On the other hand, NiO reverts to elemental Ni in a reducing atmosphere. As such, the Ni—Mg—O phase has higher chemical stability than NiO, and therefore can reliably ensure the insulation of the exposed portions of the internal electrode layers 16 on the first side surface 12c and the second side surface 12d of the laminate 12.

[0047] The presence or absence of the Ni-Mg-O phase in the first region 23 a, the second region 25 a, the third region 23 b, and the fourth region 25 b can be analyzed by FE-WDX. Also, in normal SEM observation, it can be identified from two images, a secondary electron image and a backscattered electron image.

[0048] In the first internal electrode layer 16a, the dimension WE1 in the width direction y of the first region 23a and the dimension WE2 in the width direction y of the second region 25a, ie, the dimension in the width direction y, is preferably 5 μm or more and 50 μm or less.

[0049] In the second internal electrode layer 16b, the dimension WE3 in the width direction y of the third region 23b and the dimension WE4 in the width direction y of the fourth region 25b, that is, the dimension in the width direction y, are preferably 5 μm or more and 50 μm or less.

[0050] This is due to the following reason. Specifically, if the dimensions WE1 to WE4 in the width direction y are less than 5 μm, the insulation of each region cannot be maintained. On the other hand, if the dimensions WE1 to WE4 in the width direction y are greater than 50 μm, the effective area of ​​the internal electrodes that contribute to the generation of capacitance becomes smaller. Specifically, the insulating regions (W gap portions) located between the inner layer portion 15a and the first side surface 12c and between the inner layer portion 15a and the second side surface 12d become larger.

[0051] The coverage ratio K1 of the first internal electrode layer 16a with respect to the dielectric layer 14 in the first region 23a and the second region 25a is preferably lower than the coverage ratio K2 of the first internal electrode layer 16a with respect to the dielectric layer 14 in the central portion C1 in the width direction y of the laminate 12. The central portion C1 in the width direction y of the laminate 12 refers to the region sandwiched between the first region 23a and the second region 25a in the width direction y of the first internal electrode layer 16a.

[0052] The coverage K3 of the second internal electrode layer 16b with respect to the dielectric layer 14 in the third region 23b and the fourth region 25b is preferably lower than the coverage K4 of the second internal electrode layer 16b with respect to the dielectric layer 14 in the central portion C2 in the width direction y of the laminate 12. The central portion C2 in the width direction y of the laminate 12 refers to the region sandwiched between the third region 23b and the fourth region 25b in the width direction y of the second internal electrode layer 16b.

[0053] This effectively reduces the dimensions of the W gap portion, and the effect of ensuring insulation in each region can be further improved.

[0054] Preferably, the coverage K1 is 40% or more and 70% or less, and the coverage K3 is 40% or more and 70% or less. If the coverages K1 and K3 are less than 40%, the volume expansion of the Ni-Mg-O phase causes microcracks in the laminate 12, increasing the failure rate in the moisture resistance test. On the other hand, if the coverages K1 and K3 are greater than 70%, the proportion of the Ni-Mg-O phase in each region decreases, reducing insulation, and increasing the failure rate for short circuits.

[0055] Here, the coverage of the internal electrode layer 16 on the dielectric layer 14 is generally measured as follows. That is, the internal electrode layer 16 and the dielectric layer 14 located in the center in the T direction of the laminate 12 are peeled off by electrolytic peeling or the like. Next, the vicinity of the center (position 1 / 2 in the W direction and 1 / 2 in the L direction) of the exposed internal electrode layer 16 is observed using a microscope at a magnification of about 100 times. Then, by analyzing the obtained image, the proportion of the area occupied by the internal electrode layer 16 in the exposed portion is determined as the coverage.

[0056] As shown in FIG. 8, the laminate 12 shown in FIG. 1 may have, in addition to the first internal electrode layer 16a and the second internal electrode layer 16b, a floating internal electrode layer 16c that is not extended to either the first end face 12e or the second end face 12f. The floating internal electrode layer 16c may divide the opposing electrode portion 26c into multiple portions. For example, the opposing electrode portion 26c may have a two-part structure as shown in FIG. 8(a), a three-part structure as shown in FIG. 8(b), a four-part structure as shown in FIG. 8(c), or a structure with more than four parts. By dividing the opposing electrode portion 26c into multiple portions, multiple capacitor components are formed between the opposing first internal electrode layer 16a, the second internal electrode layer 16b, and the floating internal electrode layer 16c, and these capacitor components are connected in series. This reduces the voltage applied to each capacitor component, thereby increasing the withstand voltage of the multilayer ceramic capacitor 10.

[0057] Furthermore, like the first internal electrode layer 16a and the second internal electrode layer 16b, the floating internal electrode layer 16c can be made of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0058] As shown in FIGS. 1 to 3, external electrodes 30 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12.

[0059] The external electrode 30 includes a base electrode layer 32 containing a metal component and glass, and a plating layer 34 disposed on the surface of the base electrode layer 32 .

[0060] The external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0061] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed on at least the surface of the first end face 12e. The first external electrode 30a also extends from the first end face 12e of the laminate 12 and is disposed on part of the first main face 12a, part of the second main face 12b, and part of the first side face 12c, part of the second side face 12d. In this case, the first external electrode 30a is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a.

[0062] The second external electrode 30b is connected to the second internal electrode layer 16b and is disposed on at least the surface of the second end face 12f. The second external electrode 30b also extends from the second end face 12f of the laminate 12 and is disposed on part of the first main surface 12a, part of the second main surface 12b, and part of the first side surface 12c, and part of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b.

[0063] Within the laminate 12, capacitance is formed by the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b opposing each other via the dielectric layer 14. Therefore, capacitance can be obtained between the first external electrode 30a connected to the first internal electrode layer 16a and the second external electrode 30b connected to the second internal electrode layer 16b, and the characteristics of a capacitor are exhibited.

[0064] The base electrode layer 32 includes a first base electrode layer 32a and a second base electrode layer 32b.

[0065] The first base electrode layer 32a is connected to the first internal electrode layer 16a and is disposed on the surface of the first end face 12e. The first base electrode layer 32a also extends from the first end face 12e and is disposed on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In this case, the first base electrode layer 32a is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a.

[0066] The second base electrode layer 32b is connected to the second internal electrode layer 16b and is disposed on the surface of the second end face 12f. The second base electrode layer 32b also extends from the second end face 12f and is disposed on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In this case, the second base electrode layer 32b is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b.

[0067] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0068] Hereinafter, each of the configurations when the base electrode layer 32 is the baked layer, the conductive resin layer, and the thin film layer will be described.

[0069] (In the case of a baking layer) The baking layer contains a metal component and glass. The metal component of the baking layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The baking layer is formed by applying a conductive paste containing glass and a metal to the laminate and baking it. The baking layer is formed by simultaneously baking a laminated chip having internal electrode layers 16 and dielectric layers 14 and the conductive paste applied to the laminated chip, but may also be baked after baking the laminated chip having internal electrode layers 16 and dielectric layers 14. The baking layer may be a multi-layered layer.

[0070] The thickness in the longitudinal direction z connecting the first end face 12e and the second end face 12f at the center in the height direction x of the first base electrode layer 32a located on the first end face 12e is preferably, for example, approximately 10 μm or more and 150 μm or less.

[0071] The thickness in the longitudinal direction z connecting the first end face 12e and the second end face 12f at the center in the height direction x of the second base electrode layer 32b located on the second end face 12f is preferably, for example, approximately 10 μm or more and 150 μm or less.

[0072] The thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center of the length direction z connecting the first end face 12e and the second end face 12f of the first base electrode layer 32a located on part of the first main surface 12a and the second main surface 12b is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0073] Furthermore, the thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center of the length direction z connecting the first end face 12e and the second end face 12f of the second base electrode layer 32b located on part of the first main surface 12a and the second main surface 12b is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0074] The thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z connecting the first end face 12e and the second end face 12f of the first base electrode layer 32a located on part of the first side surface 12c and the second side surface 12d is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0075] Furthermore, it is preferable that the thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z connecting the first end face 12e and the second end face 12f of the second base electrode layer 32b located on part of the first side surface 12c and the second side surface 12d is, for example, approximately 10 μm or more and 100 μm or less.

[0076] (Conductive Resin Layer) The conductive resin layer has a first conductive resin layer and a second conductive resin layer.

[0077] The first conductive resin layer is preferably arranged as a first base electrode layer 32a so as to further cover other layers such as a baked layer, and the second conductive resin layer is preferably arranged as a second base electrode layer 32b so as to further cover other layers such as a baked layer.

[0078] Specifically, the first and second conductive resin layers, as the first and second base electrode layers 32a and 32b, are preferably disposed on other layers, such as baked layers, located on the first and second end faces 12e and 12f, and extend to the first and second main faces 12a and 12b and the first and second side faces 12c and 12d, respectively. However, the first and second conductive resin layers may be disposed only on the other layers, such as baked layers, located on the first and second end faces 12e and 12f.

[0079] The thickness of the first conductive resin layer and the second conductive resin layer is preferably, for example, about 10 μm or more and 200 μm or less.

[0080] The first conductive resin layer and the second conductive resin layer contain a thermosetting resin and a metal component.

[0081] Because the first conductive resin layer and the second conductive resin layer contain a thermosetting resin, they are more flexible than the base electrode layer 32 made of, for example, a plating film or a fired product of a conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10.

[0082] Specific examples of the thermosetting resin include various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0083] The first conductive resin layer and the second conductive resin layer preferably contain a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, and imidazole-based compounds can be used as the curing agent for the epoxy resin.

[0084] The metal contained in the first conductive resin layer and the second conductive resin layer may be Ag, Cu, or an alloy thereof. Alternatively, a metal powder having an Ag-coated surface may be used. When using a metal powder having an Ag-coated surface, it is preferable to use Cu or Ni as the metal powder.

[0085] Alternatively, Cu that has been treated to prevent oxidation can also be used. The reason for using Ag-coated metal is that it allows the base metal to be inexpensive while maintaining the above-mentioned properties of Ag.

[0086] The metal contained in the first conductive resin layer and the second conductive resin layer is preferably contained in an amount of 35 vol % or more and 75 vol % or less with respect to the volume of the entire conductive resin.

[0087] The shape of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited, and the conductive filler may be spherical, flat, or the like.

[0088] The average particle size of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, about 0.3 μm or more and 10 μm or less.

[0089] The metals contained in the first conductive resin layer and the second conductive resin layer are mainly responsible for the electrical conductivity of the conductive resin layers. Specifically, contact between the conductive fillers forms an electrical path inside the conductive resin layers.

[0090] The metal contained in the first conductive resin layer and the second conductive resin layer may be spherical, flat, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0091] The conductive resin layer may be formed directly on the laminate without forming a baked layer.

[0092] (In the case of a thin film layer) When the base electrode layer 32 is formed as a thin film layer, the thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 10 μm or less in thickness on which metal particles are deposited.

[0093] Next, the first plating layer 34a and the second plating layer 34b, which are the plating layers 34 disposed on the base electrode layer 32, will be described with reference to FIGS. 2 and 3. FIG.

[0094] The first plating layer 34a and the second plating layer 34b contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag--Pd alloy, Au, and the like.

[0095] The first plating layer 34a is disposed so as to completely cover the first base electrode layer 32a, and the second plating layer 34b is disposed so as to completely cover the second base electrode layer 32b.

[0096] The first plating layer 34a and the second plating layer 34b may be formed of multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of a lower plating layer (Ni plating layer) formed on the base electrode layer 32 by Ni plating and an upper plating layer (Sn plating layer) formed on the lower plating layer by Sn plating. That is, in this case, the first plating layer 34a has a first lower plating layer and a first upper plating layer located on the surface of the first lower plating layer. Furthermore, the second plating layer 34b has a second lower plating layer and a second upper plating layer located on the surface of the second lower plating layer.

[0097] The lower plating layer made of Ni plating is used to prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10, and the upper plating layer made of Sn plating is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, making it easier to mount.

[0098] The thickness of each of the lower plating layer and the upper plating layer is preferably 1.0 μm or more and 15.0 μm or less.

[0099] The dimension in the length direction z of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension L, the dimension in the height direction x of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension T, and the dimension in the width direction y of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are as follows: L in the length direction z is 0.2 mm to 10.0 mm, W in the width direction y is 0.1 mm to 10.0 mm, and T in the height direction x is 0.1 mm to 5.0 mm. The dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0100] 1 , the first internal electrode layer 16 a and the second internal electrode layer 16 a of the internal electrode layer 16 are exposed on the first side surface 12 c and the second side surface 12 d of the laminate 12, respectively. This allows the effective area of ​​the internal electrodes that contribute to capacitance generation to be expanded in the multilayer ceramic capacitor 10. Furthermore, it is possible to omit the step of forming a dielectric layer on the side end sides in the width direction y where the first side surface 12 c and the second side surface 12 d are located, thereby reducing the manufacturing cost of the multilayer ceramic capacitor 10.

[0101] In the multilayer ceramic capacitor 10, an insulating Ni—Mg—O phase is preferably formed in the internal electrode layers 16: a first region 23 a along the first edge 16 a1 on the first side surface 12 c side of the laminate 12, a second region 25 a along the second edge 16 a2 on the second side surface 12 d side of the laminate 12, a third region 23 b along the third edge 16 b1 on the first side surface 12 c side of the laminate 12, and a fourth region 25 b along the fourth edge 16 b2 on the second side surface 12 d side of the laminate 12. This ensures insulation of exposed portions of the first internal electrode layer 16 a on the first side surface 12 c and the second side surface 12 d, and of exposed portions of the second internal electrode layer 16 b on the first side surface 12 c and the second side surface 12 d.

[0102] Furthermore, in the first internal electrode layer 16a of the multilayer ceramic capacitor 10, the dimension WE1 in the width direction y of the first region 23a and the dimension WE2 in the width direction y of the second region 25a, i.e., the dimension in the width direction y, are preferably 5 μm or more and 50 μm or less. Furthermore, in the second internal electrode layer 16b, the dimension WE3 in the width direction y of the third region 23b and the dimension WE4 in the width direction y of the fourth region 25b are preferably 5 μm or more and 50 μm or less.

[0103] Furthermore, in the multilayer ceramic capacitor 10, the coverage K1 of the first internal electrode layers 16a with respect to the dielectric layers 14 in the first region 23a and the second region 25a is preferably lower than the coverage K2 of the first internal electrode layers 16a with respect to the dielectric layers 14 in the central portion C1 in the width direction y of the laminate 12. Also, the coverage K3 of the second internal electrode layers 16b with respect to the dielectric layers 14 in the third region 23b and the fourth region 25b is preferably lower than the coverage K4 of the second internal electrode layers 16b with respect to the dielectric layers 14 in the central portion C2 in the width direction y of the laminate 12. This effectively reduces the dimension of the W gap, thereby further improving the effect of ensuring insulation in each region.

[0104] Furthermore, in the multilayer ceramic capacitor 10, it is preferable that the coverage K1 is 40% or more and 70% or less, and the coverage K3 is 40% or more and 70% or less.

[0105] 2. Method for Manufacturing a Multilayer Ceramic Capacitor Next, a method for manufacturing a multilayer ceramic capacitor will be described.

[0106] (1) Prepare a dielectric sheet and a conductive paste for the internal electrode layers. The dielectric sheet and the conductive paste for the internal electrode layers contain a binder (for example, a known organic binder) and a solvent (for example, a known organic binder).

[0107] (2) Next, a conductive paste for the internal electrode layers is printed in stripes on the dielectric sheets in a predetermined pattern by, for example, screen printing or gravure printing, to prepare a dielectric sheet on which a first internal electrode pattern corresponding to the first internal electrode layer is formed and a dielectric sheet on which a second internal electrode pattern corresponding to the second internal electrode layer is formed. Note that, with regard to the dielectric sheets, a dielectric sheet for an outer layer on which no internal electrode pattern is printed is also prepared.

[0108] (3) A predetermined number of dielectric sheets for outer layers on which no internal electrode pattern is formed are stacked to form a portion that will become the outer layer portion, and then a dielectric sheet on which a first internal electrode pattern is formed and a dielectric sheet on which a second internal electrode pattern is formed are stacked on top of the outer layer portion in sequence, shifted in the width direction (short direction) of the stripe pattern, to form a portion that will become the inner layer portion.

[0109] (4) Furthermore, a predetermined number of dielectric sheets on which no internal electrode pattern is printed are stacked on top of the internal electrode pattern corresponding to the internal electrode layer located on the outermost surface of the inner layer portion to form a portion that will become the outer layer portion, thereby producing a laminated sheet.

[0110] (5) The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0111] (6) The laminated block is cut to a predetermined size to obtain laminated chips. At this time, corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0112] (7) The laminated chip is fired to produce the laminate 12. The firing temperature depends on the materials of the ceramic and the internal electrode layers 16, but is preferably 900°C or higher and 1400°C or lower. In particular, by adjusting the oxygen concentration within the range of 900°C or higher and 1100°C or lower, a Ni-Mg-O phase can be formed in regions along both edges of the internal electrode layers 16 in the width direction y of the fired laminate 12.

[0113] (8) Subsequently, the base electrode layer is formed. The base electrode layer is a baked layer. A conductive paste for the first base electrode layer and a conductive paste for the second base electrode layer, each containing a glass component and a metal component, are prepared.

[0114] (9) A conductive paste is applied to the first end face and the second end face, which are both end faces of the laminate 12, by a method such as dipping or screen printing, and then a baking process is performed to form the first base electrode layer and the second base electrode layer. The baking temperature at this time is preferably 700° C. or higher and 900° C. or lower.

[0115] (10) When the base electrode layer is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed on the surface of the baked layer, or the conductive resin layer may be formed directly on the laminate without forming a baked layer.

[0116] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate 12, and then performing a heat treatment at a temperature of 250°C to 550°C to thermally cure the resin and form the conductive resin layer. The heat treatment is preferably performed in an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration below 100 ppm.

[0117] The conductive resin paste can be applied by, for example, a method of applying the conductive resin paste by extruding it through a slit or a roller transfer method.

[0118] (11) Plating is applied to the surface of the base electrode layer to form a plating layer. In this embodiment, two plating layers are formed on the surfaces of the first and second base electrode layers. Specifically, a Ni plating layer is formed on the first and second base electrode layers, and a Sn plating layer is formed on the Ni plating layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0119] In this manner, the multilayer ceramic capacitor 10 according to the embodiment shown in FIG. 1 is manufactured.

[0120] 3. Experimental Example Next, in order to confirm the effects of the multilayer ceramic capacitor according to the present invention described above, multilayer ceramic capacitor samples were fabricated according to the manufacturing method described above as experimental samples, and experiments were conducted to confirm the changes in insulation properties and capacitance due to the presence or absence of the first to fourth regions and the changes in the width direction y of the first to fourth regions.

[0121] (1) Specifications of Samples in Experimental Examples First, according to the above-described method for manufacturing a multilayer ceramic capacitor, samples of multilayer ceramic capacitors according to Examples 1 to 7 having the following specifications were manufactured. Note that the multilayer ceramic capacitor according to the comparative example was fired in step (7) of the manufacturing method at a temperature in the range of 900°C to 1100°C, with the oxygen concentration set to a lower level than in the experimental examples.

[0122] (Specifications of the multilayer ceramic capacitor) Dimensions of the multilayer ceramic capacitor (design values): L x W x T = 1.17 mm x 0.68 mm x 0.68 mm Main ceramic material of the dielectric layer: BaTiO3 Capacitance: 22 μF Material of the internal electrode layer: Ni Structure of the external electrode: Conductive metal (Cu) and glass component Plating layer Two layers formed: Ni plating layer and Sn plating layer Ni plating layer thickness: Approximately 3 μm Sn plating layer thickness: Approximately 5 μm

[0123] (2) Evaluation method for insulation (IR) The insulation of the multilayer capacitor was measured using a digital ultra-high resistance / microcurrent meter (5451 manufactured by ADCMT) under the measurement conditions of a rated voltage of 6.3 V-1 min. The criterion for judging insulation (IR) is 6.8 or more (150 Ω·F) as Log(IR), so taking into consideration variations, 6.8 or less was evaluated as ×, 6.9 to 7.4 was evaluated as △, and 7.5 or more was evaluated as ◯.

[0124] (3) Measurement method of capacitance (Cap) The capacitance (Cap) was measured using a meter (4278A manufactured by Agilent Technologies) under the conditions of 120 Hz and 0.5 Vrms to measure the capacitance (C). The criteria for the capacitance (Cap) were as follows: 18.7 or more and 25.3 or less: ◯; 17.6 or more and 18.7 or less: △; and 17.6 or less and 25.3 or more: ×.

[0125] (4) Results Table 1 shows the evaluation of the insulation properties and capacitance of the dielectric layers of the laminates according to Examples 1 to 7 and the comparative example, as well as the overall evaluation.

[0126]

[0127] According to Table 1, each of the samples of Examples 1 to 7 has the first to fourth regions in which the Ni—Mg—O phase is arranged in the internal electrode layer, and therefore, samples with ensured insulation were obtained.

[0128] In addition, in each of the samples of Examples 2 to 5, the length in the width direction y of the first region to the fourth region in which the Ni-Mg-O phase is arranged in the internal electrode layer is 5 μm or more and 50 μm or less, and therefore, the measurement result of the insulation property was 7.5 or more, which was a better result.

[0129] Furthermore, according to each sample of Example 1 to Example 7, it was confirmed that the smaller the length in the width direction y of the first region to the fourth region in which the Ni-Mg-O phase is arranged in the internal electrode layer, the more the effective area of ​​the internal electrode layer can be enlarged and the more the capacitance can be improved.

[0130] On the other hand, in the sample according to the comparative example, although it was confirmed that the capacitance was improved, insulation was not obtained because the internal electrode layer did not have the first to fourth regions in which the Ni-Mg-O phase was arranged.

[0131] From the above results, it has been suggested that in the present invention, when the internal electrode layers have the first to fourth regions in which the Ni-Mg-O phase is arranged, the effective area of ​​the internal electrodes that contribute to capacity development can be expanded. Also, it is possible to omit the step of forming a dielectric layer on the side end sides in the width direction y where the first side surface and the second side surface are located, thereby reducing the manufacturing cost of the multilayer ceramic capacitor 10 and ensuring insulation of the exposed portions on the first side surface and the second side surface of the first internal electrode layer and the exposed portions on the first side surface and the second side surface of the second internal electrode layer.

[0132] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited to this.

[0133] In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position or arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0134] 10 Multilayer ceramic capacitor 12 Laminate 12a First main surface 12b Second main surface 12c First side surface 12d Second side surface 12e First end surface 12f Second end surface 14 Dielectric layer 15a Inner layer portion 15b1 First outer layer portion 15b2 Second outer layer portion 16 Internal electrode layer 16a First internal electrode layer 16a1 First edge 16a2 Second edge 16b Second internal electrode layer 16b1 Third edge 16b2 Fourth edge 16c Floating internal electrode layer 18a First opposing electrode portion 18b Second opposing electrode portion 20a First lead electrode portion 20b Second lead electrode portion 22b End portion 23a First region 23b Third region 25a Second region 25b Fourth region 26c Counter electrode portion 30 External electrode 30a First external electrode 30b Second external electrode 32 Base electrode layer 32a First base electrode layer 32b Second base electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer x Height direction (stacking direction) y Width direction z Length direction

Claims

1. A laminate including a plurality of dielectric layers stacked together, the laminate having a first main surface and a second main surface facing each other in a stacking direction of the plurality of dielectric layers, a first side surface and a second side surface facing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in a length direction perpendicular to the stacking direction and the width direction; a first internal electrode layer disposed on the plurality of dielectric layers and exposed at the first end surface; a second internal electrode layer disposed on the plurality of dielectric layers and exposed at the second end surface; a first external electrode having a base electrode layer disposed on the first end surface and a plating layer disposed on the base electrode layer; and a second external electrode having a base electrode layer disposed on the second end surface and a plating layer disposed on the base electrode layer, a multilayer ceramic capacitor, wherein the first internal electrode layer has a first region along an edge of the first side surface side of the laminate and a second region along an edge of the second side surface side of the laminate, a Ni-Mg-O phase being formed in the first region and the second region; and the second internal electrode layer has a third region along the edge of the first side surface side of the laminate and a fourth region along the edge of the second side surface side of the laminate, a Ni-Mg-O phase being formed in the third region and the fourth region.

2. The multilayer ceramic capacitor as recited in claim 1, wherein the width dimension of each of the first region and the second region is 5 μm or more and 50 μm or less, and the width dimension of each of the third region and the fourth region is 5 μm or more and 50 μm or less.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the dielectric layers contain at least Mg.