Through electrode substrate, semiconductor package, and manufacturing method thereof

Abstract

This through electrode substrate comprises: a glass substrate that includes a first surface, a second surface located on a side opposite to the first surface, and first and second through holes penetrating from the first surface to the second surface; a through electrode located in the first through hole; a resin member located in the second through hole; and a wiring layer located between the glass substrate and a semiconductor element. The first through hole includes a first opening that is opened in the first surface of the glass substrate, and a second opening that is opened in the second surface of the glass substrate. The second through hole includes a third opening that is opened in the first surface of the glass substrate, and a fourth opening that is opened in the second surface of the glass substrate. The through electrode closes the first through hole between the first opening and the second opening. The resin member continuously extends from the third opening to the fourth opening in the second through hole.

Description

Through-hole electrode substrate, semiconductor package, and manufacturing method thereof

[0001] FIELD Embodiments of the present disclosure relate to a through hole electrode substrate, a semiconductor package, and methods for manufacturing the same.

[0002] Through-hole electrode substrates are used in a variety of applications. A through-hole electrode substrate is a component comprising a substrate including a first surface, a second surface, and through holes, and through electrodes located in the through holes. A through-hole electrode substrate is used, for example, as an interposer. An interposer is a component interposed between two electrical components. A through-hole electrode substrate is interposed, for example, between a semiconductor element and a mounting substrate. A through-hole electrode substrate may include a wiring layer. The wiring layer performs the function of, for example, relocating pads or terminals of a semiconductor element to another location. Such a wiring layer is also called a rewiring layer. The wiring layer is disposed on a substrate. A glass substrate may also be used as the substrate for a through-hole electrode substrate.

[0003] Japanese Patent Application Laid-Open No. 2023-75206

[0004] The wiring layer may contain gaseous components. The gaseous components contained in the wiring layer must be discharged to the outside. However, when a glass substrate is used as the substrate for the through-hole electrode substrate, in a semiconductor package in which a semiconductor element is mounted on the through-hole electrode substrate, the wiring layer is disposed between the glass substrate and the semiconductor element. In this case, since the glass substrate and the semiconductor element are not permeable to gas, the gaseous components contained in the wiring layer are not easily discharged to the outside. As a result, the gaseous components contained in the wiring layer cannot be sufficiently discharged to the outside, and the gaseous components may remain in the wiring layer. The remaining gaseous components may cause the wiring layer to expand, which may result in the wiring layer peeling off from the glass substrate. As a result, the reliability of the through-hole electrode substrate may be reduced.

[0005] An object of the embodiments of the present disclosure is to provide a through hole electrode substrate and a semiconductor package that can effectively solve such problems, as well as methods for manufacturing the same.

[0006] Embodiments of the present disclosure relate to the following [1] to

[21] : [1] A through electrode substrate on which a semiconductor element is mounted, comprising: a glass substrate including a first surface, a second surface opposite to the first surface, and a first through hole and a second through hole penetrating from the first surface to the second surface, a through electrode located in the first through hole, a resin member located in the second through hole, and a wiring layer located between the glass substrate and the semiconductor element, wherein the first through hole includes a first opening that opens in the first surface of the glass substrate and a second opening that opens in the second surface of the glass substrate, the second through hole includes a third opening that opens in the first surface of the glass substrate and a fourth opening that opens in the second surface of the glass substrate, the through electrode closes the first through hole between the first opening and the second opening, and the resin member extends continuously from the third opening to the fourth opening within the second through hole.

[0007] [2] The through electrode substrate according to [1], wherein the first through hole is located between the first opening and the second opening and includes a first minimum portion having the smallest hole diameter of the first through hole, and the through electrode does not block the first through hole at the first opening and the second opening, and blocks the first through hole at least at the first minimum portion.

[0008] [3] The through electrode substrate according to [1], wherein the through electrode is filled in the first through hole.

[0009] [4] The through-hole electrode substrate according to any one of [1] to [3], wherein the resin member is filled in the second through-hole.

[0010] [5] The through electrode substrate according to any one of [1] to [4], wherein the second through hole has the same shape as the first through hole.

[0011] [6] The through electrode substrate according to any one of [1] to [5], wherein the second through hole is located within a region that overlaps with the semiconductor element in a plan view.

[0012] [7] The through electrode substrate according to [6], wherein the second through hole is located within a region located 3 mm inward from an outer periphery of the semiconductor element in a plan view.

[0013] [8] The through electrode substrate according to [6] or [7], wherein a plurality of the second through holes are arranged at equal intervals in a region overlapping with the semiconductor element in a plan view.

[0014] [9] Within the area overlapping the semiconductor element in plan view, 100 mm ２ The through electrode substrate according to any one of [6] to [8], wherein 10 to 250 of the second through holes are located per one region.

[0015]

[10] The through-hole electrode substrate according to any one of [1] to [9], wherein the diameter of the third opening of the second through-hole is 50 μm or more and 100 μm or less.

[0016]

[11] The through hole electrode substrate according to any one of [1] to

[10] , wherein the thickness of the glass substrate is 100 μm or more and 1200 μm or less.

[0017]

[12] The planar area of ​​the semiconductor element is 100 mm ２ The through-hole electrode substrate according to any one of [1] to

[11] above.

[0018]

[13] A through electrode substrate on which a semiconductor element is mounted, comprising: a glass substrate including a first surface, a second surface located opposite to the first surface, and a first through hole and a second through hole penetrating from the first surface to the second surface; through electrodes located in the first through holes and the second through holes, respectively; a resin member located at least in the second through holes; and a wiring layer located between the glass substrate and the semiconductor element, wherein the first through hole includes a first opening that opens in the first surface of the glass substrate, a second opening that opens in the second surface of the glass substrate, and a first wall surface located between the first opening and the second opening; the second through hole includes a third opening that opens in the first surface of the glass substrate, a fourth opening that opens in the second surface of the glass substrate, and a second wall surface located between the third opening and the fourth opening; and the through electrode located in the first through hole extends along the first wall surface from the first opening to the second opening, a through electrode substrate, wherein the through electrode located in the second through hole extends along the second wall surface from the third opening to the fourth opening; the resin member is located inside the through electrode in the second through hole and extends continuously from the third opening to the fourth opening; the hole diameter of the third opening of the second through hole is 50 μm or more and 100 μm or less; and the thickness of the through electrode located in the second through hole is 5 μm or more and 25 μm or less.

[0019]

[14] The through electrode substrate according to

[13] , wherein the second through hole is located within a region that overlaps with the semiconductor element in a plan view.

[0020]

[15] Within the area overlapping the semiconductor element in plan view, ２ The through electrode substrate according to

[14] , wherein 27 to 2500 of the second through holes are located per one region.

[0021]

[16] A semiconductor package comprising: the through hole electrode substrate according to any one of [1] to

[15] ; and a semiconductor element mounted on the through hole electrode substrate.

[0022]

[17] A through electrode substrate comprising: a glass substrate including a first surface, a second surface located opposite to the first surface, and a first through hole and a second through hole penetrating from the first surface to the second surface; a through electrode located in the first through hole; and a resin member located in the second through hole, wherein the first through hole includes a first opening that opens on the first surface of the glass substrate and a second opening that opens on the second surface of the glass substrate, the second through hole includes a third opening that opens on the first surface of the glass substrate and a fourth opening that opens on the second surface of the glass substrate, the through electrode closes the first through hole between the first opening and the second opening, and the resin member extends continuously from the third opening to the fourth opening within the second through hole.

[0023]

[18] A glass substrate including a first surface, a second surface located opposite to the first surface, and a first through hole and a second through hole penetrating from the first surface to the second surface; through electrodes located in the first through holes and the second through holes, respectively; and a resin member located at least in the second through holes, wherein the first through holes include a first opening opened in the first surface of the glass substrate, a second opening opened in the second surface of the glass substrate, and a first wall surface located between the first opening and the second opening, the second through hole includes a third opening opened in the first surface of the glass substrate, a fourth opening opened in the second surface of the glass substrate, and a second wall surface located between the third opening and the fourth opening, the through electrode located in the first through hole extends along the first wall surface from the first opening to the second opening, and the through electrode located in the second through hole extends along the second wall surface from the third opening to the fourth opening, a through electrode substrate, wherein the resin member is located inside the through electrode within the second through hole and extends continuously from the third opening to the fourth opening, a diameter of the third opening of the second through hole is 50 μm or more and 100 μm or less, and a thickness of the through electrode located within the second through hole is 5 μm or more and 25 μm or less.

[0024]

[19] A method for manufacturing a through electrode substrate on which a semiconductor element is mounted, the method comprising the steps of: preparing a glass substrate including a first surface, a second surface opposite to the first surface, and a first through hole and a second through hole penetrating from the first surface to the second surface; forming a through electrode in the first through hole; forming a resin member in the second through hole; and forming a wiring layer on the first surface of the glass substrate, wherein the first through hole includes a first opening that opens on the first surface of the glass substrate and a second opening that opens on the second surface of the glass substrate, the second through hole includes a third opening that opens on the first surface of the glass substrate and a fourth opening that opens on the second surface of the glass substrate, the through electrode closes the first through hole between the first opening and the second opening, and the resin member extends continuously from the third opening to the fourth opening within the second through hole.

[0025]

[20] A method for manufacturing a through electrode substrate on which a semiconductor element is mounted, the method comprising: preparing a glass substrate including a first surface, a second surface located opposite to the first surface, and a first through hole and a second through hole penetrating from the first surface to the second surface; forming through electrodes in the first through holes and the second through holes, respectively; forming a resin member in at least the second through holes; and forming a wiring layer on the first surface of the glass substrate, wherein the first through holes include a first opening opened on the first surface of the glass substrate, a second opening opened on the second surface of the glass substrate, and a first wall surface located between the first opening and the second opening; the second through holes include a third opening opened on the first surface of the glass substrate, a fourth opening opened on the second surface of the glass substrate, and a second wall surface located between the third opening and the fourth opening; the through electrodes located in the first through holes extend along the first wall surface from the first opening to the second opening, a through electrode substrate manufacturing method, wherein the through electrode located in the second through hole extends along the second wall surface from the third opening to the fourth opening; the resin member is located inside the through electrode in the second through hole and extends continuously from the third opening to the fourth opening; a diameter of the third opening of the second through hole is 50 μm or more and 100 μm or less; and a thickness of the through electrode located in the second through hole is 5 μm or more and 25 μm or less.

[0026]

[21] A method for manufacturing a semiconductor package, comprising: a step of manufacturing a through hole electrode substrate by the method for manufacturing a through hole electrode substrate according to

[19] or

[20] ; and a step of mounting a semiconductor element on the through hole electrode substrate.

[0027] According to the embodiments of the present disclosure, the reliability of a through hole electrode substrate including a glass substrate can be improved.

[0028] 14. A cross-sectional view showing a semiconductor package according to an embodiment. A cross-sectional view showing an enlarged first through hole of FIG. 1. A cross-sectional view showing an enlarged second through hole of FIG. 1. A plan view of the semiconductor package of FIG. 1. A cross-sectional view for explaining a glass substrate preparation step in a manufacturing method of a through electrode substrate according to an embodiment. A cross-sectional view for explaining a through electrode formation step in a manufacturing method of a through electrode substrate according to an embodiment. A cross-sectional view for explaining a resin member formation step in a manufacturing method of a through electrode substrate according to an embodiment. A cross-sectional view for explaining a wiring layer formation step in a manufacturing method of a through electrode substrate according to an embodiment. A cross-sectional view for explaining a semiconductor element mounting step in a manufacturing method of a semiconductor package according to an embodiment. A cross-sectional view showing a modified first through hole of FIG. 2. A cross-sectional view showing a modified second through hole of FIG. 3. A cross-sectional view showing a further modified second through hole of FIG. 11. A cross-sectional view showing another modified first through hole of FIG. 2. A cross-sectional view showing another modified second through hole of FIG. 3. A cross-sectional view showing a further modified first through hole of FIG. 13. A cross-sectional view showing a further modified second through hole of FIG. 14. A diagram showing an example of a product in which a semiconductor package is mounted. A table showing evaluation results in a first example. A table showing evaluation results in a second example.

[0029] The through-hole electrode substrate, semiconductor package, and manufacturing method thereof will be described in detail below with reference to the drawings. The embodiments described below are examples of embodiments of the present disclosure, and the present disclosure is not limited to these embodiments. In this specification, terms such as "substrate," "base material," "sheet," and "film" are not distinguished from one another solely based on differences in name. For example, the term "substrate" is a concept that includes members that may be called sheets or films. "Surface" refers to a surface that coincides with the planar direction of the target plate-like member when viewed holistically and comprehensively. The normal direction used with respect to a plate-like member refers to the normal direction to the surface of the member. As used in this specification, terms such as "parallel" and "orthogonal," as well as values ​​of length and angle, that specify shape, geometric conditions, and their degree, are interpreted without being bound by strict meaning but include a range within which similar functions can be expected.

[0030] In this specification, when multiple upper limit value candidates and multiple lower limit value candidates are listed for a certain parameter, the numerical range of the parameter may be constructed by combining any one upper limit value candidate with any one lower limit value candidate. For example, consider a description that reads, "Parameter B is, for example, A1 or more, or may be A2 or more, or may be A3 or more. Parameter B is, for example, A4 or less, or may be A5 or less, or may be A6 or less." In this case, the numerical range of parameter B may be A1 or more and A4 or less, A1 or more and A5 or less, A1 or more and A6 or less, A2 or more and A4 or less, A2 or more and A5 or less, A2 or more and A6 or less, A3 or more and A4 or less, A3 or more and A5 or less, or A3 or more and A6 or less.

[0031] In the drawings referred to in this embodiment, the same parts or parts having similar functions are denoted by the same or similar reference numerals, and repeated explanations thereof may be omitted. Furthermore, the dimensional ratios of the drawings may differ from the actual ratios for the convenience of explanation, and some components may be omitted from the drawings.

[0032] 1 is a cross-sectional view showing a semiconductor package 1 according to one embodiment. The semiconductor package 1 is a device mounted on a mounting substrate 2. The mounting substrate 2 is, for example, a BGA substrate, a motherboard, or the like. The semiconductor package 1 includes a through-hole electrode substrate 10 and a semiconductor element 3. The semiconductor element 3 is, for example, a CPU, a GPU, an FPGA, a sensor, a memory, or the like.

[0033] (Through electrode substrate) The through electrode substrate 10 is a substrate on which the semiconductor element 3 is mounted. The through electrode substrate 10 is electrically connected to the semiconductor element 3. The through electrode substrate 10 is located between the mounting substrate 2 and the semiconductor element 3. The through electrode substrate 10 electrically connects the mounting substrate 2 and the semiconductor element 3. The through electrode substrate 10 includes a glass substrate 12, through electrodes 20, and a resin member 30. The through electrode substrate 10 may also include a wiring layer 40. Each component of the through electrode substrate 10 will be described below.

[0034] (Glass Substrate) The glass substrate 12 has insulating properties. The glass substrate 12 is made of a glass material. Examples of glass materials include alkali-free glass. The alkali-free glass is glass that does not contain alkali components such as sodium or potassium. The alkali-free glass contains, for example, boric acid instead of the alkali component. The alkali-free glass also contains, for example, an alkaline earth metal oxide such as calcium oxide or barium oxide.

[0035] The thickness T0 of the glass substrate 12 is, for example, 100 μm or more, or may be 200 μm or more, or 300 μm or more. The thickness T0 of the glass substrate 12 is, for example, 1200 μm or less, or may be 800 μm or less, or may be 500 μm or less.

[0036] The glass substrate 12 includes a first surface 13, a second surface 14, a first through hole 15, and a second through hole 16. The first surface 13 is a surface facing the semiconductor element 3 side. The first surface 13 may be formed flat. The second surface 14 is a surface facing the mounting substrate 2 side. The second surface 14 is located on the opposite side to the first surface 13. The second surface 14 may be formed flat. The first through hole 15 and the second through hole 16 penetrate from the first surface 13 to the second surface 14. The glass substrate 12 may include a plurality of first through holes 15. The glass substrate 12 may include a plurality of second through holes 16.

[0037] Figure 2 is an enlarged cross-sectional view of the first through hole 15 in Figure 1. To simplify the drawing, the dimensional ratio in Figure 2 is different from that in Figure 1. The first through hole 15 includes a first opening 15a and a second opening 15b. The first opening 15a is an opening that opens to the first surface 13 of the glass substrate 12. The second opening 15b is an opening that opens to the second surface 14 of the glass substrate 12. The second opening 15b is located on the opposite side to the first opening 15a.

[0038] The hole diameter R1 of the first opening 15a of the first through hole 15 is, for example, 50 μm or more, or may be 65 μm or more, or 75 μm or more. The hole diameter R1 is, for example, 100 μm or less, or may be 90 μm or less, or may be 85 μm or less. The same applies to the hole diameter R2 of the second opening 15b of the first through hole 15. The hole diameter R2 may be equal to the hole diameter R1. The hole diameter R2 may be smaller or larger than the hole diameter R1.

[0039] The first through hole 15 may include a first minimum portion 15c. The first minimum portion 15c is located between the first opening 15a and the second opening 15b. The first minimum portion 15c is a portion of the first through hole 15 having the smallest diameter R3. The diameter of the first through hole 15 may decrease from the first opening 15a toward the first minimum portion 15c. The diameter of the first through hole 15 may decrease from the second opening 15b toward the first minimum portion 15c.

[0040] The first through hole 15 may include a first wall surface 15d and a second wall surface 15e. The first wall surface 15d is a wall surface located between the first opening 15a and the first minimum portion 15c. The first wall surface 15d may extend straight from the first opening 15a to the first minimum portion 15c, or may extend in a curved manner. For example, the first wall surface 15d may be curved in a concave or convex shape. The second wall surface 15e is a wall surface located between the second opening 15b and the first minimum portion 15c. The second wall surface 15e may extend straight from the second opening 15b to the first minimum portion 15c, or may extend in a curved manner. For example, the second wall surface 15e may be curved in a concave or convex shape. The first wall surface 15d and the second wall surface 15e are connected to each other at the first minimum portion 15c.

[0041] The first minimum portion 15c may be located midway between the first surface 13 and the second surface 14 in the thickness direction of the glass substrate 12. The first minimum portion 15c may be located closer to the first surface 13 than to the second surface 14 in the thickness direction of the glass substrate 12. The first minimum portion 15c may be located closer to the second surface 14 than to the first surface 13 in the thickness direction of the glass substrate 12.

[0042] The diameter R3 at the first minimum portion 15c of the first through hole 15 is smaller than the diameter R1 at the first opening 15a of the first through hole 15. The diameter R3 at the first minimum portion 15c of the first through hole 15 is smaller than the diameter R2 at the second opening 15b of the first through hole 15. The diameter R3 at the first minimum portion 15c of the first through hole 15 is, for example, 20 μm or more, or may be 35 μm or more, or 45 μm or more. The diameter R3 is, for example, 80 μm or less, or may be 65 μm or less, or may be 55 μm or less.

[0043] The first opening 15a may have a circular outline in a plan view. In this case, the hole diameter R1 means the diameter of the first opening 15a. The second opening 15b may have a circular outline in a plan view. In this case, the hole diameter R2 means the diameter of the second opening 15b. The first minimum portion 15c may have a circular outline in a plan view. In this case, the hole diameter R3 means the diameter of the first minimum portion 15c. In this specification, the term "plan view" means observing an object along a direction perpendicular to the first surface 13 or the second surface 14 of the glass substrate 12 (the normal direction).

[0044] The first opening 15a may have an outline other than a circle in a plan view. In this case, the hole diameter R1 is calculated from the diameter of a circle obtained by converting the first opening 15a into a circle having the same planar area as the first opening 15a. The second opening 15b may have an outline other than a circle in a plan view. In this case, the hole diameter R2 is calculated from the diameter of a circle obtained by converting the second opening 15b into a circle having the same planar area as the second opening 15b. The first minimum portion 15c may have an outline other than a circle in a plan view. In this case, the hole diameter R3 is calculated from the diameter of a circle obtained by converting the first minimum portion 15c into a circle having the same planar area as the first opening 15a. In this specification, the term "planar area" refers to the area within the outline of an object in a plan view.

[0045] The first through-hole 15 may be located in an area A1 that overlaps with the semiconductor element 3 in a plan view. The first through-hole 15 does not have to be located in an area that does not overlap with the semiconductor element 3 in a plan view.

[0046] Figure 3 is an enlarged cross-sectional view of the second through hole 16 of Figure 1. To simplify the drawing, the dimensional ratio in Figure 3 is different from that in Figure 1. The second through hole 16 may have the same shape as the first through hole 15. The second through hole 16 includes a third opening 16a and a fourth opening 16b. The third opening 16a is an opening that opens to the first surface 13 of the glass substrate 12. The fourth opening 16b is an opening that opens to the second surface 14 of the glass substrate 12. The fourth opening 16b is located on the opposite side to the third opening 16a.

[0047] The hole diameter R4 of the third opening 16a of the second through hole 16 may be equal to the hole diameter R1 of the first opening 15a of the first through hole 15. The hole diameter R5 of the fourth opening 16b of the second through hole 16 may also be equal to the hole diameter R2 of the second opening 15b of the first through hole 15. The hole diameter R4 of the third opening 16a of the second through hole 16 is, for example, 50 μm or more, 65 μm or more, or 75 μm or more. The hole diameter R4 is, for example, 100 μm or less, 90 μm or less, or 85 μm or less. The same applies to the hole diameter R5 of the fourth opening 16b of the second through hole 16. The hole diameter R5 may be equal to the hole diameter R4. The hole diameter R5 may be smaller or larger than the hole diameter R4.

[0048] The hole diameter R4 of the third opening 16a of the second through hole 16 may be smaller than the hole diameter R1 of the first opening 15a of the first through hole 15. The hole diameter R5 of the fourth opening 16b of the second through hole 16 may also be smaller than the hole diameter R2 of the second opening 15b of the first through hole 15. In this case, the ratio of the hole diameter R4 to the hole diameter R1 is, for example, 0.2 or more, or may be 0.3 or more, or may be 0.4 or more. The ratio of the hole diameter R4 to the hole diameter R1 is, for example, 0.7 or less, or may be 0.6 or less, or may be 0.5 or less. The same applies to the ratio of the hole diameter R5 to the hole diameter R2.

[0049] The second through hole 16 may include a second minimum portion 16c. The second minimum portion 16c is located between the third opening 16a and the fourth opening 16b. The second minimum portion 16c is a portion of the second through hole 16 having the smallest diameter R6. The diameter of the second through hole 16 may decrease from the third opening 16a toward the second minimum portion 16c. The diameter of the second through hole 16 may decrease from the fourth opening 16b toward the second minimum portion 16c.

[0050] The second through hole 16 may include a third wall surface 16d and a fourth wall surface 16e. The third wall surface 16d is a wall surface located between the third opening 16a and the second minimum portion 16c. The third wall surface 16d may extend straight from the third opening 16a to the second minimum portion 16c, or may extend in a curved manner. For example, the third wall surface 16d may be curved in a concave or convex shape. The fourth wall surface 16e is a wall surface located between the fourth opening 16b and the second minimum portion 16c. The fourth wall surface 16e may extend straight from the fourth opening 16b to the second minimum portion 16c, or may extend in a curved manner. For example, the fourth wall surface 16e may be curved in a concave or convex shape. The third wall surface 16d and the fourth wall surface 16e are connected to each other at the second minimum portion 16c.

[0051] The second minimum portion 16c may be located midway between the first surface 13 and the second surface 14 in the thickness direction of the glass substrate 12. The second minimum portion 16c may be located closer to the first surface 13 than to the second surface 14 in the thickness direction of the glass substrate 12. The second minimum portion 16c may be located closer to the second surface 14 than to the first surface 13 in the thickness direction of the glass substrate 12.

[0052] The diameter R6 at the second minimum portion 16c of the second through hole 16 is smaller than the diameter R4 at the third opening 16a of the second through hole 16. The diameter R6 at the second minimum portion 16c of the second through hole 16 is smaller than the diameter R5 at the fourth opening 16b of the second through hole 16. The diameter R6 at the second minimum portion 16c of the second through hole 16 may be equal to the diameter R3 at the first minimum portion 15c of the first through hole 15. The diameter R6 at the second minimum portion 16c of the second through hole 16 is, for example, 20 μm or more, 35 μm or more, or 45 μm or more. The diameter R6 is, for example, 80 μm or less, 65 μm or less, or 55 μm or less.

[0053] The hole diameter R6 at the second minimum portion 16c of the second through hole 16 may be smaller than the hole diameter R3 at the first minimum portion 15c of the first through hole 15. In this case, the ratio of the hole diameter R6 to the hole diameter R3 is, for example, 0.2 or more, or may be 0.3 or more, or may be 0.4 or more. The ratio of the hole diameter R6 to the hole diameter R3 is, for example, 0.7 or less, or may be 0.6 or less, or may be 0.5 or less.

[0054] The third opening 16a may have a circular outline in a plan view. In this case, the hole diameter R4 means the diameter of the third opening 16a. The fourth opening 16b may have a circular outline in a plan view. In this case, the hole diameter R5 means the diameter of the fourth opening 16b. The second minimum portion 16c may have a circular outline in a plan view. In this case, the hole diameter R6 means the diameter of the second minimum portion 16c.

[0055] The third opening 16a may have an outline other than a circle in a plan view. In this case, the hole diameter R4 is calculated from the diameter of a circle obtained by converting the third opening 16a into a circle having the same planar area as the third opening 16a. The fourth opening 16b may have an outline other than a circle in a plan view. In this case, the hole diameter R5 is calculated from the diameter of a circle obtained by converting the fourth opening 16b into a circle having the same planar area as the fourth opening 16b. The second minimum portion 16c may have an outline other than a circle in a plan view. In this case, the hole diameter R6 is calculated from the diameter of a circle obtained by converting the second minimum portion 16c into a circle having the same planar area as the second opening 16c.

[0056] 4 is a plan view of the semiconductor package 1 of FIG. The second through hole 16 may be located in an area A1 that overlaps with the semiconductor element 3 in a plan view. The second through hole 16 may be located in an area that overlaps with the center of the semiconductor element 3 in a plan view. In particular, the second through hole 16 may be located in an area A2 that is located 3 mm inward from the outer peripheral edge 3e of the semiconductor element 3 in a plan view.

[0057] The second through-holes 16 may be located in a region that is a distance L1 inward from the outer peripheral edge 3 e of the semiconductor element 3 in a plan view. The distance L1 is, for example, 3 mm or more, 4 mm or more, or 5 mm or more. The distance L1 is, for example, 8 mm or less, 7 mm or less, or 6 mm or less.

[0058] The vertical dimension L2 of the semiconductor element 3 in plan view is, for example, 10 mm or more, may be 20 mm or more, or may be 30 mm or more. The same applies to the horizontal dimension L3 of the semiconductor element 3 in plan view. In this case, the planar area of ​​the semiconductor element 3 is, for example, 100 mm ２ or more, and 400 mm ２ It may be 900 mm or more. ２ It may be more than that.

[0059] The plurality of second through holes 16 may be arranged at equal intervals in an area A1 that overlaps with the semiconductor element 3 in a plan view. In particular, the plurality of second through holes 16 may be arranged at equal intervals in an area A2 that is located 3 mm inward from the outer peripheral edge 3e of the semiconductor element 3 in a plan view. In the example shown in FIG. 4 , the plurality of second through holes 16 are arranged in a lattice pattern. Although not shown, the plurality of second through holes 16 may also be arranged in a staggered pattern. The plurality of second through holes 16 may also be arranged in any other pattern.

[0060] In the area A1 overlapping with the semiconductor element 3 in a plan view, ２ In particular, in the area A2 located 3 mm inward from the outer peripheral edge 3 e of the semiconductor element 3 in a plan view, 10 to 250 second through holes 16 may be located within a 100 mm ２ There may be 10 or more and 250 or less second through holes 16 positioned per unit area.

[0061] 100mm ２ The number of second through holes 16 per unit is, for example, 10 or more, or may be 50 or more, or may be 100 or more. ２The number of second through holes 16 per hole is, for example, 1000 or less, or may be 500 or less, or may be 250 or less.

[0062] The second through holes 16 do not have to be located in areas that do not overlap with the semiconductor element 3 in a plan view.

[0063] 1 and 2 , the through electrode 20 is located inside the first through hole 15. The through electrode 20 extends along the first through hole 15 from the first surface 13 to the second surface 14. The through electrode 20 is located along the first wall surface 15 d and the second wall surface 15 e of the first through hole 15.

[0064] The through electrode 20 closes the first through hole 15 between the first opening 15a and the second opening 15b. As shown in Fig. 2, the through electrode 20 may not close the first through hole 15 at the first opening 15a and the second opening 15b, but may close the first through hole 15 at least at the first smallest portion 15c. The through electrode 20 may include a first portion 21, a second portion 22, and a closed portion 23.

[0065] The first portion 21 is located between the first opening 15a and the first smallest portion 15c. The first portion 21 is located along the first wall surface 15d of the first through hole 15. In a plan view, the first portion 21 extends along the first wall surface 15d of the first through hole 15 so as to surround the center of the first opening 15a of the first through hole 15. The first portion 21 is a portion that does not block the first through hole 15. A first recess 21c of the through electrode 20 is formed in the region surrounded by the first portion 21.

[0066] The second portion 22 is located between the second opening 15b and the first minimum portion 15c. The second portion 22 is located on the opposite side to the first portion 21 in the thickness direction of the glass substrate 12. The second portion 22 is located along the second wall surface 15e of the first through hole 15. In a plan view, the second portion 22 extends along the second wall surface 15e of the first through hole 15 so as to surround the center of the second opening 15b of the first through hole 15. The second portion 22 is a portion that does not block the first through hole 15. A second recess 22c of the through electrode 20 is formed in the region surrounded by the second portion 22.

[0067] The blocking portion 23 is located between the first portion 21 and the second portion 22. The blocking portion 23 is located along the first wall surface 15d, the second wall surface 15e, and the first narrowest portion 15c of the first through hole 15. The blocking portion 23 may be located midway between the first opening 15a and the second opening 15b. The blocking portion 23 is a portion that blocks the first through hole 15.

[0068] As shown in FIG. 3 , the through electrode 20 does not have to be located inside the second through hole 16 .

[0069] The through electrode 20 is conductive. The through electrode 20 may contain at least a plating material. The plating material may contain, for example, a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, or zinc, or an alloy using any of these. A large portion of the through electrode 20 may be made of the plating material. Although not shown, the through electrode 20 may include a seed layer. The seed layer may be located between the first wall surface 15d and the second wall surface 15e of the first through hole 15 and the plating material.

[0070] (Resin Member) As shown in Figures 1 and 3, the resin member 30 is located inside the second through hole 16. The resin member 30 extends continuously from the third opening 16a to the fourth opening 16b inside the second through hole 16. That is, the resin member 30 extends without interruption between the third opening 16a and the fourth opening 16b. As shown in Figure 3, the resin member 30 may be filled inside the second through hole 16. That is, the resin member 30 may fill the second through hole 16 without any gaps.

[0071] 1 and 2, the resin member 30 may be located inside the first through hole 15. As shown in Fig. 2, the resin member 30 may be located inside the first recess 21c and the second recess 22c of the through electrode 20 inside the first through hole 15. The resin member 30 may fill the first recess 21c and the second recess 22c of the through electrode 20. In other words, the resin member 30 may fill the first recess 21c and the second recess 22c of the through electrode 20 without any gaps.

[0072] The resin member 30 has insulating properties and heat resistance and is made of a resin material, such as an organic material such as polyimide, epoxy, acrylic, or polyphenyl ether.

[0073] The water vapor permeability of the resin member 30 measured in accordance with JIS K7129-1:2019 under an environment of a temperature of 40°C and a relative humidity of 90% is, for example, 10 g / (m ２ · day) or more, and 50 g / (m ２ · day) or more, and ２ The water vapor transmission rate may be measured using a water vapor transmission rate measuring device. For example, a Super Detect (manufactured by MS Scientific) may be used as the water vapor transmission rate measuring device.

[0074] 1 , the wiring layer 40 is located between the glass substrate 12 and the semiconductor element 3. The wiring layer 40 may be located on the first surface 13 of the glass substrate 12. The wiring layer 40 is electrically connected to the through electrodes 20 of the glass substrate 12. The wiring layer 40 includes an insulating layer 41 and a conductive layer 42.

[0075] The insulating layer 41 extends over the first surface 13 of the glass substrate 12. The conductive layer 42 is located within the insulating layer 41. The conductive layer 42 includes wiring and pads. The wiring is a portion that is not exposed from the insulating layer 41 and extends vertically and horizontally within the insulating layer 41. The pad is a portion that is exposed from the insulating layer 41 and is in electrical contact with other components.

[0076] The wiring layer 40 may include a plurality of stacked wiring layers. In the example shown in FIG. 1 , the wiring layer 40 includes a first wiring layer 40A and a second wiring layer 40B. The first wiring layer 40A is located on the first surface 13 of the glass substrate 12. The second wiring layer 40B is located on the first wiring layer 40A. The second wiring layer 40B is stacked on the first wiring layer 40A. Although not shown, the wiring layer 40 may include an additional wiring layer. Each of the plurality of wiring layers may include an insulating layer 41 and a conductive layer 42.

[0077] The semiconductor element 3 may be located on the wiring layer 40. The wiring layer 40 is electrically connected to the semiconductor element 3. The wiring layer 40 may be electrically connected to the semiconductor element 3 by bumps 43. As a result, the wiring layer 40 electrically connects the through electrodes 20 of the glass substrate 12 to the semiconductor element 3. An adhesive layer 44 may be located between the wiring layer 40 and the semiconductor element 3. The wiring layer 40 and the semiconductor element 3 may be bonded to each other by the adhesive layer 44.

[0078] The insulating layer 41 has insulating properties. The insulating layer 41 may contain an organic material. Examples of the organic material include polyimide and epoxy. The conductive layer 42 has conductivity. The conductive layer 42 may contain at least a plating material. The plating material may contain, for example, a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, or zinc, or an alloy using any of these. A large portion of the conductive layer 42 may be composed of the plating material. Although not shown, the conductive layer 42 may include a seed layer. Plating may be formed on the seed layer.

[0079] The thickness T1 of the wiring layer 40 is, for example, 20 μm or more, or may be 30 μm or more, or 35 μm or more. The thickness T1 of the wiring layer 40 is, for example, 60 μm or less, or may be 50 μm or less, or may be 45 μm or less.

[0080] 1 , a wiring layer 45 may be located between the glass substrate 12 and the mounting substrate 2. The wiring layer 45 may be located on the second surface 14 of the glass substrate 12. The wiring layer 45 may be electrically connected to the through electrodes 20 of the glass substrate 12. The wiring layer 45 may include an insulating layer 41 and a conductive layer 42.

[0081] The wiring layer 45 may include a plurality of stacked wiring layers. In the example shown in FIG. 1 , the wiring layer 45 includes a third wiring layer 45A and a fourth wiring layer 45B. The third wiring layer 45A is located on the second surface 14 of the glass substrate 12. The fourth wiring layer 45B is located on the third wiring layer 45A. The fourth wiring layer 45B is stacked on the third wiring layer 45A. Although not shown, the wiring layer 45 may include an additional wiring layer. Each of the plurality of wiring layers may include an insulating layer 41 and a conductive layer 42.

[0082] The mounting substrate 2 may be located below the wiring layer 45. The wiring layer 45 may be electrically connected to the mounting substrate 2. The wiring layer 45 may be electrically connected to the mounting substrate 2 by solder balls 46. As a result, the wiring layer 45 electrically connects the through electrodes 20 of the glass substrate 12 to the mounting substrate 2. In this way, the semiconductor element 3 and the mounting substrate 2 are electrically connected to each other via the wiring layers 40, 45 and the through electrodes 20.

[0083] The thickness T2 of the wiring layer 45 is, for example, 20 μm or more, or may be 30 μm or more, or 35 μm or more. The thickness T2 of the wiring layer 45 is, for example, 60 μm or less, or may be 50 μm or less, or may be 45 μm or less. The thickness T2 of the wiring layer 45 may be equal to the thickness T1 of the wiring layer 40. The thickness T2 of the wiring layer 45 may be smaller or larger than the thickness T1 of the wiring layer 40.

[0084] The dimensions (thickness, hole diameter, distance, etc.) of the above-mentioned components of the through hole electrode substrate 10 are calculated based on images taken by a scanning electron microscope.

[0085] (Method for Manufacturing Semiconductor Package) A method for manufacturing the semiconductor package 1 will be described. The method for manufacturing the semiconductor package 1 includes a through electrode substrate manufacturing step and a semiconductor element mounting step. In the through electrode substrate manufacturing step, the through electrode substrate 10 is manufactured by the following method for manufacturing the through electrode substrate 10.

[0086] (Method for Manufacturing Through Electrode Substrate) A method for manufacturing the through electrode substrate 10 will be described. The method for manufacturing the through electrode substrate 10 includes a glass substrate preparation step, a through electrode formation step, a resin member formation step, and a wiring layer formation step.

[0087] (Glass Substrate Preparation Step) First, a glass substrate preparation step is performed. In the glass substrate preparation step, a glass substrate 12 is prepared as shown in Fig. 5. As described above, the glass substrate 12 includes a first surface 13, a second surface 14, a first through hole 15, and a second through hole 16. The glass substrate preparation step may include a through hole formation step.

[0088] In the through hole forming step, a first through hole 15 and a second through hole 16 are formed in the glass substrate 12. More specifically, first, a resist layer is formed on at least one of the first surface 13 or the second surface 14 of the glass substrate 12. Next, openings are formed in the resist layer at positions corresponding to the first through hole 15 and the second through hole 16. Next, the glass substrate 12 is processed through the openings in the resist layer. In this way, the first through hole 15 and the second through hole 16 are formed in the glass substrate 12. As a method for processing the glass substrate 12, a dry etching method, a wet etching method, or the like may be used.

[0089] In the through hole forming step, the first through holes 15 and the second through holes 16 may be formed in the glass substrate 12 by irradiating the glass substrate 12 with a laser. In this case, a resist layer may not be provided. Alternatively, after irradiating the glass substrate 12 with a laser, the first through holes 15 and the second through holes 16 may be formed in the glass substrate 12 by performing an etching process using a wet etching method.

[0090] (Through Electrode Forming Step) Subsequently, the through electrode forming step is performed. In the through electrode forming step, the through electrode 20 is formed in the first through hole 15 as shown in Fig. 6. The through electrode forming step may include a plating step.

[0091] In the plating formation process, plating is formed in the first through hole 15. More specifically, first, a seed layer is formed in the first through hole 15 of the glass substrate 12. For example, the seed layer is formed by a method such as sputtering. Next, a resist layer is formed on the first surface 13 and the second surface 14 of the glass substrate 12. Next, plating is formed in the first through hole 15 by an electrolytic plating method. For example, the glass substrate 12 is immersed in an electrolytic plating solution. Then, a current is passed through the seed layer to deposit plating on the seed layer. Thereafter, the resist layer is removed from the first surface 13 and the second surface 14 of the glass substrate 12. In this manner, a through electrode 20 is formed in the first through hole 15.

[0092] (Resin Member Forming Process) Next, the resin member forming process is carried out. In the resin member forming process, as shown in FIG. 7 , a resin member 30 is formed in the second through hole 16. More specifically, first, a liquid resin material is poured into the second through hole 16. Next, the resin material in the second through hole 16 is cured. This may be heat curing. It may be a photosensitive type, the interior may be photocured, or light may not be applied. For example, the resin material is cured by irradiating it with ultraviolet light. In this manner, the resin member 30 is formed in the second through hole 16.

[0093] In the resin member forming step, as shown in FIG. 7 , a resin member 30 may be formed in the first through hole 15. More specifically, first, a liquid resin material is poured into the first recess 21 c and the second recess 22 c of the through electrode 20 in the first through hole 15. Next, the resin material in the first through hole 15 is cured. For example, the resin material is cured by irradiating it with ultraviolet light. In this manner, the resin member 30 is formed in the first through hole 15.

[0094] (Wiring Layer Forming Process) Thereafter, the wiring layer forming process is carried out. In the wiring layer forming process, as shown in Fig. 8, a wiring layer 40 is formed on the first surface 13 of the glass substrate 12. The wiring layer forming process may include a conductive layer forming process and an insulating layer forming process.

[0095] In the conductive layer forming process, a conductive layer 42 is formed on the first surface 13 of the glass substrate 12. More specifically, first, a seed layer is formed on the first surface 13 of the glass substrate 12. For example, the seed layer is formed by sputtering. Subsequently, a resist layer is formed on the seed layer. The resist layer is formed in a position where the conductive layer 42 will not be formed. Next, a plating layer is formed on the portion of the seed layer not covered by the resist layer by electrolytic plating. For example, the glass substrate 12 is immersed in an electrolytic plating solution. Then, a current is passed through the seed layer to deposit a plating layer on the seed layer. Thereafter, the resist layer is removed from the first surface 13 of the glass substrate 12. The seed layer overlapping the resist layer is also removed. In the insulating layer forming process, an insulating layer 41 is formed on the first surface 13 of the glass substrate 12 so as to straddle the conductive layer 42. Multiple stacked wiring layers may be formed by repeatedly forming the conductive layer 42 and the insulating layer 41. In this manner, a wiring layer 40 is formed on the first surface 13 of the glass substrate 12.

[0096] In the wiring layer forming step, a wiring layer 45 may be formed on the second surface 14 of the glass substrate 12 by a similar method, as shown in FIG.

[0097] As a result of the above, the through electrode substrate 10 including the glass substrate 12, the through electrodes 20, the resin member 30, and the wiring layer 40 is obtained.

[0098] (Semiconductor element mounting process) Then, the semiconductor element mounting process is carried out. In the semiconductor element mounting process, as shown in FIG. 9 , the semiconductor element 3 is mounted on the through hole electrode substrate 10. More specifically, the semiconductor element 3 is arranged on the wiring layer 40 of the through hole electrode substrate 10. The semiconductor element 3 is arranged on the wiring layer 40 so that the wiring layer 40 and the semiconductor element 3 are electrically connected to each other. The wiring layer 40 and the semiconductor element 3 may be electrically connected to each other by bumps 43. An adhesive layer 44 may be arranged between the wiring layer 40 and the semiconductor element 3. The wiring layer 40 and the semiconductor element 3 may be bonded to each other by the adhesive layer 44.

[0099] As a result of the above, a semiconductor package 1 including the through electrode substrate 10 and the semiconductor element 3 is obtained.

[0100] The semiconductor package 1 obtained in this manner is mounted on a mounting substrate 2, as shown in Fig. 1. The semiconductor package 1 may be mounted on the mounting substrate 2 so that the wiring layer 45 and the mounting substrate 2 are electrically connected to each other. The wiring layer 45 and the mounting substrate 2 may be electrically connected to each other by solder balls 46. In this manner, the semiconductor element 3 and the mounting substrate 2 are electrically connected to each other via the wiring layers 40, 45 and the through electrodes 20.

[0101] As described above, the wiring layer may contain gaseous components. Examples of gaseous components include residual solvents, components decomposed by thermal decomposition, and water vapor resulting from evaporation of moisture absorbed during reliability testing. The gaseous components contained in the wiring layer must be discharged to the outside. However, when the wiring layer is disposed between a glass substrate and a semiconductor element, the glass substrate and the semiconductor element are not permeable to gas, making it difficult for the gaseous components contained in the wiring layer to be discharged to the outside. As a result, the gaseous components contained in the wiring layer cannot be sufficiently discharged to the outside, and the gaseous components may remain in the wiring layer. The remaining gaseous components may cause the wiring layer to expand and peel off from the glass substrate. As a result, the reliability of the through-hole electrode substrate may be reduced.

[0102] In contrast, according to the present embodiment, the glass substrate 12 includes a second through hole 16. The resin member 30 extends continuously from the third opening 16a to the fourth opening 16b within the second through hole 16. This allows gas components in the wiring layer 40 to be discharged to the outside from the second surface 14 side through the second through hole 16, thereby preventing the gas components from accumulating in the wiring layer 40. This prevents the wiring layer 40 from expanding due to the accumulated gas components and peeling off from the glass substrate 12. As a result, the reliability of the through hole electrode substrate 10 can be improved.

[0103] Furthermore, according to this embodiment, the resin member 30 is filled in the second through-hole 16. This allows gas components in the wiring layer 40 to pass smoothly through the second through-hole 16 without stagnating therein. This allows the gas components in the wiring layer 40 to be effectively discharged to the outside from the second surface 14 side. As a result, the reliability of the through-hole electrode substrate 10 can be further improved.

[0104] Furthermore, according to this embodiment, the second through holes 16 have the same shape as the first through holes 15. As a result, in the manufacturing process of the through electrode substrate 10, the first through holes 15 and the second through holes 16 can be formed together in the glass substrate 12 without distinguishing between the first through holes 15 and the second through holes 16. This makes it possible to simplify the manufacturing of the through electrode substrate 10 and suppress an increase in the manufacturing cost of the through electrode substrate 10.

[0105] Furthermore, in this embodiment, the second through holes 16 are located in the region A1 that overlaps with the semiconductor element 3 in a plan view. Gas components in the wiring layer 40 are less likely to be discharged to the outside in the region A1 that overlaps with the semiconductor element 3 in a plan view. That is, in the region A1 that overlaps with the semiconductor element 3 in a plan view, the presence of the semiconductor element 3, which is less permeable to gas, makes it difficult for the gas components in the wiring layer 40 to be discharged to the outside. Therefore, by positioning the second through holes 16 in the region A1 that overlaps with the semiconductor element 3 in a plan view, the gas components in the wiring layer 40 can be effectively discharged to the outside from the second surface 14 side through the second through holes 16.

[0106] Furthermore, according to this embodiment, the second through holes 16 are located in a region A2 that is 3 mm inward from the outer peripheral edge 3e of the semiconductor element 3 in a planar view. Gas components in the wiring layer 40 are less likely to be discharged to the outside in a region that overlaps with the central portion of the semiconductor element 3 in a planar view than in a region that overlaps with the peripheral portion of the semiconductor element 3 in a planar view. That is, in a region that overlaps with the peripheral portion of the semiconductor element 3 in a planar view, gas components in the wiring layer 40 flow in the planar direction (a direction perpendicular to the thickness direction) and can be discharged to the outside from a region that does not overlap with the semiconductor element 3 in a planar view. On the other hand, in a region that overlaps with the central portion of the semiconductor element 3 in a planar view, the distance to the outer peripheral edge 3e of the semiconductor element 3 is long, so gas components in the wiring layer 40 are less likely to be discharged to the outside from a region that does not overlap with the semiconductor element 3 in a planar view. In particular, gas components in the wiring layer 40 are less likely to be discharged to the outside in a region A2 that is 3 mm inward from the outer peripheral edge 3e of the semiconductor element 3 in a planar view. Therefore, since the second through hole 16 is located within the region A2, which is 3 mm inside the outer peripheral edge 3e of the semiconductor element 3 when viewed in a plane, the gas components in the wiring layer 40 can be effectively discharged to the outside through the second through hole 16 from the second surface 14 side.

[0107] Furthermore, according to this embodiment, the second through holes 16 are arranged at equal intervals in the region A1 that overlaps with the semiconductor element 3 in a plan view. This allows the gas components in the wiring layer 40 to be discharged uniformly in the plane. Therefore, the gas components in the wiring layer 40 can be discharged to the outside more effectively.

[0108] Furthermore, according to this embodiment, in the area A1 that overlaps with the semiconductor element 3 in a plan view, ２ 10 to 250 second through holes 16 are located per 100 mm. ２ By providing 10 or more second through holes 16 per 100 mm, gas components contained in the wiring layer 40 can be appropriately discharged to the outside. ２ By setting the number of second through holes 16 per unit to 250 or less, a decrease in connection density can be suppressed.

[0109] Furthermore, according to this embodiment, the planar area of ​​the semiconductor element 3 is 100 mm ２ That's all. In particular, when such a large semiconductor element 3 is mounted on the through hole electrode substrate 10, the gas components in the wiring layer 40 are less likely to be discharged to the outside. That is, in the region overlapping with the center of the semiconductor element 3 in plan view, the distance to the outer periphery 3e of the semiconductor element 3 becomes longer, and the gas components in the wiring layer 40 are less likely to be discharged to the outside from the region not overlapping with the semiconductor element 3 in plan view. This embodiment can be suitably applied to the through hole electrode substrate 10 on which such a large semiconductor element 3 is mounted.

[0110] The above-described embodiment can be modified in various ways. Below, modified examples will be described with reference to the drawings as necessary. In the following description and the drawings used in the following description, parts that can be configured similarly to the above-described embodiment will be designated by the same reference numerals as those used for corresponding parts in the above-described embodiment. Duplicate descriptions will be omitted. Furthermore, if it is clear that the effects obtained in the above-described embodiment can also be obtained in modified examples, the description of those effects may be omitted.

[0111] (First Modification) Fig. 10 is a cross-sectional view showing a modification of the first through hole 15 of Fig. 2. As shown in Fig. 10, the first through hole 15 may be formed in a cylindrical shape. The first through hole 15 may not include the first minimum portion 15c as shown in Fig. 2. For example, the diameter of the first through hole 15 may be constant from the first opening 15a to the second opening 15b. The wall surface 15f of the first through hole 15 may extend straight from the first opening 15a to the second opening 15b.

[0112] In this case, the through electrode 20 may fill the first through hole 15. That is, the through electrode 20 may fill the first through hole 15 without leaving any gaps. The through electrode 20 may close the first through hole 15 at the first opening 15a and the second opening 15b. The through electrode 20 may close the first through hole 15 over the entire range from the first opening 15a to the second opening 15b.

[0113] Fig. 11 is a cross-sectional view showing a modified example of the second through hole 16 of Fig. 3. As shown in Fig. 11, the second through hole 16 may also be formed in a cylindrical shape. That is, the second through hole 16 may have the same shape as the first through hole 15. The second through hole 16 may not include the second minimum portion 16c as shown in Fig. 3. For example, the diameter of the second through hole 16 may be constant from the third opening 16a to the fourth opening 16b. The wall surface 16f of the second through hole 16 may extend straight from the third opening 16a to the fourth opening 16b.

[0114] In this case, too, the resin member 30 extends continuously from the third opening 16 a to the fourth opening 16 b within the second through hole 16. That is, the resin member 30 extends without interruption between the third opening 16 a and the fourth opening 16 b. The resin member 30 may be filled into the second through hole 16. That is, the resin member 30 may fill the second through hole 16 without any gaps.

[0115] (Second Modification) Fig. 12 is a cross-sectional view showing another modification of the second through hole 16 of Fig. 11 . As shown in Fig. 12 , a through electrode 20 may be located inside the second through hole 16. The through electrode 20 may extend along the second through hole 16 from the first surface 13 to the second surface 14. The through electrode 20 may be located along the wall surface 16f of the second through hole 16. The through electrode 20 may be formed in a cylindrical shape along the wall surface 16f of the second through hole 16. The through electrode 20 does not block the second through hole 16 at any position between the third opening 16a and the fourth opening 16b.

[0116] In this case as well, the resin member 30 extends continuously from the third opening 16a to the fourth opening 16b within the second through hole 16. That is, the resin member 30 extends without interruption between the third opening 16a and the fourth opening 16b. The resin member 30 may be located inside the through electrode 20 within the second through hole 16. The resin member 30 may fill the inside of the through electrode 20. That is, the resin member 30 may fill the inside of the through electrode 20 without any gaps.

[0117] (Third Modification) FIG. 13 is a cross-sectional view showing another modification of the first through hole 15 of FIG. 2. As shown in FIG. 13, the first through hole 15 may be formed in a cylindrical shape. The first through hole 15 may not include the first minimum portion 15c as shown in FIG. 2. For example, the diameter of the first through hole 15 may be constant from the first opening 15a to the second opening 15b. The first through hole 15 includes a wall surface 15f (first wall surface) located between the first opening 15a and the second opening 15b. The wall surface 15f of the first through hole 15 may extend straight from the first opening 15a to the second opening 15b.

[0118] The hole diameter R1 of the first opening 15a of the first through hole 15 is the same as the example shown in FIG. 2 . That is, the hole diameter R1 is, for example, 50 μm or more, and may be 65 μm or more, or 75 μm or more. The hole diameter R1 is, for example, 100 μm or less, 90 μm or less, or 85 μm or less. The same applies to the hole diameter R2 of the second opening 15b of the first through hole 15. The hole diameter R2 may be equal to the hole diameter R1. The hole diameter R2 may be smaller or larger than the hole diameter R1.

[0119] 13 , the through electrode 20 is located inside the first through hole 15. The through electrode 20 located inside the first through hole 15 is also referred to as a through electrode 20a. The through electrode 20a extends along the wall surface 15f of the first through hole 15 from the first opening 15a to the second opening 15b. The through electrode 20a may be formed in a cylindrical shape along the wall surface 15f of the first through hole 15. The through electrode 20a does not have to close the first through hole 15 between the first opening 15a and the second opening 15b.

[0120] The thickness T3 of the through electrode 20a is, for example, 5 μm or more, and may be 8 μm or more, or 10 μm or more. The thickness T3 is, for example, 25 μm or less, and may be 20 μm or less, or 15 μm or less. The thickness T3 is the dimension of the through electrode 20a in a plane perpendicular to the thickness direction of the glass substrate 12, and is the dimension of the through electrode 20a along the radial direction of the first through hole 15. The thickness T3 is measured at a midpoint between the first opening 15a and the second opening 15b.

[0121] As shown in FIG. 13 , a resin member 30 may be located inside the first through hole 15. The resin member 30 may be located inside the through electrode 20a inside the first through hole 15. The resin member 30 may be formed on the through electrode 20a inside the first through hole 15. The resin member 30 may extend continuously from the first opening 15a to the second opening 15b inside the first through hole 15. That is, the resin member 30 may extend without interruption between the first opening 15a and the second opening 15b. The resin member 30 may fill the inside of the through electrode 20a. That is, the resin member 30 may fill the inside of the through electrode 20a without any gaps.

[0122] FIG. 14 is a cross-sectional view showing another modified example of the second through hole 16 of FIG. 3 . As shown in FIG. 14 , the second through hole 16 may have a shape similar to that of the first through hole 15 shown in FIG. 13 . That is, as shown in FIG. 14 , the second through hole 16 may be formed in a cylindrical shape. The second through hole 16 does not need to include the second minimum portion 16c as shown in FIG. 3 . For example, the diameter of the second through hole 16 may be constant from the third opening 16a to the fourth opening 16b. The second through hole 16 includes a wall surface 16f (second wall surface) located between the third opening 16a and the fourth opening 16b. The wall surface 16f of the second through hole 16 may extend straight from the third opening 16a to the fourth opening 16b.

[0123] The diameter R4 of the third opening 16a of the second through hole 16 is the same as the example shown in FIG. 3 . That is, the diameter R4 of the third opening 16a of the second through hole 16 may be equal to the diameter R1 of the first opening 15a of the first through hole 15. The diameter R5 of the fourth opening 16b of the second through hole 16 may also be equal to the diameter R2 of the second opening 15b of the first through hole 15. The diameter R4 is, for example, 50 μm or more, 65 μm or more, or 75 μm or more. The diameter R4 is, for example, 100 μm or less, 90 μm or less, or 85 μm or less. The same applies to the diameter R5 of the fourth opening 16b of the second through hole 16. The diameter R5 may be equal to the diameter R4. The diameter R5 may be smaller or larger than the diameter R4.

[0124] 14 , the through electrode 20 is also located inside the second through hole 16. The through electrode 20 located inside the second through hole 16 is also referred to as a through electrode 20b. The through electrode 20b extends along the wall surface 16f of the second through hole 16 from the third opening 16a to the fourth opening 16b. The through electrode 20b may be formed in a cylindrical shape along the wall surface 16f of the second through hole 16. The through electrode 20b does not block the second through hole 16 between the third opening 16a and the fourth opening 16b.

[0125] The thickness T4 of the through electrode 20b is, for example, 5 μm or more, and may be 8 μm or more, or 10 μm or more. The thickness T4 is, for example, 25 μm or less, and may be 20 μm or less, or 15 μm or less. The thickness T4 is the dimension of the through electrode 20b in a plane perpendicular to the thickness direction of the glass substrate 12, and is the dimension of the through electrode 20b along the radial direction of the second through hole 16. The thickness T4 is measured at a midpoint between the third opening 16a and the fourth opening 16b.

[0126] The thickness T4 of the through electrode 20b may be equal to the thickness T3 of the through electrode 20a. In this case, an increase in the number of plating steps and plating time required to form the through electrodes 20a, 20b during the manufacture of the through electrode substrate 10 can be suppressed. Furthermore, the thickness T4 of the through electrode 20b may be smaller or larger than the thickness T3 of the through electrode 20a. For example, when the thickness T3 is larger than the thickness T4, i.e., when the thickness T4 is smaller than the thickness T3, gas components in the wiring layer 40 can be effectively discharged while ensuring connection density.

[0127] As shown in FIG. 14 , the resin member 30 is located inside the second through hole 16. The resin member 30 is located inside the second through hole 16, on the inner side of the through electrode 20b. The resin member 30 is formed on the through electrode 20b inside the second through hole 16. The resin member 30 extends continuously from the third opening 16a to the fourth opening 16b inside the second through hole 16. That is, the resin member 30 extends without interruption between the third opening 16a and the fourth opening 16b. The resin member 30 may fill the inside of the through electrode 20b. That is, the resin member 30 may fill the inside of the through electrode 20b without any gaps.

[0128] In this case, too, the resin member 30 extends continuously from the third opening 16a to the fourth opening 16b within the second through-hole 16, so that the gas components in the wiring layer 40 can be discharged to the outside from the second surface 14 side through the second through-hole 16. This makes it possible to prevent the gas components from remaining in the wiring layer 40.

[0129] In particular, the diameter R4 of the third opening 16 a of the second through hole 16 is 50 μm or more and 100 μm or less, and the thickness T4 of the through electrode 20 b is 5 μm or more and 25 μm or less, thereby ensuring connection density and effectively discharging gas components from the wiring layer 40.

[0130] In this case, in the area A1 overlapping with the semiconductor element 3 in a plan view, ２ In particular, in the area A2 located 3 mm inward from the outer peripheral edge 3 e of the semiconductor element 3 in a plan view, ２ There may be 27 or more and 2500 or less second through holes 16 positioned per unit area.

[0131] 100mm ２ The number of second through holes 16 per unit is, for example, 27 or more, or may be 500 or more, or may be 1000 or more. ２ The number of second through holes 16 per hole is, for example, 3,500 or less, may be 3,000 or less, or may be 2,500 or less.

[0132] In the area A1 overlapping with the semiconductor element 3 in a plan view, ２ By locating 27 to 2500 second through holes 16 per unit area, it is possible to appropriately discharge gas components contained in the wiring layer 40 to the outside while suppressing the occurrence of cracks.

[0133] (Fourth Modification) FIG. 15 is a cross-sectional view showing another modification of the first through hole 15 of FIG. 13 . As shown in FIG. 15 , the first through hole 15 may include a first minimum portion 15c, similar to the example shown in FIG. 2 . The first minimum portion 15c may be located midway between the first opening 15a and the second opening 15b. In this case, the through electrode 20a may extend along the wall surfaces 15d and 15e of the first through hole 15 from the first opening 15a to the second opening 15b. The through electrode 20a may not block the first through hole 15. That is, the through electrode 20a may not include the blocking portion 23 shown in FIG. 2 . In this case, the first recess 21c and the second recess 22c of the through electrode 20a may be connected at the first minimum portion 15c. Similarly to the example shown in FIG. 13 , the resin member 30 may be located inside the through electrode 20a within the first through hole 15. The resin member 30 may extend continuously from the first opening 15a to the second opening 15b within the first through-hole 15.

[0134] FIG. 16 is a cross-sectional view showing another modified example of the second through hole 16 of FIG. 14 . As shown in FIG. 16 , the second through hole 16 may include a second minimum portion 16 c, similar to the example shown in FIG. 3 . The second minimum portion 16 c may be located midway between the third opening 16 a and the fourth opening 16 b. In this case, the through electrode 20 b may extend along the wall surfaces 16 d and 16 e of the second through hole 16 from the third opening 16 a to the fourth opening 16 b. The through electrode 20 b may not block the second through hole 16 . That is, the through electrode 20 b may not include the blocking portion 23 shown in FIG. 3 . In this case, the first recess 21 c and the second recess 22 c of the through electrode 20 b may be connected at the second minimum portion 16 c. Similarly to the example shown in FIG. 14 , the resin member 30 may be located inside the through electrode 20 b within the second through hole 16. The resin member 30 may extend continuously from the third opening 16a to the fourth opening 16b within the second through-hole 16.

[0135] In this case, too, the resin member 30 extends continuously from the third opening 16a to the fourth opening 16b within the second through-hole 16, so that the gas components in the wiring layer 40 can be discharged to the outside from the second surface 14 side through the second through-hole 16. This makes it possible to prevent the gas components from remaining in the wiring layer 40.

[0136] In particular, the diameter R4 of the third opening 16 a of the second through hole 16 is 50 μm or more and 100 μm or less, and the thickness T4 of the through electrode 20 b is 5 μm or more and 25 μm or less, thereby ensuring connection density and effectively discharging gas components from the wiring layer 40.

[0137] In addition, in the area A1 overlapping with the semiconductor element 3 in a plan view, ２ By locating 27 to 2500 second through holes 16 per unit area, it is possible to appropriately discharge gas components contained in the wiring layer 40 to the outside while suppressing the occurrence of cracks.

[0138] 17 is a diagram showing an example of a product in which the semiconductor package 1 is mounted. The semiconductor package 1 can be used in a variety of products. For example, the semiconductor package 1 is mounted in a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, etc.

[0139] The components disclosed in the above-described embodiment and the above-described modified examples can be appropriately combined as needed.

[0140] Next, the embodiments of the present disclosure will be described in more detail with reference to examples. The embodiments of the present disclosure are not limited to the following examples, as long as they do not depart from the gist of the present disclosure.

[0141] In the first example, the semiconductor package 1 shown in FIGS. 1 to 4 was prepared. The thickness T0 of the through-hole electrode substrate 10 was 400 μm. The vertical and horizontal dimensions of the glass substrate 12 in plan view were each 60 mm. Therefore, the planar area of ​​the glass substrate 12 was 3600 mm. ２ The thickness T1 of the wiring layer 40 and the thickness T2 of the wiring layer 45 were each 40 μm. The vertical dimension L2 and horizontal dimension L3 of the semiconductor element 3 in plan view were each 10 mm. Therefore, the planar area of ​​the semiconductor element 3 was 100 mm. ２ It was.

[0142] The first through hole 15 and the second through hole 16 had the same shape. The diameter R1 of the first opening 15a of the first through hole 15 was 80 μm. The diameter R2 of the second opening 15b of the first through hole 15 was 80 μm. The diameter R3 of the first minimum portion 15c of the first through hole 15 was 50 μm. The diameter R4 of the third opening 16a of the second through hole 16 was 80 μm. The diameter R5 of the fourth opening 16b of the second through hole 16 was 80 μm. The diameter R6 of the second minimum portion 16c of the second through hole 16 was 50 μm.

[0143] The second through holes 16 were arranged in an area A1 that overlaps with the semiconductor element 3 in a plan view. In the area A1 that overlaps with the semiconductor element 3 in a plan view, the second through holes 16 were arranged in a grid pattern at equal intervals. Semiconductor packages 1 were prepared in which the number of second through holes 16 in the area A1 that overlaps with the semiconductor element 3 (within a 10 mm × 10 mm area) was changed to 5, 10, 50, 100, 250, 500, and 1000.

[0144] For each manufactured semiconductor package 1, the presence or absence of expansion of the wiring layer 40 due to the gaseous components was confirmed using an electron microscope. An expansion of the wiring layer 40 of 30 μm or more was evaluated as "existent," and an expansion of the wiring layer 40 of less than 30 μm was evaluated as "absent." The connection density of each semiconductor package 1 was also confirmed by measuring the electrical resistance of the connecting wiring. A change in electrical resistance of 10% or more was evaluated as "decreased" connection density, and a change in electrical resistance of less than 10% was evaluated as "good" connection density.

[0145] FIG. 18 is a table showing the evaluation results in Example 1. As shown in FIG. ２ When the number of second through holes 16 per unit area was five, expansion of the wiring layer 40 was observed. ２ When the number of second through holes 16 per unit is five, it is considered that the gas components contained in the wiring layer 40 cannot be sufficiently discharged to the outside. ２ When the number of second through holes 16 per unit area was 10 or more, no expansion of the wiring layer 40 was observed. ２ It is considered that when the number of second through holes 16 per 100 mm is 10 or more, the gas components contained in the wiring layer 40 can be appropriately discharged to the outside. ２ When the number of second through holes 16 per 100 mm was 500 or more, a decrease in connection density was observed. ２ When the number of second through holes 16 per 100 mm was 250 or less, the connection density was good. ２ It was confirmed that the number of the second through holes 16 per unit area is preferably 10 or more and 250 or less.

[0146] In the second example, a semiconductor package 1 was prepared including a first through hole 15 and a through electrode 20a as shown in Fig. 15 and a second through hole 16 and a through electrode 20b as shown in Fig. 16. The thickness T0 of the through electrode substrate 10 was 400 µm. The vertical and horizontal dimensions of the glass substrate 12 in plan view were each 60 mm. Therefore, the planar area of ​​the glass substrate 12 was 3600 mm ２ The thickness T1 of the wiring layer 40 and the thickness T2 of the wiring layer 45 were each 40 μm. The vertical dimension L2 and horizontal dimension L3 of the semiconductor element 3 in plan view were each 10 mm. Therefore, the planar area of ​​the semiconductor element 3 was 100 mm. ２ It was.

[0147] The first through hole 15 and the second through hole 16 had the same shape. The diameter R1 of the first opening 15a of the first through hole 15 was 80 μm. The diameter R2 of the second opening 15b of the first through hole 15 was 80 μm. The diameter R3 of the first minimum portion 15c of the first through hole 15 was 50 μm. The thickness T3 of the through electrode 20a was 10 μm. The diameter R4 of the third opening 16a of the second through hole 16 was 80 μm. The diameter R5 of the fourth opening 16b of the second through hole 16 was 80 μm. The diameter R6 of the second minimum portion 16c of the second through hole 16 was 50 μm. The thickness T4 of the through electrode 20b was 10 μm.

[0148] The second through holes 16 were arranged in an area A1 that overlaps with the semiconductor element 3 in a plan view. In the area A1 that overlaps with the semiconductor element 3 in a plan view, the plurality of second through holes 16 were arranged in a grid pattern at equal intervals. In the area A1 that overlaps with the semiconductor element 3 (within an area of ​​10 mm × 10 mm), semiconductor packages 1 were prepared in which the number of second through holes 16 was changed to 10, 27, 500, 1000, 2500, 3000, and 3500.

[0149] As in the first example, the presence or absence of expansion of the wiring layer 40 due to gas components was confirmed using an electron microscope in each manufactured semiconductor package 1. Also, as in the first example, the connection density in each semiconductor package 1 was confirmed by measuring the electrical resistance of the connection wiring.

[0150] 19 is a table showing the evaluation results in Example 2. As shown in FIG. ２ When the number of second through holes 16 per unit was 10, expansion of the wiring layer 40 was observed. ２ It is considered that when the number of second through holes 16 per unit is 10, the gas components contained in the wiring layer 40 cannot be sufficiently discharged to the outside. ２ When the number of second through holes 16 per unit area was 27 or more, no expansion of the wiring layer 40 was observed. ２ When the number of second through holes 16 per 100 mm is 27 or more, it is considered that the gas components contained in the wiring layer 40 can be appropriately discharged to the outside. ２ When the number of second through holes 16 per unit area was 3000 or more, cracks occurred in the glass substrate 12 and the wiring layer 40. ２ When the number of second through holes 16 per 100 mm was 2500 or less, no cracks occurred and the connection density was good. ２ It was confirmed that the number of the second through holes 16 per hit is preferably 27 or more and 2500 or less.

Claims

1. A through electrode substrate on which a semiconductor element is mounted, comprising: a glass substrate including a first surface, a second surface located opposite to the first surface, and a first through hole and a second through hole penetrating from the first surface to the second surface; a through electrode located in the first through hole; a resin member located in the second through hole; and a wiring layer located between the glass substrate and the semiconductor element, wherein the first through hole includes a first opening that opens on the first surface of the glass substrate and a second opening that opens on the second surface of the glass substrate, the second through hole includes a third opening that opens on the first surface of the glass substrate and a fourth opening that opens on the second surface of the glass substrate, the through electrode blocks the first through hole between the first opening and the second opening, and the resin member extends continuously from the third opening to the fourth opening within the second through hole.

2. The through electrode substrate according to claim 1, wherein the first through hole is located between the first opening and the second opening and includes a first minimum portion having the smallest hole diameter of the first through hole, and the through electrode does not block the first through hole at the first opening and the second opening, but blocks the first through hole at least at the first minimum portion.

3. The through electrode substrate according to claim 1, wherein the through electrode is filled in the first through hole.

4. The through electrode substrate according to claim 1, wherein the resin member is filled in the second through hole.

5. The through electrode substrate according to claim 1, wherein the second through hole has the same shape as the first through hole.

6. The through electrode substrate according to claim 1, wherein the second through hole is located within a region overlapping with the semiconductor element in a plan view.

7. The through electrode substrate according to claim 6, wherein the second through hole is located within a region that is 3 mm inward from an outer periphery of the semiconductor element in a plan view.

8. The through electrode substrate according to claim 6, wherein a plurality of the second through holes are arranged at equal intervals within a region overlapping with the semiconductor element in a plan view.

9. Within the area overlapping the semiconductor element in plan view, ２ The through electrode substrate according to claim 6 , wherein 10 to 250 of the second through holes are located per one substrate.

10. The through electrode substrate according to claim 1, wherein the hole diameter of the third opening of the second through hole is 50 μm or more and 100 μm or less.

11. The through hole electrode substrate according to claim 1, wherein the glass substrate has a thickness of 100 μm or more and 1200 μm or less.

12. The planar area of ​​the semiconductor element is 100 mm ２ The through hole electrode substrate according to claim 1 .

13. A through electrode substrate on which a semiconductor element is mounted, comprising: a glass substrate including a first surface, a second surface located opposite to the first surface, and a first through hole and a second through hole penetrating from the first surface to the second surface; through electrodes located in the first through holes and the second through holes, respectively; a resin member located at least in the second through hole; and a wiring layer located between the glass substrate and the semiconductor element, wherein the first through hole includes a first opening that opens on the first surface of the glass substrate, a second opening that opens on the second surface of the glass substrate, and a first wall surface located between the first opening and the second opening, the second through hole includes a third opening that opens on the first surface of the glass substrate, a fourth opening that opens on the second surface of the glass substrate, and a second wall surface located between the third opening and the fourth opening, and the through electrode located in the first through hole extends along the first wall surface from the first opening to the second opening, a through electrode substrate, wherein the through electrode located in the second through hole extends along the second wall surface from the third opening to the fourth opening, the resin member is located inside the through electrode in the second through hole and extends continuously from the third opening to the fourth opening, a hole diameter of the third opening of the second through hole is 50 μm or more and 100 μm or less, and a thickness of the through electrode located in the second through hole is 5 μm or more and 25 μm or less.

14. The through electrode substrate according to claim 13, wherein the second through hole is located within a region overlapping with the semiconductor element in a plan view.

15. Within the area overlapping the semiconductor element in plan view, ２ The through electrode substrate according to claim 14 , wherein 27 to 2500 of the second through holes are located per one substrate.

16. A semiconductor package comprising: a through hole electrode substrate according to any one of claims 1 to 15; and a semiconductor element mounted on the through hole electrode substrate.

17. A through electrode substrate comprising: a glass substrate including a first surface, a second surface located opposite to the first surface, and a first through hole and a second through hole penetrating from the first surface to the second surface; a through electrode located in the first through hole; and a resin member located in the second through hole, wherein the first through hole includes a first opening opened on the first surface of the glass substrate and a second opening opened on the second surface of the glass substrate, the second through hole includes a third opening opened on the first surface of the glass substrate and a fourth opening opened on the second surface of the glass substrate, the through electrode blocks the first through hole between the first opening and the second opening, and the resin member extends continuously from the third opening to the fourth opening within the second through hole.

18. A glass substrate including a first surface, a second surface located opposite to the first surface, a first through hole and a second through hole penetrating from the first surface to the second surface, through electrodes located in the first through hole and the second through hole, respectively, and a resin member located at least in the second through hole, wherein the first through hole includes a first opening that opens on the first surface of the glass substrate, a second opening that opens on the second surface of the glass substrate, and a first wall surface located between the first opening and the second opening, wherein the second through hole includes a third opening that opens on the first surface of the glass substrate, a fourth opening that opens on the second surface of the glass substrate, and a second wall surface located between the third opening and the fourth opening, wherein the through electrode located in the first through hole extends along the first wall surface from the first opening to the second opening, and wherein the through electrode located in the second through hole extends along the second wall surface from the third opening to the fourth opening, a through electrode substrate, wherein the resin member is located inside the through electrode within the second through hole and extends continuously from the third opening to the fourth opening, a hole diameter of the second through hole at the third opening is 50 μm or more and 100 μm or less, and a thickness of the through electrode located within the second through hole is 5 μm or more and 25 μm or less.

19. A method for manufacturing a through electrode substrate on which a semiconductor element is mounted, comprising the steps of: preparing a glass substrate including a first surface, a second surface opposite to the first surface, and a first through hole and a second through hole penetrating from the first surface to the second surface; forming a through electrode in the first through hole; forming a resin member in the second through hole; and forming a wiring layer on the first surface of the glass substrate, wherein the first through hole includes a first opening that opens on the first surface of the glass substrate and a second opening that opens on the second surface of the glass substrate, the second through hole includes a third opening that opens on the first surface of the glass substrate and a fourth opening that opens on the second surface of the glass substrate, the through electrode blocks the first through hole between the first opening and the second opening, and the resin member extends continuously from the third opening to the fourth opening within the second through hole.

20. A method for manufacturing a through electrode substrate on which a semiconductor element is mounted, comprising the steps of: preparing a glass substrate including a first surface, a second surface located opposite to the first surface, and a first through hole and a second through hole penetrating from the first surface to the second surface; forming through electrodes in the first through hole and the second through hole, respectively; forming a resin member in at least the second through hole; and forming a wiring layer on the first surface of the glass substrate, wherein the first through hole includes a first opening that opens on the first surface of the glass substrate, a second opening that opens on the second surface of the glass substrate, and a first wall surface located between the first opening and the second opening; the second through hole includes a third opening that opens on the first surface of the glass substrate, a fourth opening that opens on the second surface of the glass substrate, and a second wall surface located between the third opening and the fourth opening; the through electrode located in the first through hole extends along the first wall surface from the first opening to the second opening, a through electrode substrate manufacturing method, wherein the through electrode located in the second through hole extends along the second wall surface from the third opening to the fourth opening, the resin member is located inside the through electrode in the second through hole and extends continuously from the third opening to the fourth opening, a hole diameter of the third opening of the second through hole is 50 μm or more and 100 μm or less, and a thickness of the through electrode located in the second through hole is 5 μm or more and 25 μm or less.

21. A method for manufacturing a semiconductor package, comprising: a step of manufacturing a through hole electrode substrate by the method for manufacturing a through hole electrode substrate according to claim 19 or 20; and a step of mounting a semiconductor element on the through hole electrode substrate.