Driver circuit

Abstract

A driver circuit according to the present invention comprises: a first-stage inverter circuit group (1) having M inverter circuits (11) to (1M) connected in series between a power source potential node and a ground potential node; a capacitor element group (40) corresponding to each of the M inverter circuits (11) to (1M) in the first-stage inverter circuit group (1) and having M capacitor elements (401) to (40M) connected in series between a power source potential node VDD and a ground potential node VSS; second to (M-1)th stage inverter circuit groups (2) to (M-1) which have one less inverter circuit than the number of inverter circuits in the preceding inverter circuit group, are connected without connecting a capacitor element between the output nodes of two inverter circuits in the preceding inverter circuit group, and in which input nodes are connected to the source node of the NMOS of the inverter circuit on the ground potential node side in the preceding inverter circuit group; and an Mth stage inverter circuit (M) which is connected without connecting a capacitor element between the output nodes of two inverter circuits (M-1)1, (M-1)2 in the (M-1)th stage inverter circuit group (M-1), and in which input nodes are connected to the source node of the NMOS of the inverter circuit (M-1)1.

Description

Driver Circuit

[0001] The present disclosure relates to a driver circuit having a House of Cards (HoC) type configuration using an inverter circuit made of a complementary metal oxide semiconductor (CMOS).

[0002] A CMOS power amplifier that generates a high voltage using MOS transistors with a low breakdown voltage is disclosed in Non-Patent Document 1. The power amplifier disclosed in Non-Patent Document 1 has a three-stage HoC configuration using inverter circuits made of CMOS, and capacitive elements are connected in parallel to all of the inverter circuits.

[0003] LG Salem et al. “A Recursive Switched-Capacitor House-of-Cards Power Amplifier” IEEE Journal of Solid-State Circuits, vol. 52, no. 7, July 2017. PP1719−1738

[0004] The power amplifier disclosed in Non-Patent Document 1 has a capacitive element connected in parallel to each of the inverter circuits in the HoC configuration, which results in a larger power amplifier circuit. As the circuit size increases, the influence of parasitic capacitance generated in the wiring between the inverter circuits increases, resulting in longer rise and fall times for the output voltage of the power amplifier.

[0005] The present disclosure is intended to solve the above-mentioned problems, and has an object to provide a driver circuit in which the rise and fall times of the output voltage are made faster.

[0006] A driver circuit according to the present disclosure includes: a first-stage inverter circuit group having inverter circuits each composed of M PMOS and NMOS connected in series between a power supply potential node and a ground potential node; a capacitance element group each having M capacitance elements connected in series between the power supply potential node and the ground potential node, each corresponding to the M inverter circuits in the first-stage inverter circuit group; and second- to (M-1)-th inverter circuit groups in which the number of inverter circuits each composed of PMOS and NMOS is one less than the number of inverter circuits in the previous-stage inverter circuit group, and which are connected between output nodes of two inverter circuits in the previous-stage inverter circuit group without connecting capacitance elements, and whose input node is connected to a source node of a PMOS of an inverter circuit on the ground potential node side in the previous-stage inverter circuit group, and an M-th inverter circuit composed of PMOS and NMOS, which is connected between output nodes of two inverter circuits in the (M-1)-th inverter circuit group without connecting capacitance elements, and whose input node is connected to a source node of a PMOS of an inverter circuit on the ground potential node side in the (M-1)-th inverter circuit group.

[0007] According to the present disclosure, in an inverter circuit composed of a PMOS and an NMOS in the next stage or later, when no capacitive element is connected between the output nodes of two inverter circuits in the inverter circuit group in the previous stage, the source node of the PMOS is connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits, and the source node of the NMOS is connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits, thereby making it possible to speed up the rise and fall times of the output voltage of the driver circuit.

[0008] FIG. 1 is a configuration diagram showing a driver circuit according to a first embodiment. FIG. 2 is a conceptual plan view showing the positional relationship between a capacitive element, a first-stage inverter circuit, and an input signal line in the driver circuit according to the first embodiment. FIG. 3 is a diagram showing an operating state when a PMOS transistor of an inverter circuit is turned on in the driver circuit according to the first embodiment. FIG. 4 is a diagram showing an operating state when an NMOS transistor of an inverter circuit is turned on in the driver circuit according to the first embodiment. FIG. 5 is a configuration diagram showing a driver circuit according to a second embodiment. FIG. 6 is a diagram showing an operating state when a PMOS transistor of an inverter circuit is turned on in the driver circuit according to the second embodiment. FIG. 7 is a diagram showing an operating state when an NMOS transistor of an inverter circuit is turned on in the driver circuit according to the second embodiment.

[0009] First Embodiment A driver circuit according to the first embodiment will be described with reference to Figures 1 to 4. The driver circuit according to the first embodiment is a driver circuit with a three-stage HoC configuration using inverter circuits made of CMOS. The driver circuit according to the first embodiment includes a first-stage inverter circuit group 1, a second-stage inverter circuit group 2, a third-stage inverter circuit 3, and a capacitive element group 40.

[0010] First, we will explain the inverter circuits that make up each of the inverter circuit groups 1 to 3. As shown in Fig. 1, the inverter circuits are complementary CMOS inverter circuits in which a P-type MOS transistor (hereinafter abbreviated as PMOS) and an N-type MOS transistor (hereinafter abbreviated as NMOS) are connected in series.

[0011] The drain electrode of the PMOS is electrically connected to the drain electrode of the NMOS, and is electrically connected to the output node (output terminal) of the inverter circuit. The gate electrode of the PMOS and the gate electrode of the NMOS are electrically connected, and are electrically connected to the input node (input terminal) of the inverter circuit. The source electrode of the PMOS is electrically connected to the source node (source terminal of the PMOS) of the PMOS of the inverter circuit. The source electrode of the NMOS is electrically connected to the source node (source terminal of the NMOS) of the NMOS of the inverter circuit.

[0012] The PMOS and NMOS are formed and integrated on the surface of a semiconductor substrate by a commonly known semiconductor manufacturing technique. In the following description, the inverter circuits corresponding to each stage are designated by the same reference numerals, and in each stage, the ground potential node V ＳＳ The inverter circuit arranged at the lowest position, i.e., the first position, is connected to the power supply potential node V ＤＤ Numbers are added as subscripts in order from

[0013] For example, in the first stage inverter circuit group 1, the inverter circuit arranged first is １ The inverter circuit placed at the third position is ３ The inverter circuits in the second-stage inverter circuit group 2 and the third-stage inverter circuit group 3 are similarly designated by symbols. In addition, in the inverter circuits, PMOS is designated by the suffix P, and NMOS is designated by the suffix N. For example, in the inverter circuit 1, １ The PMOS is 1 １Ｐ and NMOS is 1 １Ｎ It is expressed as:

[0014] The first stage inverter circuit group 1 is connected to the power supply potential node V ＤＤ and the ground potential node V ＳＳ Three inverter circuits 1 connected in series between １ ~1 ３ Inverter circuit 1 １ ~1 ３ The source node of the PMOS is connected to the power supply potential node V ＤＤ The source node of the NMOS is connected to the ground potential node VＳＳ The two are connected in series on the same side.

[0015] That is, the inverter circuit 1 placed first １ The source node of the NMOS is the ground potential node V ＳＳ The inverter circuit 1 is connected to the second ２ The source node of the NMOS of the inverter circuit 1 １ The third inverter circuit 1 is connected to the source node of the PMOS transistor 1. ３ The source node of the NMOS of the inverter circuit 1 ２ The third inverter circuit 1 is connected to the source node of the PMOS transistor 1. ３ The source node of the PMOS is the power supply potential node V ＤＤ is connected to.

[0016] Inverter circuit 1 １ From inverter circuit 1 ３ Each input node of the １ ~In ３ Each input signal line 50 １ ~50 ３ and the input terminal In １ ~In ３ The input signal is input to each of the input signal lines 50. １ ~50 ３ The conductive layer is formed on the surface of a semiconductor substrate via an insulating layer, and then patterned.

[0017] Input terminal In １ ~In ３ The input signals input to each inverter circuit have the same amplitude and phase, and the direct current (DC) level is the inverter circuit 1 placed first. １ A first input terminal In connected to the input node １ In the first embodiment, the power supply potential node V ＤＤ For example, the potential applied to the ground potential node V ＳＳ If the potential of the input terminal In is set to 0V, １ ~In ３The input signals input to each of the circuits are the signals shown in FIG.

[0018] That is, the first input terminal In １ The input signal input to the second input terminal In is a signal whose H level is 1V and whose L level is 0V. ２ The input signal input to the third input terminal In is a signal having an H level of 2V and an L level of 1V. ３ The input signal input to is a signal having an H level of 3V and an L level of 2V.

[0019] The second stage inverter circuit group 2 is the inverter circuit 1 of the first stage inverter circuit group 1. １ ~1 ３ The number of inverter circuits 2 is one less than the number of inverter circuits 2 １ , 2 ２ Two inverter circuits 2 １ , 2 ２ are connected in series. １ , 2 ２ are the ground potential nodes V ＳＳ In order from the left, the ground potential node V ＳＳ When no capacitance element is connected between the output nodes of two inverter circuits connected adjacently from the side, the source node of the PMOS is connected to the power supply potential node V of the two inverter circuits. ＤＤ The source node of the NMOS is connected to the output node of the inverter circuit connected to the side, and the source node of the NMOS is connected to the ground potential node V of the two inverter circuits. ＳＳ The output node of the inverter circuit connected to the side of the power supply is electrically connected to the output node of the inverter circuit.

[0020] That is, the inverter circuit 2 placed at the lowest position, i.e., the first position １ The source node of the NMOS is the inverter circuit 1 arranged first in the first stage inverter circuit group 1. １ The inverter circuit 2 is electrically connected to the output node of the inverter circuit 2. １ The source node of the PMOS is the inverter circuit 1 arranged second in the first stage inverter circuit group 1. ２ The output node of the

[0021] The inverter circuit 2 placed at the top, i.e., the second position ２ The source node of the NMOS is the second inverter circuit 1 in the first stage inverter circuit group 1. ２ The inverter circuit 2 is electrically connected to the output node of the inverter circuit 2. ２ The source node of the PMOS is the third inverter circuit 1, which is the highest inverter circuit in the first stage inverter circuit group 1. ３ The output node of the

[0022] Two inverter circuits 2 １ , 2 ２ Each input node is connected to the ground potential node V ＳＳ The inverter circuits 2 and 3 are electrically connected to the source nodes of the PMOS transistors of the inverter circuits in the first-stage inverter circuit group 1 in order from the inverter circuit 1 on the side. １ The input node of the inverter circuit 1 of the first stage inverter circuit group 1 １ The source node of the PMOS and the inverter circuit 1 ２ The inverter circuit 2 is electrically connected to the source node of the NMOS transistor 1. ２ The input node of the inverter circuit 1 of the first stage inverter circuit group 1 ２ The source node of the PMOS and the inverter circuit 1 ３ The source node of the NMOS is electrically connected to the source node of the NMOS.

[0023] The third-stage inverter circuit 3 is a combination of the two inverter circuits 2 in the second-stage inverter circuit group 2. １ , 2 ２ When no capacitance element is connected between the source node of the PMOS and the output node of the power supply potential node V ＤＤ Inverter circuit 2 connected to the side ２ and the source node of the NMOS is connected to the ground potential node V ＳＳ Inverter circuit 2 connected to the side １ The input node of the inverter circuit 3 is connected to the output node of the inverter circuit 2 in the second stage inverter circuit group 2.１ The source node of the PMOS and the inverter circuit 2 ２ The output node of the inverter circuit 3 is electrically connected to the output terminal Out by an output signal line 6.

[0024] The first stage inverter circuit group 1, the second stage inverter circuit group 2, and the third stage inverter circuit 3 are stacked vertically in the order of the first stage, second stage, and third stage on the surface of a semiconductor substrate with an insulating layer interposed between them.

[0025] Inverter circuit 2 in the second stage inverter circuit group 2 １ , 2 ２ Furthermore, since the third-stage inverter circuit 3 is connected between the output nodes of adjacent inverter circuits in the preceding-stage inverter circuit group without connecting a capacitive element, the length of the circuit wiring connecting the inverter circuits can be shortened, and the parasitic capacitance generated in the circuit wiring can be reduced, thereby shortening the rise and fall times of the output voltage output from the output node of the inverter circuit 3.

[0026] The capacitance element group 40 is composed of three inverter circuits 1 in the first stage inverter circuit group 1. １ ~1 ３ Corresponding inverter circuits 1 １ ~1 ３ and a power supply potential node V ＤＤ and the ground potential node V ＳＳ Three capacitance elements 40 connected in series between １ ~40 ３ It has.

[0027] Three capacitance elements 40 connected in series １ ~40 ３ is the power supply potential node V ＤＤ and the ground potential node V ＳＳ The power supply potential node V ＤＤ The potential applied to V ＤＤ (for example, 3 V), and the ground potential node V ＳＳ is set to 0V, the capacitance element 40 placed first１ and the second most placed capacitive element 40 ２ The potential at the connection point is V ＤＤ / 3 (for example, 1 V), the capacitive element 40 placed in the second place ２ and the third capacitor element 40 ３ The potential at the connection point is 2 V ＤＤ / 3 (for example, 2V).

[0028] In addition, three capacitance elements 40 １ ~40 ３ The inverter circuits 2 in the second stage inverter circuit group 2 are charged by the charges they hold. １ , 2 ２ and the PMOS3 of the third-stage inverter circuit 3 １Ｐ and NMOS3 １Ｎ The third (top) capacitor element 40 has a function of charging the gate electrodes of the first and second capacitor elements. ３ is the input terminal In １ ~In ３ When an L-level potential is input to each of the inverter circuits and the PMOS of each inverter circuit is turned on (hereinafter, abbreviated as "turning the PMOS on"), the inverter circuit 2 arranged in the second (highest) position in the second-stage inverter circuit group 2 ２ PMOS2 in ２Ｐ Inverter circuit 2 is connected so that a negative voltage is applied between the gate electrode and the source electrode of ２ PMOS2 in ２Ｐ The gate electrode of the

[0029] At the same time, the capacitance element 40 ３ is the PMOS3 of the third stage inverter circuit 3 １Ｐ PMOS3 in inverter circuit 3 is connected so that a negative voltage is applied between the gate electrode and the source electrode of １Ｐ Therefore, the gate electrode of the capacitance element 40 ３ The capacitance value of is the parasitic capacitance between the gate electrode and source electrode of the PMOS Ｐ Then, PMOS2 ２Ｐ and PMOS3 １Ｐ To turn on the ＰIt is set to.

[0030] As a result, the inverter circuit 1 in the first stage inverter circuit group 1 １ ~1 ３ PMOS1 １Ｐ ~1 ３Ｐ When the inverter circuit 2 is turned on, the inverter circuit 2 arranged second in the second stage inverter circuit group 2 ２ PMOS2 in ２Ｐ and PMOS3 of the third-stage inverter circuit 3 １Ｐ Therefore, the output terminal Out is connected to the power supply potential node V ＤＤ The potential V applied to ＤＤ (for example, 3V) is output.

[0031] Capacitor element 40 placed in the second (middle) position ２ When the PMOS is turned on, the inverter circuit 2 arranged first in the second stage inverter circuit group 2 １ PMOS2 in １Ｐ Inverter circuit 2 is connected so that a negative voltage is applied between the gate electrode and the source electrode of ２ PMOS2 in １Ｐ Therefore, the gate electrode of the capacitance element 40 ２ The capacitance value of PMOS2 １Ｐ In order to turn on Ｐ A capacitance value of

[0032] In addition, the second most placed capacitor element 40 ２ is the input terminal In １ ~In ３ When an H-level potential is input to each of the inverter circuits and the NMOS of each inverter circuit is turned on (hereinafter referred to as turning on the NMOS), the inverter circuit 2 arranged second in the second-stage inverter circuit group 2 ２ NMOS2 in ２Ｎ Inverter circuit 2 is connected so that a positive voltage is applied between the gate electrode and the source electrode of ２ NMOS2 in ２Ｎ The gate electrode of the

[0033] Therefore, the capacitance element 40２ The capacitance value of is the parasitic capacitance between the gate electrode and source electrode of the NMOS, C Ｎ Then, NMOS2 ２Ｎ In order to turn on Ｎ Therefore, the capacitance value of the capacitance element 40 ２ The capacitance value of Ｐ or C Ｎ The capacitance value is set to the larger value of either

[0034] The first (lowest) placed capacitive element 40 １ When the NMOS is turned on, the inverter circuit 2 arranged at the first (lowest) position in the second-stage inverter circuit group 2 １ NMOS2 in １Ｎ At the same time, the gate electrode of the capacitor element 40 １ is the NMOS3 of the third stage inverter circuit 3 １Ｎ Therefore, the gate electrode of the capacitance element 40 １ The capacitance value of NMOS2 １Ｎ and NMOS3 １Ｎ To turn on the Ｎ It is set to.

[0035] As a result, the inverter circuit 1 in the first stage inverter circuit group 1 １ ~1 ３ NMOS1 １Ｎ ~1 ３Ｎ When the inverter circuit 2 is turned on, the inverter circuit 2 arranged first in the second stage inverter circuit group 2 １ NMOS2 in １Ｎ and NMOS3 of the third-stage inverter circuit 3 １Ｎ Therefore, the output terminal Out is connected to the ground potential node V ＳＳ and grounded (for example, 0 V).

[0036] In this way, the third (highest) placed capacitive element 40 ３ The capacitance value of C is doubled Ｐ , the capacitive element 40 placed in the second (middle) position ２ The capacitance value of C Ｐ or C Ｎthe capacitance value of the capacitance element 40 that is placed first (lowest) １ Double C Ｎ Therefore, inverter circuit 2 １ Inverter circuit 1 １ output node and inverter circuit 1 ２ The output node of the inverter circuit 2 ２ Inverter circuit 1 ２ output node and inverter circuit 1 ３ The inverter circuit 3 is connected to the output node of the inverter circuit 2. １ output node and inverter circuit 2 ２ Even if the output nodes of the inverter circuits 1 to 3 are connected without connecting a capacitance element, the inverter circuits constituting the inverter circuit groups 1 to 3 operate quickly and complementarily both when the PMOS is turned on and when the NMOS is turned on.

[0037] As a result, the input terminal In １ ~In ３ Depending on the H level and L level input to each, signals with fast rise and fall times and output voltages exceeding the withstand voltages of PMOS and NMOS, for example, 0V and 3V, can be output to the output terminal Out.

[0038] In addition, the inverter circuit 1 in the first stage inverter circuit group 1 １ ~1 ３ The output of inverter circuit 1 １ through the PMOS or NMOS constituting the capacitance element 40 １ ~40 ３ , the inverter circuit 2 in the second stage inverter circuit group 2 is connected to １ , 2 ２ Furthermore, the third stage inverter circuit 3 does not need to have a capacitance element between the source node of the PMOS and the source node of the NMOS. １ , 2 ２ An appropriately divided voltage is applied between the source node of the PMOS and the source node of the NMOS in the third-stage inverter circuit 3 .

[0039] The capacitance element group 40 is modularized together with the first-stage inverter circuit group 1 to the third-stage inverter circuit group 3. １ ~40 ３ Each of the capacitor elements 40 is made of a parallel metal plate, and the two electrodes (metal plates) have long and short sides. １ ~40 ３ are the input signal lines 50 １ ~50 ３ The short sides of the input signal lines 50 are provided directly above the respective lines via an insulating layer. １ ~50 ３ The long side of the input signal line 50 is perpendicular to the wiring direction of the input signal line 50. １ ~50 ３ are arranged parallel to the wiring direction.

[0040] Capacitor element 40 １ ~40 ３ and inverter circuit 1 of the first stage inverter circuit group 1 １ ~1 ３ The layout relationship of the capacitance element 40 will be explained with reference to FIG. １ and inverter circuit 1 １ and input signal line 50 １ 1 is a conceptual plan view showing the layout relationship between the capacitor element 40 and the capacitor element 40. ２ , 40 ３ and inverter circuit 1 ２ , 1 ３ Input signal line 50 ２ , 50 ３ The layout of the capacitance element 40 １ and inverter circuit 1 １ and input signal line 50 １ The layout is similar to that of the

[0041] PMOS1 １Ｐ and NMOS1 １Ｎ Each has a comb-shaped gate electrode, and the gate electrode is connected to the inverter circuit 1 １ The PMOS1 is electrically connected to the input signal line 50 via the input node 1. The wiring direction of the input signal line 50 is arranged perpendicular to the gate electrode. １Ｐ The source electrode of the inverter circuit 1 is formed in a comb shape. １The P-side wiring layer is electrically connected to the P-side wiring layer (circuit wiring) through the source node of the PMOS of the inverter circuit. The P-side wiring layer is wired in parallel with the input signal line 50.

[0042] PMOS1 １Ｐ The drain electrode of the inverter circuit 1 is disposed opposite to the source electrode with the gate electrode sandwiched therebetween. １ The wiring direction of the output wiring layer is opposite to that of the input signal line 50, and the output wiring layer is arranged in a straight line with the input signal line 50.

[0043] NMOS1 １Ｎ The source electrode of the inverter circuit 1 is formed in a comb shape, and the other end of the source electrode of the inverter circuit 1 is formed in a comb shape. １ The NMOS1 is electrically connected to an N-side wiring layer (circuit wiring) through the source node of the NMOS of the inverter circuit. The N-side wiring layer is wired in parallel with the input signal line 50. １Ｎ The drain electrode of the inverter circuit 1 is disposed opposite to the source electrode with the gate electrode sandwiched therebetween. １ is electrically connected to the output wiring layer via the output node.

[0044] The input signal line 50, the output wiring layer, the P-side wiring layer, and the N-side wiring layer are formed by patterning the same conductive layer on the surface of the semiconductor substrate. The input signal line 50, the P-side wiring layer, and the N-side wiring layer are arranged in parallel. Capacitor element 40 １ is the input signal line 50 １ The conductive layer is disposed directly above the P-side wiring layer and the N-side wiring layer, and is electrically insulated from these conductive layers and is disposed between the P-side wiring layer and the N-side wiring layer.

[0045] Capacitor element 40 １ The long side of the input signal line 50 １ and the short sides are located inside the outer edges of the P-side wiring layer and the N-side wiring layer. １ One electrode of the capacitor element 40 is electrically connected to a portion directly above the P-side wiring layer. １ The other electrode is electrically connected directly above the N-side wiring layer.

[0046] Capacitor element 40 １ ~40 ３The length of each short side, which is indicated by W in FIG. 2, is equal to or less than the distance between the source node of the PMOS and the source node of the NMOS of the inverter circuit. １ ~40 ３ The length of each long side, indicated by L in FIG. 2, is five times or less the length of the short side.

[0047] Capacitor element 40 １ ~40 ３ The size of the electrode in the input signal line 50 is such that the length W of the short side is equal to or less than the distance between the source node of the PMOS and the source node of the NMOS of the inverter circuit, and the length L of the long side is equal to or less than five times the length of the short side. １ ~50 ３ As a result, the rise and fall times of the output voltage output from the output node of the inverter circuit 3 can be shortened.

[0048] The capacitive element group 40 may be integrated on the surface of a semiconductor substrate together with the first-stage inverter circuit group 1 to the third-stage inverter circuit group 3. In this case, the capacitive element 40 １ ~40 ３ Each of them is an input signal line 50 １ ~50 ３ The capacitor element 40 is formed with an insulating layer interposed therebetween, and is composed of a pair of conductive layers with an insulating layer interposed therebetween. １ ~40 ３ Each is arranged between the P-side wiring layer and the N-side wiring layer with the short side length W being equal to or less than the distance between the source node of the PMOS and the source node of the NMOS of the inverter circuit, and the long side length L being equal to or less than five times the length of the short side.

[0049] Next, the operation of the driver circuit according to the first embodiment will be described. ＤＤ The potential applied to the ground potential node V ＳＳ is set to 0 V. The first input terminal In １ The input signal input to the second input terminal In is a signal whose H level is 1V and whose L level is 0V. ２ The input signal input to the third input terminal In is a signal having an H level of 2V and an L level of 1V.３ The input signal input to is a signal having an H level of 3V and an L level of 2V.

[0050] First, the input terminal In １ ~In ３ A case where an input signal having an L level potential is input to each of the inverter circuits 1 and 2 will be described with reference to FIG. １ ~1 ３ PMOS1 １Ｐ ~1 ３Ｐ is on, NMOS1 １Ｎ ~1 ３Ｎ is off.

[0051] Power supply potential node V ＤＤ and the ground potential node V ＳＳ A capacitance element 40 that divides the voltage between １ ~40 ３ The electric potential state of each inverter circuit is as follows: ２ The input node of the capacitor 40 ３ The charge held by the capacitance element 40 ３ and the capacitance element 40 ２ The inverter circuit 1 arranged in the third (highest) position in the first-stage inverter circuit group 1 is set to 2 V, which is the potential at the connection point of ３ PMOS1 ３Ｐ When the inverter circuit 2 is turned on, ２ PMOS2 ２Ｐ will be turned on.

[0052] The inverter circuit 2 arranged first in the second-stage inverter circuit group 2 １ The input node of the capacitor 40 ２ The charge held by the capacitance element 40 ２ and the capacitance element 40 １ The potential of the connection point of the inverter circuit 1 in the first stage is set to 1 V. ２ PMOS1 ２Ｐ When the inverter circuit 2 is turned on, １PMOS2 １Ｐ will be turned on.

[0053] The input node of the third-stage inverter circuit 3 is connected to the input node of the inverter circuit 1 arranged second in the first-stage inverter circuit group 1. ２ PMOS1 ２Ｐ When the capacitor element 40 is turned on, ３ The charge held by the capacitance element 40 ３ and the capacitance element 40 ２ The potential of the third inverter circuit 1 in the first-stage inverter circuit group 1 is 2V. ３ PMOS1 ３Ｐ and inverter circuit 2 ２ PMOS2 ２Ｐ is turned on, the PMOS3 of the inverter circuit 3 １Ｐ will be turned on.

[0054] Inverter circuit 1 in the first stage inverter circuit group 1 １ ~1 ３ PMOS1 １Ｐ ~1 ３Ｐ , inverter circuit 2 in the second stage inverter circuit group 2 １ , 2 ２ PMOS2 １Ｐ , 2 ２Ｐ , PMOS3 of the third-stage inverter circuit 3 １Ｐ is turned on, and the potential in the circuit wiring connecting the inverter circuits becomes as follows, as shown in FIG.

[0055] That is, solid line A in FIG. １ As shown, the power supply potential node V ＤＤ (The third (highest) placed capacitor element 40 ３ ) to the power supply potential node V ＤＤ and the inverter circuit 1 arranged in the third (highest) position in the first-stage inverter circuit group 1. ３ Circuit wiring connecting the source nodes of the PMOS transistors, inverter circuit 1 ３ and the inverter circuit 2 arranged in the second (highest) position in the second-stage inverter circuit group 2. ２ Circuit wiring connecting the source nodes of the PMOS transistors, inverter circuit 2２ The potential of the path leading to the output terminal Out via the circuit wiring connecting the source node of the PMOS of the third-stage inverter circuit 3 and the circuit wiring connecting the output node of the inverter circuit 3 and the output terminal Out is 3V.

[0056] The dashed line B in Figure 3 １ As shown in the figure, the third capacitor element 40 ３ The other electrode of the capacitor element 40 ３ The other electrode of the capacitor element 40 is disposed at the second position. ２ a circuit wiring that connects one electrode of the capacitor element 40 ３ The other electrode of the inverter circuit 2 is connected to the second inverter circuit 2 in the second stage. ２ The inverter circuit 2 is connected to the input node of the inverter circuit 2 via the circuit wiring. ２ The potential of the path leading to the input node of the inverter circuit 2 is 2V. ２ PMOS2 ２Ｐ turns on.

[0057] The dashed line B in Figure 3 １ As shown in the figure, the capacitance element 40 ３ The other electrode of the capacitor element 40 ３ The other electrode and the inverter circuit 1 ３ The inverter circuit 1 is connected to the source node of the NMOS transistor 1 through a circuit wiring. ３ The potential of the path leading to the source node of the NMOS is 2V.

[0058] Also, in FIG. １ As shown in the figure, the capacitance element 40 ３ The other electrode of the capacitor element 40 ３ The other electrode of the inverter circuit 1 is connected to the second inverter circuit 1 in the first stage inverter circuit group 1. ２ Circuit wiring connecting the source nodes of the PMOS transistors, inverter circuit 1 ２ and the output node of the inverter circuit 2 arranged first in the second-stage inverter circuit group 2. １ and a circuit wiring for connecting the source nodes of the PMOS transistors in the inverter circuit 2. １The potential of the path leading to the input node of the inverter circuit 3 via the circuit wiring connecting the output node of the inverter circuit 3 to the input node of the third-stage inverter circuit 3 is 2V. １Ｐ turns on.

[0059] The dashed line B in Figure 3 １ As shown in the figure, the inverter circuit 1 ２ output node and inverter circuit 2 ２ The inverter circuit 2 is connected to the source node of the NMOS transistor 1 through a circuit wiring. ２ The potential of the path leading to the source node of the NMOS is 2V. ２ NMOS2 ２Ｎ is off.

[0060] The dashed line B in Figure 3 １ As shown in the figure, the inverter circuit 1 ２ output node and inverter circuit 2 １ and a circuit wiring for connecting the source nodes of the PMOS transistors in the inverter circuit 2. １ The potential of the path leading to the source node of the NMOS of the inverter circuit 3 via the circuit wiring connecting the output node of the NMOS of the inverter circuit 3 to the source node of the NMOS of the inverter circuit 3 is 2V. １Ｎ is off.

[0061] Furthermore, the dashed line C in FIG. １ As shown in the figure, the second most placed capacitive element 40 ２ The other electrode of the capacitor element 40 ２ The other electrode of the capacitor element 40 is connected to the first electrode of the capacitor element 40. １ a circuit wiring that connects one electrode of the capacitor element 40 ２ The other electrode of the inverter circuit 2 and the inverter circuit 2 arranged in the first position in the second stage inverter circuit group 2 １ The inverter circuit 2 is connected to the input node of the inverter circuit 2 via the circuit wiring. １ The potential of the path leading to the input node of inverter circuit 2 is 1 V. ２ PMOS2 １Ｐ turns on.

[0062] The dashed line C in FIG. １As shown in the figure, the capacitance element 40 ２ The other electrode of the capacitor element 40 ２ The other electrode and the inverter circuit 1 １ a circuit wiring for connecting the source nodes of the PMOS transistors, and an inverter circuit 1 １ output node and inverter circuit 2 １ The inverter circuit 2 is connected to the source node of the NMOS transistor 1 through a circuit wiring. １ The potential of the path leading to the source node of the NMOS is 1 V. １ NMOS2 １Ｎ is off. Inverter circuit 1 １ The source node of the NMOS is indicated by the two-dot chain line D in FIG. １ As shown, it is 0V.

[0063] Next, the input terminal In １ ~In ３ A case where an input signal having a high potential is input to each of the inverter circuits 1 and 2 will be described with reference to FIG. １ ~1 ３ NMOS1 １Ｎ ~1 ３Ｎ is on, PMOS1 １Ｐ ~1 ３Ｐ is off.

[0064] Power supply potential node V ＤＤ and the ground potential node V ＳＳ A capacitance element 40 that divides the voltage between １ ~40 ３ The electric potential state of each inverter circuit is as follows: １ The input node of the capacitor 40 ２ The charge held by the capacitance element 40 ２ and the capacitance element 40 １ The inverter circuit 1 arranged at the first (lowest) position in the first-stage inverter circuit group 1 is set to 1 V, which is the potential at the connection point of １ NMOS1 １Ｎ When the inverter circuit 2 is turned on,１ NMOS2 １Ｎ will be turned on.

[0065] The inverter circuit 2 arranged second in the second-stage inverter circuit group 2 ２ The input node of the capacitor 40 ３ The charge held by the capacitance element 40 ３ and the capacitance element 40 ２ The potential of the connection point of the inverter circuit 1 is set to 2V. ２ NMOS1 ２Ｎ When the inverter circuit 2 is turned on, ２ NMOS2 ２Ｎ will be turned on.

[0066] The input node of the third-stage inverter circuit 3 is connected to the input node of the inverter circuit 1 arranged second in the first-stage inverter circuit group 1. ２ NMOS1 ２Ｎ When the capacitor element 40 is turned on, ２ The charge held by the capacitance element 40 ２ and the capacitance element 40 １ The potential of the first inverter circuit 1 in the first-stage inverter circuit group 1 is 1 V. １ NMOS1 １Ｎ and inverter circuit 2 １ NMOS21 ２Ｎ is turned on, the NMOS3 of the inverter circuit 3 １Ｎ will be turned on.

[0067] Inverter circuit 1 in the first stage inverter circuit group 1 １ ~1 ３ NMOS1 １Ｎ ~1 ３Ｎ , inverter circuit 2 in the second stage inverter circuit group 2 １ , 2 ２ NMOS2 １Ｎ , 2 ２Ｎ , NMOS3 of the third-stage inverter circuit 3 １Ｎ is turned on, and the potential in the circuit wiring connecting the inverter circuits becomes as follows, as shown in FIG.

[0068] That is, the dashed two-dot line D in FIG. ２ As shown, the ground potential node V ＳＳ (The first (lowest) placed capacitive element 40 １ ) to the ground potential node V ＳＳ and the inverter circuit 1 arranged at the first (highest) position in the first-stage inverter circuit group 1. １ Circuit wiring connecting the source nodes of the NMOS, inverter circuit 1 １ and the inverter circuit 2 arranged at the first (lowest) position in the second-stage inverter circuit group 2. １ Circuit wiring connecting the source nodes of the NMOSs, inverter circuit 2 １ The circuit wiring connecting the output node of the inverter circuit 3 to the source node of the NMOS of the third stage inverter circuit 3 and the circuit wiring connecting the output node of the inverter circuit 3 to the output terminal Out are electrically connected, and the ground potential node V ＳＳ The potential of the path from the output terminal Out is 0V.

[0069] The dashed line C in FIG. ２ As shown in the figure, the second most placed capacitive element 40 ２ The other electrode of the capacitor element 40 ２ The other electrode of the capacitor element 40 is connected to the first electrode of the capacitor element 40. １ a circuit wiring that connects one electrode of the capacitor element 40 ２ The other electrode of the inverter circuit 2 and the inverter circuit 2 arranged in the first position in the second stage inverter circuit group 2 １ The inverter circuit 2 is connected to the input node of the inverter circuit 2 via the circuit wiring. １ The potential of the path leading to the input node of inverter circuit 2 is 1 V. １ NMOS2 １Ｎ is turned on. Inverter circuit 2 １ PMOS2 １Ｐ is off.

[0070] The dashed line C in FIG. ２ As shown in the figure, the capacitance element 40 ２ The other electrode of the capacitor element 40 ２ The other electrode and the inverter circuit 1 ２a circuit wiring for connecting the source nodes of the NMOS transistors, and an inverter circuit 1 ２ The potential of the path leading to the input node of the inverter circuit 3 via the circuit wiring connecting the output node of the inverter circuit 3 and the input node of the inverter circuit 3 is 1V. １Ｎ is turned on. Inverter circuit 2 １ PMOS3 １Ｐ is off.

[0071] The dashed line C in FIG. ２ As shown in the figure, the capacitance element 40 ２ The other electrode of the capacitor element 40 ２ The other electrode and the inverter circuit 1 ２ a circuit wiring for connecting the source nodes of the NMOS transistors, and an inverter circuit 1 ２ output node and inverter circuit 2 １ The inverter circuit 2 is connected to the source node of the PMOS transistor 1 through a circuit wiring. １ The potential of the path leading to the source node of the PMOS is 1 V. ２ As shown in the figure, the inverter circuit 1 ２ output node and inverter circuit 2 ２ The inverter circuit 2 is connected to the source node of the NMOS transistor 1 through a circuit wiring. ２ The potential of the path leading to the source node of the NMOS is 1V.

[0072] The dashed line B in Figure 4 ２ As shown in the figure, the third capacitor element 40 ３ The other electrode of the capacitor element 40 ３ The other electrode of the capacitor element 40 is disposed at the second position. ２ a circuit wiring that connects one electrode of the capacitor element 40 ３ The other electrode of the inverter circuit 2 is connected to the second inverter circuit 2 in the second stage. ２ The inverter circuit 2 is connected to the input node of the inverter circuit 2 via the circuit wiring. ２ The potential of the path leading to the input node of the inverter circuit 2 is 2V. ２ NMOS2 ２Ｎ is turned on. Inverter circuit 2 ２ PMOS2２Ｐ is off.

[0073] The dashed line B in Figure 4 ２ As shown in the figure, the capacitance element 40 ３ The other electrode of the capacitor element 40 ３ The other electrode of the inverter circuit 1 is connected to the second inverter circuit 1 in the first stage inverter circuit group 1. ２ The inverter circuit 1 is connected to the source node of the PMOS transistor 1 through a circuit wiring. ２ The potential of the path leading to the source node of the PMOS is 2V.

[0074] The dashed line B in Figure 4 ２ As shown in the figure, the capacitance element 40 ３ The other electrode of the capacitor element 40 ３ The other electrode and the inverter circuit 1 ３ The inverter circuit 1 is connected to the source node of the NMOS transistor 1 through a circuit wiring. ３ The potential of the path leading to the source node of the NMOS is 2V. ３ The source node of the PMOS is shown by the solid line A in FIG. ２ As shown, it is 3V.

[0075] The driver circuit according to the first embodiment is a three-stage driver circuit using inverter circuits made of CMOS, ＤＤ and the ground potential node V ＳＳ Three inverter circuits 1 connected in series between １ ~1 ３ a first stage inverter circuit group 1 having three inverter circuits 1 １ ~1 ３ Corresponding to each inverter circuit 1 １ ~1 ３ and a power supply potential node V ＤＤ and the ground potential node V ＳＳ Three capacitance elements 40 connected in series between １ ~40 ３ and an inverter circuit 1 arranged in the first position. １ The output node of the inverter circuit 1 is connected to the second ２The input node is connected to the output node of the inverter circuit 1 without connecting a capacitance element therebetween. １ The source node of the PMOS and the inverter circuit 1 ２ a first inverter circuit 2 electrically connected to the source node of the NMOS transistor １ , and inverter circuit 1 ２ The output node of the inverter circuit 1 is connected to the third node. ３ The input node is connected to the output node of the inverter circuit 1 without connecting a capacitance element therebetween. ２ The source node of the PMOS and the inverter circuit 1 ３ The second inverter circuit 2 is electrically connected to the source node of the NMOS transistor 1. ２ a second stage inverter circuit group 2 having the inverter circuit 2 １ output node and inverter circuit 2 ２ The input node is connected to the output node of the inverter circuit 2 without connecting a capacitance element therebetween. １ The source node of the PMOS and the inverter circuit 2 ２ Since the third-stage inverter circuit 3 is electrically connected to the source node of the NMOS of the first stage, the number of capacitance elements can be reduced, the length of the circuit wiring connecting the inverter circuits can be shortened, and the parasitic capacitance generated in the circuit wiring can be reduced. As a result, the rise and fall times of the output voltage of the driver circuit can be made faster.

[0076] In addition, the driver circuit according to the first embodiment has a capacitance element 40 １ The capacitance value of the parasitic capacitance C of the NMOS Ｎ The capacitance value of the second-placed capacitor element 40 is twice that of the first-placed capacitor element 40. ２ The capacitance value of the PMOS parasitic capacitance C Ｐ or the parasitic capacitance C of the NMOS Ｎ the capacitance value of whichever is larger, and the capacitance element 40 placed in the third place ３ The capacitance value of the PMOS parasitic capacitance C Ｐ Therefore, when the PMOS and when the NMOS are turned on, the inverter circuits constituting the inverter circuit groups 1 to 3 operate quickly and complementarily.

[0077] Furthermore, the driver circuit according to the first embodiment includes the capacitance element 40 １ ~40 ３ In the capacitor element 40, the length of the short side of the electrode is set to be equal to or less than the distance between the source node of the PMOS and the source node of the NMOS of the inverter circuit, and the length of the long side is set to be equal to or less than five times the length of the short side. １ ~40 ３ and input signal line 50 １ ~50 ３ As a result, the rise and fall times of the output voltage output from the output node of the inverter circuit 3 can be shortened.

[0078] Second Embodiment A driver circuit according to a second embodiment will be described with reference to Figures 5 to 7. The driver circuit according to the second embodiment is the same as the first embodiment except that, while the driver circuit according to the first embodiment is a driver circuit with a three-stage HoC configuration, the driver circuit according to the second embodiment is a driver circuit with an M-stage HoC configuration. M is a natural number equal to or greater than 4. In Figures 5 to 7, the same reference numerals as those in Figures 1 to 4 indicate the same or corresponding parts.

[0079] The driver circuit according to the second embodiment is basically configured based on the same concept as the driver circuit according to the first embodiment, and includes M inverter circuits 1 as a first-stage (initial stage) inverter circuit group 1. １ ~1 Ｍ The driver circuit has an M-stage HoC configuration, and is configured with M stages of inverter circuits, each of which has one inverter circuit less than the number of inverter circuits in the preceding stage inverter circuit group. The Mth stage (final stage) inverter circuit group M is a single inverter circuit M.

[0080] 5, the driver circuit according to the second embodiment includes a first-stage inverter circuit group 1, a second-stage inverter circuit group 2 to an (M-1)th-stage inverter circuit group M-1, an Mth-stage inverter circuit M, and a capacitive element group 40. The first-stage inverter circuit group 1 is connected to a power supply potential node V ＤＤ and the ground potential node Vｓｓ M inverter circuits 1 connected in series between １ ~1 Ｍ It has.

[0081] Power supply potential node V ＤＤ The potential of the first stage inverter circuit group 1 is M inverter circuits 1 １ ~1 Ｍ Therefore, if the breakdown voltage of each of the PMOS and NMOS that make up the inverter circuit is 1V, the voltage is M times 1V, which is MV. ｓｓ The potential of is the ground potential, that is, 0V.

[0082] Inverter circuit 1 １ From inverter circuit 1 Ｍ Each input node of the １ to input terminal In Ｍ Each input signal line 50 １ to input signal line 50 Ｍ The inverter circuit 1 is electrically connected by １ From inverter circuit 1 Ｍ The input terminals In １ to input terminal In Ｍ An input signal is input to each of them.

[0083] Input terminal In １ ~In Ｍ The input signals input to each inverter circuit have the same amplitude and phase, and the direct current (DC) level is the inverter circuit 1 placed first. １ A first input terminal In connected to the input node １ These are signals that are offset by an equal voltage in order from .

[0084] That is, the input terminal In arranged at the first (lowest) position １ The input signal input to the second input terminal In is a signal whose L level potential is 0V and whose H level potential is 1V. ２ The input signal input to the input terminal In １ The potential difference between the input terminal In and the H level potential of the input signal is 1V. １The potential difference of the input signal is the same as that of the input signal input to the input terminal 1, and the H level potential is 2V.

[0085] Similarly, the input signals input to the input terminals In arranged from the third place onwards to the (M-1)th place have a potential difference of 1V, and are signals that change the H level potential of the input signal input to the input terminal In arranged in the order preceding it to an L level. Ｍ The input signal input to is a signal whose L level potential is (M-1)V and whose H level potential is MV.

[0086] The capacitance element group 40 includes M inverter circuits 1 in the first stage (initial stage) of the inverter circuit group 1. １ ~1 Ｍ Corresponding inverter circuits 1 １ ~1 Ｍ and a power supply potential node V ＤＤ and the ground potential node V ＳＳ M capacitance elements 40 connected in series between １ ~40 Ｍ It has.

[0087] M capacitance elements 40 connected in series １ ~40 Ｍ is the power supply potential node V ＤＤ and the ground potential node V ＳＳ The first capacitor element 40 has a function of dividing the voltage between the first capacitor element 40 and the second capacitor element 40. １ and the second most placed capacitive element 40 ２ The potential at the connection point is V ＤＤ -V ＤＤ (M-1) / M (=V ＤＤ / M), which is 1V in the first embodiment, and the first-placed input terminal In １ The H level potential of the input signal input to the input terminal In ２ This is the same as the L level potential of the input signal input to the input terminal.

[0088] In other words, the potential at the connection point where adjacent capacitance elements 40 are connected is the same as the H level potential of the input signal input to the lower input terminal In and the L level potential of the input signal input to the upper input terminal In.

[0089] The capacitive element 40 located at the Mth position Ｍ and the capacitive element 40 arranged at the (M-1) position Ｍ－１ The potential at the connection point is V ＤＤ -V ＤＤ / M (=V ＤＤ (M-1) / M), and the input terminal In １ and the H level potential of the input signal input to the input terminal In ２ This is the same as the L level potential of the input signal input to the input terminal.

[0090] In addition, M capacitive elements 40 １ ~40 Ｍ have the function of charging the gate electrodes of the PMOS or NMOS of each of the inverter circuits in the second-stage inverter circuit group 2 to the (M-1)th-stage inverter circuit group M-1 and the Mth-stage inverter circuit M, using the charges they hold.

[0091] In each of the inverter circuit groups 2 to M-1 in the second to (M-1) stages, a plurality of inverter circuits are connected in series. In each of the inverter circuit groups 2 to M-1 in the middle stages, a plurality of inverter circuits are connected to a ground potential node V ＳＳ In order from the left, the ground potential node V ＳＳIn a state where no capacitance element is connected between the output nodes of two inverter circuits connected adjacently from the left, the source node of the PMOS is connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits, and the source node of the NMOS is electrically connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits. In each of the middle inverter circuit groups 2 to M-1, the input nodes of the multiple inverter circuits are connected to the source nodes of the PMOS of the inverter circuits in the previous inverter circuit group in order from the inverter circuit on the ground potential node side in the previous inverter circuit group.

[0092] That is, the second stage inverter circuit group 2 has (M-1) inverter circuits 2 １ ~2 Ｍ－１ The inverter circuit 2 arranged at the lowest position, i.e., the first position, １ is the inverter circuit 1 placed first in the first stage inverter circuit group 1. １ The output node of the inverter circuit 1 is connected to the second ２ The inverter circuit 2 is electrically connected to the output node of the inverter circuit 1 without connecting a capacitance element therebetween. １ The input node of the inverter circuit 1 of the first stage inverter circuit group 1 １ The source node of the PMOS and the inverter circuit 1 ２ The source node of the NMOS is electrically connected to the source node of the NMOS.

[0093] Inverter circuit 2 placed in second place ２ is the inverter circuit 1 placed second in the first stage inverter circuit group 1. ２ The output node of the inverter circuit 1 is connected to the third node. ３ The inverter circuit 2 is electrically connected to the output node of the inverter circuit 1 without connecting a capacitance element therebetween. ２ The input node of the inverter circuit 1 of the first stage inverter circuit group 1 ２ The source node of the PMOS and the inverter circuit 1 ３ The source node of the NMOS is electrically connected to the source node of the NMOS.

[0094] Inverter circuit 2 placed in the third or subsequent (M-1)th place (highest place) ２ ~2 Ｍ－１ Similarly, the inverter circuits 2 arranged at the third and (M-1)th positions are electrically connected to the output nodes of the adjacent inverter circuits in the first-stage inverter circuit group 1 without connecting any capacitance element between them. ３ ~2 Ｍ－１ Similarly, the input node of is electrically connected to the source node of the PMOS of the inverter circuit arranged lower in the adjacent inverter circuit in the first stage inverter circuit group 1 and the source node of the NMOS of the inverter circuit arranged higher in the adjacent inverter circuit.

[0095] Inverter circuit 2 arranged at the (M-1)th position Ｍ－１ is the inverter circuit 1 arranged at the (M-1)th position in the first stage inverter circuit group 1. Ｍ－１ The output node of the inverter circuit 1 Ｍ The inverter circuit 2 arranged at the (M-1)th position is electrically connected to the output node of the inverter circuit 2 without connecting a capacitance element therebetween. Ｍ－１ The input node of the inverter circuit 1 arranged at the (M-1)th position in the first stage inverter circuit group 1 is Ｍ－１ and the source node of the PMOS and the inverter circuit 1 arranged at the Mth position. Ｍ The source node of the NMOS is electrically connected to the source node of the NMOS.

[0096] The third stage inverter circuit group 3 has (M-2) inverter circuits 3 １ ~3 Ｎ－２ The inverter circuit 3 arranged at the lowest position, i.e., the first position, １ is the inverter circuit 2 placed first in the second stage inverter circuit group 2 １ The output node of the inverter circuit 2 ２ The inverter circuit 3 is electrically connected to the output node of the inverter circuit 3 without connecting a capacitance element therebetween. １ The input node of the inverter circuit 2 of the second stage inverter circuit group 2 １ The source node of the PMOS and the inverter circuit 2 ２The source node of the NMOS is electrically connected to the source node of the NMOS.

[0097] Inverter circuit 3 placed in second place ２ is the inverter circuit 2 arranged second in the second stage inverter circuit group 2 ２ The output node of the inverter circuit 2 ３ The inverter circuit 3 is electrically connected to the output node of the inverter circuit 3 without connecting a capacitance element therebetween. ２ The input node of the inverter circuit 2 of the second stage inverter circuit group 2 ２ The source node of the PMOS and the inverter circuit 2 ３ The source node of the NMOS is electrically connected to the source node of the NMOS.

[0098] Inverter circuits 3 arranged from the third place to the (M-2)th place (highest place) ２ ~3 Ｍ－２ Similarly, the inverter circuits 3 arranged at the third and (M-2)th positions are electrically connected to the output nodes of the adjacent inverter circuits in the second-stage inverter circuit group 2 without connecting any capacitance element between them. ３ ~3 Ｍ－２ Similarly, the input node of is electrically connected to the source node of the PMOS of the inverter circuit arranged lower and the source node of the NMOS of the inverter circuit arranged upper in the adjacent inverter circuit in the second stage inverter circuit group 2.

[0099] Inverter circuit 3 arranged at the (M-2)th position Ｍ－２ is the inverter circuit 2 arranged at the (M-2)th position in the second stage inverter circuit group 2. Ｍ－２ and the inverter circuit 1 arranged at the (M-1)th position. Ｍ－１ The inverter circuit 3 arranged at the (M-2)th position is electrically connected to the output node of the inverter circuit 3 without connecting a capacitance element therebetween. Ｍ－２ The input node of the inverter circuit 2 is located at the (M-2)th position in the second-stage inverter circuit group 2. Ｍ－２ and the source node of the PMOS transistor and the inverter circuit 1 arranged at the (M-1)th position. Ｍ－１ The source node of the NMOS is electrically connected to the source node of the NMOS.

[0100] For the fourth-stage inverter circuit group 4 to the (M-1)th-stage inverter circuit group M-2, similarly to the second-stage inverter circuit group 2 to the third-stage inverter circuit group 3, multiple inverter circuits are connected between the output nodes of adjacent inverter circuits in the previous-stage inverter circuit group without connecting any capacitive elements.

[0101] Similarly to the second-stage inverter circuit group 2 to the third-stage inverter circuit group 3, the input nodes of the fourth-stage inverter circuit group 4 to the (M-1)th-stage inverter circuit group M-2 are electrically connected to the source node of the PMOS of the inverter circuit located lower in the adjacent inverter circuit in the previous-stage inverter circuit group and the source node of the NMOS of the inverter circuit located higher.

[0102] The M-th inverter circuit M is the inverter circuit group M-1 in the (M-1)th stage, and the (M-1)-th inverter circuit group M-1 is the inverter circuit (M-1) arranged in the first place (lowest position). １ The output node of the inverter circuit (M-1) is located at the second (highest) position. ２ The input node of the M-th inverter circuit M is electrically connected to the output node of the inverter circuit (M-1) of the (M-1)-th inverter circuit group M-1 without connecting a capacitance element between the inverter circuit M and the output node of the inverter circuit (M-1) of the (M-1)-th inverter circuit group M-1. １ The source node of the PMOS and the inverter circuit (M-1) ２ The source node of the NMOS is electrically connected to the source node of the NMOS.

[0103] The first stage inverter circuit group 1, the second stage inverter circuit group 2, the third stage inverter circuit group 3, ..., the (M-1)th stage inverter circuit group, and the Mth stage inverter circuit are stacked vertically on the surface of a semiconductor substrate via an insulating layer in the order of the first stage, second stage, third stage, ..., (M-1)th stage, and Mth stage.

[0104] Capacitor element 40 arranged at the Mth position (top position) Ｍ When the PMOS is turned on, the inverter circuit 2 arranged at the (M-1)th (highest) position in the second-stage inverter circuit group 2 is turned on. Ｍ－１ PMOS2 in Ｍ－１Ｐ, the gate electrode of the inverter circuit 3 arranged at the top in the inverter circuit group 3 to M-1 in the third to (M-1) stages. Ｍ－２ ~ (M-1) ２ PMOS3 in Ｍ－２Ｐ ~ (M-1) ２Ｐ the gate electrode of the PMOS M in the M-th inverter circuit M １Ｐ Therefore, the gate electrode of the capacitance element 40 located at the Mth position is charged. Ｍ The capacitance value of PMOS2 Ｍ－１Ｐ From PMOS M １Ｐ In order to turn on the Ｐ It is set to.

[0105] As a result, the inverter circuit 1 in the first stage inverter circuit group 1 １ ~1 Ｍ PMOS1 １Ｐ ~1 ＭＰ When the inverter circuit 3 is turned on, the inverter circuit 3 is arranged at the top of the inverter circuit groups 2 to M-1 in the second to (M-1) stages. Ｍ－１ ~ (M-1) ２ PMOS3 in Ｍ－１Ｐ ~ (M-1) ２Ｐ and a PMOS M in the M-th inverter circuit M １Ｐ Therefore, the output terminal Out is connected to the power supply potential node V ＤＤ The potential V applied to ＤＤ (for example, NV) is output.

[0106] Capacitor element 40 located at the (M-1)th position Ｍ－１ When the PMOS is turned on, the inverter circuit 2 arranged at the (M-2)th position (one position lower than the highest position) in the second-stage inverter circuit group 2 is turned on. Ｍ－２ PMOS2 in Ｍ－２Ｐ , the gate electrode of the inverter circuit 3 arranged one step lower from the top in the inverter circuit group 3 to M-1 in the third to (M-1) stages. Ｍ－２ ~ (M-2) １ PMOS2 in Ｍ－２Ｐ ~ (M-1) １Ｐ Therefore, the gate electrode of the capacitor element 40 located at the (M-1)th position is charged. Ｍ－１The capacitance value of PMOS2 Ｍ－２Ｐ From PMOSM-1 １Ｐ In order to turn on the Ｐ is necessary.

[0107] Capacitor element 40 located at the (M-1)th position Ｍ－１ When the NMOS is turned on, the inverter circuit 2 arranged at the (M-1)th (highest) position in the second-stage inverter circuit group 2 Ｍ－１ NMOS2 in Ｍ－１Ｎ Therefore, the gate electrode of the capacitor element 40 located at the (M-1)th position is charged. Ｍ－１ The capacitance value of NMOS2 Ｍ－１Ｎ In order to turn on Ｎ Therefore, the capacitance element 40 Ｍ－１ The capacitance value is (M-2)C Ｐ or C Ｎ The capacitance value is set to the larger value of either

[0108] The capacitive elements 40 arranged from the (M-2)th place to the 2nd place Ｍ－２ ~40 ２ Similarly, when turning on the PMOS, the gate electrodes of the PMOSs in the inverter circuits arranged one level lower are charged, and the capacitive elements 40 arranged from the (M-2)th to the 2nd highest are charged. Ｍ－２ ~40 ２ The capacitance value of Ｐ From C Ｐ When the PMOS is turned on, the m-th capacitance element 40 arranged from the (M-2)th position to the 2nd position is ｍ The capacitance value of C is (m-1) times Ｐ requires.

[0109] The capacitive elements 40 arranged from the (M-2)th place to the 2nd place Ｍ－２ ~40 ２ Similarly, when the NMOS is turned on, the gate electrodes of the NMOSs in the inverter circuits arranged in the same order are charged, and the capacitive elements 40 arranged from the (M-2)th to the 2nd Ｍ－２ ~40 ２ The capacitance value of Ｎ From (M-3) times C ＮWhen the NMOS is turned on, the m-th capacitance element 40 arranged from the (M-2)th position to the 2nd position is ｍ The capacitance value of is (M-m) times C Ｎ Therefore, the m-th capacitor element 40 arranged from the (M-2)th place to the 2nd place is ｍ The capacitance value of is (m-1)C Ｐ or (M-m)C Ｎ The capacitance value is set to the larger value of either

[0110] The first (lowest) placed capacitive element 40 １ When the NMOS is turned on, the inverter circuit 2 arranged at the first (lowest) position in the second-stage inverter circuit group 2 １ NMOS2 in １Ｎ , the gate electrode of the inverter circuit 3 arranged at the lowest position in the inverter circuit group 3 to M-1 in the third to (M-1)th stages. １ ~ (M-1) １ NMOS3 in １Ｎ ~ (M-1) １Ｎ the gate electrode of the NMOS M in the M-th inverter circuit M １Ｎ Therefore, the gate electrode of the capacitance element 40 located at the Mth position is charged. Ｍ The capacitance value of NMOS2 １Ｎ From NMOSM １Ｎ In order to turn on the Ｎ It is set to.

[0111] As a result, the inverter circuit 1 in the first stage inverter circuit group 1 １ ~1 Ｍ NMOS1 １Ｎ ~1 ＭＮ When the inverter circuit 2 is turned on, the inverter circuit 2 is turned on. １ NMOS2 in １Ｎ ~ (M-1) １Ｎ and the NMOS M of the M-th stage inverter circuit M １Ｎ Therefore, the output terminal Out is connected to the ground potential node V ＳＳ and grounded (for example, 0 V).

[0112] In short, in the driver circuit according to the second embodiment, in the first stage inverter circuit group 1, the ground potential node V ｓｓ The source node of the NMOS is electrically connected to the inverter circuit 1. １ is the first, and the power supply potential node V ＤＤ The source node of the PMOS is electrically connected to the inverter circuit 1. Ｍ is the Mth rank, the mth rank capacitive element 40 arranged from the 1st rank to the Mth rank ｍ The capacitance value of is (m-1)C Ｐ or (M-m)C Ｎ The capacitance value is set to the larger value of m.

[0113] In this way, the capacitance elements 40 arranged from the first place to the Mth place １ ~40 Ｍ By setting the capacitance value of , even if each inverter circuit in the inverter circuit groups 2 to M of the second to Mth stages is connected without connecting a capacitance element between the output nodes of the adjacent inverter circuits in the inverter circuit group of the previous stage, the inverter circuits constituting the inverter circuit groups 1 to M will operate quickly and complementarily both when the PMOS is turned on and when the NMOS is turned on.

[0114] As a result, the input terminal In １ ~In Ｍ Depending on the H level and L level input to each, it is possible to output an output voltage, for example, 0V or NV signal, with a fast rise and fall time that exceeds the withstand voltage of the PMOS and NMOS, to the output terminal Out.

[0115] The capacitive element group 40 is modularized or integrated in the same manner as in the first embodiment. １ ~40 Ｍ The length of the short side of each electrode is equal to or less than the distance between the source node of the PMOS and the source node of the NMOS in the inverter circuit, as in the first embodiment. １ ~40 Ｍ The length of the long side of each electrode is five times or less the length of the short side.

[0116] Capacitor element 40 １ ~40 Ｍ The size of the electrode in the input signal line 50 is such that the length of the short side is equal to or less than the distance between the source node of the PMOS and the source node of the NMOS of the inverter circuit, and the length of the long side is equal to or less than five times the length of the short side. １ ~50 Ｍ As a result, the rise and fall times of the output voltage output from the output node of the inverter circuit 3 can be shortened.

[0117] Next, the operation of the driver circuit according to the second embodiment will be described. １ ~In Ｍ A case where an input signal having an L level potential is input to each of the inverter circuits 1 and 2 will be described with reference to FIG. １ ~1 Ｍ PMOS1 １Ｐ ~1 ＭＰ is on, NMOS1 １Ｎ ~1 ＭＮ is off.

[0118] Power supply potential node V ＤＤ and the ground potential node V ＳＳ A capacitance element 40 that divides the voltage between １ ~40 Ｍ The electric potential state is as follows depending on the charge held by each of them. In order to avoid complexity and redundancy of the explanation, the names of the components will be omitted and the explanation will be given by reference numerals. For example, ＤＤ and the inverter circuit 1 arranged at the top of the first stage inverter circuit group 1. Ｍ "Circuit wiring connecting the source nodes of the PMOS transistors" is "V ＤＤ -1 Ｍ The source node of the PMOS transistor is described as "the source node of the PMOS transistor."

[0119] Solid line A in FIG. ３ As shown in V ＤＤ (40 Ｍ one electrode) to V ＤＤ -1 Ｍ the source node of the PMOS,Ｍ Output node-2 of Ｍ－１ the source node of the PMOS, Ｍ－１ Output node-2 of Ｍ－２ The source nodes of the PMOS transistors M-1, M-2, M-3, M-4, M-5, M-6, M-7, M-8, M-9, M-10, M-11, M-12, M-13, M-14, M-15, M-16, M-17, M-18, M-19, M-20, M-21, M-22, M-23, M-24, M-25, M- ２ The potential of the path from the output node of M to the source node of the PMOS of M, via the output node of M-Out and the output terminal Out, is MV.

[0120] 40 Ｍ From the other electrode, 40 Ｍ The other electrode -40 Ｍ－１ One electrode of the Ｍ The other electrode -1 Ｍ The source node of the NMOS Ｍ－１ The source node of the PMOS Ｍ－１ input node of ,1 Ｍ－１ Output node-2 of Ｍ－１ The source node of the NMOS Ｍ－２ The source node of the PMOS and Ｍ－２ input node, 2 Ｍ－２ Output node-3 of Ｍ－２ The source node of the NMOS and Ｍ－３ The source node of the PMOS and Ｍ－３ Input nodes of (M-2) ２ Output node-3 of ２ The source node of the NMOS and １ the source node of the PMOS of １ The path from the output node of NMOS transistor M to the source node of NMOS transistor M is (M-1)V.

[0121] The dashed line B in FIG. ３ As shown in ３ From the other electrode, 40 ３ The other electrode -40 ２ One electrode of the ３ The other electrode -1 ３ The source node of the NMOS ２ The source node of the PMOS ２ input node of ,1 ２ Output node-2 of ２ The source node of the NMOS １ The source node of the PMOS of 3 and the input node of 2１ Output node-3 of １ The path at the source node of the NMOS is 2V.

[0122] The dashed line C in FIG. ３ As shown in ２ From the other electrode, 40 ２ The other electrode -40 １ One electrode of the ２ The other electrode -1 ２ The source node of the NMOS １ The source node of the PMOS １ input node of ,1 １ Output node-2 of １ The path at the source node of the NMOS is 1V. １ The source node of the NMOS is indicated by the two-dot chain line D in FIG. ３ As shown in the figure, the potential is 0 V. Because of the above potential relationship, all PMOS transistors are on and all NMOS transistors are off.

[0123] Next, the input terminal In １ ~In Ｍ A case where an input signal having a high potential is input to each of the inverter circuits 1 and 2 will be described with reference to FIG. １ ~1 Ｍ NMOS1 １Ｎ ~1 ＭＮ is on, PMOS1 １Ｐ ~1 ＭＰ is off. The power supply potential node V ＤＤ and the ground potential node V ＳＳ A capacitance element 40 that divides the voltage between １ ~40 Ｍ Depending on the charge they hold, the potential state is as follows:

[0124] The dashed double-dashed line D in FIG. ４ As shown, the ground potential node V ＳＳ (The first (lowest) placed capacitive element 40 １ one electrode of ＳＳ -1 １ the source node of the NMOS, １Output node-2 of １ the source node of the NMOS, １ Output node-3 of １ the source node of the NMOS, １ Output node-4 １ the source node of the NMOS, ..., (M-1) １ Output node of M １ The source node of the NMOS, M １ The output terminal Out is at the ground potential, that is, 0V, via the output node -Out.

[0125] The dashed line C in FIG. ４ As shown in ２ From the other electrode, 40 ２ The other electrode -40 １ One electrode and one ２ The source node of the NMOS １ The source node of the PMOS １ input node of ,1 ２ Output node-2 of ２ The source node of the NMOS １ The source node of the PMOS and １ input node, 2 ２ Output node-3 of ２ The source node of the NMOS and １ The source node of the PMOS and １ Input nodes of (M-2) ２ Output node of (M-1) ２ The source node of the NMOS and (M-1) １ the source node of the PMOS of (M-1) and the input node of (M-1) ２ The path at the output node of -M's PMOS is 1V.

[0126] The dashed line B in FIG. ４ As shown in ３ From the other electrode, 40 ３ The other electrode -40 ２ One electrode and one ３ The source node of the NMOS ２ The source node of the PMOS ２ input node of ,1 ３ Output node-2 of３ The source node of the NMOS ２ The source node of the PMOS and ２ input node, 2 ３ Output node-3 of ３ The source node of the NMOS and ２ The source node of the PMOS and ２ Input nodes of (M-2) ３ Output node of (M-1) ３ The source node of the NMOS and (M-1) ２ The path at the source node of the PMOS is 2V.

[0127] Part of the four-dot chain line F in FIG. ４ As shown in Ｍ－１ From the other electrode, 40 Ｍ－１ The other electrode -40 Ｍ－２ One electrode and one Ｍ－２ The source node of the NMOS Ｍ－１ The source node of the PMOS Ｍ－２ input node of ,1 Ｍ－１ Output node-2 of Ｍ－１ The source node of the NMOS Ｍ－２ The source node of the PMOS and Ｍ－２ input node, 2 Ｍ－１ Output node-3 of Ｍ－２ The path at the source node of the PMOS is (M-2)V.

[0128] Part of the three-dot chain line E in FIG. ４ As shown in Ｍ From the other electrode, 40 Ｍ The other electrode -40 Ｍ－１ One electrode and one Ｍ The source node of the NMOS Ｍ－１ The source node of the PMOS Ｍ－１ input node of ,1 Ｍ Output node-2 of Ｍ－１ The path at the source node of the PMOS is (M-1)V. １ The source node of the NMOS is at MV as shown by the solid line A4 in Fig. 7. Because of the above potential relationship, all PMOS are off and all NMOS are on.

[0129] The driver circuit according to the second embodiment is a driver circuit having an M-stage configuration using inverter circuits made of CMOS, in which a power supply potential node V ＤＤ and the ground potential node V ＳＳ M inverter circuits 1 connected in series between １ ~1 Ｍ a first stage inverter circuit group 1 having M inverter circuits 1; １ ~1 Ｍ Corresponding to each inverter circuit 1 １ ~1 Ｍ and a power supply potential node V ＤＤ and the ground potential node V ＳＳ M capacitance elements 40 connected in series between １ ~40 Ｍ and inverter circuit groups 2 to (M-1) in the second to (M-1)th stages, in which the number of inverter circuits is one less than the number of inverter circuits in the inverter circuit group in the previous stage, and in which, in a state in which no capacitance element is connected between the output nodes of two inverter circuits connected adjacently in order from the ground potential node side in the inverter circuit group in the previous stage, the source node of the PMOS is connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits, the source node of the NMOS is connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits, and the input node is connected to the source node of the PMOS of the inverter circuit in the inverter circuit group in order from the inverter circuit on the ground potential node side in the inverter circuit group in the previous stage. １ The output node and inverter circuit (M-1) ２ When no capacitance element is connected between the source node of the PMOS and the output node of the inverter circuit (M-1), ２ The source node of the NMOS is connected to the output node of the inverter circuit (M-1). １ The input node is connected to the output node of the inverter circuit (M-1). １The source node of the PMOS and the inverter circuit (M-1) ２ Since the inverter circuit M is provided at an Mth stage, which is electrically connected to the source node of the NMOS of the driver circuit, the number of capacitance elements can be reduced, the length of the circuit wiring connecting the inverter circuits can be shortened, and the parasitic capacitance generated in the circuit wiring can be reduced. As a result, the rise and fall times of the output voltage of the driver circuit can be made faster.

[0130] Furthermore, in the driver circuit according to the second embodiment, the capacitance value of the m-th capacitance element arranged from the 1st to Mth positions in the capacitance element group 40 is set to the larger of either the capacitance value that is (m-1) times the parasitic capacitance value of the PMOS or the capacitance value that is (M-m) times the parasitic capacitance value of the NMOS. Therefore, when both the PMOS and the NMOS are turned on, the inverter circuits constituting the inverter circuit groups 1 to 3 operate quickly and complementarily.

[0131] Furthermore, the driver circuit according to the second embodiment includes the capacitance element 40 １ ~40 Ｍ In the capacitor element 40, the length of the short side of the electrode is set to be equal to or less than the distance between the source node of the PMOS and the source node of the NMOS of the inverter circuit, and the length of the long side is set to be equal to or less than five times the length of the short side. １ ~40 Ｍ and input signal line 50 １ ~50 Ｍ As a result, the rise and fall times of the output voltage output from the output node of the inverter circuit 3 can be shortened.

[0132] Third Embodiment A driver circuit according to a third embodiment will be described with reference to Fig. 8. The driver circuit according to the third embodiment is a driver circuit that uses two of the driver circuits according to the first embodiment or the second embodiment, and obtains double the amplitude of the output voltage by differentially operating the two driver circuits.

[0133] The first driver circuit 100 is either the driver circuit according to embodiment 1 or the driver circuit according to embodiment 2. The second driver circuit 200 is either the driver circuit according to embodiment 1 or the driver circuit according to embodiment 2, and has the same configuration as the first driver circuit 100.

[0134] V1 is output as an H-level potential and V2 is output as an L-level potential from the output terminal Out of the first driver circuit 100. V1 is also output as an H-level potential and V2 is output as an L-level potential from the output terminal Out of the second driver circuit 200, and potentials that are 180 degrees out of phase are output via the 180-degree phase shift circuit 200A. The L-level potential is the ground potential, and the H-level potential is 3 V when the driver circuit according to the first embodiment is used and MV when the driver circuit according to the second embodiment is used.

[0135] The output terminal Out of the first driver circuit 100 is electrically connected to the gate electrode of the amplifying NMOS transistor 300 that constitutes the amplifier circuit. The output terminal Out of the second driver circuit 200 is electrically connected to the source electrode of the amplifying NMOS transistor 300 via a 180-degree phase shift circuit 200A. The drain electrode of the amplifying NMOS transistor 300 is electrically connected to the output terminal Out1 and is also connected to the power supply potential node V via a resistor element 400. Ｄ is electrically connected to

[0136] When V1 is applied to the gate electrode of the amplifying NMOS transistor 300 as an H level potential from the output terminal Out of the first driver circuit 100, V2, which is 180 degrees out of phase, is simultaneously applied to the source electrode of the amplifying NMOS transistor 300. Therefore, the potential difference between the gate electrode and the source electrode is 2 (V1 - V2), and an output voltage of 2 (V1 - V2) is obtained from the drain electrode of the amplifying NMOS transistor 300. Note that the power supply potential node V Ｄ The potential applied to is 2(V1-V2).

[0137] The potential difference between the gate electrode and source electrode of the amplifying NMOS transistor 300 is 6 V when the driver circuit according to the first embodiment is used, and is 2×MV when the driver circuit according to the second embodiment is used.

[0138] The driver circuit of embodiment 3 has the same effect as the driver circuit of embodiment 1 or the driver circuit of embodiment 2, and in addition, it can obtain twice the output voltage of the driver circuit of embodiment 1 or the driver circuit of embodiment 2.

[0139] It should be noted that the embodiments may be freely combined, or any of the components in each embodiment may be modified, or any of the components in each embodiment may be omitted.

[0140] The driver circuit according to the present disclosure uses an inverter circuit made of CMOS manufactured using a semiconductor process, and is suitable for a driver circuit that outputs a voltage equal to or higher than the withstand voltage of PMOS and NMOS.

[0141] 1 first stage inverter circuit group, 1 １ ~1 ３ ~1 Ｍ Inverter circuit, 2 Second stage inverter circuit group, 2 １ , 2 ２ ~2 Ｍ－１ Inverter circuit, 3 Third stage inverter circuit (group), 3, 3 １ , 3 ２ ~3 Ｍ－１ , 3 Ｍ Inverter circuit, M Mth stage inverter circuit, 40 Capacitance element group, 40 １ ~40 ３ ~40 Ｍ Capacitive element, 50 １ ~50 ３ ~50 Ｍ Input signal line, 100 first driver circuit, 200 second driver circuit, 300 amplifying MOS transistor.

Claims

1. a first-stage inverter circuit group including M inverter circuits, each inverter circuit being composed of a PMOS and an NMOS, each inverter circuit having an input node, an output node, a source node of the PMOS, and a source node of the NMOS, the M inverter circuits being connected in series between a power supply potential node and a ground potential node, with the source node of the PMOS being electrically connected to the source node of the NMOS in order from a first inverter circuit having an NMOS source node electrically connected to the ground potential node to an M-th inverter circuit having a PMOS source node electrically connected to the power supply potential node, and an input signal being input to the input node of each inverter circuit; a capacitance element group, each of which corresponds to one of the M inverter circuits in the first stage inverter circuit group, and is connected between a source node of a PMOS and a source node of an NMOS of the corresponding inverter circuit, and has M capacitance elements connected in series between the power supply potential node and the ground potential node, wherein the capacitance value of the m-th capacitance element arranged from the first to Mth places is the larger of either a capacitance value that is (m-1) times the parasitic capacitance value of the PMOS or a capacitance value that is (M-m) times the parasitic capacitance value of the NMOS; a second to (M-1)th inverter circuit group, each of which is composed of a PMOS and an NMOS, and has a plurality of inverter circuits each having an input node, an output node, a source node of the PMOS, and a source node of the NMOS, the number of which is one less than the number of inverter circuits in the inverter circuit group in the previous stage, the plurality of inverter circuits being connected in series, and each of which is arranged in order from the ground potential node side, with the source node of the PMOS connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits between output nodes of two inverter circuits connected adjacently in order from the ground potential node side in the inverter circuit group in the previous stage, and the source node of the NMOS connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits, the input node being connected to the source node of the PMOS of the inverter circuit in the inverter circuit group in the previous stage, in order from the inverter circuit on the ground potential node side in the inverter circuit group in the previous stage; an M-th stage inverter circuit composed of a PMOS and an NMOS, having an input node, an output node, a source node of the PMOS, and a source node of the NMOS, and between output nodes of two inverter circuits in an (M-1)th stage inverter circuit group, the source node of the PMOS is connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits, the source node of the NMOS is connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits, and the input node is connected to the source node of the PMOS of the inverter circuit on the ground potential node side in the (M-1)th stage inverter circuit group; A driver circuit comprising:

2. 2. The driver circuit according to claim 1, wherein the length of the short side of the electrode of each of the M capacitance elements is equal to or less than the distance between the source node of the PMOS and the source node of the NMOS of the inverter circuit, and the length of the long side is equal to or less than five times the length of the short side.

3. A first stage inverter circuit group comprising M inverter circuits, each inverter circuit being a natural number of 3 or more, each inverter circuit being composed of a PMOS and an NMOS, each inverter circuit having an input node, an output node, a source node of the PMOS, and a source node of the NMOS, the M inverter circuits being connected in series between a power supply potential node and a ground potential node with the source node of the PMOS being on the power supply potential node side, and an input signal being input to the input node of each inverter circuit; a capacitance element group including M capacitance elements, each of which corresponds to one of the M inverter circuits in the first-stage inverter circuit group, connected between a source node of a PMOS and a source node of an NMOS of the corresponding inverter circuit, and connected in series between the power supply potential node and the ground potential node, the length of a short side of each electrode of which is equal to or less than the distance between the source node of the PMOS and the source node of the NMOS of the inverter circuit, and the length of a long side of which is equal to or less than five times the length of the short side; a second to (M-1)th inverter circuit group, each of which is composed of a PMOS and an NMOS, and has a plurality of inverter circuits each having an input node, an output node, a source node of the PMOS, and a source node of the NMOS, the number of which is one less than the number of inverter circuits in the inverter circuit group in the previous stage, the plurality of inverter circuits being connected in series, and each of which is arranged in order from the ground potential node side, with the source node of the PMOS connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits between output nodes of two inverter circuits connected adjacently in order from the ground potential node side in the inverter circuit group in the previous stage, and the source node of the NMOS connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits, the input node being connected to the source node of the PMOS of the inverter circuit in the inverter circuit group in the previous stage, in order from the inverter circuit on the ground potential node side in the inverter circuit group in the previous stage; an M-th stage inverter circuit which is composed of a PMOS and an NMOS, has an input node, an output node, a source node of the PMOS, and a source node of the NMOS, and is connected between output nodes of two inverter circuits in an (M-1)th stage inverter circuit group with the source node of the PMOS connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits, and the source node of the NMOS connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits, and has an input node connected to the source node of the PMOS of the inverter circuit on the ground potential node side in the (M-1)th stage inverter circuit group; In the first stage inverter circuit group, the inverter circuit whose source node of an NMOS is electrically connected to the ground potential node is taken as the first-order inverter circuit, and the inverter circuit whose source node of a PMOS is electrically connected to the power supply potential node is taken as the M-th inverter circuit. The capacitance value of the m-th capacitance element arranged from the 1st to Mth positions in the capacitance element group is the larger of either a capacitance value that is (m-1) times the parasitic capacitance value of a PMOS or a capacitance value that is (M-m) times the parasitic capacitance value of an NMOS. Driver circuit.

4. a first driver circuit comprising the driver circuit according to claim 1 or 3; a second driver circuit comprising the driver circuit according to claim 1 or 3; an amplifying MOS transistor having a drain electrode connected to a power supply potential node and an output node, a gate electrode to which the output voltage from the first driver circuit is applied, and a source electrode to which the output voltage from the second driver circuit is applied, the output voltage being 180 degrees out of phase with the output voltage from the first driver circuit; A driver circuit comprising:

5. A device comprising: a first driver circuit; a second driver circuit; and an amplifying MOS transistor having a drain electrode connected to a power supply potential node and an output node, a gate electrode to which the output voltage from the first driver circuit is applied, and a source electrode to which the output voltage from the second driver circuit is applied as a voltage 180 degrees out of phase with the output voltage from the first driver circuit; The first driver circuit and the second driver circuit each include: a first-stage inverter circuit group including M inverter circuits, each inverter circuit being a natural number of 3 or more, each inverter circuit being composed of a PMOS and an NMOS, each inverter circuit having an input node, an output node, a source node of the PMOS, and a source node of the NMOS, the M inverter circuits being connected in series between a power supply potential node and a ground potential node, with the source node of the PMOS being on the power supply potential node side, and an input signal being input to the input node of each inverter circuit; a capacitance element group including M capacitance elements each corresponding to one of the M inverter circuits in the first stage inverter circuit group, connected between a source node of a PMOS and a source node of an NMOS of the corresponding inverter circuit, and connected in series between the power supply potential node and the ground potential node; a second to (M-1)th inverter circuit group, each of which is composed of a PMOS and an NMOS, and has a plurality of inverter circuits each having an input node, an output node, a source node of the PMOS, and a source node of the NMOS, the number of the inverter circuits being one less than the number of inverter circuits in a previous-stage inverter circuit group, the plurality of inverter circuits being connected in series, and in a state in which no capacitive element is connected between the output nodes of two inverter circuits connected adjacently in the previous-stage inverter circuit group from the ground potential node side of the plurality of inverter circuits, the source node of the PMOS being connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits, the source node of the NMOS being connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits, and the input node being connected to the source node of the PMOS of the inverter circuit in the previous-stage inverter circuit group in the order from the inverter circuit on the ground potential node side in the previous-stage inverter circuit group; an M-th stage inverter circuit which is composed of a PMOS and an NMOS, and has an input node, an output node, a source node of the PMOS, and a source node of the NMOS, and in a state where no capacitive element is connected between the output nodes of two inverter circuits in an M-1-th stage inverter circuit group, the source node of the PMOS is connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits, the source node of the NMOS is connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits, and the input node is connected to the source node of the PMOS of the inverter circuit on the ground potential node side in the M-1-th stage inverter circuit group; Driver circuit.

6. A device comprising: a first driver circuit; a second driver circuit; and an amplifying MOS transistor having a drain electrode connected to a power supply potential node and an output node, a gate electrode to which the output voltage from the first driver circuit is applied, and a source electrode to which the output voltage from the second driver circuit is applied as a voltage 180 degrees out of phase with the output voltage from the first driver circuit; The first driver circuit and the second driver circuit each include: a first-stage inverter circuit group including M inverter circuits, each inverter circuit being a natural number of 3 or more, each inverter circuit being composed of a PMOS and an NMOS, each inverter circuit having an input node, an output node, a source node of the PMOS, and a source node of the NMOS, the M inverter circuits being connected in series between a power supply potential node and a ground potential node, with the source node of the PMOS being on the power supply potential node side, and an input signal being input to the input node of each inverter circuit; a capacitance element group including M capacitance elements, each of which corresponds to one of the M inverter circuits in the first-stage inverter circuit group, connected between a source node of a PMOS and a source node of an NMOS of the corresponding inverter circuit, and connected in series between the power supply potential node and the ground potential node, the length of a short side of each electrode of which is equal to or less than the distance between the source node of the PMOS and the source node of the NMOS of the inverter circuit, and the length of a long side of which is equal to or less than five times the length of the short side; a second to (M-1)th inverter circuit group, each of which is composed of a PMOS and an NMOS, and has a plurality of inverter circuits each having an input node, an output node, a source node of the PMOS, and a source node of the NMOS, the number of which is one less than the number of inverter circuits in the inverter circuit group in the previous stage, the plurality of inverter circuits being connected in series, and each of which is arranged in order from the ground potential node side, with the source node of the PMOS connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits between output nodes of two inverter circuits connected adjacently in order from the ground potential node side in the inverter circuit group in the previous stage, and the source node of the NMOS connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits, the input node being connected to the source node of the PMOS of the inverter circuit in the inverter circuit group in the previous stage, in order from the inverter circuit on the ground potential node side in the inverter circuit group in the previous stage; an M-th stage inverter circuit which is composed of a PMOS and an NMOS, has an input node, an output node, a source node of the PMOS, and a source node of the NMOS, and is connected between output nodes of two inverter circuits in an M-1-th stage inverter circuit group with the source node of the PMOS connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits, and the source node of the NMOS connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits, and has an input node connected to the source node of the PMOS of the inverter circuit on the ground potential node side in the M-1-th stage inverter circuit group; Driver circuit.