Semiconductor device manufacturing method

Abstract

The semiconductor device comprises a semiconductor substrate (12), a channel layer (14) formed on the semiconductor substrate (12), a barrier layer (16) formed on the channel layer (14), and an electrode (18) formed on the barrier layer (16) and having a region diffused into the barrier layer (16) to a depth of at least half the thickness of the barrier layer (16).

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Among semiconductor devices using nitride semiconductors such as gallium nitride (GaN), there are those in which a high electron mobility transistor (HEMT) having a source electrode, a drain electrode, and a gate electrode is formed on a semiconductor layer. In such semiconductor devices, in order to increase the amount of current flowing between the source electrode and the drain electrode, it is important to increase the electron density of the semiconductor layer as well as to reduce the contact resistance between the source electrode and the drain electrode and the semiconductor layer.

[0003] In the semiconductor device described in Patent Document 1, in order to reduce the above-mentioned contact resistance, a heat treatment is performed after the source electrode and the drain electrode are formed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-36586 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, the diffusion of the metal atoms constituting the electrodes is insufficient by heat treatment alone, and the reduction in contact resistance is small. Therefore, in the semiconductor device described in Patent Document 1, it is necessary to remove a part of the electron supply layer by etching to thin the film thickness before forming the source electrode and the drain electrode. In addition, since the electron supply layer is thin, the control of the etching time becomes complicated. Thus, in Patent Document 1, an etching process is required to reduce the contact resistance, which complicates the manufacturing process.

[0006] The present disclosure has been made to solve the above problems, and has an object to provide a semiconductor device and a method for manufacturing a semiconductor device that can reduce contact resistance while suppressing the complication of the manufacturing process. [Means for solving the problem]

[0008] A method for manufacturing a semiconductor device according to the present disclosure includes the steps of forming a channel layer on a semiconductor substrate, and forming a barrier layer on the channel layer. Without etching the barrier layer The method includes the steps of forming an electrode on the barrier layer and thermally annealing the electrode so that the electrode has a region diffused to a depth of at least half the thickness of the barrier layer, the electrode including Nb. Effect of the Invention

[0009] According to the present disclosure, a semiconductor device can be obtained that can reduce contact resistance while suppressing the complication of the manufacturing process. [Brief description of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 1A to 1C are diagrams for explaining a manufacturing method of a semiconductor device according to a first embodiment. [Diagram 3] 1A to 1C are diagrams for explaining a manufacturing method of a semiconductor device according to a first embodiment. [Figure 4] 1A to 1C are diagrams for explaining a manufacturing method of a semiconductor device according to a first embodiment. [Diagram 5] 1 is an electron microscope photograph of a cross section of a conventional semiconductor device. [Figure 6] 2 is an electron microscope photograph of a cross section of the semiconductor device according to the first embodiment. [Figure 7] FIG. 4 is a diagram showing the annealing temperature dependence of the contact resistivity of the semiconductor device according to the first embodiment. [Figure 8] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 9]13A to 13C are diagrams for explaining a method for manufacturing a semiconductor device according to a second embodiment. [Figure 10] 13A to 13C are diagrams for explaining a method for manufacturing a semiconductor device according to a second embodiment. [Figure 11] 13A to 13C are diagrams for explaining a method for manufacturing a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Embodiment 1 A semiconductor device 10 according to a first embodiment is shown in Fig. 1. The semiconductor device 10 is a semiconductor device including a HEMT formed using a nitride semiconductor. Fig. 1 shows a cross section including a source electrode or a drain electrode that constitutes the HEMT.

[0012] The semiconductor device 10 includes a semiconductor substrate 12. The semiconductor substrate 12 is made of, for example, Si.

[0013] A channel layer 14 is formed on a semiconductor substrate 12. The channel layer 14 is made of, for example, GaN.

[0014] A barrier layer 16 is formed on the channel layer 14. The barrier layer 16 is made of, for example, AlGaN. A high concentration of two-dimensional electron gas is formed at the boundary between the channel layer 14 and the barrier layer 16.

[0015] An electrode 18 is formed on the barrier layer 16. The electrode 18 is a source electrode or a drain electrode. A lower portion of the electrode 18 is diffused into the barrier layer 16 to a depth of at least half the thickness of the barrier layer 16. It is not necessary that the entire region of the electrode 18 is diffused into the barrier layer 16 to a depth of at least half the thickness of the barrier layer 16 when viewed in a direction perpendicular to the semiconductor substrate 12, but it is sufficient that a portion of the electrode 18 is diffused into the barrier layer 16 to a depth of at least half the thickness of the barrier layer 16.

[0016] The electrode 18 has a first alloy layer 20 and a second alloy layer 22 laminated from the side closer to the semiconductor substrate 12. The first alloy layer 20 has a region diffused into the barrier layer 16 to a depth of more than half the thickness of the barrier layer 16. The first alloy layer 20 contains, for example, Ga, N, Ta, Al, Au, and Nb, and further contains any one of Ti, Ni, Mo, and Pt. The second alloy layer contains, for example, Al, Au, and Nb, and further contains any one of Ti, Ni, Mo, and Pt. The electrode 18 may have more than the above two alloy layers laminated, as long as it has a multilayer structure in which at least the first alloy layer 20 and the second alloy layer 22 are laminated from the side closer to the semiconductor substrate 12.

[0017] A method for manufacturing the semiconductor device 10 according to the first embodiment will be described. First, as shown in Fig. 2, a channel layer 14 is formed on a semiconductor substrate 12. The channel layer 14 is formed, for example, by a Metal Organic Chemical Vapor Deposition (MOCVD) method. Next, as shown in Fig. 3, a barrier layer 16 is formed on the channel layer 14. The barrier layer 16 is also formed, for example, by a MOCVD method.

[0018] Next, as shown in Fig. 4, an electrode 18 is formed on the barrier layer 16. The electrode 18 thus formed is, for example, a laminate of Ta / Al / Ni / Au / Nb from the bottom up. To form the electrode 18, a resist is formed on the barrier layer 16. Next, the materials for the electrode 18 are sequentially deposited by, for example, an electron beam deposition method. Next, the resist is removed by a lift-off method.

[0019] Next, a first alloy layer 20 and a second alloy layer 22 are formed by performing thermal annealing, thereby forming the semiconductor device 10 shown in FIG. 1. Rapid thermal annealing, for example, can be used as the thermal annealing method. The thermal annealing is performed in a nitrogen atmosphere at a temperature range of 830 to 900°C. During the thermal annealing, the electrode 18 may be in a bare state, but the thermal annealing may also be performed after forming an insulating film such as SiN by chemical vapor deposition, for example.

[0020] Cross-sectional photographs of a conventional semiconductor device and the semiconductor device 10 according to the first embodiment are compared. FIG. 5 is a photograph of the cross section of the conventional semiconductor device taken using an electron microscope. As can be seen from FIG. 5, the electrode does not diffuse deep into the barrier layer made of AlGaN. In the conventional semiconductor device, Ta / Al / Ni / Au are laminated as electrodes, and then thermal annealing is performed. In the conventional semiconductor device, alloying occurs due to thermal annealing, but only phases such as TaAlAuNi, AlNi, and AlAu are formed, and the degree of alloy diffusion is small.

[0021] FIG. 6 shows an electron microscope photograph of a cross section of the semiconductor device 10 according to the first embodiment. The semiconductor device 10 according to the first embodiment is obtained by stacking Ta / Al / Ni / Au / Nb as an electrode and then performing thermal annealing in a temperature range of 830 to 900° C. As shown in FIG. 6, the semiconductor device 10 has a large degree of diffusion of the electrode 18 compared to the conventional semiconductor device. Specifically, a region in the electrode that is diffused to more than half the depth of the barrier layer, which was not observed in the conventional semiconductor device, is observed. When thermal annealing is performed in the semiconductor device 10 according to the first embodiment, AlAuNb is formed on the upper layer side of the electrode at about 800° C. during the temperature rise, and TaAlAuNi is formed on the lower layer side. When the annealing temperature reaches at least 830° C. or more, Nb on the upper layer side diffuses to the lower layer side, and in the process, the TaAlAuNbNi layer diffuses deep into the barrier layer. Due to this action, a region in the electrode that is diffused to more than half the depth of the barrier layer exists.

[0022] 7 is a graph showing the results of measuring the contact resistivity of the electrode 18 in the semiconductor device 10 according to the first embodiment. The horizontal axis represents the annealing temperature (° C.), and the vertical axis represents the contact resistivity of the electrode 18 (Ωcm 2 ) It can be seen from this figure that the contact resistivity is lower when the annealing temperature is 830 to 900° C. than when it is 600 to 800° C. In this way, if the electrode contains Nb and thermal annealing is performed at an annealing temperature of 830 to 900° C., the electrode 18 diffuses into the barrier layer 16, and the contact resistivity can be reduced.

[0023] As described above, in the semiconductor device 10 according to the first embodiment, the first alloy layer 20 has a region diffused into the barrier layer 16 to a depth of at least half the thickness of the barrier layer 16, and therefore the contact resistance of the electrode 18 is low. Furthermore, the electrode 18 having low contact resistance can be obtained simply by carrying out thermal annealing, which makes it possible to suppress the complication of the manufacturing process.

[0024] Embodiment 2 The second embodiment is similar to the first embodiment, but differs in that the center of the electrode does not diffuse into the barrier layer to a depth of half the thickness of the barrier layer when viewed from a direction perpendicular to the semiconductor substrate.

[0025] 8 shows a cross-sectional view of a semiconductor device 20 according to the second embodiment. In an electrode 38 of the semiconductor device 20, a laminated structure of a first alloy layer 40 and a second alloy layer 42 similar to that of the first embodiment is formed in a peripheral portion 48 located on the periphery when viewed from a direction perpendicular to the semiconductor substrate 12, and at least a portion of the peripheral portion 48 is diffused into the barrier layer 16 to a depth equal to or greater than half the thickness of the barrier layer 16.

[0026] On the other hand, in a central portion 46 which is located in the center when viewed in a direction perpendicular to the semiconductor substrate 12, the alloy particles do not diffuse into the barrier layer 36 to a depth equal to or greater than half the thickness of the barrier layer 36. In the central portion 46, a laminated structure consisting of the first alloy layer 40 and the second alloy layer 42 may or may not be formed.

[0027] A method for manufacturing the semiconductor device 20 according to the second embodiment will be described. The method for manufacturing the semiconductor device 20 is the same as that of the first embodiment up to the step of forming the electrode as shown in FIG. 4. The layer structure of the electrode 38 is the same as that of the first embodiment, and for example, Ta / Al / Ni / Au / Nb are laminated. After the electrode 38 shown in FIG. 4 is formed, a resist 44 is formed to cover the peripheral portion 48 of the electrode 38 as shown in FIG. 9. Thereafter, as shown in FIG. 10, Nb in the center portion 46 of the electrode 38 is etched by reactive dry etching using a fluorine-based gas such as SF6 or CF4. At this time, Nb may be completely removed or may be partially left. Next, as shown in FIG. 11, the resist 44 is removed. Removal methods include a dry ashing method and a method using a resist removal chemical.

[0028] Next, thermal annealing is performed in the same manner as in the first embodiment to obtain the semiconductor device 20 shown in Fig. 8. By the thermal annealing, a layer structure consisting of the first alloy layer 40 and the second alloy layer 42 is obtained in the peripheral portion 48 containing a sufficient amount of Nb, and the first alloy layer 40 diffuses into the barrier layer 36, thereby reducing the contact resistance of the electrode 38.

[0029] By etching the Nb in the central portion 46 in this manner, it is possible to prevent Al from melting and protruding from the electrode 38. Since the melting point of Al is approximately 660°C, there is a concern that Al in the electrode 38 may melt and protrude from the side surface of the electrode 38 when thermal annealing is performed at 830 to 900°C, depending on the layer structure of the electrode 38. On the other hand, by etching the Nb in the electrode 38 as in this embodiment, Al is more likely to move to the central portion 46 where there is less Nb, and thus the protrusion of Al is prevented.

[0030] Furthermore, since the electrode 38 is sufficiently thicker than the barrier layer 36, precise control of the etching time is not required during etching, and the manufacturing process can be prevented from becoming complicated. [Explanation of symbols]

[0031] 10, 20 semiconductor device, 12 semiconductor substrate, 14 channel layer, 16 barrier layer, 18 electrode, 20, 40 first alloy layer, 22, 42 second alloy layer, 46 central portion.

Claims

1. a semiconductor substrate; a channel layer formed on the semiconductor substrate; a barrier layer formed on the channel layer; an electrode formed on the barrier layer and having a region diffused into the barrier layer to a depth of at least half the thickness of the barrier layer; Equipped with The semiconductor device wherein the electrode contains Nb.

2. the electrode has a multilayer structure in which at least a first alloy layer and a second alloy layer are stacked from the side closest to the semiconductor substrate, The first alloy layer has a region diffused into the barrier layer to a depth of at least half the thickness of the barrier layer. The semiconductor device according to claim 1 .

3. the channel layer is made of GaN; the first alloy layer contains Ga, N, Ta, Al, Au, and Nb, and further contains at least one of Ti, Ni, Mo, and Pt; The second alloy layer contains Al, Au, and Nb, and further contains at least one of Ti, Ni, Mo, and Pt. The semiconductor device according to claim 2 .

4. The electrode has, in a central portion thereof, a region that has not diffused into the barrier layer to a depth equal to or greater than half the thickness of the barrier layer when viewed from a direction perpendicular to the semiconductor substrate. The semiconductor device according to claim 1 .

5. forming a channel layer on a semiconductor substrate; forming a barrier layer on the channel layer; forming an electrode on the barrier layer; a thermal annealing step of thermally annealing the electrode so that the electrode has a region diffused to a depth of at least half the thickness of the barrier layer; Equipped with The method for manufacturing a semiconductor device, wherein the electrode contains Nb.

6. The thermal annealing step is carried out at a temperature ranging from 830 to 900°C. The method for manufacturing a semiconductor device according to claim 5 .

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