TDC including multiplexer reconfiguring input signal, and FPGA including same

Abstract

Disclosed are: a plurality of TDCs, each TDC configured to determine a generation time difference between two signals and including a pair of input nodes for receiving inputs of the two signals; and an FPGA programmed to include a multiplexer configured to selectively connect a plurality of input signals to each of the pair of input nodes of the TDC.

Description

A TDC including a multiplexer that reconstructs an input signal and an FPGA including the same

[0001] The present invention relates to a technology related to FPGA, and more particularly, to an FPGA technology including a TDC including a multiplexer that reconstructs an input signal.

[0002] A time-to-digital converter (TDC) is a device or circuit that converts the time interval between two events into a digital output. TDCs play a crucial role in many scientific and industrial applications that require precise timing measurements. They are widely used in applications requiring high-precision timing measurements, such as time-of-flight (TOF) measurements in particle physics, medical imaging, radar systems, and laser ranging. A TDC operates by measuring the time difference between two events, such as the arrival of a signal at two points in a circuit, or the transmission and reflection of a signal. Typically, a counter is used to count the number of clock cycles between the two events. The count is then converted into a digital output representing the time interval. There are various types of TDCs, such as leading-edge TDCs, trailing-edge TDCs, and interpolating TDCs. A leading-edge TDC measures the time between the leading edge of a start signal and the leading edge of a stop signal, while a trailing-edge TDC measures the time between the trailing edge of a start signal and the trailing edge of a stop signal. Interpolation TDC increases the resolution of TDC by using interpolation techniques to estimate the time interval between two clock cycles.

[0003] TDCs include Application-Specific Integrated Circuits (ASICs), Microcontrollers (MCUs), Programmable System-on-Chip (PSoC), Digital Signal Processors (DSPs), Field Programmable Analog Arrays (FPAAs), Time-to-Amplitude Converters (TACs), Time-to-Frequency Converters (TFCs), and FPGAs (Field Programmable Analog Arrays). It can be implemented using a Programmable Gate Array, etc.

[0004] Implementing TDCs using FPGAs can present the following challenges. First, the resources provided in FPGAs, including logic cells, lookup tables (LUTs), and routing channels, are limited, which can limit the resolution and accuracy of TDCs implemented in FPGAs. Second, at high clock frequencies, jitter can introduce errors into TDC measurements. Jitter refers to variations in the timing of clock signals caused by factors such as noise and temperature. Third, factors such as voltage drops, temperature variations, and manufacturing process differences can cause TDCs to exhibit nonlinear behavior, resulting in errors in TDC measurements at high resolutions. Fourth, FPGAs incur delays through signal processing and routing, which can introduce errors into TDC measurements for small time intervals.

[0005] In FPGAs, routing refers to the process of connecting programmable logic elements (such as lookup tables, flip-flops, and multiplexers) on the chip to form the desired logic circuit. Routing determines how signals propagate through the chip and can significantly impact the overall performance of the design. One major factor that can cause delays in FPGA routing is the capacitance of the interconnect wires connecting the logic elements. As the number of logic elements and the distance between them increase, the capacitance of the interconnect wires also increases. This capacitance delays signal propagation along the wires, increasing the overall design delay. Another factor that can cause delays in FPGA routing is routing congestion. Routing congestion occurs when an FPGA's routing resources are limited and the number of logic elements to be connected is large. Routing congestion increases the distance between logic elements, which increases the capacitance of the interconnect wires, which can lead to delays.

[0006] A tempered delay line is a digital signal processing technique used to implement thermometer codes. In thermometer code, each bit of a binary number is represented by a separate signal line, with the line corresponding to the "on" bit indicating the value of the binary number. To implement a thermometer code using a tempered delay line, a series of delay elements are used to represent each bit. The input binary number is converted into a series of pulses, each representing one bit of the binary number. These pulses are delayed by a different amount depending on the position of each bit before being fed to the tempered delay line. At the output of the tempered delay line, each output signal line represents a bit of the binary number, with the "on" line indicating the value of the binary number. This technique is commonly used in digital-to-analog converters (DACs) to convert digital signals to analog signals.

[0007] In FPGAs, a carry chain block is a hardware block used to perform fast arithmetic operations, particularly additions and subtractions. In digital circuits, adding and subtracting multi-bit numbers requires calculating the carry bit, which can become a bottleneck in high-speed operations. The carry chain block efficiently handles this carry bit calculation, enabling faster and more efficient arithmetic operations. A carry chain block typically consists of a series of full adder circuits interconnected in a specific manner to form a carry chain. Each full adder circuit computes one bit of its output and the carry bit, which is then passed to the next stage in the chain. By chaining these full adder circuits, the carry bit propagates through the chain in one clock cycle, enabling fast additions and subtractions of multi-bit numbers. In addition to providing fast arithmetic operations, the carry chain block can also be used to implement counters and other sequential circuits that require carry bit calculation.

[0008] The timing report tool is a software tool used to analyze the timing performance of designs implemented in FPGAs. It generates a report providing information about the design's timing characteristics. This report includes information about the design's timing characteristics, including data path delay, critical path, setup and hold times, clock skew, and maximum operating frequency. Data path delay is the time it takes for a data signal to propagate through the FPGA's logic elements.

[0009] A multiplexer, or "MUX," is an electronic circuit that selects one of several input signals and routes the selected input to an output line. The input-output structure of a multiplexer typically consists of several input lines, a select line, and one or more output lines. The number of input lines corresponds to the number of input signals the multiplexer can select, and the select line determines the selected input signal. For example, a 4-to-1 multiplexer has four input lines, one output line, and a select line that determines which of the four input signals is sent to the output. The select line can be controlled by a binary code representing the selected input line. Multiplexers are often used in digital systems to reduce the number of wires required to transmit data and control signals. They can be used to implement functions such as data selectors, memory address decoders, and bus allocation circuits.

[0010] The present invention aims to provide a configuration of an FPGA that can be used for multiple purposes by combining multiple TDCs.

[0011] According to one aspect of the present invention, an FPGA provided may be programmed to include a plurality of Time to Digital Converters (TDCs), each of the TDCs being configured to determine an occurrence time difference between two signals and having a pair of input nodes for receiving the two signals; and a multiplexer being configured to selectively connect a plurality of input signals to the pair of input nodes of each of the TDCs.

[0012] At this time, the plurality of input signals include a first start signal and a first end signal, and the multiplexer is configured to commonly supply the first start signal and the first end signal to the plurality of TDCs, and may be programmed to further include a correction operation unit that determines an average value of a plurality of occurrence time differences output by the plurality of TDCs with respect to the first start signal and the first end signal as a corrected occurrence time difference between the first start signal and the first end signal.

[0013] At this time, the plurality of input signals include a first start signal and a first end signal, and each of the TDCs includes a first delay line part into which an input pulse having a width equal to the occurrence time difference between the first start signal and the first end signal is input; a code conversion part that converts and outputs the order of elements of a thermometer code output by the first delay line part; and an operation part that determines the occurrence time difference determined by each of the TDCs using the conversion code output by the code conversion part; wherein the conversion code is a code that arranges the order of elements of the thermometer code according to a predetermined standard, and the predetermined standard may be a data path delay from an output node of the first input pulse to output nodes of each of the plurality of flip-flops included in the first delay line part.

[0014] Alternatively, the plurality of input signals include a first start signal and a first end signal, and each of the TDCs includes: a plurality of delay line parts to which an input pulse having a width equal to the occurrence time difference between the first start signal and the first end signal is input; a code conversion part that merges a plurality of thermometer codes output by the plurality of delay line parts and outputs one conversion code; and an operation part that determines the occurrence time difference determined by each of the TDCs using the conversion code; wherein the conversion code is obtained by arranging the order of elements of the plurality of thermometer codes according to a predetermined standard, and the predetermined standard may be a data path delay from an output node of the first input pulse to output nodes of each of the plurality of flip-flops in the plurality of delay line parts.

[0015] Alternatively, the plurality of input signals may include a first start signal, a first end signal, and a second end signal, and the multiplexer may be configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and to supply the first start signal and the second end signal to a second TDC among the plurality of TDCs, and to provide a first time difference, which is an occurrence time difference between the first start signal and the first end signal determined by the first TDC, to a circuit connected to the first TDC, and to provide a second time difference, which is an occurrence time difference between the first start signal and the second end signal determined by the second TDC, to a circuit connected to the second TDC.

[0016] Alternatively, the plurality of input signals may include a first start signal, a second start signal, and a first end signal, and the multiplexer may be configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and to supply the second start signal and the first end signal to a second TDC among the plurality of TDCs, and to provide a first time difference, which is an occurrence time difference between the first start signal and the first end signal determined by the first TDC, to a circuit connected to the first TDC, and to provide a second time difference, which is an occurrence time difference between the second start signal and the first end signal determined by the second TDC, to a circuit connected to the second TDC.

[0017] According to one aspect of the present invention, a nonvolatile recording medium readable by an electronic device may be provided, wherein a binary file including configuration data for programming the FPGA to implement a digital circuit including a plurality of TDCs (Time to Digital Converters), each of the TDCs being configured to determine a time difference between two signals and having a pair of input nodes for receiving the two signals; and a multiplexer being configured to selectively connect a plurality of input signals to the pair of input nodes of each of the TDCs may be recorded.

[0018] At this time, the plurality of input signals include a first start signal and a first end signal, the multiplexer is configured to commonly supply the first start signal and the first end signal to the plurality of TDCs, and the digital circuit may further include a correction operation unit that determines an average value of a plurality of occurrence time differences output by the plurality of TDCs with respect to the first start signal and the first end signal as a corrected occurrence time difference between the first start signal and the first end signal.

[0019] At this time, the plurality of input signals include a first start signal and a first end signal, and each of the TDCs includes a first delay line part into which an input pulse having a width equal to the occurrence time difference between the first start signal and the first end signal is input; a code conversion part that converts and outputs the order of elements of a thermometer code output by the first delay line part; and an operation part that determines the occurrence time difference determined by each of the TDCs using the conversion code output by the code conversion part; wherein the conversion code is a code that arranges the order of elements of the thermometer code according to a predetermined standard, and the predetermined standard may be characterized in that the data path delay from the output node of the first input pulse to the output nodes of each of the plurality of flip-flops included in the first delay line part.

[0020] Alternatively, the plurality of input signals may include a first start signal and a first end signal, and each of the TDCs may include: a plurality of delay line parts to which an input pulse having a width equal to the occurrence time difference between the first start signal and the first end signal is input; a code conversion part that merges a plurality of thermometer codes output by the plurality of delay line parts and outputs one conversion code; and an operation part that determines the occurrence time difference determined by each of the TDCs using the conversion code; wherein the conversion code is a sequence of elements of the plurality of thermometer codes arranged according to a predetermined standard, and the predetermined standard may be characterized by being a data path delay from an output node of the first input pulse to output nodes of each of the plurality of flip-flops in the plurality of delay line parts.

[0021] Alternatively, the plurality of input signals may include a first start signal, a first end signal, and a second end signal, and the multiplexer may be configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and to supply the first start signal and the second end signal to a second TDC among the plurality of TDCs, and may be configured to provide a first time difference, which is an occurrence time difference between the first start signal and the first end signal determined by the first TDC, to a circuit connected to the first TDC, and to provide a second time difference, which is an occurrence time difference between the first start signal and the second end signal determined by the second TDC, to a circuit connected to the second TDC.

[0022] Alternatively, the plurality of input signals may include a first start signal, a second start signal, and a first end signal, and the multiplexer may be configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and to supply the second start signal and the first end signal to a second TDC among the plurality of TDCs, and may be configured to provide a first time difference, which is an occurrence time difference between the first start signal and the first end signal determined by the first TDC, to a circuit connected to the first TDC, and to provide a second time difference, which is an occurrence time difference between the second start signal and the first end signal determined by the second TDC, to a circuit connected to the second TDC.

[0023] A TDC system provided according to one aspect of the present invention may include a PCB board (600) including the FPGA (1) described above; and a computing device (700) that obtains the occurrence time difference from the PCB board.

[0024] According to the present invention, it is possible to provide a configuration of an FPGA that enables a plurality of TDCs to be combined for multi-purpose use.

[0025] Figure 1 illustrates a configuration diagram of an FPGA according to one embodiment of the present invention.

[0026] FIG. 2 is a drawing for explaining an input pulse input to a first delay line part according to one embodiment of the present invention.

[0027] Figure 3 illustrates the configuration of a first delay line part according to one embodiment of the present invention.

[0028] Figure 4 is a drawing for explaining the indexes of the buffers of Figure 3.

[0029] FIG. 5 is a table illustrating data path delay according to one embodiment of the present invention.

[0030] FIG. 6a and FIG. 6b illustrate a parallel configuration of multiple delay line parts according to one embodiment of the present invention.

[0031] FIG. 7a illustrates the configuration of the first delay line part and the second delay line part of FIG. 6b, and FIG. 7b is for explaining the operation of the code conversion part when two delay line parts are used according to one embodiment of the present invention.

[0032] Figure 8 is a graph showing delay depending on whether a code conversion part is applied according to one embodiment of the present invention.

[0033] FIG. 9 is a drawing for explaining the arrangement criteria of flip-flop output values ​​and the increase value of the number of taps in FIG. 8 depending on whether a code conversion part is applied according to one embodiment of the present invention.

[0034] FIG. 10 is a drawing for explaining a method of providing input pulses for multiple TDCs using multiple input signals according to one embodiment of the present invention.

[0035] Figure 11 shows the input signals and the input pulse of the TDC in Figure 10.

[0036] FIG. 12 is a graph illustrating jitter verification using TDC according to one embodiment of the present invention.

[0037] FIG. 13 is a drawing for explaining the operation of a multiplexer according to another embodiment of the present invention.

[0038] Figure 14 shows the input pulse of the TDC according to the signals input to each TDC of Figure 13.

[0039] FIG. 15 is a drawing for explaining the operation of a multiplexer according to another embodiment of the present invention.

[0040] Figure 16 shows the input pulse of the TDC according to the signals input to each TDC of Figure 15.

[0041] FIG. 17 is a block diagram of a TDC system provided according to one embodiment of the present invention.

[0042] Hereinafter, embodiments of the present invention will be described with reference to the attached drawings. However, the present invention is not limited to the embodiments described herein and may be implemented in various other forms. The terminology used herein is intended to aid understanding of the embodiments and is not intended to limit the scope of the present invention. Furthermore, the singular forms used below also include the plural forms, unless the context clearly indicates otherwise.

[0043] Figure 1 illustrates a configuration diagram of an FPGA according to one embodiment of the present invention.

[0044] FIG. 2 is a drawing for explaining an input pulse input to a first delay line part according to one embodiment of the present invention.

[0045] Hereinafter, the description will be made with reference to FIG. 1 and FIG. 2 together.

[0046] FPGA (1) may include an input signal generation part (10), a first delay line part (20), a code conversion part (30), a clock pulse counter part (40), a priority encoder part (50), and an operation part (60).

[0047] Specifically, the configurations of the FPGA (1) described above may be configurations of a TDC (Time to Digital converter).

[0048] As shown in Fig. 2, the input signal generation part (10) can generate an input pulse (P1) having a width equal to the time difference (T) between the rising edge (E1) of a given start signal (S1) and the rising edge (E2) of a given end signal (S2). The input signal generation part (10) can be composed of logic gates necessary for the above generation.

[0049] The first delay line part (20) can receive an input pulse (P1) having a width equal to the time difference (T) between the occurrence of a start signal (S1) and an end signal (S2). In addition, the first delay line part (20) can output a thermometer code (O1). At this time, the thermometer code is a value of, for example, 8 bits, composed of output values ​​of flip-flops included in the first delay line part (20), and the output value of each flip-flop can be referred to as an element of the thermometer code.

[0050] Figure 3 illustrates the configuration of a first delay line part according to one embodiment of the present invention.

[0051] Figure 4 is a drawing for explaining the indexes of the buffers of Figure 3.

[0052] The first delay line part (20) may include a delay line (D_L) including a plurality of buffers (delay elements, delay components) (B) and D-flip-flops (FF) tapped to the output terminals of each buffer (B) of the delay line.

[0053] Multiple buffers can be connected in a cascade delay manner. That is, multiple buffers can be arranged in the order in which the input pulses (P1) flow.

[0054] The waveform (Signal) of the input pulse (P1) of Fig. 3 can be output with a predetermined delay from the output terminal of each buffer (B). That is, the output value of the first buffer (B1) is output with a predetermined delay from the output terminal of the first buffer (B1), and the output terminal of the first buffer (B1) is connected to the input terminal of the second buffer (B2). The output value (e.g., '1') of the first buffer (B1) can also be input to the first flip-flop (FF1).

[0055] At this time, a data path delay may occur between each buffer (B) and through the flip-flop (FF). For example, a delay of d1 may occur until the input value ('1') of the first buffer (B1) is transmitted to the second buffer (B2), and a delay of d11 may occur until the output value ('1') of the first buffer (B1) is transmitted to the first flip-flop (FF1). Similarly, a delay may occur whenever data is transmitted from the previous buffer to the next buffer, and a delay may occur whenever data is transmitted from any buffer to a flip-flop connected to any buffer.

[0056] FIG. 4 is a diagram for explaining an index of a buffer according to one embodiment of the present invention.

[0057] Each field in the table in Figure 4 represents the buffer name, index, and output value of the buffer.

[0058] Each buffer may be assigned an index that defines the order of each buffer. For example, the first buffer (B1) may be assigned an index of '1', the second buffer (B2) may be assigned an index of '2', and similarly, the eighth buffer (B8) may be assigned an index of '8'. In this way, when each buffer (B) is arranged according to the order in which the input pulse (P1) flows and the indexes are arranged according to that order, for example, 1000 buffers may each be assigned an index of 1 to 1000.

[0059] FIG. 5 is a table illustrating data path delay according to one embodiment of the present invention.

[0060] Referring to FIGS. 1 and 5, the code conversion part (30) can convert and output the order of elements (e.g., 1, 2, 3, 4, 5, 6, 7, 8) of the thermometer code (O1) (e.g., 11100000) output from the first delay line part (20). At this time, the code (e.g., 11010000) (the order of the indexes of the corresponding buffer is 1, 2, 4, 5, 3, 6, 7, 8) output by the code conversion part (30) can be referred to as a 'conversion code (CO1)'.

[0061] The conversion code (CO1) output by the code conversion part (30) may be a sequence of elements of the thermometer code (O1) arranged according to a predetermined standard. In this case, the predetermined standard may be the data path delay from the output node (N1) of the input pulse (P1) to the output nodes (N2) of each of the plurality of flip-flops (FF) included in the first delay line part (20). This will be described in detail with reference to Fig. 5.

[0062] Each field in the table presented in Fig. 5 may represent a buffer index number, a first delay value, a second delay value, and a sum (rank). The rank may represent a ranking of all sums. The buffer with the smallest sum may have the first rank, while the buffer with the highest sum may have the last rank. Alternatively, the reverse may be true in other embodiments.

[0063] As described above in Fig. 3, the above sum value may mean the time taken for data to be transmitted from the node (N1) where the input pulse (P1) is output to an arbitrary flip-flop (e.g., FF4).

[0064] A first delay, which is the time it takes for an input value of an arbitrary buffer to be transmitted to another buffer connected to the arbitrary buffer, and a second delay, which is the time it takes for an output value of the arbitrary buffer to be transmitted to an input of a flip-flop connected to the arbitrary buffer, may occur.

[0065] At this time, the value obtained by adding the value of the first delay and the value of the second delay for each buffer can be referred to as the data path delay.

[0066] Referring to FIGS. 3 and 5 together, when the indexes of each buffer are listed in order, the order of the sum of the values ​​of the first delay and the second delay may be different from the order of the index numbers of each buffer. For example, in the case of the third buffer, since the buffer array order is 3rd, the index number may be '3', but the order of the sum may be '5'. Looking at it in detail, in order for data to be transmitted to the third flip-flop (FF3), it passes through the first buffer (B1), the second buffer, and the third buffer. At this time, a predetermined delay (d1, d2, d3) occurs each time it passes through the first buffer (B1), the second buffer (B2), and the third buffer (B3), and a delay (d13) may also occur until the data output from the third buffer (B3) is output as the output value of the third flip-flop (FF3). That is, the delay until data is transmitted from the output node (N1) of the input pulse (P1) to the output node (N2, N23) of the third flip-flop (FF3) may be the sum of d1, d2, d3, and d13.

[0067] In this way, the delay (i.e., the sum value) until data is transmitted to the output node of each flip-flop (FF3) can be calculated.

[0068] For example, in this embodiment, the buffer index for the third flip-flop (FF3) is 3, and the buffer index for the fourth flip-flop (FF4) is 4. That is, the fourth flip-flop (FF3) must pass through one more buffer than the third flip-flop (FF4), but despite this, the sum of the delays to the output node of the third flip-flop, which has a buffer index of 3, may be greater.

[0069] The code conversion part (30) can convert the order of elements of the thermometer code (O1) based on the calculated delay (sum value) (e.g., from the smallest sum value).

[0070] The conversion code (CO1) output by the code conversion part (30) can be provided to the priority encoder part (50).

[0071] The priority encoder part (50) can digitize a long thermometer code. For example, the priority encoder part (50) can convert a 5200-bit thermometer code into a 13-bit thermometer code. For example, if the number of buffers (delay elements) (B) described above in FIG. 3 and the number of flip-flops (FFs) connected to the buffers are 5200, 5200 consecutive binary number sequences are output, which can be expressed as 13-bit binary numbers.

[0072] That is, the priority encoder part (50) can express the first thermometer code (TC1) of 5200 bits and the second thermometer code (TC2) as a 13-bit binary number as the time-dependent output value (CO1) of the code conversion part (30).

[0073] Referring to FIG. 2, the first thermometer code (TC1) may be a code output by the code conversion part (30) in relation to the rising edge of the input pulse (P1) at the time of the rising edge (E4) of the clock pulse (CK2) that first occurs after the rising edge (E1) of the input pulse (P1) among the generated clock pulses (CK). The first thermometer code (TC1) expressed in 13 bits may be provided as an input to the operation part (60).

[0074] And the second thermometer code (TC2) may be a code output by the code conversion part (30) in relation to the falling edge (E2) of the input pulse (P1) at the time of the rising edge (E6) of the clock pulse (CK4) that first occurs after the falling edge (E2) of the input pulse (P1) among the generated clock pulses (CK). The second thermometer code (TC2) expressed in 13 bits may be provided as an input to the operation part (60).

[0075] At this time, the time period of the first thermometer code (TC1) and the time period of the second thermometer code (TC2) may be smaller than the period of the clock pulse (CK).

[0076] Referring again to FIGS. 1 and 2, the clock pulse counter part (40) can receive an input pulse (P1) from the input signal generation part (10).

[0077] The clock pulse counter part (40) can count the number of clock pulses (CK) generated during the maintenance period (T) of the input pulse (P1). For example, in Fig. 2, since there are two rising edges of the clock pulses generated during the period when the input pulse (P1) is in the ON state, such as edges (E4, E5), the counted value can be two.

[0078] The output value (Coarse count) of the clock pulse counter part (40), i.e. the counted value, can be provided to the operation part (60).

[0079] Referring to FIGS. 1 and 2, the operation part (60) can determine the value of the occurrence time difference using the first thermometer code (TC1), the second thermometer code (TC2), and the number of counted clock pulses. For example, the occurrence time difference can be 2*Period+TC1-TC2.

[0080] FIG. 6a and FIG. 6b illustrate a parallel configuration of multiple delay line parts according to one embodiment of the present invention.

[0081] As shown in Fig. 6a, two or more delay line parts (20) may be connected in parallel. At this time, the input pulse (P1) output from the input signal generation part (10) may be input to the first delay line part (21), the second delay line part (22), the third delay line part (23), and the fourth delay line part (24), respectively. In addition, the first thermometer code (O1), the second thermometer code (O2), the third thermometer code (O3), and the fourth thermometer code (O4) output from the first delay line part (21), the second delay line part (22), the third delay line part (23), and the fourth delay line part (24) may be input to the code conversion part (30).

[0082] In another embodiment, as shown in Fig. 6b, it can be assumed that two delay line parts (20) are connected in parallel.

[0083] For example, an input pulse (P1) output from an input signal generating part (10) can be provided along a first path (path1) in which the output terminal of the input signal generating part (10) and the input terminal of the first delay line part (21) are connected to each other, and a second path (path2) in which the output terminal of the input signal generating part (10) and the input terminal of the second delay line part (22) are connected to each other.

[0084] At this time, the time at which the input pulse (P1) output from the input signal generation part (10) reaches the input terminal of the first delay line part (21) and the input terminal of the second delay line part (22) may be different. This is because there is an input delay due to the difference in length between the first path (path1) and the second path (path). In the embodiment of Fig. 6b, since the length of the first path (path1) is shorter than the length of the second path (path2), it can be seen that the input time interval of the input pulse (path1) through the first path (path1) is shorter than the input time interval of the input pulse (path2) through the second path (path2).

[0085] FIG. 7a illustrates the configuration of the first delay line part and the second delay line part of FIG. 6b, and FIG. 7b is for explaining the operation of the code conversion part when two delay line parts are used according to one embodiment of the present invention.

[0086] For convenience of explanation in Fig. 7a, each delay line part is illustrated as containing four buffers and four flip-flops.

[0087] In Fig. 7b, each field of the table may represent a delay line part number, a buffer index number, a first delay value, a second delay value, a first sum value (first priority), and a first sum value (overall ranking). At this time, the first priority may represent a rank for each sum value for the buffer index of the buffers in each delay line part. And the overall ranking may represent a rank for each sum value for the buffer index of all buffers in the first delay line part and the second delay line part. At this time, in the first priority and the overall ranking, the buffer with the smallest sum value may have the first rank and the buffer with the highest sum value may have the last rank. Or, in another embodiment, the opposite is also possible. The method for obtaining the sum value may be the same as described in Fig. 5.

[0088] The code conversion part (30) may be configured to generate one conversion code by merging the elements of the first set (e.g., {(D1, 1), (D2, 2), (D3, 3), (D4, 4)}) in which the sum of the elements of the thermometer code output by the first delay line part (21) and the buffer index pairs are listed in descending order of sum values, and the elements of the second set (e.g., {(D5, 5), (D6, 6), (D7, 7), (D8, 8)}) in which the sum of the elements of the thermometer code output by the second delay line part (22) and the index pairs are listed in descending order of sum values.

[0089] That is, each element of the first set and each element of the second set can be sorted in order of lowest sum value.

[0090] For example, in the first delay line part (21), the output value based on the buffer index may be {1, 2, 3, 4}, and in the second delay line part (22), the output value based on the buffer index may be {5, 6, 7, 8}. In addition, in the embodiments of FIGS. 6b and 7a, the delay (d1) may be smaller than the delay (d5). Therefore, the sorted order may be (D1, 1), (D2, 2), (D5, 5), (D3, 3), (D6, 6), (D4, 4), (D7, 7), (D8, 8). The output values ​​of the flip-flops for each buffer index may be sorted in the sorted order. For example, the sorted values ​​(buffer indexes) may be 0(1), 0(2), 1(4), 1(6), 1(3), 1(5), 0(7), 0(8).

[0091] As described above, when multiple delay line parts (20) are used, slightly different input delays may be achieved depending on the arrangement. Fig. 8, described below, shows the delays according to the arrangement when multiple delay line parts are used.

[0092] Figure 8 is a graph showing delay depending on whether a code conversion part is applied according to one embodiment of the present invention.

[0093] FIG. 9 is a drawing for explaining the arrangement criteria of flip-flop output values ​​and the increase value of the number of taps in FIG. 8 depending on whether a code conversion part is applied according to one embodiment of the present invention.

[0094] Figure 8 (a) shows a delay graph according to the number of taps in a state where the code conversion part (30) is not applied, and Figure 8 (b) shows a delay graph according to the number of taps in a state where the code conversion part (30) is applied.

[0095] The fields in the table of Fig. 9 include the arrangement order of the flip-flop output values ​​before and after sorting, and the arrangement order of the total delay sum value.

[0096] Hereinafter, the description will be made with reference to FIGS. 8 and 9.

[0097] The horizontal axis of graphs (g1, g2) represents the number of taps. Referring to Fig. 7b, one tap may mean a pair of buffers (delay elements) (e.g., B1) and flip-flops (FF1) connected thereto. For example, if the total number of buffers and pairs of flip-flops connected thereto is 1000, the total number of taps may be 1000.

[0098] The vertical axis of graphs (g1, g2) represents the delay time (ns). The delay time may refer to the sum of the delays required for data to be transmitted to the output nodes of the flip-flops tapped in each buffer described above in Fig. 5.

[0099] Referring to FIGS. 7a to 9 together, an increase in the number of taps in the graph (g1) may mean, for example, an increase in the buffer index. For example, if the number of taps on the horizontal axis of the graph (g1) is 4, it may mean a buffer index of 4. At this time, the delay value on the vertical axis of the graph (g1) may be D4 (= d1 + d2 + d3 + d4 + d14) as in FIG. 7b. For example, if the number of taps is 5, it may mean a buffer index of 5. At this time, the delay value on the vertical axis of the graph (g1) may be D5 (= d5 + d15) as in FIG. 7b. At this time, referring to FIG. 9, D4 > D5. Here, it can be seen that the delay observed in the flip-flop of each tap does not increase as the index of the tap (e.g., index 4 -> index 5) increases, but sometimes locally decreases even when the index of the tap increases.

[0100] On the other hand, an increase in the number of taps in the graph (g2) may not mean an increase in the buffer index, but may mean an increase in the position according to the sorting order in which the output values ​​of each flip-flop are sorted by the code conversion part (30). For example, if the number of taps on the horizontal axis of the graph (g2) is 4, the position order of the sorted buffer index may be 1, 2, 5, 3, which may mean buffer index 3. In this case, the delay value on the vertical axis of the graph (g2) may be D3 (= d1 + d2 + d3 + d13). For example, if the number of taps is 5, the position order of the sorted buffer index may be 1, 2, 5, 3, 6, which may mean buffer index 6. In this case, the delay value may be D6 (= d5 + d6 + d16). At this time, referring to FIG. 9, D3 <D6 일 수 있다.

[0101] That is, as shown in (a) of Fig. 8, when the code conversion part (30) of the present invention is not applied, it can be seen that the graph (g1) for the delay according to the increase in the number of taps does not have a monotonically increasing property. On the other hand, as shown in (b) of Fig. 8, when the code conversion part (30) of the present invention is applied, it can be seen that the graph (g2) for the delay according to the increase in the number of taps shows an increasing phenomenon without decreasing.

[0102] For example, unlike ASICs, which are application-specific integrated circuits (ASICs), FPGAs can be directly designed through programming, allowing the chip's functionality to be changed based on programming. Therefore, unlike ASICs, the functionality of each component within an FPGA can vary (or depend on the configuration). Therefore, as the number of taps increases, delay may not always increase but instead decrease, preventing a phenomenon of constant increase without decreasing.

[0103] However, as explained, it can be confirmed through the graph (g2) that the code conversion part (30) can correct the output of the first delay line part (20).

[0104] As described above, when multiple delay line parts (20) are used, delay alignment can be provided through the code conversion part. As a result, errors due to jitter can be compensated for and a TDC with high temporal resolution can be provided. For example, when four delay line parts are configured in parallel to have a total of 9,600 taps, a TDC with a resolution of 0.8 ps per tap can be provided.

[0105] FIG. 10 is a drawing for explaining a method of providing input pulses for multiple TDCs using multiple input signals according to one embodiment of the present invention.

[0106] In order to provide input pulses to each of a plurality of TDCs using a plurality of input signals, the FPGA (2) may include a plurality of TDCs (100), a multiplexer (200), and a correction operation unit (300).

[0107] At this time, a plurality of TDCs (100) may be configured to determine the occurrence time difference between two signals. For example, the two signals may be the same as the start signal (S1) and the end signal (S2) of FIG. 2, and the occurrence time difference may mean, for example, T of FIG. 2.

[0108] At this time, each of the plurality of TDCs (100) may include the configurations described above in FIGS. 1 to 9.

[0109] At this time, each of the plurality of TDCs (100) may have a pair of input nodes that receive the two signals.

[0110] For example, the plurality of TDCs (100) may include a first TDC (110), a second TDC (120), and a third TDC (130). The first TDC (110) may include a node (NN1) and a node (NN2) which are input node pairs. The second TDC (120) may include a node (NN3) and a node (NN4) which are input node pairs. And the third TDC (130) may include a node (NN5) and a node (NN6) which are input node pairs.

[0111] The multiplexer (200) can selectively connect multiple input signals (I1, I2, ..., IN) to each pair of input nodes of the TDC (100).

[0112] For example, as shown in FIG. 10, the input signals of the multiplexer (200) may include a first input signal (I1), a second input signal (I2), ..., and an Nth input signal (IN).

[0113] In one embodiment, the multiplexer (200) can commonly supply a first input signal (I1) among the input signals as a start signal (S11) of the first TDC (110), the second TDC (120), and the third TDC (130), and can commonly supply a second input signal (I2) among the input signals as a stop signal (S12) of the first TDC (110), the second TDC (120), and the third TDC (130).

[0114] The correction operation unit (300) can determine the average value of multiple occurrence time differences output by multiple TDCs (100) as the 'corrected occurrence time difference' (CO10) between the start signal (S11) and the end signal (S12).

[0115] For example, the correction operation unit (300) can calculate the average value of the output value (out10) (occurrence time difference) of the first TDC (110), the output value (out20) of the second TDC (120), and the output (out30) of the third TDC (130). The correction operation unit (300) can determine the calculated average value as the corrected occurrence time difference (CO10) between the start signal (S11) and the end signal (S12) and output it.

[0116] The above corrected occurrence time difference (CO10) is likely to be more accurate than each of the above output values ​​(out10, out20, out30).

[0117] Figure 11 shows the input signals and the input pulse of the TDC in Figure 10.

[0118] The horizontal axis of each input signal and input pulse represents the flow of time.

[0119] Referring to FIGS. 10 and 11 together, the multiplexer (200) can receive an input signal (I1), an input signal (I2), and an input signal (IN), but since only the input signal (I1) and the input signal (I2) are commonly provided to the TDCs (100) as a start signal and an end signal, respectively, the input pulses (P1) generated within the TDCs (100) can all be the same.

[0120] FIG. 12 is a graph illustrating jitter verification using TDC according to one embodiment of the present invention.

[0121] The left chart (500) is a case where the correction operation unit (300) of Fig. 10 is not applied, and the right chart (510) is a case where the correction operation unit (300) of Fig. 10 is applied.

[0122] That is, the left chart (500) is a histogram showing the dispersion in the case where the final result value is repeatedly measured when the final result value is selected by selecting any one of the output values ​​(out10, out20, out30) without using the correction calculation unit (300) of Fig. 10. In addition, the right chart (510) is a histogram showing the dispersion in the case where the final result value is repeatedly measured when the corrected occurrence time difference (CO10) is selected as the final result value using the correction calculation unit (300) of Fig. 10.

[0123] The horizontal axis of each graph (g1, g2, g3) of the charts (500, 510) represents time (unit: ps) and the vertical axis represents a normalized count value.

[0124] In the left chart (500), the standard deviation (dotted line) of the first graph (g11) is 20 ps, ​​and the standard deviation (solid line) of the second graph (g12) is 18.7 ps. At this time, the full width at half maximum (FWHM) of the first graph (g11) and the second graph (g12) is 44 ps.

[0125] In the right chart (510), the standard deviation of the third graph (g13) is 7 ps. At this time, the full width at half maximum in the third graph (g13) is 17 ps.

[0126] Comparing the half-width of the left chart (500) and the right chart, it can be seen that the half-width of the right chart is more than half that of the left chart (510). In other words, thanks to the application of the correction operation unit (300), it can be confirmed that the error due to delay caused by jitter within the FPGA is reduced.

[0127] FIG. 13 is a drawing for explaining the operation of a multiplexer according to another embodiment of the present invention.

[0128] Figure 14 shows the input pulse of the TDC according to the signals input to each TDC of Figure 13.

[0129] Hereinafter, the description will be made with reference to FIGS. 13 and 14.

[0130] The multiple input signals (I1, I2, I3) input to the multiplexer (200) may include a first start signal (S21), a first end signal (S22), and a second end signal (S23).

[0131] The multiplexer (200) can supply a first start signal (S21) and a first end signal (S22) to a first TDC (110) among a plurality of TDCs (100), and can supply a first start signal (S21) and a second end signal (S23) to a second TDC (120) among a plurality of TDCs (100).

[0132] A first input pulse (P1) can be generated through a first start signal (S21) and a first end signal (S22) within the first TDC (110). A first time difference (out41, T1), which is a time difference between the occurrence of the first start signal (S21) and the first end signal (S22) determined by the first TDC (110), can be provided to a circuit connected to the first TDC (110) (e.g., a first circuit (400, 410)).

[0133] A second input pulse (P2) can be generated through a first start signal (S21) and a second end signal (S23) within the second TDC (120). A second time difference (out42, T2), which is the time difference between the occurrence of the first start signal (S21) and the second end signal (S23) determined by the second TDC (120), can be provided to a circuit connected to the second TDC (120) (e.g., a second circuit (400, 420)).

[0134] FIG. 15 is a drawing for explaining the operation of a multiplexer according to another embodiment of the present invention.

[0135] Figure 16 shows the input pulse of the TDC according to the signals input to each TDC of Figure 15.

[0136] Hereinafter, the description will be made with reference to FIGS. 15 and 16.

[0137] The multiple input signals (I11, I12, I13) input to the multiplexer (200) may include a first start signal (S31), a second start signal (S32), and a first end signal (S33).

[0138] The multiplexer (200) can supply a first start signal (S31) and a first end signal (S33) to a first TDC (110) among a plurality of TDCs (100), and can supply a second start signal (S32) and a first end signal (S33) to a second TDC (120) among a plurality of TDCs (100).

[0139] A first input pulse (P11) can be generated using a first start signal (S31) and a first end signal (S33) within the first TDC (110). A first time difference (out41, T11), which is a time difference between the occurrence of the first start signal (S31) and the first end signal (S33) determined by the first TDC (110), can be provided to a circuit connected to the first TDC (110) (e.g., a first circuit (400, 410)).

[0140] A second input pulse (P12) can be generated through a second start signal (S32) and a first end signal (S33) within the second TDC (120). A second time difference (out42, T12), which is the time difference between the occurrence of the second start signal (S32) and the first end signal (S33) determined by the second TDC (120), can be provided to a circuit connected to the second TDC (120) (e.g., a second circuit (400, 420)).

[0141] At this time, the first circuit (410) and the second circuit (420) may be a correction operation unit (300).

[0142] As described above through FIGS. 10 to 16, an FPGA can be provided that improves the accuracy and usability of a TDC by averaging the driving results of multiple TDCs and reconstructing the input signals of the TDC using a multiplexer.

[0143] In one embodiment of the present invention, a nonvolatile recording medium readable by an electronic device according to the present invention may have recorded thereon a binary file including configuration data for programming the FPGA to implement a digital circuit including the above-described plurality of TDCs and the above-described multiplexer using the above-described FPGA.

[0144] FIG. 17 is a block diagram of a TDC system provided according to one embodiment of the present invention.

[0145] The TDC system (1000) may include a PCB board (600) and a computing device (700).

[0146] The PCB board (600) is a device capable of digital signal processing and may include the above-described FPGA (1), data interface (601), signal interface (602), clock generation unit (603), and power supply unit (604).

[0147] The data interface (601) is a device that enables data exchange between the PCB mode (600) and the computing device (700), and may be formed of, but is not limited to, USB, Ethernet, or UART.

[0148] The signal interface (602) has the function of receiving signals for measuring time differences from the outside using the FPAG (1) and transmitting them to the FPGA (1).

[0149] The clock generation unit (603) can provide a train of clock pulses counted by the FPGA (1).

[0150] The time difference value of the two selected signals calculated by the FPGA (1) can be output from the FPGA (1) and provided to the data interface (601). The data interface (601) can provide the time difference value of the two signals to the computing device (700).

[0151] The power supply unit (104) supplies power used in the PCB board (600).

[0152] The computing device (700) may include a data interface (701), a CPU (702), and a memory (703).

[0153] The computing device (700) may be configured to execute a predetermined, pre-planned algorithm using the time difference value of two selected signals received from the PCB board (600). The time difference value of the two received signals may be processed by a process executed in the CPU (702). A program composed of instructions for executing the process may be stored in the memory (703). The program may be loaded from the memory (703) to the CPU (702) and executed. The memory (703) may be a non-volatile memory.

[0154] By utilizing the embodiments of the present invention described above, those skilled in the art will be able to easily implement various changes and modifications without departing from the essential characteristics of the present invention. The content of each claim may be combined with other claims that are not in a citation relationship within the scope of this specification, as long as it is understood.

[0155] [Explanation of symbols]

[0156] 1: FPGA

[0157] 10: Input signal generation part

[0158] 20: 1st Delay Line Part

[0159] 30: Code Conversion Part

[0160] 40: Clock pulse counter

[0161] 50: Priority encoder part

[0162] 60: Operation part

[0163] 100: TDC

[0164] 200: Multiplexer

[0165] 300: Compensation operation unit

[0166] 400: Circuit

[0167] 500: Chart

[0168] 510: Chart

[0169] 600: PCB board

[0170] 700: Computing Device

[0171] 1000: TDC system

Claims

1. A plurality of TDCs (Time to Digital Converters), each of which is configured to determine the time difference between two signals and has a pair of input nodes for receiving the two signals; and A multiplexer configured to selectively connect a plurality of input signals to each pair of input nodes of the TDC; Programmed to include, FPGA.

2. In paragraph 1, The above plurality of input signals include a first start signal and a first end signal, The above multiplexer is configured to commonly supply the first start signal and the first end signal to the plurality of TDCs, It is programmed to further include a correction operation unit that determines an average value of a plurality of occurrence time differences output by the plurality of TDCs for the first start signal and the first end signal as a corrected occurrence time difference between the first start signal and the first end signal. FPGA.

3. In paragraph 1, The above plurality of input signals include a first start signal and a first end signal, Each of the above TDCs is, A first delay line part into which an input pulse having a width equal to the occurrence time difference between the first start signal and the first end signal is input; A code conversion part that converts and outputs the order of elements of the thermometer code output by the first delay line part; and An operation part that determines the occurrence time difference determined by each TDC using the conversion code output by the code conversion part; Includes, The above conversion code arranges the order of elements of the above thermometer code according to a predetermined standard, The above-mentioned predetermined standard is a data path delay from the output node of the first input pulse to the output nodes of each of the plurality of flip-flops included in the first delay line part. FPGA.

4. In paragraph 1, The above plurality of input signals include a first start signal and a first end signal, Each of the above TDCs is, A plurality of delay line parts to which input pulses having a width equal to the occurrence time difference between the first start signal and the first end signal are input; A code conversion part that merges multiple thermometer codes output by the multiple delay line parts and outputs them as a single conversion code; and An operation part that determines the occurrence time difference determined by each TDC using the above conversion code; Includes, The above conversion code arranges the order of elements of the plurality of thermometer codes according to a predetermined standard, The above-mentioned predetermined standard is a data path delay from the output node of the first input pulse to the output nodes of each of the plurality of flip-flops in the plurality of delay line parts. FPGA.

5. In paragraph 1, The above plurality of input signals include a first start signal, a first end signal, and a second end signal, The multiplexer is configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and to supply the first start signal and the second end signal to a second TDC among the plurality of TDCs. The first time difference, which is the time difference between the first start signal and the first end signal determined by the first TDC, is provided to the circuit connected to the first TDC, and the second time difference, which is the time difference between the first start signal and the second end signal determined by the second TDC, is provided to the circuit connected to the second TDC. FPGA.

6. In paragraph 1, The above plurality of input signals include a first start signal, a second start signal, and a first end signal, The multiplexer is configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and to supply the second start signal and the first end signal to a second TDC among the plurality of TDCs. The first time difference, which is the time difference between the first start signal and the first end signal determined by the first TDC, is provided to the circuit connected to the first TDC, and the second time difference, which is the time difference between the second start signal and the first end signal determined by the second TDC, is provided to the circuit connected to the second TDC. FPGA.

7. Using FPGA, A plurality of TDCs (Time to Digital Converters), each of which is configured to determine the time difference between two signals and has a pair of input nodes for receiving the two signals; and A multiplexer configured to selectively connect a plurality of input signals to each pair of input nodes of the TDC; A binary file containing configuration data that is configured to program the FPGA to implement a digital circuit including A nonvolatile recording medium that can be read by an electronic device.

8. In paragraph 7, The above plurality of input signals include a first start signal and a first end signal, The above multiplexer is configured to commonly supply the first start signal and the first end signal to the plurality of TDCs, The digital circuit is characterized in that it further includes a correction operation unit that determines an average value of a plurality of occurrence time differences output by the plurality of TDCs for the first start signal and the first end signal as a corrected occurrence time difference between the first start signal and the first end signal. A nonvolatile recording medium that can be read by an electronic device.

9. In paragraph 7, The above plurality of input signals include a first start signal and a first end signal, Each of the above TDCs is, A first delay line part into which an input pulse having a width equal to the occurrence time difference between the first start signal and the first end signal is input; A code conversion part that converts and outputs the order of elements of the thermometer code output by the first delay line part; and An operation part that determines the occurrence time difference determined by each TDC using the conversion code output by the code conversion part; Includes, The above conversion code arranges the order of elements of the above thermometer code according to a predetermined standard, The above-mentioned predetermined standard is characterized in that the data path delay from the output node of the first input pulse to the output nodes of each of the plurality of flip-flops included in the first delay line part. A nonvolatile recording medium that can be read by an electronic device.

10. In paragraph 7, The above plurality of input signals include a first start signal and a first end signal, Each of the above TDCs is, A plurality of delay line parts to which input pulses having a width equal to the occurrence time difference between the first start signal and the first end signal are input; A code conversion part that merges multiple thermometer codes output by the multiple delay line parts and outputs them as a single conversion code; and An operation part that determines the occurrence time difference determined by each TDC using the above conversion code; Includes, The above conversion code arranges the order of elements of the plurality of thermometer codes according to a predetermined standard, The above predetermined criterion is characterized in that the data path delay from the output node of the first input pulse to the output nodes of each of the plurality of flip-flops in the plurality of delay line parts. A nonvolatile recording medium that can be read by an electronic device.

11. In paragraph 7, The above plurality of input signals include a first start signal, a first end signal, and a second end signal, The multiplexer is configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and to supply the first start signal and the second end signal to a second TDC among the plurality of TDCs. It is characterized in that the first time difference, which is the time difference between the first start signal and the first end signal determined by the first TDC, is provided to the circuit connected to the first TDC, and the second time difference, which is the time difference between the first start signal and the second end signal determined by the second TDC, is provided to the circuit connected to the second TDC. A nonvolatile recording medium that can be read by an electronic device.

12. In paragraph 7, The above plurality of input signals include a first start signal, a second start signal, and a first end signal, The multiplexer is configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and to supply the second start signal and the first end signal to a second TDC among the plurality of TDCs. It is characterized in that the first time difference, which is the time difference between the first start signal and the first end signal determined by the first TDC, is provided to the circuit connected to the first TDC, and the second time difference, which is the time difference between the second start signal and the first end signal determined by the second TDC, is provided to the circuit connected to the second TDC. A nonvolatile recording medium that can be read by an electronic device.

13. A PCB board (600) including an FPGA (1) of any one of claims 1 to 6; and A computing device (700) that obtains the occurrence time difference from the PCB board; including, TDC system.

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