Heat sink including ceramic interface layer

Abstract

A heat sink (100) including an interface layer (501) of ceramic material having a thermal conductivity of 50 W / (m·K) or greater, wherein the interface layer (501) includes cooling channels defined by cooling walls (502) extending from a surface of the interface layer (501); a manifold body (510) having an inlet (506) and an outlet (507) for coolant to the plurality of coolant channels; and an adhesive layer (505) between the interface layer (501) of the ceramic material and the manifold body (501).

Description

HEAT SINK INCLUDING CERAMIC INTERFACE LAYERTECHNICAL FIELD

[0001] The present invention relates generally to structures and methods for thermal dissipation, and in particular embodiments, to using thermally conductive ceramics in thermal dissipation structures.BACKGROUND

[0002] In the operation of electrical components, such as integrated circuits, some of the devices in the electrical components will generate heat. Also, some devices in integrated circuits are susceptible to heat and may have certain electrical characteristics negatively influenced by heating. Heating effects can be especially harmful to high precision devices, where the heating effects ruin the precision with which the particular device operates.

[0003] Printed Circuit Boards (PCBs) are utilized in most electrical devices in use today. PCBs are used to mechanically support and electronically connect electronic components. PCBs typically contain a plurality of electronic devices, such as transistors and resistors, which are physically attached to the substrate. The metal circuitry printed (etched) on the PCBs provides the electrical connections between the components and provides electrical power for them to operate. The substrate material of typical PCBs are not thermally conductive. One challenge in the design of electronics is effectively removing the heat that is generated, such as heat generated by electrical components attached on or integrated within the substrate materials of PCBs that have a poor thermal conductivity.SUMMARY

[0004] Technical advantages are generally achieved by embodiments of this disclosure including thermally conductive ceramic compositions used in applications for cooling electrical components.

[0005] In accordance with an embodiment, a heat sink is described that includes an interface layer of ceramic material having a thermal conductivity of 50 W / (m-K) or greater, wherein the interface layer comprises cooling channels defined by cooling walls extending from a surface of the interface layer; a manifold body having an inlet and an outlet for coolant to the plurality of coolant channels; and an adhesive layer between the interface layer of theceramic material and the manifold body. In some embodiments, the cooling walls are integral with the interface layer of the ceramic material. In some embodiments, the interface layer of the ceramic material includes a composition of aluminum nitride, diamond-like carbon (DLC), beryllium oxide (BeO), silicon carbide (SiC), boron nitride (BN), copper aluminum oxide (CuA102), or combinations thereof. In some embodiments, the cross-section for the cooling channels have a height and width dimension that both range from to microns to 500 microns. In some embodiments, the manifold body includes a plurality of coolant passages in communication with the inlet and the outlet. In some embodiments, the manifold body includes liquid crystal polymer, polyimide, or epoxy, with or without fiberglass reinforcement. In some embodiments, an adhesive film layer is present between the second thermally conductive layer and the manifold body. In some embodiments, the adhesive film includes epoxy polymer, polyurethane, silicone, buna-n rubber, FKM rubber or combinations thereof. In some embodiment, the adhesive film has a thickness ranging from 10 microns to too microns.

[0006] In some embodiments, an electronics package is provided that includes a thermal chip, and a capacitor structure contacting the thermal chip. The capacitor structure includes a positive electrode separated from a negative electrode by a dielectric fill to provide a multilayered structure, a first thermally conductive layer on a first surface of the multilayered structure providing a thermal interface between the capacitor structure and the thermal chip, and a second thermally conductive layer on a second surface of the multilayered structure that is opposing the first surface, wherein at least one of the first thermally conductive layer and the second thermally conductive layer is comprised of a ceramic material having a thermal conductivity of 50 W / (m-K) or greater. The electronics package may also include a heat sink integrated with the second thermally conductive layer, wherein the second thermally conductive layer includes a plurality of coolant channels. In some embodiments, the plurality of cooling channels are defined by cooling walls extending from a surface of the second thermally conductive layer that is opposite the surface of the second thermally conductive layer contacting the multilayered structure. In some embodiments, the second thermally conductive layer includes a composition comprising of aluminum nitride, diamond-like carbon (DLC), beryllium oxide (BeO), silicon carbide (SiC), boron nitride (BN), copper aluminum oxide (CuA102), or combinations thereof. In some embodiments, theheat sink comprises a manifold body having an inlet and an outlet for coolant to the plurality of coolant channels. In some embodiments, the manifold body is composed of liquid crystal polymer, polyimide, or epoxy, with or without fiberglass reinforcement. In some embodiments, the manifold body is composed of a material having a low thermal conductivity o.t~2W / (m-K) or less.

[0007] In another aspect, method is described for cooling an electronic component that includes contacting a surface of a heat producing component with a capacitor structure. The capacitor structure including a positive electrode separated from a negative electrode by a dielectric fill to provide a multilayered structure, a first thermally conductive layer on a first surface of the multilayered structure providing a thermal interface between the capacitor structure and the heat producing component, and a second thermally conductive layer on a second surface of the multilayered structure that is opposing the first surface, wherein at least one of the first thermally conductive layer and the second thermally conductive layer is comprised of a ceramic material having a thermal conductivity of 50 W / (m-K) or greater. In some embodiments, the method further includes bonding a manifold body to the second thermally conductive layer of the capacitor structure to provide a heat sink. In some embodiments, the second thermally conductive layer includes plurality of cooling walls that extend into the manifold body to define cooling channels. In some embodiments, the plurality of cooling walls are formed in the second thermally conductive layer using mechanical subtractive machining, laser engraving, plasma engraving, powder injection formation or combinations thereof. In some embodiments, the manifold body includes a plurality of coolant passages in communication with the inlet and the outlet. In some embodiments, bonding the manifold to the second thermally conductive layer includes forming a uniform coating of an adhesive material on a transfer substrate; patterning the uniform coating to provide cooling openings corresponding to the plurality of coolant passages of the manifold body, transferring the uniform coating of the adhesive material having the cooling openings from the transfer substrate to at least one of the manifold body and the second thermally conductive layer; and adhesively- joining the manifold body and the second thermally conductive lay er through the uniform coating of the adhesive material to provide an adhesive layer at an interface of the manifold body and the second thermally- conductive layer. In some embodiments, the method further includes adhesive curing following joining the manifold body and the second thermally conductive lay er.

[0008] Brief Description of the Drawings

[0009] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a side cross-sectional view illustrating a multilayered ceramic capacitor (MLCC), in which the metallic electrodes are configured to provide a vertical heat pathway, in accordance with some embodiments;

[0011] Figure 2 is a orthographic view of a multilayered ceramic capacitor (MLCC) structure, in accordance with some embodiments;

[0012] Figure 3 is a side orthographic view of an electrode design that includes a top electrode tab and a bottom electrode tab on opposing ends of the electrode, in accordance with some embodiments;

[0013] Figure 4 is a side orthographic view of an electrode design within the multilayered ceramic capacitor (MLCC) structure, in which the plurality of negative electrodes and the plurality of positive electrodes each include a top electrode tab and a bottom electrode tab on opposing ends of each electrode, in accordance with some embodiments;

[0014] Figure 5 is a side view of an electrode design within the multilayered ceramic capacitor (MLCC) structure illustrating the X-shaped geometry provided by the top electrode tab and the bottom electrode tab on opposing ends of each positive and negative electrode, in accordance with some embodiments;

[0015] Figure 6A is a side view illustrating a positive side tab that provides an electrical contact to a positive electrical pathway of the multilayered ceramic capacitor (MLCC) structure, in accordance with some embodiments;

[0016] Figure 6B is a side view illustrating a negative side tab that provides an electrical contact to a negative electrical pathway of the multilayered ceramic capacitor (MLCC) structure, in accordance with some embodiments;

[0017] Figure 6C illustrates a two component side tab, in which a first component includes an electrical contact to a negative electrical pathway, in accordance with some embodiments;

[0018] Figure 7 illustrates another side view of a side tab, in accordance with some embodiments;

[0019] Figure 8 is a flow chart illustrating some steps of a method for forming a multilayered ceramic capacitor (MLCC) structure as depicted in Figures 1-7, in accordance with some embodiments;

[0020] Figure 9 is a orthographic view of an electrical component package including an MLCC structure with thermally conductive ceramic interface layers beneath and in contact with a thermal chip for enhancing heat dissipation for heat generated by the thermal chip and for delivering power to the thermal chip, in accordance with some embodiments;

[0021] Figure 10 is a side cross-sectional view of the structure depicted in Figure 9 across section line B in Figure 9, in accordance with some embodiments;

[0022] Figure 11 is a side cross-sectional view of the structure depicted in Figure 9 across section line A in Figure 9, in accordance with some embodiments;

[0023] Figure 12 is a magnified view of the engagement of the thermal chip to the MLCC structure that is depicted in Figure 11, in accordance with some embodiments;

[0024] Figure 13A is a side cross-sectional view of another embodiment of the structure depicted in Figure 9 across section line A, in which the structure further includes a backside heat-generating device contacting the second thermally conductive layer at the backside of the MLCC structure, in accordance with one embodiment of the present disclosure;

[0025] Figure 13B is a side cross-sectional view of a portion of an MLCC structure for the embodiment illustrated in Figure 13A, in which the MLCC structure includes vias for power transmission to the underlying heat-generating device, and for upwards heat transmission from the heat-generating devices towards the frontside of the electronics package including the MLCC structure, in accordance with some embodiments;

[0026] Figure 14 is a side cross-sectional view of the preparation of side tabs of the MLCC structure to be embedded into the sidewalls of the first printed circuit board (PCB) using lamination, in accordance with some embodiments;

[0027] Figure 15 is a side cross-sectional view illustrating the lamination of the structure depicted in Figure 14 to add exterior printed circuit board (PCB)layers to a core printed circuit board (PCB) layer, in accordance with some embodiments;

[0028] Figure t6 is a side cross-sectional view illustrating post printed circuit board (PCB) process, in accordance with some embodiments;

[0029] Figure 17 is a side cross-sectional view illustrating the final assembly for the printed circuit board (PCB), in accordance with some embodiments;

[0030] Figure 18 is an exploded view of a heat sink, in accordance with some embodiments;

[0031] Figure 19 is a magnified view of the heat sink illustrating fluid passages in the manifold, and the microchannels in the thermal interface layer, in accordance with some embodiments; and

[0032] Figure 20 is an orthographic view of one embodiment of an assembled heat sink, in accordance with some embodiments.

[0033] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.DETAILED DESCRIPTION

[0034] The making and using of embodiments of this disclosure are discussed in detail below. It should be appreciated, however, that the concepts disclosed herein can be embodied in a wide variety of specific contexts, and that the specific embodiments discussed herein are merely illustrative and do not serve to limit the scope of the claims. Further, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0035] In some embodiments, the methods and structures described herein provide for increased cooling of integrated circuit packaging structures using backside structures to thermally dissipate heat. Integrated circuit packages can include logic chips and high bandwidth memory (HBM) devices that are engaged to a supporting substrate through an interposer structure. In integrated chip packaging structures, such as 2.5D and 3D chip packages, bottom-side interconnects provide for interconnectivity to memory bandwidth devices, but limit area scaling. The bottom-side interconnects may engage a substrate, such as a printed circuit board (PCB). Heat dissipation is managed primarily throughthe top side of the integrated circuit package. Electrical interconnects are concentrated on the bottom side of the integrated circuit package. As integrated circuit design evolves, and dimensions scale to increasingly smaller sizes, top side elements of the integrated circuit package, such as the logic chips and the high-bandwidth memory (HBM) devices may be brought close together. The higher density of the logic chips and the high bandwidth memory at the top side of the device reduces the area for heat dissipation through the top side of the integrated circuit package. Further, heat that passes through the HBM can degrade performance.

[0036] In some embodiments, to overcome the aforementioned deficiencies, the methods and structures described herein employ additional backside cooling by introducing heat dissipating structures to the backside of the integrated circuit package. The term “backside” as used herein refers to the side of a thermal chip (integrated circuit) that includes the electrical connections for connectivity to the package, including the printed circuit boards (PCBs). A “thermal chip” is an electrical component that generates heat. More particularly, in some embodiments, backside cooling for the integrated circuit package can be provided via heat dissipation through multilayer ceramic capacitors (MLCC). Multilayer ceramic capacitors (MLCCs) are a type of capacitor that have multiple layers of ceramic material that act as a dielectric. MLCCs have alternating layers of metallic electrodes along with layers of dielectric ceramic. The multilayer ceramic capacitors are generally employed for power decoupling. In logic chips, as used in the above described integrated circuit packages, capacitances charge and discharge at a high frequency, which can result in spike currents, and unstable power rails. Decoupling is when the MLCCs buffer energy with low inductance and absorb transient power.

[0037] In yet further embodiments, in addition to a thermal pathway extending from the thermal chip on the top of an electronics package to a heat sink at the back of the electronics package; embodiments also contemplate a heat-generating device present at the back of the electronics package. In this example, the heat-generating device at the back of the electronics package is in thermal connectivity to the thermal chip on the top of the electronics package though MLCC structures that provide a thermal pathway. In this example, when the heat-generating device at the back of the electronics package is generating more heat than the thermal chip on top of the electronics package, heat from the heat-generating device can be transferred via the MLCC structure to the thermalchip. The heat received at the thermal chip from the heat-generating device may be dissipated by a heat sink that is present on a top side of the thermal chip. This is an example of upwards heat transfer through the MLCC structure.

[0038] Referring to Figure 1, in some embodiments, the multilayered structures 205 of electrodes 201 within the MLCC structures 200 are employed as a heat transfer path Pi. For example, as will be described herein, the multilayered structures 205 of the MLCC structures 200 can be positioned on the backside of a heat-producing electrical component, such as a thermal chip too, e.g., an integrated circuit package (IC), and can provide for a heat transfer path Pt to a heat sink 500. In this type of application, the MLCC structure 200 can provide a vertical heat transfer path Pi. It is noted that the vertical heat transfer path Pl is not limited to being a downward heat path. For example, in the embodiment depicted in Figure 13A, the vertical heat transfer path can also be an upward heat path P5, in which heat is transmitted from the back of an electronics package 100 to the top of an electronics package 1000.

[0039] Referring to Figure 2C, each MLCC structure 200 includes a plurality of metallic electrodes 201 that are separated by a dielectric ceramic fill 202 to provide a plurality of multilayered structures 205. As will be described below with reference to Figures 2-17, a plurality of multilayered structures 205 electrically connected by metallic interconnects 211, 211b, 212a, 212b to side tabs 300 provide an MLCC structure 200. Each MLCC structure 200 also includes thermally conductive ceramic layers 206, 207.

[0040] The plurality of metallic electrodes 201 are composed of electrically conductive and thermally conductive material, such as a metal. For example, the stacked metallic electrodes 201 may be composed of copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), palladium (Pd), molybdenum (Mo), tungsten (W), or combinations thereof. In some embodiments, the thermal conductivity of the stacked metallic electrodes 201 can range from 90 W / (m-K) to 430 W / (m-K). For example, nickel (Ni) has a thermal conductivity of 90.0 W / (m-K), aluminum (Al) has a thermal conductivity of 237 W / (m-K), copper (Cu) has a thermal conductivity of 401 W / (m-K), and silver (Ag) has a thermal conductivity of 429 W / (m-K). The dielectric ceramic fill 202 of the MLCC 200 separating the metallic electrodes 201 may be barium titanate (BaTiO,). In some examples, the dielectric fill is a ceramic, e.g., dielectric ceramic fill 202, including barium titanate including an additive comprising aluminum silicate, magnesium silicate,aluminum oxide or combinations thereof. The dielectric ceramic fill 202 has a thermal conductivity significantly less than the thermal conductivity of the metallic electrodes. In some embodiments, the thermal conductivity for the dielectric ceramic fill 202 is less than 5 W / (m-K). For example, barium titanate has a thermal conductivity of 2.85 W / (m-K). The dielectric ceramic fill 202 has a relative permittivity greater than 1000.

[0041] In some embodiments, the electrode planes, e.g., the plurality of metallic electrodes 201, conduct heat quickly. However, prior to the methods and the structures described herein, the stacks of multilayered structures 205 of metallic electrodes 201 and dielectric ceramic fill 202 in the MLCC structure 200 conduct heat slowly at the interfaces 203, 204 of the MLCCs 200 with the thermal chip too and the heat sink 500, as illustrated in Figure 1. In some embodiments, the methods and structures described herein provide for a thermally conductive interface at the interfaces 203, 204 of the MLCCs 200 with the thermal chip too and the heat sink 500 by incorporating thermally conductive ceramic interface layers 206, 207, as illustrated in Figure 2. It is noted that the methods and structures described herein are not limited to the downward transfer of heat from the thermal chip too to the heat sink 500 through the MLCC structure 200. For example, in some embodiments, the MLCC structure 200 may be between a thermal chip too that is on the top side of an electronics package 1000, and a heat-generating device 700 on a bottom side of the electronics package 1000, in which heat is transmitted from the heatgenerating device 700 in an upward transfer of heat P5 to the thermal chip too at the top side of the electronics package 1000, as depicted in Figure 13A. In some embodiments, a heat sink may be present on a top surface of the thermal chip, which dissipates the heat received from the upward transfer from the heatgenerating device 700.

[0042] Figure 2 illustrates an embodiment of a capacitor structure, e.g., MLCC structure 200, that includes a top thermally conductive ceramic interface layer 206 at a top surface of the multilayered structures 205 for the MLCC structure 200, and a bottom thermally conductive ceramic interface layer 207 at the bottom surface of the multilayered structure 205 of the MLCC 200. The multilayered structure 205 includes the stacked metallic electrodes 201 and the dielectric ceramic fill 202. The metallic electrodes 201 include positive electrodes and negative electrodes (the positive metallic electrode is identified by reference number 201a, and the negative metallic electrode is identified byreference number 201b in Figure 3). In some embodiments, the top thermally conductive ceramic interface layer 206 is intended to provide the thermal interface 203 between the MLCC structure 200 and the thermal chip too, as depicted in Figure 1. In some embodiments, the bottom thermally conductive ceramic interface layer 207 is intended to provide the thermal interface 204 between the MLCC 200 and a heat sink 500, as depicted in Figure 1.

[0043] Figure 2 illustrates an embodiment of multilayered ceramic capacitor structures (MLCC) 200 comprising a plurality of positive electrodes (a first set of the stacked metallic electrodes 201a) separated from a plurality of negative electrodes (a second set of the metallic electrodes 201b) by a dielectric ceramic fill 202; and at least one thermally conductive ceramic interface layer 206, 207 on a surface of the multilayered structure 205 of the MLCC 200. In some embodiments, the multilayered structure 205 can include 1000 layers within a 1- millimeter thickness.

[0044] In some embodiments, the thermally conductive ceramic interface layer, e.g., at least one of the top thermally conductive interface layer 206 and the bottom thermally conductive interface layer 207, has a thermal conductivity of 50 W / (m-K) or greater. In some embodiments, at least one of the top thermally conductive ceramic interface layer 206 and the bottom thermally conductive ceramic interface layer 207 includes a composition comprising aluminum nitride, diamond-like carbon (DLC), beryllium oxide (BeO), silicon carbide (SiC), boron nitride (BN), copper aluminum oxide (CuAlCL), or combinations thereof. In some examples, aluminum nitride (A1N) is used for the top thermally conductive ceramic interface layer 206 and the bottom thermally conductive ceramic interface layer 207. Aluminum nitride (A1N) is a solid nitride of aluminum. It has a high thermal conductivity of up to 321 W / (m-K). Diamond has a strong thermal conductivity. The theoretical value of thermal conductivity of its single crystal is 2200 W / (m-K). At room temperature, BeO ceramics can have a thermal conductivity as great as 280 W / (m-K). In some examples, the thermal conductivity of the thermally conductive ceramic interface layer, e.g., at least one of the top thermally conductive ceramic interface layer 206 and the bottom thermally conductive ceramic interface layer 207, may range from 50 W / (m-K) to 2200 W / (m-K). The thickness of the thermally conductive ceramic interface layer, e.g., at least one of the top thermally conductive ceramic interface layer 206 and the bottom thermally conductive ceramic interface layer 207, may range from 50 microns to 600 microns. In some embodiments, thedielectric breakdown strength for the material of the thermally conductive ceramic interface layer is 5 kV / mm or greater. The thermally conductive ceramic interface layer 207 is an electrical insulator and mechanical binder. The thermally conductive ceramic interface layer 207 does not contribute to the capacitance.

[0045] Referring to Figure 2, in some embodiments, the multilayered capacitor structures (MLCC structure 200) further include contact pads 208 through the top thermally conductive interface layer 206. The top thermally conductive ceramic interface layer 206 is electrically insulating. For example, the top thermally conductive ceramic interface layer may have a dielectric breakdown strength that is equal to 5 kV / mm or greater. The contact pad 208 may be formed in openings through the top thermally conductive layer 206, and provide for electrical contact of the thermal chip too to the metallic electrodes 201 of the MLCC 200. In some embodiments, the contact pads 208 may be configured for solder bonding. Bonding of the thermal chip too to the contact pads 208 electrically connects the thermal chip too to the metallic electrodes 201 of the MLCC 200, which allows for the MLCC 200 to function for power decoupling.

[0046] In some embodiments, the top thermally conductive ceramic interface layer 206 and the bottom thermally conductive ceramic interface layer 207 can secure multiple multilayered structures 205 in an MLCC structure 200. For example, in the embodiment that is depicted in Figure 2 only two multilayered structures 205 are being depicted being secured by the top thermally conductive ceramic interface layer 206 and the bottom thermally conductive ceramic interface layer 207. It is noted that the present disclosure is not limited to only this example. Any number of multilayered structures 205 may be present in the MLCC structure 200.

[0047] Figures 3-5 illustrate electrode design for the MLCC structure 200. Not only do the electrodes contribute to a vertically oriented thermal pathway Pt (as depicted in Figure 1) that can be used to dissipate heat from a thermal chip too that is engaged to the contact pads 208; the electrode design of the present disclosure can provide for electrical current pathways that extend horizontally (also referred to as a “horizontally oriented electrical pathway P2”) across the electrically connected end-to-end multilayered structures 205, as depicted in Figures 4 and 5. In some embodiments, the MLCC electrode pattern exposesboth polarities on each long edge, for both top and bottom connection, as depicted in Figure 3.

[0048] Figure 3 illustrates an embodiment of electrode designs for use with the MLCC structure 200 depicted in Figures 1 and 2. Figure 3 illustrates an embodiment of a positive metallic electrode 201a and a negative metallic electrode 201b. The positive metallic electrode 201a includes a top electrode tab 209a and a bottom electrode tab 210a on opposing ends of the positive metallic electrode 201a. Figure 3 also illustrates an embodiment of a negative metallic electrode 201b that includes a top electrode tab 209b and a bottom electrode tab 210b on opposing ends of the negative metallic electrode 201b.

[0049] Figure 4 illustrates an embodiment of the electrode design, e.g., the positive metallic electrode 201a and the negative metallic electrode 201b, within the multilayered ceramic capacitor (MLCC) structure 200, in which the plurality of negative electrodes 201b and the plurality of positive electrodes 201a each include a top electrode tab 209a, 209b and a bottom electrode tab 210a, 210b on opposing ends of each positive and negative metallic electrode 201a, 201b.

[0050] Figures 3 and 4 illustrate an embodiment of a plurality of positive metallic electrodes 201a and a plurality of negative metallic electrodes 201b that are positioned to have an end-to-end configuration to provide an electrical current path that passes from the top electrode tab 209a, 209b to the bottom electrode tab 210a, 210b for each electrode 201a, 201b. The adjacent top electrode tabs 209a, 209b and adjacent bottom electrode tabs 210a, 210b for the end-to-end aligned electrodes are connected by metallic interconnects 211a, 211b, 212a, 212b. As the electrical current path propagates from one multilayer structure 205 to another adjacent multilayer structure 205 via the metallic interconnects 211a, 211b, 212a, 21b, the electrical current path is horizontal (also referred to as a “horizontally oriented electrical pathway P2”). In some embodiments, the at least one multilayer structure 205 includes an upper positive metallic interconnect 211a, an upper negative metallic interconnect 211b, a lower positive metal interconnect line 212a, and a lower negative metal interconnect line 212b.

[0051] Referring to Figure 4, one example of a negative current pathway can include starting at a lower negative electrode tab 210b of a negative metallic electrode 201b of a first multilayered structure 205, in which a negative current is passed by a lower negative interconnect line 212b to the lower negativeelectrode tab 210b of a negative metallic electrode 201b of an adjacently end-to- end positioned second multilayered structure 205. This portion of the negative current pathway is illustrated by reference number 214b, which is horizontally oriented. From that point, the negative current pathway includes a current pathway that is passed from the lower negative electrode tab 210b to an upper negative electrode tab 209b of the same negative metallic electrode 201b. This portion of the negative current pathway has a vertical component. From the upper negative electrode 209b of the negative metallic electrode 201b of the second multilayered structure 205, the negative current path can then extend horizontally again from the upper negative electrode tab 209b of the negative metallic electrode 201b of the second multilayered structure 205 to an adjacently end-to-end positioned third multilayered structure 205. For example, the negative current is passed by an upper negative metallic interconnect 211b to an upper electrode tab 209b of the negative metallic electrode 201b of an adjacently end-to-end positioned second multilayered structure 205. This portion of the negative current pathway is illustrated by reference number 214a, which is horizontally oriented.

[0052] Referring to Figure 4, one example of a positive current pathway can include starting at an upper positive electrode tab 209a of a positive metallic electrode 201a of a first multilayered structure 205, in which a positive current is passed by a positive metallic interconnect 211a to an upper positive electrode tab 209a of a positive metallic electrode 201a of an adjacently end-to-end positioned second multilayered structure 205. This portion of the positive current pathway is illustrated by reference number 213a, which is horizontally oriented. From that point, the positive current pathway includes a current pathway that is passed from the upper positive electrode tab 209a to a lower positive electrode tab 210a of the same positive metallic electrode 201a. This portion of the positive current pathway has a vertical component. From the lower positive electrode tab 210a of the positive metallic electrode 201a of the second multilayered structure 205, the positive current path can then extend horizontally again from the lower positive electrode tab 210a of the positive metallic electrode 201a of the second multilayered structure 205 to an adjacently end-to-end positioned third multilayered structure 205. For example, the positive current is passed by a lower positive interconnect line 212a to a lower positive electrode tab 210a of the positive metallic electrode 201a of an adjacently end-to-end positioned second multilayered structure 205. Thisportion of the negative current pathway is illustrated by reference number 213b, which is horizontally oriented. The vertical thermal conduction path Pl depicted in Figure 1 is perpendicular to the horizontal electrical current path P2 depicted in Figure 4.

[0053] Figure 5 depicts a cross-sectional view of an embodiment of a metallic electrode design 201a, 201b within the multilayered ceramic capacitor 200, illustrating the X-shaped geometry provided by the top electrode tabs 209a, 209b and the bottom electrode tabs 210a, 210b on opposing ends of each positive and negative metallic electrode 201a, 201b. The upper positive electrode tab 209a of the positive metallic electrode 201a is positioned on a first side Si of the positive metallic electrode 201a, and the lower positive electrode tab 210a of the positive metallic electrode 201a is present on a second side S2 of the positive metallic electrode 201a, in which the first side Si and the second side S2 are opposing end-to-end sides of the positive metallic electrode 201a. The lower negative electrode tab 210b of the negative metallic electrode 201b is present on a first side Si of the negative metallic electrode 201b, and the upper negative electrode tab 209b of the negative metallic electrode 201b is present on a second side S2 of the negative metallic electrode 201b. When arranged in the multilayered structure 205, the first side Si of the positive metallic electrode 201a, and the first side Si of the negative metallic electrode 201b are positioned on the same first side of the multilayered structure 205; and the second side S2 of the positive metallic electrode 201a, and the second side S2 of the negative metallic electrode 201b are positioned on the same second side of the multilayered structure 205. When viewed from a side view, the configuration of the electrode tabs for the positive and negative electrodes in the multilayered structure provides an X-shaped geometry, as depicted in Figure 5.

[0054] Figures 3-5 illustrate an embodiment of an MLCC structure 200 having an electrode design that includes a first plurality of positive metallic electrodes 201a having a lower positive electrode tab 210a at a first side Si of the positive metallic electrode 201a and an upper positive electrode tab 209a at a second side S2 of the positive metallic electrode 201a; and a second plurality of negative metallic electrodes 201b having an upper negative electrode tab 209b at a first side Si of the negative metallic electrode 201b and a low-er negative electrode tab 210b at a second side S2 of the second metallic electrode. Although not depicted in Figure 5, a dielectric ceramic fill 202 separates the first plurality of metallic electrodes from the second plurality of metallic electrodes to formmultilayer capacitor structures. The dielectric ceramic fill 202 is described in Figure 1.

[0055] Referring to Figures 4 and 5, a portion of the plurality of the positive metallic electrodes 201a are aligned so that the lower positive electrode tabs 210a are adjacent to one another for adjacent positive metallic electrodes 210a, and upper positive electrode tabs 209a are adjacent to one another for the adjacent positive metallic electrodes 201a.

[0056] Referring to Figure 5, electrical connectivity between the adjacently positioned tabs is provided by interconnect metal layers. For example, an upper positive metallic interconnect 211a is connecting the upper positive electrode tabs 209a of the positive metallic electrodes 201a, wherein the upper positive interconnect 211a is present between the multilayered structure 205 and the first (upper) thermally conductive ceramic interface layer 206. The upper and lower interconnects may be implemented as predefined patterns of copper and the nanopaste sintering material.

[0057] In some embodiments, in each MLCC structure 200, at least a portion of the positive metallic electrodes 201a are aligned so that the upper positive electrode tabs 209a of adjacent multilayered structures 205 are adjacent to one another and lower positive electrode tabs 210a of adjacent multilayered structures 205 are adjacent to one another. In some embodiments, in each MLCC 200, at least a portion of the negative metallic electrodes 201b are aligned so that the upper negative electrode tabs 209b of adjacent multilayered structures 205 are adjacent to one another and lower negative electrode tabs 210b of adjacent multilayered structures 205 are adjacent to one another. The alignment of the electrodes and edge-to-edge positioning of similar upper and lower tabs provides ease in electrical connectivity of the adjacent multilayered structures 205 across a horizontal plane.

[0058] Referring to Figure 5, in an embodiment, an upper negative metallic interconnect 211b is connecting the upper negative electrode tabs 209b of the negative metallic electrodes 201b, wherein the upper negative metallic interconnect 211b is present between the multilayered structure 205 and the first (upper) thermally conductive ceramic interface layer 206. In some embodiments, these interconnects may be implemented as a predefined pattern of copper in combination with nanopaste sintering material.

[0059] Referring to Figure 5, in an embodiment, a lower positive metallic interconnect 212a is connecting the lower positive electrode tabs 210a of the positive metallic electrodes 201a, wherein the lower positive interconnect 212a is present between the multilayered structure 205 and a second (lower) thermally conductive ceramic interface layer 207. In some embodiments, these interconnects may be implemented as a predefined pattern of copper in combination with the nanopaste sintering layer.

[0060] Referring to Figure 5, in an embodiment, a lower negative metallic interconnect 212b is connecting the lower negative electrode tabs 210b of the negative metallic electrodes 201b, wherein the lower negative metallic interconnect 212b is present between the multilayered structure 205 and the second (lower) thermally conductive ceramic interface layer 207. In some embodiments, these interconnects may be implemented as a predefined pattern of copper in combination with a nanopaste sintering material.

[0061] Figure 5 further illustrates a spacing (gap) between the electrodes of the multilayered structures 205 to allow thermal expansion and epoxy filling.

[0062] Figures 6A-6C illustrate some embodiments of side tabs 300a, 300b, 300c’, 300c” positioned at the edge of the structure of electrically interconnected multilayered structures 205 of positive and negative metallic electrodes 209a, 209b, in which the side tabs 300a, 300b, 300c’, 300c” are for an electrical connection layer, in which the multilayered structures 205 are aligned end-to-end. In some embodiments, the side tabs 300a, 300b, 300c’, 300c” are in electrical communication to the metallic interconnect 211a, 211b, 212a, 212b, wherein the side tabs 300a, 300b, 300c’, 300c” provide for electrical communication of the MLCC structure 200 to an external electrical component, such as a printed circuit board (PCB).

[0063] For example, the aforementioned positive and negative horizontal electrical pathways (“horizontally oriented electrical pathway P2”) as illustrated by reference numbers 213a, 213b, 214a, 214b, in Figure 4, can be for supplying voltage potentials (VDD & GND) inside the MLCC structure 200, which are electrically connected to the side tabs 300a, 300b, 300c’, 300c” providing an external connection (termination) for the MLCC structure 200. In some embodiments, the electrical pathways described above can pass VDD and GND between MLCCs to form a power delivery network.

[0064] In some embodiments, the side tabs 300a, 300b, 300c’, 300c” are provided by metallic blocks that are positioned at the edge of multilayered structures 205 of the MLCC 200 to allow for interconnect with external electrical components, such as PCBs, through drilling processes. The side tabs 300a, 300b, 300c’, 300c” may be composed of a metal, such as copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), palladium (Pd), molybdenum (Mo), tungsten (W), or combinations thereof.

[0065] The side tabs 300a, 300b, 300c’, 300c” are connected (secured) to the metallic interconnects 211a, 211b, 212a, 212b. In some embodiments, the side tabs 300a, 300b, 300c’, 300c” are only partially overlapped with the upper thermally conductive ceramic interface layer 206 and the lower thermally conductive ceramic interface layer 207. The portion of the side tabs 300a, 300b, 300c’, 300c” that is not covered with the upper thermally conductive ceramic interface layer 206 and the lower thermally conductive ceramic interface layer 207, e.g., the oversized part of the side tabs 300a, 300b, 300c’, 300c”, can be laminated into a printed circuit board (PCB), providing mechanical fixture. In some embodiments, the height of the side tabs 300a, 300b, 300c’, 300c” is equal to the height of the positive and negative metallic electrodes 201a, 201b. Each of the side tabs 300a, 300b, 300c’, 300c” may be drilled 302.

[0066] Figure 6A illustrates an embodiment of a positive side tab 300a that provides an electrical contact to a positive electrical pathway. More particularly, the positive side tab 300a is in direct electrical contact with a lower positive interconnect line 212a to a lower positive electrode tab 210a of the positive metallic electrode 201a of a multilayered structure 205 within the MLCC 200. This is at the bottom surface of the side tab 300a. The top surface of the positive side tab 300a is in contact with a portion of the upper negative metallic interconnect 211b. However, a cut 303a is formed in the upper negative metallic interconnect 211b separating the portion of the upper negative metallic interconnect 211b that is in direct contact with the positive side tab 300a from the portion of the upper negative metallic interconnect 211b that is in direct contact with the upper electrode tab 209b of the negative metallic electrode 201b. Therefore, the positive side tab 300a is electrically isolated from the negative metallic electrodes 201b in the MLCC structure 200.

[0067] Figure 6B illustrates an embodiment of a negative side tab 300b that provides an electrical contact to a negative electrical pathway. Moreparticularly, the negative side tab 300b is in direct electrical contact with an upper negative metallic interconnect 211b to an upper negative electrode tab 209b of the negative metallic electrode 201b of a multilayered structure 205 within the MLCC structure 200. This is at the upper surface of the negative side tab 300b. The bottom surface of the negative side tab 300b is in contact with a portion of the lower positive interconnect 212a. However, a cut 303b is formed in the lower positive interconnect 212a separating the portion of the lower positive interconnect 212a that is in direct contact with the negative side tab 300b from the portion of the lower positive interconnect 212a that is in direct contact with the lower electrode tab 210a of the positive metallic electrode 201a. Therefore, the negative side tab 300b is electrically isolated from the positive metallic electrodes 201a in the MLCC structure 200.

[0068] Figure 6C illustrates a two-component side tab 300c’, 300c”. The upper portion of the two-component side tab 300c’ provides an electrical contact to a negative electrical pathway. More particularly, the upper portion of the two- component side tab 300c’ is in direct electrical contact with an upper negative metallic interconnect 211b to an upper negative electrode tab 209b of the negative metallic electrode 201b of a multilayered structure 205 within the MLCC structure 200. The lower portion of the two-component side tab 300c” provides an electrical contact to a positive electrical pathway. More particularly, the lower portion of the two-component side tab 300c” is in direct electrical contact with a lower positive interconnect 212a to a lower positive electrode tab 210a of the positive metallic electrode 201a of a multilayered structure 205 within the MLCC structure 200. The upper and lower portions of the two- component side tabs 300c’, 300c” are separated by a dielectric fill 303c. The side tabs 300a, 300b, 300c’ and 300c” may be collectively referred to as side tabs having reference number 300.

[0069] Figure 7 illustrates another view of a positive side tab 300a that is described in Figure 6A. Each reference number for elements illustrated in Figure 7 having the same reference number in Figure 6A may be described using the description for the numbered elements made above w ith reference to Figure 6A. In the embodiment depicted in Figure 7, the copper layers having reference numbers 208a, 208b are a part of interconnect betw-een the MLCC structure 200 and the thermal chip too. The interconnect may include a solder pad pattern 208a to solder bond w ith the thermal chip too. In some embodiments, vias 209a are present extending from the metallic interconnects, e.g., upper negativemetallic interconnect 211b, through the upper thermally conductive ceramic interface layer 206, in which the vias 209a provide a power path from the positive and negative interconnects towards the solder ball, e.g., upper C4 ball, providing connectivity to the thermal chip too. In this embodiment, the heat pathway may be downward.

[0070] Referring to Figure 13B, in some other embodiments, the bottom via 209b and copper layers 208c, 2o8d of the lower interface are used when there is at least one bottom heat generating component, e.g., heat-generating device 700, on the bottom side of the electronics package 1000, as depicted in Figure 13A. In some embodiments, vias 209b are present extending from the metallic interconnect, e.g., lower positive metallic interconnect 212a, through the lower thermally conductive ceramic interface layer 207. In this embodiment, the heat path P5 may be upward, as depicted in Figure 13A.

[0071] The MLCC structure 200 depicted in Figures 1-7 can provide a vertical thermal conduction path Pi that extends across the plurality of positive metallic electrodes 201a, and the plurality of negative metallic electrodes 201b of the multilayered structures 205, the upper thermally conductive ceramic interface layer 206, and the lower thermally conductive ceramic interface layer 207. The MLCC structure 200 depicted in Figures 1-7 also provides an electrically conductive path. For example, the MLCC structure 200 includes a plurality of negative metallic electrodes 201b and a plurality of positive metallic electrodes 201a that each include a top electrode tab 209a, 209b and a bottom electrode tab 210a, 210b on opposing ends of each electrode. The plurality of positive electrodes 201a and the plurality of negative electrodes 201b are positioned to have an end-to-end configuration to provide an electrical current path P2 that passes from the top electrode tab to the bottom electrode tab for each electrode and then for a horizontal electrical current path P2 across the end-to-end configuration of the plurality of positive electrodes and negative electrodes. The vertical thermal conduction path Pl is perpendicular to the horizontal electrical current path P2.

[0072] In another aspect, a method of forming a capacitor structure is provided, such as the MLCC structure 200 depicted in Figures 1-7. Figure 8 illustrates an embodiment of a process flow for forming the MLCC structure 200 as depicted in Figures 1-7. It is noted that additional steps, such as additional initial steps, additional intermediate steps, and additional final process stepsmay be applicable to the methods of the present disclosure, which are not specifically depicted in Figure 8. In an embodiment of a process flow for forming the MLCC structure 200, the method may begin with forming multilayered capacitor structures (multilayered structures 205) including a plurality of positive metallic electrodes 201a separated from a plurality of negative metallic electrodes 201b by a dielectric ceramic fill 202 at block 1 of Figure 8. Providing the multilayered structures 205 may include electrode patterning, firing, and dicing. Following the formation of the multilayered structures 205, the multilayered structures 205 and the end tabs 300 may be arranged end-to-end to provide a horizontal electrically conductive path P2.

[0073] In some embodiments, the method may continue with binding the at least one thermally conductive ceramic interface layer 206, 207 on the surface of the multilayered capacitor structures 205. In some embodiments, the thermally conductive ceramic interface layers 206, 207 may be formed by tape casting or powder injection followed by sintering and have a thickness ranging from approximately 50 pm to approximately 750 pm.

[0074] Binding the at least one thermally conductive ceramic interface layers 206, 207 can include patterning sintering pads 208 on a side of the at least one thermally conductive ceramic interface layer 206, 207 at block 2 of Figure 8. In some embodiments, the sintering pads 208 are for binding the internal multilayered structures 205 of the multilayered ceramic capacitor (MLCC) structures 200. In some embodiments, the thermal chip too is solder bonded to the MLCC structures 200 and is an external component. In some embodiments, forming the sintering pads 208 can begin with metallization (e.g., direct bond copper DBG or direct-plated copper DPC) directly on each of the at least one thermally conductive ceramic interface layers 206, 207. In a following step, plated drilled vias may be formed to conductive pads 208. Inner side patterning of the thermally conductive ceramic interface layers 206, 207 may provide the pad area for the sintering pads 209 hosting MLCCs 200.

[0075] Referring to block 3 of Figure 8, the method may continue with silk printing metallic nano-paste on the sintering pads 208. For example, the metallic nano-paste may be composed of a metal, such as silver (Ag). In other examples, the metallic nano-paste may be composed of silver or surface-treated copper. In yet other examples, the metallic nano-paste may consist of micron- size larger particles in addition to nanoparticles. In some embodiments, thediameter for the nanoparticles of silver (Ag) or copper in the metallic nano-paste may range from approximately 5 nm to approximately too nm.

[0076] Referring to Figure 8, at block 4, the method may continue with placing the multilayered structures 205 and side tabs 300 on the at least one thermally conductive ceramic interface layer 206, 207, wherein connections for the plurality of positive electrodes 201a and the plurality of negative electrodes 201b are aligned with the metallic nano-paste. It is noted that the metallic nanopaste following sintering provides the metallic interconnects 211a, 211b, 212a, 212b that provide for electrical contact between the top electrode tabs 209a, 209b and the bottom electrode tabs 210a, 210b on opposing ends of each positive and negative metallic electrode 201a, 201b in the multilayered structures 205.

[0077] Referring to block 5 of the method illustrated in Figure 8, the metallic nano-paste may be sintered at low temperature. In some embodiments, the sintering temperature for the metallic nano-paste to convert the material to metallic interconnects 211a, 211b, 212a, 212b may range from 2OO°C to 4OO°C. In one example, the sintering temperature for the metallic nano-paste to convert the material to metallic interconnects 211a, 211b, 212a, 212b may be equal to 300 °C. During the sintering process, pressure may also be applied to press the thermally conductive ceramic interface layers 206, 207 to the multilayered structures 205, and the side tabs 300. The pressure applied to press the thermally conductive ceramic interface layers 206, 207 to the multilayered structures 205 and side tabs 300 may range from 1 MPa to 10 MPa. In one example, the pressure applied to press the thermally conductive ceramic interface layers 206, 207 to the multilayered structures 205 and side tabs 300 may be equal to 5 MPa.

[0078] Nanoscale metal particles, such as the silver nanoparticles in the metallic nano-paste, densify under modest temperature and pressure forming metallurgical bonds, e.g., forming the metallic interconnects 211a, 211b, 212a, 212b. For example, a metallic nano-paste may be densified to 80% density following the application of pressure equal to 5 MPa at a sintering temperature of 300 °C. Following sintering, once the metallic powder of the nano-paste densifies, the metallic powder is stable and will not melt again.

[0079] In some embodiments, after the thermally conductive ceramic interface layers 206, 207 are bound to the multilayered structures 205 and the side tabs 300, a plurality of vias may be formed to the plurality of positiveelectrodes 201a and plurality of negative electrodes 201b, the vias composed of a conductive material, such as a metal, extending through the at least one thermally conductive ceramic interface layer 206, 207.

[0080] In some embodiments, following binding of the thermally conductive ceramic interface layers 206, 207 to the multilayered structures 205 and the side tabs 300, a resin fill (resin 301) is applied to fill gaps between the adjacent multilayered structures 205. In some embodiments, the resin 301 can improve reliability under chemical and physical stresses. In some examples, liquid resin (viscous fluid) is forced to flow using an injection mold and to fill the clearance gaps between adjacent multilayered structures 205 or between the edge multilayered structures 205 and external leads, such as the side tabs 300. Once cooled, the liquid resin can form a hermetic seal to protect the inner elements of the MLCC structure 200 from chemicals and reduce the stress in the sintering joints. In some embodiments, portions of the resin and the thermally conductive ceramic interface layers 206, 207 may be removed from the side tabs 300. For example, the resin and thermally conductive ceramic interface layers 206, 207 may be removed from the side tabs 300 using mechanical grinding and / or laser processes / ablation.

[0081] The MLCC structure 200 described with reference to Figures 1-8 may be used with an integrated chip for dissipating heat from a thermal chip too in a package including one or more printed circuit board (PCB) substrates.Integrated circuit (IC) packages typically bind a thermal chip too, such as a silicon-based chip, to a printed circuit board (PCB) substrate, which in some examples can include solder bonding, such as C4 ball solder bonding, e.g., bonding of the thermal chip to the printed circuit board (PCB) using a fine-pitch solder array. The printed circuit boards (PCBs) and solder bonded assemblies can be thermal barriers, e.g., structures having low heat conductivity, for dissipating heat, such as heat generated by the thermal chip. In some embodiments, the aforementioned thermal barriers can be mitigated or overcome using the structures and methods described herein. For example, additional thermal cooling can be applied to the backside of the thermal chip too via backside contact using the MLCC 200 structure to provide a vertical heat transfer path Pl from the thermal chip too extending through the conductive ceramic interface layers 206, 207 and the vertically oriented positive and negative metallic electrodes 201a, 201b. The vertical heat path Pi may be ineither an upward direction (as illustrated by P5 in Figure 13A) or downward direction depending upon the application.

[0082] In some embodiments, to eliminate the thermal barriers, the methods and structures described herein can embed the MLCC structures 200 described with references to Figures 1-8 in a void that is formed through a first printed circuit board (PCB) 400, in which the thermally conductive ceramic interface layers 206 touch the backside surface of the thermal chip too. The void section of the printed circuit board (PCB) 400 is dimensioned to accommodate the MLCC structure 200, which allows the vertical heat transfer path Pl of the MLCC structure 200 to directly touch the heat generating part, e.g., a thermal chip too. Further, the MLCC structure 200 can provide for transmission of electrical current between the thermal chip too and the first printed circuit board 400. For example, the power current route P3 for powering the MLCC structure 200 is routed from the printed circuit board (PCB) 400 through the MLCC structure 200. IO signals 407 are dense wires that are routed within the printed circuit board (PCB) 400. The IO signals 407 are intended to show the IO routing direction that connects from the electronic die towards the first PCB edge directly, without passing through the MLCC structure.

[0083] Figures 9-11 illustrate some embodiments of an electronics package 1000 including an MLCC structure 200 with a thermally conductive ceramic interface layer 206 that is beneath and in contact with a thermal chip too for enhancing heat dissipation from the thermal chip too and for delivering power to the thermal chip too. In some embodiments, the thermally conductive ceramic interface layer 206 is a ceramic material with high heat conductivity for transferring heat vertically from the thermal chip too along the height direction of the MLCC structure 200. The heat path may be downward. The electronics package 1000 also includes at least one ceramic material, e.g., dielectric ceramic fill 202 within the multilayered structures 205, with a high relative permittivity, e.g., Er> 1000, for forming multilayer capacitors for power rail decoupling and handling high transient currents. The electronics package 1000 also includes at least one metal material of high thermal and electrical conductivity forming the electrodes, e.g., the positive metallic electrode 201a and the negative metallic electrode 201b, of the multilayer (multilayer structure 205) capacitor. In the embodiments described herein, the electrodes are employed for providing a current path for power delivery and for providing a heat path for vertical heat transfer Pt (upwards or downwards). The electronics package 1000 alsoincludes at least one metal material of high electrical conductivity, forming an interconnect between the logic IC pads (bumps, balls) 208 and the multilayer capacitor electrodes 201a, 201b. The electronics package 1000 can also include an interconnect, e.g., side tab 300, between at least one multilayer capacitor electrodes 201a, 201b and a polymer resin-based IC package section, e.g., printed circuit board (PCB) 400. In some embodiments, the electronics package 1000 can also include at least one polymer resin-based filler 301 for insulation, gap filling and / or mechanical stress relief.

[0084] Figures 9-11 illustrate an embodiment of an electronics package 1000 that includes a thermal chip too; a first printed circuit board 400 having a first opening 405; and a capacitor structure, e.g., MLCC structure 200, positioned in the first opening 405 in the first printed circuit board 400. The thermal chip too may be any electrical component that generates heat. For example, the thermal chip too may be a semiconductor die including an integrated circuit (IC) on a type IV semiconductor substrate, e.g., silicon substrate, or type III-V semiconductor substrate, e.g., gallium arsenide (GaAs) substrate. The integrated circuit may include metal lines, metal vias, transistors (such as field-effect transistors) and passive electrical devices, such as capacitors and resistors. The semiconductor die may also include memory devices. In some embodiments, the thermal chip too may be a 2.5D or 3D package including logic chips and high- bandwidth memory (HBM) components that is present on an interposer including a redistribution layer, in which the interposer is present on a supporting substrate.

[0085] In some embodiments, the first printed circuit board (PCB) 400 includes the first opening 405, in which the first opening 405 is dimensioned to allow for the MLCC structure 200 to be positioned therein so that the MLCC structure 200 can directly contact the backside surface of the thermal chip too. The thermal chip too is positioned directly over the first opening 405. A printed circuit board (PCB) is an electronic assembly that uses copper conductors to create electrical connections between components. A PCB includes multiple insulation and conductive layers. PCBs also provide mechanical support for electronic components so that a device can be mounted in an enclosure. PCBs are built from alternating layers of conductive metals, such as copper and / or aluminum, with layers of electrically insulating material.[oo86] Conductive features on printed circuit boards include copper traces, pads, and conductive planes. The mechanical structure is made up of the insulating material laminated between the layers of conductors. In some embodiments, the base material for the insulating material of the printed circuit board comprises porcelain, mica, glass, plastics, metal oxides, and combinations thereof. In some embodiments, the insulating material for the printed circuit board may be FR4. The conductive features may be composed of a metal, such as copper, aluminum, nickel, titanium, silver, molybdenum (Mo), tungsten (W), or combinations thereof.

[0087] For example, the PCB may be laminated from a core with two sides. For example, as will further be described with reference to Figures 13-16, the first printed circuit board 400 may include a core printed circuit board (PCB) layer 415, and external printed circuit board (PCB) layers 416, 417 laminated to the core layer. PCBs can include vertical interconnects. One example of a vertical interconnect in a PCB may be a plated through hole (PTH). A plated through hole is typically the last formed vertical interconnect in a PCB, and typically occupies space in all layers of the PCB. Other examples of vertical interconnects in PCBs can include buried holes and micro-vias, which can each be formed using drilling and plating steps.

[0088] Still referring to Figures 9-11, the capacitor structure, e.g., MLCC structure 200, includes a positive electrode 201a separated from a negative electrode 201b by a dielectric fill 202 to provide a multilayered structure 205 and includes at least an upper thermally conductive ceramic layer 206 on a first (upper) surface of the multilayered structure 205 providing a thermal interface between the multilayered structure 205 and the thermal chip too. The MLCC structure 200 and its components, such as the upper thermally conductive ceramic layer 206, have been described above with reference to Figures 1-8. The above description of the MLCC structure 200 depicted in Figures 1-8 is suitable for describing the elements of the MLCC structure 200 as integrated into the electronics package 1000 that is depicted in Figures 9-11. Therefore, elements having reference numbers in Figures 9-11 that are the same as elements having the same reference numbers in Figures 1-8 are the same, and the description for the elements in Figures 1-8 is suitable for describing the elements having the same reference numbers in Figures 9-11. For example, the first (upper) thermally conductive ceramic layer 206 may be comprised of a ceramic material having a thermal conductivity of 50 W / (m-K) or greater. Further, the MLCCstructure 200 depicted in Figures 9-11 may include a second thermally conductive ceramic layer 207 on a second (bottom) surface of the multilayered structure 205. In some embodiments, at least one first (upper) thermally conductive ceramic interface layer 206 and the second (lower) thermally conductive layer 207 includes a composition selected from the group consisting of aluminum nitride, diamond-like carbon (DLC), beryllium oxide (BeO), silicon carbide (SiC), boron nitride (BN), copper aluminum oxide (CUA1O2), and combinations thereof.

[0089] Figures 9-11 also illustrate a second printed circuit board 450 having a second opening, and a backside heat sink 500 contacting the second thermally conductive layer, wherein the backside heat sink 500 is housed within the second opening. The second printed circuit board 450 is similar to the first printed circuit board 400. Some embodiments of the backside heat sink 500 are later described below with reference to Figure 17.

[0090] As described above, the MLCC structure 200 can provide a thermal conductive pathway Pl, which in the embodiment depicted in Figures 9-11 can extend from the backside of the thermal chip too that is in contact with the first (upper) thermally conductive ceramic interface layer 206 of the MLCC structure 200 to the heat sink 500 that is in contact with the backside surface of the second (lower) thermally conductive ceramic interface layer 207. The thermal pathway Pl across the MLCC structure 200 is via the positive and negative metallic electrodes 201a, 201b.

[0091] Still referring to Figures 9-11, the electronics package 1000 further includes an MLCC structure 200 that includes side tabs 300 and electrically connected positive and negative metallic electrodes 201a, 201b, which can transmit the supply voltage (Vdd) received from the first printed circuit board (PCB) 400 to the thermal chip 100. The current pathway for the supply voltage (Vdd) is depicted by reference number P3 in Figure 11. The path identified by reference number 407 is input / output (I / O) signal. In some examples, the current pathway for the supply voltage (Vdd), including the positive and negative current pathways, is received at the side tabs 300, as depicted in Figures 6A-6C.

[0092] Figure 11 illustrates the current pathway for the supply voltage (Vdd) traveling through the MLCC structure 200. Following entry into the MLCC structure 200 through the side tabs 300, the current for the supply voltage (Vdd) can then propagate through the multilayered structure 205 that has beenadjacently positioned end-to-end. For example, the positive metallic electrodes 201a of the capacitor structure, e.g., multilayered structure 205, are configured to provide a positive electrical current path for the supply voltage (Vdd) extending from the first printed circuit board (PCB) 400 across the capacitor structures, e.g., multilayered structures 205, to the thermal chip too. For example, the negative electrodes 201b of the capacitor structure, e.g., multilayered structure 205, are configured to provide a negative electrical current path for ground extending from the first printed circuit board 400 across the capacitor structures, e.g., MLCC structure 200, to the thermal chip too. More particularly referring to Figure 4, the positive electrical pathways through the positive metallic electrodes 201a are illustrated by reference numbers 213a, 213b for the supply voltage (Vdd), and the negative electrical pathways through the negative metallic electrodes 201b are illustrated by reference numbers 214a, 214b.

[0093] One example of a positive current pathway for the supply voltage (Vdd) can include starting at an upper positive electrode tab 209a of a positive metallic electrode 201a of a first multilayered structure 205, in which a positive current is passed by a positive metallic interconnect 211a to an upper positive electrode tab 209a of a positive metallic electrode 201a of an adjacently end-to- end positioned second multilayered structure 205. This portion of the positive current pathway is illustrated by reference number 213a. From that point, the positive current pathway includes a current pathway that is passed from the upper positive electrode tab 209a to a lower positive electrode tab 210a of the same positive metallic electrode 201a. From the lower positive electrode 210a of the positive metallic electrode 201a of the second multilayered structure 205, the positive current path can then extend horizontally again from the lower positive electrode tab 210a of the positive metallic electrode 201a of the second multilayered structure 205 to an adjacently end-to-end positioned third multilayered structure 205. For example, the positive current is passed by a lower positive interconnect line 212a to a lower positive electrode tab 210a of the positive metallic electrode 201a of an adjacently end-to-end positioned second multilayered structure 205.

[0094] Referring to Figures 11 and 12, the positive supply voltage path P3 may then extend from the MLCC structure 200 to the thermal chip too. Referring to Figure 12, in an embodiment, the positive supply voltage path P3 may extend through an opening in the first (upper) thermally conductive ceramic interfacelayer 206 into electrical contact with the thermal chip too. It is noted that the thermally conductive interface layer 206 is electrically insulating. To provide for electrical conduction between the MLCC structure 200 and the thermal chip too, vertical vias 209a of electrically conductive metal may extend through the first (upper) thermally conductive ceramic interface layer 206, as depicted in Figure 7. The vertical vias 209 provide for electrical contact between the contact pads 208 on the upper surface of the upper thermally conductive ceramic interface layer 206 and the metallic interconnect 211a, 211b. The contact pads 208 are in electrical contact with the solder bonds 105 that provide electrical connectivity to the thermal chip too. The metallic interconnect 211a, 211b are in electrical contact with the positive metallic electrode 201a and the negative metallic electrode 201b of the MLCC structure 200.

[0095] The positive electrodes 201a are separated from a negative metallic electrode 201b by a dielectric ceramic fill 202 to provide a multilayered structure, e.g., capacitor. For example, dielectric ceramic fill 202 has a relative permittivity greater than 1000. The multilayered structures 205 of positive electrodes 201a, dielectric ceramic fill 202, and negative electrodes 201b are electrically connected through the vertical vias 209a and solder bonds 105 to the thermal chips too, and can provide decoupling capacitors.

[0096] Figures 13A-13B illustrate an electronics package 1000 that, in addition to the thermal chip too and the MLCC structure 200, further includes a backside heat-generating device 700 contacting the second thermally conductive layer 207 at the backside of the MLCC structure 200. In some embodiments, the thermal chip too is a frontside device, wherein the electronics package 1000 further includes a backside heat-generating device 700 contacting the second thermally conductive layer 207. In some embodiments, the backside heatgenerating device 700 produces greater heat than the frontside device, wherein heat from the backside heat-generating device 700 is conducted through the capacitor structure, e.g., MLCC structure 200, to the frontside device to be dissipated. This is an example of an upward heat path P5. In some embodiments, a frontside heat sink contacts an upper surface of the thermal chip too that provides the frontside device.

[0097] In some embodiments, when the heat travels upwards, e.g., via the upward heat path P5, the electronics package 1000 can cool the internal heat source in the substrate section that includes the MLCC structure 200. In someembodiments, the backside heat-generating device 700 may include semiconductor or magnetic devices. For example, the backside heat-generating device 700 can include components and materials, such as inductors, ferromagnetic materials, active power electronics, and / or semiconductors, such as Si, GaN, GaAs, SiC and combinations thereof. The methods, structures and materials for the MLCC structure 200 integrated with the electronics package 1000 depicted in Figures 13A and 13B can establish efficient horizontal & vertical current path and vertical thermal path.

[0098] In some embodiments, to dissipate the heat received from the upward heat flow P5 at the thermal chip too, top coolers and / or side coolers may be integrated into the structure including the thermal chip too.

[0099] In some embodiments, the applications for the structure depicted in Figures 13A and 13B may include portable electronics, such as laptops, tablet computers, phones (smartphones), augmented reality (AR), virtual reality (VR) and similar electrical devices having a thickness less than 50 mm.

[0100] In another aspect, a method of forming an electronics package 1000 is provided that includes forming a first printed circuit board 400 having a first opening; and positioning a thermal die chip's backside surface over the first opening 405; and contacting the backside surface of the thermal chip too with a capacitor structure, e.g., MLCC structure 200. In some embodiments, the capacitor structure, e.g., MLCC structure 200, is positioned within the first opening 405 in the first printed circuit board 400. In some embodiments, the capacitor structure, e.g., MLCC structure 200, includes a positive electrode 201a separated from a negative electrode 201b by a dielectric ceramic fill 202 to provide a multilayered structure 205, and a first thermally conductive layer 206 on a first surface of the multilayered structure 205 provides a thermal interface between the capacitor structure, MLCC structure 200, and the thermal chip too, wherein the first thermally conductive layer 206 is comprised of a ceramic material having a thermal conductivity of 50 W / (m-K) or greater. In some embodiments, the capacitor structure, e.g., MLCC structure 200, provides for power rail decoupling and controlling high transient currents for the electronics package 1000. In some embodiments, the capacitor structure, e.g., MLCC structure 200, provides a thermal conduction path Pi from the backside of the thermal chip through the first thermally conductive layer 206 to the positiveelectrodes 201a and the negative electrodes 201b of the capacitor structure, e.g., MLCC structure 200.

[0101] In another aspect, the side tabs 300 of the MLCC structure 200 also provide for a mechanical interconnect between the MLCC structure 200 and the first printed circuit board (PCB) 400 through lamination methods, as illustrated in Figures 14-17.

[0102] In one embodiment, the side tabs 300 of the MLCC structure 200 maybe integrated into a package 1000 including at least the first printed circuit board 400, as depicted in Figures 8-17. In addition to the side tabs 300, the MLCC structure 200 can include a plurality of positive metallic electrodes 201a and a plurality of negative metallic electrodes 201b. The plurality of positive metallic electrodes 201a having a lower positive electrode tab 210a at a first side51 of the positive metallic electrode 201a, and an upper positive electrode tab 209a at a second side S2 of the positive metallic electrode 201a. The plurality of negative electrodes 201b having an upper negative electrode tab 209b at a first side Si of the electrode and a lower negative electrode tab 210b at a second side52 of the electrode. The positive and negative electrodes 201a, 201b are connected to the side tabs 300 through metallic interconnects 211a, 211b, 212a, 212b. For example, for the upper electrode tabs 209a, 209b, a first set of metallic interconnects 211a, 211b is on a top surface of the capacitor, e.g., multilayered 205, structure, the first set of metallic interconnects 211a, 211b including a first portion of the first set of metal interconnects 211b connecting each adjacent upper negative electrode tab 209b and a separate second portion of the first metallic interconnects 211a connecting each adjacent upper positive electrode tab 209a. Similarly, for the lower electrode tabs 210a, 210b, a second set of metallic interconnects 212a, 212b is on a bottom surface of the multilayer structure 205, the second set of interconnect lines including a first portion of the second set of metallic interconnects 212b connecting each adjacent lower negative electrode tab 210b and a separate second portion of the second set of metallic interconnects 212a connecting each adjacent lower positive electrode tab 210a.

[0103] The side tabs 300 are positioned at the ends of the string of electrically connected multilayered structures 205 and are in electrical contact with the metallic interconnect lines 211a, 211b, 212a, 212b. The first (upper) thermally conductive ceramic interface layer 206 is between the multilayered structure 205and the first set of interconnect lines 211a, 211b. The second (lower) thermally conductive ceramic interface layer 207 is between the multilayered structure 205 and the second set of interconnect lines 212a, 212b. The first and second thermally conductive interface layers extend over an inner portion (first portion 305) of the side tabs 300 leaving an exterior portion (second portion 306) of the side tabs 300 that is free of the first and second (upper and lower) thermally conductive interface layers 206, 207.

[0104] The MLCC structure 200 including the side tabs 300 is positioned within the hole 405 in the first printed circuit board 400, and is secured to the first printed circuit board (400) using the lamination method described with reference to Figures 13-16. For example, the MLCC structure 200 can be fixed to the sidewalls of the opening 405 in the first printed circuit board (PCB) 400 by lamination. In some embodiments, the side tabs 300 have a substantially same height as the core printed circuit board (PCB) layer 415 for the first printed circuit board (PCB) 400. During the lamination process, exterior printed circuit board (PCB) layers 416, 417 are laminated to the core printed circuit board (PCB) layer 415, which substantially matches the height of the whole MLCC structure 200. To apply pressure during lamination, the structure can be clamped in a mechanical fixture. Micro-vias and buried vias (castellated) are used to form electrical connections between PCB power planes and side tabs 300.

[0105] At the conclusion of the lamination process, the side tabs 300 of the MLCC structure 200 are embedded into the portions of the first printed circuit board 400 within the opening 405. In summation, the lamination process to embed the side tabs 300 into the first printed circuit board (PCB) 400 can include: side tab preparation, lamination, plated holes fabrication, and surface machining.

[0106] Figure 14 illustrates an embodiment of preparation of side tabs 300 from the MLCC structure 200 to embed the side tabs 200 into the sidewalls of the first printed circuit board (PCB) 200 using lamination. In some embodiments, a method of securing the MLCC structure 200 to the first printed circuit board (PCB) 400 can include electrically connecting a plurality of end-to- end arranged multilayered structures 205 of positive electrodes 201a and negative electrodes 201b separated by a dielectric ceramic fill 202. The MLCC structure 200 and its components, such as the upper thermally conductive ceramic layer 206, have been described above with reference to Figures 1-8. Theabove description of the MLCC structure 200 depicted in Figures 1-8 is suitable for describing the elements of the MLCC structure 200 included in the methods described with reference to Figures 14-17. Therefore, elements having reference numbers in Figures 14-17 that are the same as elements having the same reference numbers in Figures 1-8 are the same, and the description for the elements in Figures 1-8 are suitable for describing the elements having the same reference numbers in Figures 14-17. For example, the first (upper) thermally conductive ceramic layer 206 may be comprised of a ceramic material having a thermal conductivity of 50 W / (m-K) or greater.

[0107] It is noted that the side tabs 300 depicted in Figures 14-17 may have any geometry as depicted in Figures 6A-6C.

[0108] Preparing the side tabs 300 can further include electrically connecting side tabs 300 at each end of the plurality of end-to end arranged multilayered structures 205, and forming a thermally conductive ceramic layer 206, 207 on at least one of the upper and lower surfaces of the plurality of end-to-end arranged multilayered structures 205. In some embodiments, the thermally conductive ceramic layer 206, 207 extends onto a first portion 305 of the side tabs 300 and does not extend onto a second portion 306 of the side tabs 300. The thermally conductive ceramic layer 206, 207 is removed from the second portion 306 of the side tabs 300 that are drilled to provide vertical interconnects, e.g., vias. It has been determined that drilling can damage the ceramic material, e.g., aluminum nitride, of the side tabs 300. Removing the thermally conductive ceramic interface layers 206, 207 from the side tabs 300 may include mechanical grinding and / or laser processes / ablation. In some embodiments, a CNC mill can remove the extra coating materials around the side tab 300 and expose the second (exterior) portion 306 of the side tab 300. In some embodiments, chemical treatment (browning) may be applied to at least the second portion 306 of the side tab 300 for a surface suitable for lamination. In some embodiments, a partial printed circuit board (PCB) laminate is formed to bind the structure temporarily with adhesive. In some examples, the adhesive fills all air gaps in between the multilayered structures 205 of the MLCC structures 200.

[0109] In some embodiments, through vias 307 can then be formed through the second portion 306 of the side tabs 300. The through vias 307 may be fabricated by drilling, e.g., drilling holes through the second portion 306 of the side tabs 300, and by filling the holes with an electrically conductive material.In an embodiment, the holes formed through the second portion 306 of the side tabs 300 may be filled using a plating process, and the electrically conductive material may be a metal, such as copper (Cu), aluminum (Al), silver (Ag), titanium (Ti) and combinations thereof. The through vias 307 can provide an electrical connection between the side tabs 300 of the MLCC structure 200 and the metal lines of the first printed circuit board (PCB) 400.

[0110] In some embodiments, following preparation of the side tabs 300, the MLCC structure 200 may be positioned in the opening 405 in the core printed circuit board layer 415 of the first printed circuit board (PCB) 400, and exterior printed circuit board layers 416, 417 are laminated onto the core printed circuit board layer 415 and the second portion 306 of the side tabs 300, as depicted in Figure 14. The exterior printed circuit board layers 416, 417 include metal lines within a printed circuit board dielectric. A portion of the upper exterior printed circuit board layer 416 extends to cover the upper surface of the second portion 306 of the side tab 300. A portion of the lower exterior printed circuit board layer 417 extends to cover the lower surface of the second portion 306 of the side tab 300. By covering the previously exposed second portion 306 of the side tab 300 in the material of the upper and lower exterior printed circuit board (PCB) layers 416, 417, the second portion 306 of the side tab 300 is embedded within the material of the first printed circuit board (PCB) 400. This ensures that laminating the exterior printed circuit board layers 416, 417 onto the core printed circuit board layer 415 and the second portion 306 of the side tabs 300 mechanically secures the MLCC structure 200 to the first printed circuit board 400.

[0111] In some embodiments, electrical pathways in the exterior printed circuit board layer 416, 417 are in electrical contact with the via connections, e.g., through via 307, in the second portion 306 of the side tabs 300. In some embodiments, lamination of the exterior printed circuit board layer 416, 417 to the core printed circuit board 415 includes applying an epoxy to engage the exterior printed circuit board layer 416, 417 to the core printed circuit board 415.

[0112] In some embodiments, the exterior printed circuit board (PCB) layers 416, 417 of the first printed circuit board (PCB) 400 are laminated at a raised temperature and pressure with the existing partial PCB, e.g., the core printed circuit board (PCB) layer 415. For example, the temperature of the laminatingprocess may range from 125 °C to 300 °C. For example, the pressure of the laminating process may range from 5 MPa to 30 MPa.

[0113] Referring to Figure 15, in some embodiments, after laminating the exterior printed circuit board (PCB) layers 416, 417 to the core printed circuit board (PCB) layer 415, micro-vias 308 may be formed connecting metal lines from the exterior printed circuit board (PCB) layers 415 to the second portion 306 of the side tab 300. The micro-vias 308 may be formed by drilling openings through the material of the exterior printed circuit board (PCB) layer 416, 417, and then filling the openings with an electrically conductive material. For example, the micro-vias 308 may be fabricated after lamination of each layer using laser drilling and electroplating. In some examples, the micro-vias 308 can provide for connecting the power planes from the exterior printed circuit board (PCB) layers 416, 417 to the metallic side tab 300.

[0114] Figure 16 illustrates an embodiment of post printed circuit board (PCB) processes. For example, Figure 16 illustrates machining of the exterior surfaces of the printed circuit board (PCB) exterior layers 416, 417. Machining the exterior surfaces can include removing excess resin coating from embedded components and removing resin spillage during lamination. Machining the exterior surfaces of the printed circuit board (PCB) exterior layers 416, 417 can also include compensating for height errors of embedded components to form a flat surface suitable for soldering. Figure 16 further illustrates exterior layer patterning to define the top circuitry and C4 ball solder pads in both PCB and ceramic parts, e.g., thermally conductive ceramic interface layers 206, 207. The patterning at this stage of the process flow can define the motherboard connections.

[0115] Figure 17 illustrates an embodiment of final assembly for the printed circuit board (PCB), e.g., the first printed circuit board (PCB) 400. Final assembly may include bonding of the thermal chip too to the first printed circuit board (PCB) 400 and the MLCC structure 200. For example, solder bonds 105 may be formed bonding the thermal chip too to the first printed circuit board (PCB) 400 and the MLCC structure 200. Additionally, solder balls 106, such as a ball grid array (BGA), may be formed on the opposing backside of the first printed circuit board (PCB) 400. In some embodiments, the structure may be applied to a reflow process for the solder of the package, and an underfill (not depicted) may be applied. In some embodiments, the bottom surface of thethermally conductive ceramic interface layers 207 may be further processed to ensure a flat surface for interfacing with a thermal sink 500, e.g., a cold plate. For example, coolant channels can be directly formed within thermally conductive ceramic interface layers 207 to further reduce thermal resistance.

[0116] The method described with reference to Figures 14-17 can provide a connection structure for embedding a ceramic substrate, e.g., the thermally conductive ceramic interface layers 206, 207, into an organic substrate, e.g., the first printed circuit board (PCB) 400.

[0117] In yet another aspect of the present disclosure, a heat sink 500 is described, which may be integrated with the lower thermally conductive ceramic interface layer 207. Figures 18-20 illustrate an embodiment of a heat sink 500 that includes an interface layer 501 of ceramic material and a manifold body 510, in which the manifold body 510 is bonded to the interface layer 501 using an adhesive layer 505. The heat sink 500 may be integrated into the lower thermally conductive interface layer 207 of the MLCC structure 200 as integrated into the electronics package 1000 as depicted in Figure 11. It is noted that the heat sink 500 does not necessarily have to be integrated into the lower thermally conductive layer 207 of the MLCC structure 200. Other embodiments have been contemplated in which the interface layer 501 of the heat sink is provided by a ceramic material having a thermal conductivity of 50 W / (m-K) or greater.

[0118] The interface layer 501 is intended to be in contact with a heat source. The interface layer 501 is composed of a thermally conductive material for transferring the heat from the heat source contacting one side of the interface layer 501 to a coolant source that contacts the opposing side of the interface layer 501. For the purposes of providing the interface layer 501 of the heat sink 500, the interface layer 501 includes cooling channels defined by cooling walls 502 extending from a surface of the interface layer 501. In some embodiments, the cooling walls 502 are integral with the interface layer 501 of the ceramic material. In some embodiments, the plurality of coolant channels have a width and height dimension each ranging from 10 microns to 500 microns. In some embodiments, the cooling walls 502 may be machined into the base material of the interface layer 501. In some embodiments, the cooling walls 502 may provide microchannels that are formed into the interface layer 501 by mechanical, laser, or plasma engraving. In some embodiments, the cooling walls502 can be formed using powder injection formation. Ceramic powder injection forming combines ceramic powder with a binder to create a feedstock. This mixture is injected into molds under high pressure to form complex shapes, such as the cooling walls 502. After molding, the binder is removed through debinding, followed by sintering to densify and harden the final ceramic part. It is noted that any material that has been described above for the thermally conductive ceramic interface layers 206, 207 of the MLCC structure 200 is suitable for use as the interface layer 501 of the heat sink 500.

[0119] The heat sink 500 also includes a manifold body 510 having an inlet and an outlet for coolant to the plurality of coolant channels in the interface layer 501. The manifold body 510 includes a plurality of coolant passages 507 in communication with the inlet 506 and the outlet 507. In some embodiments, the manifold body 510 is composed of a material having a low thermal conductivity. In some embodiments, by constructing the manifold body 510 of a low thermal conductivity material, the heat sink design can avoid premature heating of the inlet coolants by neighboring coolant passages 507. The material of the manifold body 510 may be selected to have a thermal conductivity of less than 10 W / (m-K). In some examples, the manifold body 510 is composed of liquid crystal polymer, polyimide, and / or epoxy, with or without fiberglass reinforcement. In some examples, the manifold body 510 is composed of epoxy polymer, polyurethane, silicone, buna-n rubber, or FKM rubber. The manifold body 510 may have a thickness ranging from to microns to too microns.

[0120] The manifold body 510 may be engaged to the lower thermally conductive interface layer 207 using an adhesion method that prevents premature coolant escaping before heat exchange. The manifold body 510 is installed onto the lower thermally conductive interface layer 207 under modest conditions. For example, the temperature at which bonding may be performed can range from 10 °C to 150 °C. For example, the pressure at which bonding may be performed can range from 0.02 MPa to 1 MPa. The manifold body 510 is installed after the fragile package 1000 including the thermal chip too and MLCC structure 200 has been built. Therefore, the process conditions for bonding the manifold body 510 to the lower thermally conductive interface layer 207 cannot negatively impact the already assembled portions of the package 1000. In some embodiments, the manifold interface is flat to bind with the lower thermally conductive interface layer 207, providing a uniform seal without blocking coolant flow.

[0121] The heat sink 500 further includes the adhesive layer 505 between the interface layer 501 of the ceramic material and the manifold body 510. In some embodiments, the adhesive layer 505 is patterned for precise bonding between a microchannel cooler, e.g., interface layer 501, and manifold body 510. In some examples, the adhesive layer 505 is composed of epoxy polymer, polyurethane, silicone, buna-n rubber, FKM rubber. The adhesive layer 505 may have a thickness ranging from 10 microns to too microns.

[0122] The adhesive layer 505 can provide for bonding between the interface layer 501 and the manifold body 510 under modest pressure and temperature. For example, the temperature at which bonding may be performed can range from io°C to 15O°C. For example, the pressure at which bonding may be performed can range from 0.02 MPa to 1 MPa. The adhesive layer 505 can be applied by layer transfer. For example, the adhesive layer may be transferred onto the manifold body 510 from a liner material, which can function as a temporary supporting substrate.

[0123] In some embodiments, forming the adhesive layer 505 on the liner material may include a uniform coating of the adhesive material on the liner material, in which the liner material provides a supporting substrate prior to transfer of the adhesive layer 505 to the manifold body 510. The uniform coating may be deposited by spin coating and / or doctor blade coating. The doctor blade coating process involves spreading a liquid adhesive uniformly over the liner using a precise blade set at a specific gap. The blade's pressure and movement control the adhesive's thickness, ensuring an even coating for consistent adhesive film formation. In a following step, the coating for the adhesive layer 505 may be patterned for engagement to the geometry of the manifold body 510. Patterning can include forming cut-outs corresponding to the coolant channel on the manifold body 510. For example, the adhesive layer 505 can be patterned for cut-outs corresponding to the manifold inlet / outlet shape of the manifold body 510. In some embodiments, following patterning, an optional pre-drying step under controlled temperature and atmosphere may be applied to the patterned adhesive layer.

[0124] Following patterning, and optional pre-drying, the adhesive layer 505 may be applied to the manifold body 510. In some embodiments, the supporting liner can be peeled off after application of the adhesive layer 505 to the surface of the manifold body 510. The adhesive layer 505 has two bonding surfaces.Following bonding of the first bonding surface of the adhesive layer 505 to the manifold body 510, removing the supporting liner exposes the second bonding surface. The second bonding surface of the adhesive layer 505 is applied to the interface layer 501, while the first bonding surface of the adhesive layer 505 is engaged to the manifold body 510. Bonding between the microchannel surface of the interface layer 501 and the manifold body 510 through the adhesive layer 505 is done under modest pressure and temperature. For example, the temperature at which bonding may be performed can range from 10 °C to 150 °C.

[0125] For adhesive materials that are organic, the bonding strength can be further enhanced by a curing process. The curing process can be performed by changing, e.g., increasing, temperature. For raised temperature curing, the adhesive layer 505 starts polymerization / crosslinking when the ambient temperature reaches a threshold. The curing process can also be performed by adjusting moisture in the adhesive layer 505. In some embodiments, by adjusting moisture, e.g., humidity, the adhesive starts polymerization / crosslinking when there are enough water molecules to be absorbed from the ambient to start the reaction. The curing process can also be performed with the application of a catalyst.

[0126] Once cured, the adhesive layer 505 may stay stable under the specified coolant being massed through the passages of the manifold body 510 and across the cooling channels of the interface layer 501. The coolant may include water, glycol, mixtures of water and glycol, and fluorinated liquids.

[0127] As noted, in one application the heat sink 500 depicted in Figure 17 may be applied to the electronics package 1000 depicted in Figure 11. In some embodiments, the lower thermally conductive ceramic interface layers 207 of the MLCC structure 200 may provide the ceramic interface layer 501, and the MLCC structure 200 may provide the structure that includes the heat pathway that is being cooled by the heat sink 500. In an embodiment, the method for cooling an electronic package 1000 can include contacting a surface of a heat producing component, e.g., thermal chip too, with a capacitor structure, e.g., MLCC structure 200. The capacitor structure includes a positive electrode 201a separated from a negative electrode 201b by a dielectric fill 202 to provide a multilayered structure 205. In some embodiments, a first thermally conductive ceramic layer 206 is on a first surface of the multilayered structure 205 providing a thermal interface between the capacitor structure, e.g., MLCCstructure 200, and the heat producing component, e.g., thermal chip too. In some embodiments, the capacitor structure, e.g., MLCC structure 200, also includes a second thermally conductive ceramic layer 207 on a second surface of the multilayered structure 205 that is opposite the first surface of the multilayered structure 205 that the first thermally conductive ceramic layer 206 is on. The second thermally conductive ceramic layer 207 provides the interface layer 501 of the heat sink 500. In some embodiments, at least one of the first thermally conductive ceramic layer 206 and the second thermally conductive ceramic layer 207 is comprised of a ceramic material having a thermal conductivity of 50 W / (m-K) or greater.

[0128] To provide the heat sink 500 for dissipating heat from the vertical heat path Pt through the MLCC structure 200, a manifold body 510 is bonded to the second (lower) thermally conductive ceramic layer 207 of the capacitor structure, e.g., MLCC structure 200. In some embodiments, the second thermally conductive ceramic layer 207 has been processed, e.g., machined, to include a plurality of cooling walls 502 that extend into the manifold body 510 to define the cooling channels of the interface layer 501.

[0129] In one embodiment, bonding the manifold body 510 to the second thermally conductive ceramic layer 207 includes forming a uniform coating of an adhesive material on a transfer substrate, e.g., liner. The uniform coating may then be patterned to provide cooling openings corresponding to the plurality of coolant passages of the manifold body 150. In a following step, the uniform coating may be transferred from the transfer substrate, e.g., liner, to the manifold body 510. The supporting substrate, e.g., liner, may then be removed from the adhesive material that is bonded to the manifold body 510. The manifold body 510 is then bonded to the second thermally conductive ceramic layer 207 through the uniform coating of the adhesive material to provide an adhesive layer 505 at an interface of the manifold body 510 and the second thermally conductive ceramic layer 207, in which the second thermally conductive ceramic layer 207 provides the interface layer 501 of the heat sink 500.

[0130] In another aspect, an electronics package 1000 is provided, in which the heat sink 500 described with reference to Figure 17 is integrated into the electronics package 1000 structure depicted in Figure 11. For example, the electronics package 1000 includes a thermal chip too, and a capacitor structure,e.g., MLCC structure 200, contacting the thermal chip too. The capacitor structure, e.g., MLCC structure 200, includes a positive metallic electrode 201a separated from a negative metallic electrode 201b by a ceramic dielectric fill 202 to provide a multilayered structure 205. Further, a first thermally conductive ceramic layer 206 is present on a first surface of the multilayered structure 205 providing a thermal interface between the capacitor structure, e.g., MLCC structure 200, and the thermal chip too. A second thermally conductive ceramic layer 207 is present on a second surface of the multilayered structure 205. In some embodiments, at least one of the first thermally conductive ceramic layer 206 and the second thermally conductive ceramic layer 207 is comprised of a material having a thermal conductivity of 50 W / (m-K) or greater. In some embodiments, the heat sink 500 includes a thermal interface layer 501 that is provided by the second thermally conductive layer 207 of the capacitor structure, e.g., MLCC structure 200. In some embodiments, the second thermally conductive layer 207 includes a plurality of coolant channels for the thermal interface layer 501 that will contact the coolant from the passageways through the manifold body 510. In some embodiments, the plurality of cooling channels are defined by cooling walls 502 extending from a surface of the second thermally conductive layer 407 providing the thermal interface layer 501 of the thermal sink 500 that is opposite the surface of the second thermally conductive layer 407 contacting the multilayered structures 205 of the MLCC structure 200. Further details on the electronics package 1000 and the MLCC structure 200 are provided above with reference to Figure 11. Further details on the heat sink 500 are provided above with reference to Figure 17.

[0131] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carry ing out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

WHAT IS CLAIMED IS:

1. A heat sink comprising: an interface layer 501 of ceramic material having a thermal conductivity of 50 W / (m-K) or greater, wherein the interface layer 501 comprises cooling channels defined by cooling walls 502 extending from a surface of the interface layer 501; a manifold body 510 having an inlet 506 and an outlet 507 for coolant to the cooling channels; and an adhesive layer 505 betw een the interface layer 501 of the ceramic material and the manifold body 510.

2. The heat sink of claim 1, wherein the cooling walls are integral with the interface layer of the ceramic material.

3. The heat sink of any of claims 1-2, wherein the interface layer of the ceramic material includes a composition comprising aluminum nitride, diamond-like carbon (DLC), beryllium oxide (BeO), silicon carbide (SiC), boron nitride (BN), copper aluminum oxide (CuA102), or combinations thereof.

4. The heat sink of any of claims 1-3, wherein a cross-section of the cooling channels has height and width dimensions that both range from to microns to 500 microns.

5. The heat sink of any of claims 1-4, wherein the manifold body comprises a plurality of coolant passages in communication with the inlet and the outlet.

6. The heat sink of any of claims 1-5, wherein the manifold body comprises liquid crystal polymer, polyimide, or epoxy, with or without fiberglass reinforcement.

7. The heat sink of any of claims 1-6, wherein an adhesive film layer is present between the interface layer and the manifold body.

8. The heat sink of any of claims 1-7, wherein the adhesive film comprises epoxy polymer, polyurethane, silicone, Buna-N rubber, FKM rubber, or combinations thereof.

9. The heat sink of any of claims 1-8, wherein the adhesive film has a thickness ranging from 10 microns to too microns.

10. An electronics package comprising: a thermal chip too; a capacitor structure 200 contacting the thermal chip too, the capacitor structure 200 including a positive electrode 201a separated from a negative electrode 201b by a dielectric fill 202 to provide a multilayered structure 205, a first thermally conductive layer 206 on a first surface of the multilay ered structure 205 providing a thermal interface between the capacitor structure 200 and the thermal chip 100, and a second thermally conductive layer 207 on a second surface of the multilayered structure 205 that is opposing the first surface, wherein at least one of the first thermally conductive layer 206 and the second thermally conductive layer 207 is comprised of a ceramic material having a thermal conductivity of 50 W / (m-K) or greater; and a heat sink 500 integrated with the second thermally conductive layer 207, wherein the second thermally conductive layer 207 includes a plurality of coolant channels 503.

11. The electronics package of claim 10, wherein the plurality of cooling channels are defined by cooling walls extending from a surface of the second thermally conductive layer that is opposite the surface of the second thermally conductive layer contacting the multilayered structure.

12. The electronics package of any of claims 10-11, wherein the second thermally conductive layer includes a composition comprising aluminum nitride, diamond-like carbon (DLC), beryllium oxide (BeO), silicon carbide (SiC), boron nitride (BN), copper aluminum oxide (CuA102), or combinations thereof.

13. The electronics package of any of claims 10-12, wherein the heat sink comprises a manifold body having an inlet and an outlet for coolant to the plurality of coolant channels.

14. The electronics package of any of claims 10-13, wherein the manifold body comprises liquid crystal polymer, polyimide, or epoxy, with or without fiberglass reinforcement.

15. The electronics package of any of claims 10-13, wherein the manifold body comprises a material having a low thermal conductivity 0.1 ~2 W / (m-K) or less.

16. A method of cooling an electronic component comprising: contacting a surface of a heat-producing component 100 with a capacitor structure 200, the capacitor structure 200 including a positive electrode 201a separated from a negative electrode 201b by a dielectric fill 202 to provide a multilayered structure 205, a first thermally conductive layer 206 on a first surface of the multilayered structure 205 providing a thermal interface between the capacitor structure 200 and the heatproducing component too, and a second thermally conductive layer 207 on a second surface of the multilayered structure 205 that is opposing the first surface, wherein at least one of the first thermally conductive layer 206 and the second thermally conductive layer 207 is comprised of a ceramic material having a thermal conductivity of 50 W / (m-K) or greater; and bonding a manifold body 510 to the second thermally conductive layer 207 of the capacitor structure 200 to provide a heat sink 500, wherein the second thermally conductive layer 207 includes a plurality of cooling walls 502 that extend into the manifold body 510 to define cooling channels.

17. The method of claim 16, wherein the plurality of cooling walls are formed in the second thermally conductive layer using mechanical subtractive machining, laser engraving, plasma engraving, powder injection formation, or combinations thereof.

18. The method of any of claims 16-17, wherein the manifold body comprises a plurality of coolant passages in communication with an inlet and an outlet.

19. The method of any of claims 16-18, wherein bonding the manifold to the second thermally conductive layer comprises: forming a uniform coating of an adhesive material on a transfer substrate; patterning the uniform coating to provide cooling openings corresponding to the cooling channels of the manifold body, and transferring the uniform coating of the adhesive material having the cooling openings from the transfer substrate to at least one of the manifold body and the second thermally conductive layer; and adhesively joining the manifold body and the second thermally conductive layer through the uniform coating of the adhesive material to provide an adhesive layer at an interface of the manifold body and the second thermally conductive layer.

20. The method of claim 19, further comprising adhesive curing following joining the manifold body and the second thermally conductive layer.

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