Display substrate and display apparatus

Abstract

The present disclosure provides a display substrate and a display apparatus. The display substrate comprises a connecting structure, a first common electrode, a second common electrode, a first conductive layer and a second conductive layer, wherein the connecting structure comprises a first connecting portion, a second connecting portion and a guide connecting portion; the first connecting portion is electrically connected to the first common electrode by means of a first via hole, and the second connecting portion is electrically connected to the second common electrode by means of a second via hole; the guide connecting portion comprises a first guide connecting sub-portion and a second guide connecting sub-portion; the first connecting portion is electrically connected to the second connecting portion by means of the first guide connecting sub-portion, and the first connecting portion is electrically connected to the second connecting portion by means of the second guide connecting sub-portion; and a length-width ratio of the first via hole is X1, a length-width ratio of the second via hole is X2, and X1＜1＜X2. By means of the present disclosure, the resistance of the connecting portions can be reduced, and thus the uniformity of a common electrode network of the entire display panel is increased.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] In related technologies, high-refresh-rate products (such as esports displays) can achieve refresh rates exceeding 240Hz, or even 500Hz, resulting in a very short line scan time. At a 500Hz refresh rate, a line scan time is only 1.8μs. If the common electrode voltage cannot recover after being coupled with the data voltage on the data line, it will cause line image retention.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising a connection structure, a first common electrode, a second common electrode, a first conductive layer, and a second conductive layer; the connection structure comprises a first connection portion, a second connection portion, and a conductive portion;

[0005] The first connection portion is electrically connected to the first common electrode through a first via hole, and the second connection portion is electrically connected to the second common electrode through a second via hole;

[0006] The conductive connection portion includes a first conductive sub-portion and a second conductive sub-portion; the first connection portion is electrically connected to the second connection portion via the first conductive sub-portion, and the first connection portion is electrically connected to the second connection portion via the second conductive sub-portion;

[0007] The first conductive sub-portion is located in the first conductive layer, and the second conductive sub-portion is located in the second conductive layer;

[0008] The aspect ratio of the first via hole is X1, the aspect ratio of the second via hole is X2, and X1<1<X2;

[0009] The aspect ratio of the first via hole is the ratio of the maximum length of the first via hole along the first direction to the maximum width of the first via hole along the second direction; the aspect ratio of the second via hole is the ratio of the maximum length of the second via hole along the first direction to the maximum width of the second via hole along the second direction;

[0010] The first direction intersects the second direction.

[0011] Optionally, the electrical conductivity of the first conductive layer is less than the electrical conductivity of the second conductive layer.

[0012] Optionally, the first connecting portion includes a first connecting portion and a second connecting portion; the first connecting portion is electrically connected to the first common electrode and the second connecting portion through the first via hole;

[0013] The second connecting portion includes a third connecting portion and a fourth connecting portion, and the third connecting portion is electrically connected to the second common electrode and the fourth connecting portion through the second via hole;

[0014] The first connection portion is electrically connected to the third connection portion through the first conductive sub-portion, and the second connection portion is electrically connected to the fourth connection portion through the second conductive sub-portion.

[0015] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a base substrate, the connection structure is provided on the base substrate; the first via hole includes a first via hole portion and a second via hole portion arranged along the second direction;

[0016] The orthographic projection of the first via portion on the base substrate does not overlap with the orthographic projection of the second connection portion on the base substrate; the orthographic projection of the first via portion on the base substrate is inside the orthographic projection of the first common electrode on the base substrate;

[0017] The orthographic projection of the second via portion on the base substrate is inside the orthographic projection of the first common electrode on the base substrate, and the orthographic projection of the second via portion on the base substrate is inside the orthographic projection of the second connection portion on the base substrate;

[0018] An orthographic projection of the second connection portion on the base substrate at least partially overlaps with an orthographic projection of the first common electrode on the base substrate.

[0019] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a third conductive layer;

[0020] The first common electrode is located in the third conductive layer, the first connecting portion is located in the first conductive layer, and the second connecting portion is located in the second conductive layer.

[0021] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a base substrate; the connection structure is provided on the base substrate; the second via hole includes a third via hole portion and a fourth via hole portion arranged along the first direction;

[0022] The orthographic projection of the third via portion on the base substrate does not overlap with the orthographic projection of the fourth connection portion on the base substrate; the orthographic projection of the third via portion on the base substrate is inside the orthographic projection of the third connection portion on the base substrate;

[0023] The orthographic projection of the fourth via portion on the base substrate is inside the orthographic projection of the fourth connection portion on the base substrate; the orthographic projection of the fourth via portion on the base substrate is inside the orthographic projection of the third connection portion on the base substrate;

[0024] An orthographic projection of the fourth connection portion on the base substrate at least partially overlaps with an orthographic projection of the second common electrode on the base substrate.

[0025] Optionally, the display substrate described in at least one embodiment of the present disclosure further includes a fourth conductive layer; the second common electrode is located in the fourth conductive layer, the third connecting portion is located in the first conductive layer, and the fourth connecting portion is located in the second conductive layer.

[0026] Optionally, X1 is less than or equal to 0.8, and X2 is greater than or equal to 1.2.

[0027] Optionally, X1 / X2 is greater than or equal to 0.3 and less than or equal to 0.6.

[0028] Optionally, a distance between a first edge of an orthographic projection of the second via portion on the base substrate and a second edge of an orthographic projection of the second connection portion on the base substrate is greater than a first distance, and the first distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm;

[0029] The first edge and the second edge are opposite edges.

[0030] Optionally, the shortest distance along the second direction between the edge of the orthographic projection of the first via portion on the base substrate and the edge of the orthographic projection of the second connection portion on the base substrate is greater than a second distance, and the second distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

[0031] Optionally, a length of the second via portion along the second direction is greater than a first length, and the first length is greater than or equal to 3.9 μm and less than or equal to 4.3 μm.

[0032] Optionally, a distance between an edge of an orthographic projection of the first via on the base substrate and an edge of an orthographic projection of the first connection portion on the base substrate is greater than a third distance, and the third distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

[0033] Optionally, a length of the first via hole along the first direction is greater than a second length, and the second length is greater than or equal to 3.8 μm and less than or equal to 4.2 μm.

[0034] Optionally, a distance between a third edge of an orthographic projection of the fourth via portion on the base substrate and a fourth edge of an orthographic projection of the fourth connection portion on the base substrate is greater than a fourth distance, and the fourth distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm;

[0035] The third edge and the fourth edge are opposite edges.

[0036] Optionally, the shortest distance along the second direction between the edge of the orthographic projection of the third via portion on the base substrate and the edge of the orthographic projection of the fourth connection portion on the base substrate is greater than a fifth distance, and the fifth distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

[0037] Optionally, a length of the fourth via portion along the first direction is greater than a third length, and the third length is greater than or equal to 3.9 μm and less than or equal to 4.3 μm.

[0038] Optionally, the shortest distance along the first direction between the edge of the orthographic projection of the second via on the base substrate and the edge of the orthographic projection of the third connection portion on the base substrate is greater than a sixth distance, and the sixth distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

[0039] Optionally, a length of the second via hole along the second direction is greater than a fourth length, and the fourth length is greater than or equal to 3.8 μm and less than or equal to 4.2 μm.

[0040] Optionally, the length of the orthographic projection of the first via portion on the base substrate along the first direction is greater than the length of the orthographic projection of the second via portion on the base substrate along the first direction; or

[0041] A length of an orthographic projection of the first via portion on the base substrate along the first direction is smaller than a length of an orthographic projection of the second via portion on the base substrate along the first direction.

[0042] Optionally, the length of the third via portion along the second direction is greater than the length of the fourth via portion along the second direction; or,

[0043] A length of the third via portion along the second direction is smaller than a length of the fourth via portion along the second direction.

[0044] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a base substrate and gate lines disposed on the base substrate;

[0045] There is a first overlapping area between the orthographic projection of the gate line on the base substrate and the orthographic projection of the first conductive sub-portion in the connection structure on the base substrate;

[0046] There is a second overlapping area between the orthographic projection of the gate line on the base substrate and the orthographic projection of the second conductive sub-portion in the connection structure on the base substrate;

[0047] An area of ​​the first overlapping region is smaller than an area of ​​the second overlapping region.

[0048] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a base substrate and pixel electrodes, data lines, gate lines and switching transistors arranged on the base substrate;

[0049] The gate line includes a first gate line portion and a second gate line portion that are interconnected; the first gate line portion is multiplexed as the gate of the switching transistor;

[0050] The first electrode of the switching transistor is electrically connected to the data line;

[0051] The second electrode of the switching transistor includes a transition portion, a first electrode portion, and a second electrode portion; the transition portion is electrically connected to the pixel electrode, the first electrode portion is disposed on a first side of the transition portion, and the second electrode portion is disposed on a second side of the transition portion, wherein the first side and the second side are opposite sides;

[0052] The orthographic projection of the first electrode portion on the base substrate at least partially overlaps with the orthographic projection of the first gate line portion on the base substrate;

[0053] An orthographic projection of the second electrode portion on the base substrate at least partially overlaps with an orthographic projection of the second gate line portion on the base substrate.

[0054] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a base substrate; the display substrate includes a first transparent conductive layer, a gate electrode layer, a source-drain electrode layer, and a second transparent conductive layer arranged in sequence in a direction away from the base substrate;

[0055] The first conductive layer is the second transparent conductive layer, and the second conductive layer is the source-drain electrode layer.

[0056] In a second aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] FIG1 is a layout diagram of a connection structure according to at least one embodiment of the present disclosure;

[0058] FIG2 is a layout diagram of the first transparent conductive layer in FIG1 ;

[0059] FIG3 is a layout diagram of the gate electrode layer in FIG1 ;

[0060] FIG4 is a layout diagram of the source-drain electrode layer in FIG1 ;

[0061] FIG5 is a layout diagram of the second transparent conductive layer in FIG1 ;

[0062] FIG6 is a cross-sectional view of AA' in FIG1;

[0063] FIG7 is a BB' cross-sectional view in FIG1;

[0064] FIG8A is an enlarged schematic diagram of the first via hole in FIG1 ;

[0065] FIG8B is an enlarged schematic diagram of the first via hole in FIG1 ;

[0066] FIG9A is an enlarged schematic diagram of the second via hole in FIG1 ;

[0067] FIG9B is an enlarged schematic diagram of the second via hole in FIG1 ;

[0068] FIG10 is a structural diagram of at least one embodiment of a first via hole;

[0069] FIG11 is a structural diagram of at least one embodiment of a first via hole;

[0070] FIG12 is a structural diagram of at least one embodiment of a second via hole;

[0071] FIG13 is a structural diagram of at least one embodiment of a third hole;

[0072] FIG14 is a layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0073] FIG15 is a layout diagram of the first transparent conductive layer in FIG14;

[0074] FIG16 is a layout diagram of the gate electrode layer in FIG14;

[0075] FIG17 is a layout diagram of the source-drain electrode layer in FIG14;

[0076] FIG18 is a layout diagram of the second transparent conductive layer in FIG14;

[0077] FIG19 is a layout diagram of the gate electrode layer in FIG14;

[0078] FIG20 is a layout diagram of the source-drain electrode layer in FIG14;

[0079] FIG21 is a stacked diagram of the gate electrode layer and the second transparent conductive layer in FIG14;

[0080] FIG22 is a stacked diagram of the gate electrode layer and the source / drain electrode layer in FIG14;

[0081] FIG23 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0082] FIG24 is a structural diagram of a base substrate and a first transparent conductive layer included in a display substrate according to at least one embodiment of the present disclosure;

[0083] FIG25 is a structural diagram of a base substrate, a first transparent conductive layer, and a gate electrode layer included in a display substrate according to at least one embodiment of the present disclosure;

[0084] FIG26 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure, including a base substrate, a first transparent conductive layer, a gate electrode layer, a gate insulating layer, a semiconductor layer, and a source-drain electrode layer;

[0085] 27 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure, including a base substrate, a first transparent conductive layer, a gate electrode layer, a gate insulating layer, a semiconductor layer, a source-drain electrode layer, and a passivation layer;

[0086] Figure 28 is a structural diagram of the display substrate described in at least one embodiment of the present disclosure, including a base substrate, a first transparent conductive layer, a gate electrode layer, a gate insulating layer, a semiconductor layer, a source-drain electrode layer, a passivation layer and a second transparent conductive layer. DETAILED DESCRIPTION

[0087] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0088] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0089] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0090] The display substrate of the embodiment of the present disclosure includes a connection structure, a first common electrode, a second common electrode, a first conductive layer and a second conductive layer; the connection structure includes a first connection portion, a second connection portion and a conductive portion;

[0091] The first connection portion is electrically connected to the first common electrode through a first via hole, and the second connection portion is electrically connected to the second common electrode through a second via hole;

[0092] The conductive connection portion includes a first conductive sub-portion and a second conductive sub-portion; the first connection portion is electrically connected to the second connection portion via the first conductive sub-portion, and the first connection portion is electrically connected to the second connection portion via the second conductive sub-portion;

[0093] The first conductive sub-portion is located in the first conductive layer, and the second conductive sub-portion is located in the second conductive layer;

[0094] The aspect ratio of the first via hole is X1, the aspect ratio of the second via hole is X2, and X1<1<X2;

[0095] The aspect ratio of the first via hole is the ratio of the maximum length of the first via hole along the first direction to the maximum width of the via hole along the second direction; the aspect ratio of the second via hole is the ratio of the maximum length of the second via hole along the first direction to the maximum width of the second via hole along the second direction;

[0096] The first direction intersects the second direction.

[0097] In the connection structure described in the embodiment of the present disclosure, the first connection part is electrically connected to the second connection part through the first conductive sub-part and the second conductive sub-part respectively. The second conductive sub-part can reduce the resistance of the conductive part, increase the uniformity of the common electrode network of the entire display panel, and enhance the recovery force of the common electrode voltage after being pulled by the data voltage coupling.

[0098] In at least one embodiment of the present disclosure, the first common electrode may be located in the gate electrode layer, the second common electrode may be located in the first transparent conductive layer, the first conductive sub-portion may be located in the second transparent conductive layer, and the second conductive sub-portion may be located in the source-drain electrode layer, but is not limited thereto.

[0099] Optionally, the first transparent conductive layer may be a first ITO (indium tin oxide) layer, and the second transparent conductive layer may be a second ITO layer.

[0100] In the related art, in high refresh rate products, for example, in e-sports display products, the refresh rate can reach above 240Hz, or even 500Hz, and the corresponding line scan time is very short. When the refresh rate is 500Hz, the line scan time is only 1.8μs. If the common electrode voltage cannot be recovered after being coupled by the data voltage on the data line, line afterimages will occur. In the related connection structure, the first connection part and the second connection part are electrically connected through the first conductive sub-part. The first conductive sub-part can be located in the second transparent conductive layer, for example. The resistivity of the second transparent conductive layer is relatively large, and M24 defects may occur. Based on this, in at least one embodiment of the present disclosure, the first connection part is electrically connected to the second connection part through the first conductive sub-part, and the first connection part is electrically connected to the second connection part through the second conductive sub-part. The second conductive sub-part can reduce the resistance of the conductive part.

[0101] Optionally, the electrical conductivity of the first conductive layer is less than the electrical conductivity of the second conductive layer.

[0102] In at least one embodiment of the present disclosure, the resistivity of the second transparent conductive layer is relatively large, and the resistivity of the source-drain electrode layer is relatively small. By electrically connecting the first common electrode and the second common electrode through the second transparent conductive layer and the source-drain electrode layer, the resistance uniformity of the common electrode of the entire display panel can be improved.

[0103] Optionally, the first direction may be a horizontal direction, and the second direction may be a vertical direction, but is not limited thereto.

[0104] Optionally, the first connecting portion includes a first connecting portion and a second connecting portion; the first connecting portion is electrically connected to the first common electrode and the second connecting portion through the first via hole;

[0105] The second connecting portion includes a third connecting portion and a fourth connecting portion, and the third connecting portion is electrically connected to the second common electrode and the fourth connecting portion through the second via hole;

[0106] The first connection portion is electrically connected to the third connection portion through the first conductive sub-portion, and the second connection portion is electrically connected to the fourth connection portion through the second conductive sub-portion.

[0107] In at least one embodiment of the present disclosure, the first connecting portion and the first common electrode may be located in different conductive layers, the first connecting portion and the second connecting portion may be located in different conductive layers, the third connecting portion and the second common electrode may be located in different conductive layers, and the third connecting portion and the fourth connecting portion may be located in different conductive layers.

[0108] In at least one embodiment of the present disclosure, the first connecting portion may be located in the second transparent conductive layer, the second connecting portion may be located in the source-drain electrode layer, the third connecting portion may be located in the second transparent conductive layer, and the fourth connecting portion may be located in the source-drain electrode layer, but is not limited thereto.

[0109] In at least one embodiment of the present disclosure, the display substrate may further include a base substrate; the connection structure is provided on the base substrate; the first via hole includes a first via hole portion and a second via hole portion arranged along the second direction;

[0110] The orthographic projection of the first via portion on the base substrate does not overlap with the orthographic projection of the second connection portion on the base substrate; the orthographic projection of the first via portion on the base substrate is inside the orthographic projection of the first common electrode on the base substrate;

[0111] The orthographic projection of the second via portion on the base substrate is inside the orthographic projection of the first common electrode on the base substrate, and the orthographic projection of the second via portion on the base substrate is inside the orthographic projection of the second connection portion on the base substrate;

[0112] An orthographic projection of the second connection portion on the base substrate at least partially overlaps with an orthographic projection of the first common electrode on the base substrate.

[0113] In a specific implementation, the first via hole may be designed as a half-via hole, and the first via hole may be an upper and lower half via hole, the lower half via hole of the first via hole being used to electrically connect the first common electrode and the first connecting portion, and the upper half via hole of the first via hole being used to electrically connect the first connecting portion and the second connecting portion; at least one embodiment of the present disclosure, by adopting a half-via hole design for the first via hole, can facilitate the diffusion of PI (polyimide) liquid and improve M24 defects (M24 defects may be Mura (display unevenness) type defects).

[0114] In at least one embodiment of the present disclosure, the lower half of the first via hole can be drilled on the gate electrode layer, the upper half of the first via hole can be drilled on the source-drain electrode layer, and the middle bridge portion of the first via hole can be a source-drain metal pattern located in the source-drain electrode layer, but is not limited to this.

[0115] M24 defects can be caused by abnormal PI around the via when there is no PI liquid in the via, or by periodic mura caused by uneven diffusion of PI liquid in the via. A semi-via design facilitates PI liquid diffusion.

[0116] Optionally, the display substrate may further include a third conductive layer; the first common electrode is located in the third conductive layer, the first connecting portion is located in the first conductive layer, and the second connecting portion is located in the second conductive layer.

[0117] In at least one embodiment of the present disclosure, the third conductive layer may be a gate electrode layer, the first conductive layer may be a second transparent conductive layer, and the second conductive layer may be a source-drain electrode layer, but the present invention is not limited thereto.

[0118] In at least one embodiment of the present disclosure, the display substrate further includes a base substrate; the connection structure is provided on the base substrate; the second via hole includes a third via hole portion and a fourth via hole portion arranged along the first direction;

[0119] The orthographic projection of the third via portion on the base substrate does not overlap with the orthographic projection of the fourth connection portion on the base substrate; the orthographic projection of the third via portion on the base substrate is inside the orthographic projection of the third connection portion on the base substrate;

[0120] The orthographic projection of the fourth via portion on the base substrate is inside the orthographic projection of the fourth connection portion on the base substrate; the orthographic projection of the fourth via portion on the base substrate is inside the orthographic projection of the third connection portion on the base substrate;

[0121] An orthographic projection of the fourth connection portion on the base substrate at least partially overlaps with an orthographic projection of the second common electrode on the base substrate.

[0122] In a specific implementation, the second via can be designed as a half-via, and the second via can be a left via. The left half of the second via can be used to electrically connect the second common electrode and the third connecting part, and the right half of the second via can be used to electrically connect the third connecting part and the fourth connecting part. At least one embodiment of the present disclosure adopts a half-via design for the second via, which can facilitate the diffusion of PI liquid and improve M24 defects (M24 defects can be Mura-type defects).

[0123] In at least one embodiment of the present disclosure, the left half of the second via hole can be drilled on the second common electrode, the right half of the second via hole can be drilled on the source and drain electrode layer, and the middle bridge portion of the second via hole can be a source and drain metal pattern, but is not limited to this.

[0124] Optionally, the display substrate may further include a fourth conductive layer; the second common electrode is located in the fourth conductive layer, the third connecting portion is located in the first conductive layer, and the fourth connecting portion is located in the second conductive layer.

[0125] In at least one embodiment of the present disclosure, the fourth conductive layer may be the first transparent conductive layer, but is not limited thereto.

[0126] Optionally, X1 is less than or equal to 0.8, and X2 is greater than or equal to 1.2. Further, X1 is less than or equal to 0.64, and X2 is greater than or equal to 1.55.

[0127] In at least one embodiment of the present disclosure, X1 / X2 is greater than or equal to 0.3 and less than or equal to 0.6. For example, X / X2 may be 0.3, 0.35, 0.4, 0.45, 0.5, 0.55 or 0.6.

[0128] Optionally, a distance between a first edge of an orthographic projection of the second via portion on the base substrate and a second edge of an orthographic projection of the second connection portion on the base substrate is greater than a first distance, and the first distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm. For example, the first distance may be 1.9 μm, 2 μm, 2.1 μm, 2.2 μm, or 2.3 μm, so that the first via hole can be drilled on the second conductive layer;

[0129] The first edge and the second edge are opposite edges.

[0130] Optionally, the shortest distance along the second direction between the edge of the orthographic projection of the first via portion on the base substrate and the edge of the orthographic projection of the second connection portion on the base substrate is greater than a second distance, and the second distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm. For example, the second distance can be 1.9 μm, 2 μm, 2.1 μs, 2.2 μm or 2.3 μm to ensure the formation of a half via.

[0131] Optionally, the length of the second via portion along the second direction is greater than the first length, and the first length is greater than or equal to 3.9 μm and less than or equal to 4.3 μm. For example, the first length may be 3.9 μm, 4 μm, 4.1 μm, 4.2 μm or 4.3 μm, so that even if the second connection portion moves up a certain distance due to process deviation when manufacturing the display substrate, the overlapping distance between the second conductive layer and the first via hole reaches more than 2 μm, ensuring that it can be electrically connected to the second conductive layer through the first via hole.

[0132] In at least one embodiment of the present disclosure, a distance between an edge of an orthographic projection of the first via on the base substrate and an edge of an orthographic projection of the first connecting portion on the base substrate is greater than a third distance, and the third distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm. For example, the third distance may be 1.9 μm, 2 μm, 2.1 μs, 2.2 μm or 2.3 μm to ensure that the first conductive layer wraps the first via to prevent the first via from being exposed and corroded by water vapor and air.

[0133] Optionally, the length of the first via along the first direction is greater than a second length, and the second length is greater than or equal to 3.8 μm and less than or equal to 4.2 μm. For example, the second length may be 3.8 μm, 3.9 μm, 4 μm, 4.1 μm or 4.2 μm.

[0134] In at least one embodiment of the present disclosure, a distance between a third edge of an orthographic projection of the fourth via portion on the base substrate and a fourth edge of an orthographic projection of the fourth connection portion on the base substrate is greater than a fourth distance, and the fourth distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm. For example, the fourth distance may be 1.9 μm, 2 μm, 2.1 μm, 2.2 μm, or 2.3 μm, so that the second via hole can be drilled on the second conductive layer.

[0135] The third edge and the fourth edge are opposite edges.

[0136] In at least one embodiment of the present disclosure, the shortest distance along the second direction between the edge of the orthographic projection of the third via portion on the base substrate and the edge of the orthographic projection of the fourth connection portion on the base substrate is greater than a fifth distance, and the fifth distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm. For example, the fifth distance can be 1.9 μm, 2 μm, 2.1 μs, 2.2 μm or 2.3 μm to ensure the formation of a half via.

[0137] Optionally, the length of the fourth via portion along the first direction is greater than the third length, and the third length is greater than or equal to 3.9 μm and less than or equal to 4.3 μm. For example, the first length may be 3.9 μm, 4 μm, 4.1 μm, 4.2 μm or 4.3 μm, so that even if the fourth connection portion is shifted to the right by a certain distance due to process deviation when manufacturing the display substrate, the overlapping distance between the second conductive layer and the second via hole reaches more than 2 μm, ensuring that it can be electrically connected to the second conductive layer through the second via hole.

[0138] In at least one embodiment of the present disclosure, the shortest distance along the first direction between the edge of the orthographic projection of the second via on the base substrate and the edge of the orthographic projection of the third connecting portion on the base substrate is greater than the sixth distance, and the sixth distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm. For example, the fifth distance can be 1.9 μm, 2 μm, 2.1 μs, 2.2 μm or 2.3 μm to ensure that the first conductive layer wraps the second via to prevent the second via from being exposed and corroded by water vapor and air.

[0139] Optionally, the length of the second via along the second direction is greater than a fourth length, and the fourth length is greater than or equal to 3.8 μm and less than or equal to 4.2 μm. For example, the second length may be 3.8 μm, 3.9 μm, 4 μm, 4.1 μm or 4.2 μm.

[0140] Figure 1 is a layout diagram of the connection structure described in at least one embodiment of the present disclosure, Figure 2 is a layout diagram of the first transparent conductive layer in Figure 1, Figure 3 is a layout diagram of the gate electrode layer in Figure 1, Figure 4 is a layout diagram of the source and drain electrode layer in Figure 1, and Figure 5 is a layout diagram of the second transparent conductive layer in Figure 1.

[0141] In FIG3 , the gate lines are labeled GA.

[0142] As shown in FIG1 to FIG5 , the first common electrode CM1 is electrically connected to the first connection portion L1 and the second connection portion L2 through the first via hole H1;

[0143] The second common electrode CM2 is electrically connected to the third connection portion L3 and the fourth connection portion L4 through the second via hole H2;

[0144] The first common electrode CM1 is located in the gate electrode layer, the first connection portion L1 is located in the second transparent conductive layer, the second connection portion L2 is located in the source-drain electrode layer, the second common electrode CM2 is located in the first transparent conductive layer, the third connection portion L3 is located in the second transparent conductive layer, and the fourth connection portion L4 is located in the source-drain electrode layer;

[0145] The first connection portion L1 is electrically connected to the third connection portion L3 via the first conductive sub-portion D1, and the second connection portion L2 is electrically connected to the fourth connection portion L4 via the second conductive sub-portion D2;

[0146] The first conductive sub-portion D1 is located in the second transparent conductive layer, and the second conductive sub-portion D2 is located in the source-drain electrode layer, but the present invention is not limited thereto.

[0147] FIG6 is a cross-sectional view taken along line AA′ in FIG1 , and FIG7 is a cross-sectional view taken along line BB′ in FIG1 .

[0148] In FIG6 and FIG7, reference numeral 60 is a base substrate, reference numeral 61 is a first transparent conductive layer, reference numeral 62 is a gate electrode layer, reference numeral 63 is a source-drain electrode layer, and reference numeral 64 is a second transparent conductive layer;

[0149] The reference numeral 601 is a gate insulating layer, and the reference numeral 602 is a passivation layer.

[0150] FIG8A is an enlarged schematic diagram of the first via hole in FIG1 , and FIG9A is an enlarged schematic diagram of the second via hole in FIG1 .

[0151] As shown in FIG8A , the first via hole H1 includes a first via hole portion H11 and a second via hole portion H12 arranged in a vertical direction;

[0152] As shown in FIG1 to FIG8A , the orthographic projection of the first via portion H11 on the base substrate does not overlap with the orthographic projection of the second connection portion L2 on the base substrate; the orthographic projection of the first via portion H11 on the base substrate is inside the orthographic projection of the first common electrode CM1 on the base substrate;

[0153] The orthographic projection of the second via portion H12 on the base substrate is inside the orthographic projection of the first common electrode CM1 on the base substrate, and the orthographic projection of the second via portion H12 on the base substrate is inside the orthographic projection of the second connection portion L2 on the base substrate;

[0154] An orthographic projection of the second connection portion L2 on the base substrate at least partially overlaps with an orthographic projection of the first common electrode CM1 on the base substrate.

[0155] As shown in FIG8A , the distance b′ is the vertical distance between the lower edge of the orthographic projection of the first via portion H11 on the substrate and the lower edge of the orthographic projection of the second connection portion L2 on the substrate. b′ is greater than 2.1 μm to ensure the formation of upper and lower half vias.

[0156] The vertical length of the second via portion H12 is designated by c', and c' is greater than 4.1 μm. This ensures that even if the second connection portion L2 is moved upward by 2.1 μm due to process deviations during the manufacture of the display substrate, the overlapping distance between the source-drain electrode layer and the first via hole H1 is greater than 2 μm, ensuring electrical connection to the source-drain electrode layer through the first via hole H1.

[0157] The distance labeled a1' is the shortest distance between the left edge of the orthographic projection of the first via hole H1 on the base substrate and the left edge of the orthographic projection of the first connection portion L1 on the base substrate. The distance labeled a2' is the shortest distance between the right edge of the orthographic projection of the first via hole H1 on the base substrate and the right edge of the orthographic projection of the first connection portion L1 on the base substrate. Both a1' and a2' are greater than 2.1 μm to ensure that the second transparent conductive layer can wrap the via hole and prevent the via hole from being exposed and corroded by water vapor and air.

[0158] The horizontal distance between the left edge of the orthographic projection of the second via portion H12 on the substrate and the left edge of the orthographic projection of the second connection portion L2 on the substrate is marked with a reference numeral e', and e' is greater than 2.1 μm to ensure that the first via hole H1 can be drilled on the source-drain electrode layer.

[0159] d' is the length of the first via hole H1 in the horizontal direction, and d' is greater than 4 μm;

[0160] But it is not limited to this.

[0161] In actual operation, the length of the first via hole H1 in the horizontal direction needs to be set to be relatively small so as not to affect the pixel aperture ratio.

[0162] In at least one embodiment shown in FIG. 8A , the first edge and the second edge may both be lower edges, but the present invention is not limited thereto.

[0163] In at least one embodiment shown in FIG8A , the first via hole is a rectangular via hole, but the present invention is not limited thereto. In actual operation, the first via hole can be of other shapes.

[0164] As shown in FIG. 8B , the first via hole H1 may be a rounded rectangular via hole, but the present invention is not limited thereto.

[0165] As shown in FIG. 1 to FIG. 9A , the second via hole includes a third via hole portion H23 and a fourth via hole portion H24 arranged along the horizontal direction;

[0166] The orthographic projection of the third via portion H23 on the base substrate does not overlap with the orthographic projection of the fourth connection portion L4 on the base substrate; the orthographic projection of the third via portion H3 on the base substrate is inside the orthographic projection of the third connection portion L3 on the base substrate;

[0167] The orthographic projection of the fourth via portion H24 on the base substrate is inside the orthographic projection of the fourth connection portion L4 on the base substrate; the orthographic projection of the fourth via portion H24 on the base substrate is inside the orthographic projection of the third connection portion L3 on the base substrate;

[0168] An orthographic projection of the fourth connection portion L4 on the base substrate at least partially overlaps with an orthographic projection of the second common electrode CM2 on the base substrate.

[0169] As shown in FIG9A , the distance b along the horizontal direction between the left edge of the orthographic projection of the third via portion H23 on the base substrate and the left edge of the orthographic projection of the fourth connection portion L4 on the base substrate is greater than 2.1 μm to ensure that the left and right half vias are formed.

[0170] The horizontal length of the fourth via portion H24 is designated by c, and c is greater than 4.1 μm. This ensures that even if the fourth connection portion L4 shifts rightward by 2.1 μm due to process deviations during the manufacture of the display substrate, the overlapping distance between the source-drain electrode layer and the second via hole H2 is greater than 2 μm, ensuring electrical connection to the source-drain electrode layer through the second via hole H2.

[0171] The distance labeled a1 is the shortest distance between the lower edge of the orthographic projection of the second via hole H2 on the base substrate and the lower edge of the orthographic projection of the third connection portion L3 on the base substrate. The distance labeled a2 is the shortest distance between the upper edge of the orthographic projection of the second via hole H2 on the base substrate and the upper edge of the orthographic projection of the third connection portion L3 on the base substrate. Both a1 and a2 are greater than 2.1 μm to ensure that the second transparent conductive layer can wrap the via hole and prevent the via hole from being exposed and corroded by water vapor and air.

[0172] The shortest distance in the vertical direction between the lower edge of the orthographic projection of the fourth via portion H24 on the substrate and the lower edge of the orthographic projection of the fourth connection portion L4 on the substrate is marked with a reference numeral e. e is greater than 2.1 μm to ensure that the second via hole H2 can be drilled on the source-drain electrode layer.

[0173] The length of the second via hole H2 in the vertical direction is d, which is greater than 4 μm.

[0174] But it is not limited to this.

[0175] In actual operation, the length of the second via hole H2 in the vertical direction needs to be set to be relatively small so as not to affect the pixel aperture ratio.

[0176] In at least one embodiment shown in FIG. 9A , the third edge and the fourth edge may both be left edges, but the present invention is not limited thereto.

[0177] In the embodiment of FIG. 1 to FIG. 9A , the first via hole H1 and the second via hole H2 are both rectangular via holes, but the present invention is not limited thereto.

[0178] In at least one embodiment shown in FIG9A , the second via hole is a rectangular via hole, but the present invention is not limited thereto. In actual operation, the second via hole can be of other shapes.

[0179] As shown in FIG. 9B , the second via hole H2 may be a rounded rectangular via hole, but the present invention is not limited thereto.

[0180] In at least one embodiment of the present disclosure, the length of the orthographic projection of the first via portion on the base substrate along the first direction is greater than the length of the orthographic projection of the second via portion on the base substrate along the first direction; or

[0181] A length of an orthographic projection of the first via portion on the base substrate along the first direction is smaller than a length of an orthographic projection of the second via portion on the base substrate along the first direction.

[0182] As shown in FIG. 10 , the length of the orthographic projection of the first via portion H11 on the base substrate along the horizontal direction is greater than the length of the orthographic projection of the second via portion H12 on the base substrate along the horizontal direction.

[0183] As shown in FIG11 , the length of the orthographic projection of the first via portion H11 on the base substrate along the horizontal direction is smaller than the length of the orthographic projection of the second via portion H12 on the base substrate along the horizontal direction.

[0184] In at least one embodiment of the present disclosure, the length of the third via portion along the second direction is greater than the length of the fourth via portion along the second direction; or,

[0185] A length of the third via portion along the second direction is smaller than a length of the fourth via portion along the second direction.

[0186] As shown in FIG. 12 , the length of the third via hole portion H23 along the vertical direction is greater than the length of the fourth via hole portion H24 along the vertical direction.

[0187] As shown in FIG. 13 , the length of the third via hole portion H23 along the vertical direction is smaller than the length of the fourth via hole portion H24 along the vertical direction.

[0188] In a specific implementation, the first via hole and the second via hole can be "convex" shaped via holes. No matter the flow is from narrow to wide or from wide to narrow, the "convex" shaped via hole is more conducive to the diffusion of PI liquid in the via hole.

[0189] The display substrate according to the embodiment of the present disclosure includes a base substrate and a first common electrode, a second common electrode and the above-mentioned connection structure provided on the base substrate;

[0190] The connection structure is used to electrically connect the first common electrode and the second common electrode.

[0191] The display substrate according to at least one embodiment of the present disclosure further includes a gate line provided on the base substrate;

[0192] There is a first overlapping area between the orthographic projection of the gate line on the base substrate and the orthographic projection of the first conductive sub-portion in the connection structure on the base substrate;

[0193] There is a second overlapping area between the orthographic projection of the gate line on the base substrate and the orthographic projection of the second conductive sub-portion in the connection structure on the base substrate;

[0194] The area of ​​the first overlapping region is smaller than the area of ​​the second overlapping region. Specifically, the area of ​​the first overlapping region and the area of ​​the second overlapping region are smaller than the first area, and the first area is greater than or equal to 14 μm. 2 Less than or equal to 18μm 2 For example, the first area may be 14 μm 2 , 15μm 2 , 16μm 2 , 17μm 2 or 18 μm 2 , to reduce the parasitic capacitance between the gate line and the first conductive sub-portion, reduce the parasitic capacitance between the gate line and the second conductive sub-portion, and prevent the load on the gate line from increasing.

[0195] As shown in Figures 14 to 18, the display substrate described in at least one embodiment of the present disclosure includes a base substrate, and, provided on the base substrate are a first row gate line GA1, a second row gate line GA2, a first row common electrode line CML1, a second row second common electrode line CML2, a first column data line DL1, a second column data line DL2, a third column data line DL3, a fourth column data line DL4, a first second common electrode CM12, a second second common electrode CM22, a third second common electrode CM32, a first row and first column switching transistor M11, a first row and second column switching transistor M12, a first row and third column switching transistor M13, a second row and first column switching transistor M21, a second row and second column switching transistor M22, a second row and third column switching transistor M23, a first connection structure LJ1, a second connection structure LJ2, a first pixel electrode PJ1, a second pixel electrode PJ2, and a third pixel electrode PJ3;

[0196] The first row of common electrode lines CML1 is used as a first first common electrode CM11, and the second row of common electrode lines CML2 is used as a second first common electrode CM21;

[0197] CML1, CML2, GA1 and GA2 are all located in the gate electrode layer;

[0198] DL1, DL2, DL3, DL4, the first electrode of M11, the second electrode of M11, the first electrode of M12, the second electrode of M12, the first electrode of M13, the second electrode of M13, the first electrode of M21, the second electrode of M21, the first electrode of M22, the second electrode of M22, the first electrode of M23, and the second electrode of M23 are all located in the source-drain electrode layer;

[0199] CM12, CM22 and CM32 are all located in the first transparent conductive layer;

[0200] PJ1 , PJ2 and PJ3 are all located in the second transparent conductive layer.

[0201] FIG14 is a layout diagram of a display substrate according to at least one embodiment of the present disclosure. FIG15 is a layout diagram of the first transparent conductive layer in FIG14 . FIG16 is a layout diagram of the gate electrode layer in FIG14 . FIG17 is a layout diagram of the source / drain electrode layer in FIG14 . FIG18 is a layout diagram of the second transparent conductive layer in FIG14 . FIG19 is a layout diagram of the gate electrode layer in FIG14 . FIG20 is a layout diagram of the source / drain electrode layer in FIG14 . FIG21 is a stack diagram of the gate electrode layer and the second transparent conductive layer in FIG14 . FIG22 is a stack diagram of the gate electrode layer and the source / drain electrode layer in FIG14 .

[0202] The display substrate according to at least one embodiment of the present disclosure further includes a base substrate and pixel electrodes, data lines, gate lines and switching transistors arranged on the base substrate;

[0203] The gate line includes a first gate line portion and a second gate line portion that are interconnected; the first gate line portion is multiplexed as the gate of the switching transistor;

[0204] The first electrode of the switching transistor is electrically connected to the data line;

[0205] The second electrode of the switching transistor includes a transition portion, a first electrode portion, and a second electrode portion; the transition portion is electrically connected to the pixel electrode, the first electrode portion is disposed on a first side of the transition portion, and the second electrode portion is disposed on a second side of the transition portion, wherein the first side and the second side are opposite sides;

[0206] The orthographic projection of the first electrode portion on the base substrate at least partially overlaps with the orthographic projection of the first gate line portion on the base substrate;

[0207] An orthographic projection of the second electrode portion on the base substrate at least partially overlaps with an orthographic projection of the second gate line portion on the base substrate.

[0208] As shown in FIG. 14 to FIG. 18 , the first electrode S11 of M11 is electrically connected to the first column data line DL1 , and the first electrode S21 of M21 is electrically connected to the first column data line DL1 ;

[0209] The first electrode S12 of M12 is electrically connected to the second column data line DL2, and the first electrode S22 of M22 is electrically connected to the second column data line DL2;

[0210] The first electrode S13 of M13 is electrically connected to the third column data line DL3, and the first electrode S23 of M23 is electrically connected to the third column data line DL3;

[0211] As shown in FIG19 , the first row of gate lines includes a first first gate line portion GB11, a first second gate line portion GB12, a second first gate line portion GB21, a second second gate line portion GB22, a third first gate line portion GB31, and a third second gate line portion GB32 that are interconnected; the second row of gate lines includes a fourth first gate line portion GB41, a fourth second gate line portion GB22, a fifth first gate line portion GB51, a fifth second gate line portion GB52, a sixth first gate line portion GB61, and a sixth second gate line portion GB62;

[0212] GB11 is multiplexed as the gate of M11, GB12 is multiplexed as the gate of M12, GB13 is multiplexed as the gate of M13, GB21 is multiplexed as the gate of M21, GB22 is multiplexed as the gate of M22, and GB23 is multiplexed as the gate of M23.

[0213] As shown in FIG20 , the second electrode of M23 includes a transition portion Z1 , a first electrode portion B1 , and a second electrode portion B2 ;

[0214] The first electrode portion B1 is disposed on the left side of the transition portion Z1, and the second electrode portion B2 is disposed on the right side of the transition portion Z1;

[0215] As shown in Figures 14 to 20, the orthographic projection of the first electrode portion B1 on the substrate at least partially overlaps with the orthographic projection of GB61 on the substrate, and the orthographic projection of the second electrode portion B2 on the substrate at least partially overlaps with the orthographic projection of GB62 on the substrate, so that even if the second row gate line GA2 moves right or left due to process deviations, Cgs can be roughly the same, where Cgs is the gate-source parasitic capacitance.

[0216] As shown in FIG14 to FIG22 , there is a first overlapping area A1 between the orthographic projection of the second row gate line GA2 on the base substrate and the orthographic projection of the first conductive sub-portion D1 included in the second connection structure on the base substrate, and there is a second overlapping area A2 between the orthographic projection of the second row gate line GA2 on the base substrate and the orthographic projection of the second conductive sub-portion D2 included in the second connection structure on the base substrate;

[0217] The area of ​​the first overlapping region A1 is less than 16 μm 2 , the area of ​​the second overlapping region A2 is less than 16 μm 2 , so as to reduce the parasitic capacitance between the second row gate line GA2 and the first conductive sub-portion D1, reduce the parasitic capacitance between the second row gate line GA2 and the second conductive sub-portion D2, and prevent the load on the second row gate line GA2 from increasing.

[0218] As shown in FIG23 , the display substrate described in at least one embodiment of the present disclosure may include a first row gate line GA1, a first row common electrode line CML1, a second row gate line GA2, a second row common electrode line CML2, a third row gate line GA3, a third row common electrode line CML3, a common electrode bus VBL, a first column data line DL1, a second column data line DL2, a third column data line DL3, a fourth column data line DL4, a fifth column data line DL5, a sixth column data line DL6, a first row and first column pixel electrode P11, a first row and second column pixel electrode P12, a first row and third column pixel electrode P13, a first row and fourth column pixel electrode P14, a first row and fifth column pixel electrode P15, a first row and sixth column pixel electrode P16, a second row and first column pixel electrode P21, a second row and second column pixel electrode P22, a second row and third column pixel electrode P23, a second row and fourth column pixel electrode P24, a second row and fifth column pixel electrode P25, a second row and sixth column pixel electrode P26, and a plurality of switching transistors;

[0219] GA1, GA2, GA3, CML1, CML2, CML3 and VBL are all located in the gate electrode layer;

[0220] The VBL is set around the display area;

[0221] There is communication between VBL, CML1, CML2 and CML3;

[0222] DL1, DL2, DL3, DL4, DL5 and DL6 are all located in the source and drain electrode layer;

[0223] P11, P12, P13, P14, P15, P16, P21, P22, P23, P24, P25 and P16 are all located in the second transparent conductive layer;

[0224] CML1 is electrically connected to the first second common electrode in the first transparent conductive layer through the third connection structure LJ3, and is electrically connected to the second second common electrode in the first transparent conductive layer through the fourth connection structure LJ4; the first second common electrode is electrically connected to VBL through the first conductive portion DB1 in the second transparent conductive layer, and the second second common electrode is electrically connected to VBL through the second conductive portion DB2 in the second transparent conductive layer;

[0225] CML2 is electrically connected to the third second common electrode located in the first transparent conductive layer through a fifth connection structure LJ5, and CML2 is electrically connected to the fourth second common electrode located in the first transparent conductive layer through a sixth connection structure LJ6;

[0226] CML3 is electrically connected to the fifth second common electrode located in the first transparent conductive layer through the seventh connection structure LJ7, and CML2 is electrically connected to the sixth second common electrode located in the first transparent conductive layer through the eighth connection structure LJ8; CML3 is electrically connected to VBL through the third conductive portion DB3 located in the second transparent conductive layer, and CML3 is electrically connected to VBL through the fourth conductive portion DB4 located in the second transparent conductive layer.

[0227] In at least one embodiment of the present disclosure, the display substrate includes a first transparent conductive layer, a gate electrode layer, a source-drain electrode layer, and a second transparent conductive layer arranged in sequence in a direction away from the base substrate;

[0228] The first conductive sub-portion in the connection structure is located in the first conductive layer; the second conductive sub-portion in the connection structure is located in the second conductive layer;

[0229] The first conductive layer is the second transparent conductive layer, and the second conductive layer is the source-drain electrode layer.

[0230] When manufacturing the display substrate,

[0231] First, as shown in FIG. 24 , a first transparent conductive layer 61 is formed on a base substrate 60 . The thickness of the first transparent conductive layer 61 may be 700 angstroms. The first transparent conductive layer 61 is subjected to coating, exposure, development, and wet etching to form a second common electrode.

[0232] As shown in FIG25 , a gate electrode layer 62 is then formed. The gate electrode layer includes a first Mo (molybdenum) layer, a first Al (aluminum) layer, and a second Mo layer, which are sequentially arranged in a direction away from the base substrate 60. The thickness of the first Mo layer is 150 angstroms, the thickness of the first Al layer is 3000 angstroms, and the thickness of the second Mo layer is 800 angstroms. After plating, exposure, development, and wet etching, gate lines and common electrode lines are formed.

[0233] As shown in FIG26 , after the gate lines and common electrode lines are formed, a whole layer of gate insulating layer 601 is laid. The thickness of the gate insulating layer 601 is 4000 angstroms and the gate insulating layer 601 is made of SiNx (silicon nitride).

[0234] Then, a semiconductor layer 65 is deposited. The semiconductor layer 65 has a thickness of 1700 angstroms. Then, a source-drain electrode layer 63 is deposited. The source-drain electrode layer may include a third Mo (molybdenum) layer, a second Al (aluminum) layer, and a fourth Mo layer sequentially arranged in a direction away from the substrate 60. The third Mo layer has a thickness of 150 angstroms, the second Al layer has a thickness of 3000 angstroms, and the fourth Mo layer has a thickness of 800 angstroms. Then, using an SSM (Single Slit Mask) process (4Mask process), a wet etching process and a dry etching process are performed to form the first electrode, the second electrode, and the channel of the switching transistor. The first wet etching process removes the source-drain metal to form the first electrode and the second electrode of the switching transistor. The second dry etching process is performed to expose the channel.

[0235] As shown in FIG27 , a passivation layer 602 is then formed by depositing a full layer of passivation layer having a thickness of 4000 angstroms and made of SiNx. After exposure, development, and etching, unnecessary insulating layers are dry-etched away to expose vias, such as the connection vias for the pixel electrodes, the first vias, and the second vias.

[0236] As shown in FIG28 , a second transparent conductive layer 64 is produced. The thickness of the second transparent conductive layer 64 is 700 angstroms. After coating, exposure, development and wet etching, the desired pattern (mainly pixel electrodes) and the conductive pattern located in the second transparent conductive layer including the connection structure are formed.

[0237] The 4Mask process is described as follows: the semiconductor layer and the source-drain electrode layer are produced at the same time. Compared with the traditional 5Mask process, the 4Mask process deposits the semiconductor layer and the source-drain electrode layer together, and only performs one mask after coating the photoresist. The SSM process is used to form partial exposure in the channel area. The source and drain metal patterns are first etched out, and then the channel is exposed through ashing.

[0238] The display device described in the embodiment of the present disclosure includes the above-mentioned display substrate.

[0239] In at least one embodiment of the present disclosure, the display device may be a liquid crystal display, but is not limited thereto. In actual operation, the display device may also be other types of display devices.

[0240] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising a connection structure, a first common electrode, a second common electrode, a first conductive layer and a second conductive layer; the connection structure comprises a first connection portion, a second connection portion and a conductive connection portion; The first connection portion is electrically connected to the first common electrode through a first via hole, and the second connection portion is electrically connected to the second common electrode through a second via hole; The conductive connection portion includes a first conductive sub-portion and a second conductive sub-portion; the first connection portion is electrically connected to the second connection portion through the first conductive sub-portion, and the first connection portion is electrically connected to the second connection portion through the second conductive sub-portion; The first conductive sub-portion is located in the first conductive layer, and the second conductive sub-portion is located in the second conductive layer; The length-to-width ratio of the first via hole is X1, the length-to-width ratio of the second via hole is X2, and X1<1<X2; The aspect ratio of the first via hole is the ratio of the maximum length of the first via hole along the first direction to the maximum width of the first via hole along the second direction, and the aspect ratio of the second via hole is the ratio of the maximum length of the second via hole along the first direction to the maximum width of the second via hole along the second direction; The first direction intersects the second direction.

2. The display substrate according to claim 1, wherein: The electrical conductivity of the first conductive layer is lower than the electrical conductivity of the second conductive layer.

3. The display substrate according to claim 1, wherein: The first connecting portion includes a first connecting portion and a second connecting portion; the first connecting portion is electrically connected to the first common electrode and the second connecting portion through the first via hole; The second connection portion includes a third connection portion and a fourth connection portion, and the third connection portion is electrically connected to the second common electrode and the fourth connection portion through the second via hole; The first connection portion is electrically connected to the third connection portion through the first conductive sub-portion, and the second connection portion is electrically connected to the fourth connection portion through the second conductive sub-portion.

4. The display substrate according to claim 3, wherein: Also included is a base substrate, the connection structure is arranged on the base substrate; the first via hole includes a first via hole portion and a second via hole portion arranged along the second direction; The orthographic projection of the first via portion on the base substrate does not overlap with the orthographic projection of the second connection portion on the base substrate; The orthographic projection of the first via portion on the base substrate is inside the orthographic projection of the first common electrode on the base substrate; The orthographic projection of the second via portion on the base substrate is inside the orthographic projection of the first common electrode on the base substrate, and the orthographic projection of the second via portion on the base substrate is inside the orthographic projection of the second connection portion on the base substrate; An orthographic projection of the second connection portion on the base substrate at least partially overlaps with an orthographic projection of the first common electrode on the base substrate.

5. The display substrate according to claim 4, wherein: Also comprising a third conductive layer; The first common electrode is located in the third conductive layer, the first connecting portion is located in the first conductive layer, and the second connecting portion is located in the second conductive layer.

6. The display substrate according to claim 3, wherein: Also includes a base substrate; the connection structure is arranged on the base substrate; the second via hole includes a third via hole portion and a fourth via hole portion arranged along the first direction; The orthographic projection of the third via portion on the base substrate does not overlap with the orthographic projection of the fourth connection portion on the base substrate; The orthographic projection of the third via portion on the base substrate is inside the orthographic projection of the third connection portion on the base substrate; The orthographic projection of the fourth via portion on the base substrate is inside the orthographic projection of the fourth connection portion on the base substrate; The orthographic projection of the fourth via portion on the base substrate is inside the orthographic projection of the third connection portion on the base substrate; An orthographic projection of the fourth connection portion on the base substrate at least partially overlaps with an orthographic projection of the second common electrode on the base substrate.

7. The display substrate according to claim 6, wherein: It also includes a fourth conductive layer; the second common electrode is located in the fourth conductive layer, the third connecting portion is located in the first conductive layer, and the fourth connecting portion is located in the second conductive layer.

8. The display substrate according to claim 1, wherein: X1 is less than or equal to 0.8, and X2 is greater than or equal to 1.

2.

9. The display substrate according to any one of claims 1 to 8, wherein: X1 / X2 is greater than or equal to 0.3 and less than or equal to 0.

6.

10. The display substrate according to claim 4, wherein: A distance between a first edge of an orthographic projection of the second via portion on the substrate and a second edge of an orthographic projection of the second connection portion on the substrate is greater than a first distance, and the first distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm; The first edge and the second edge are opposite edges.

11. The display substrate according to claim 4, wherein: The shortest distance along the second direction between an edge of an orthographic projection of the first via portion on the base substrate and an edge of an orthographic projection of the second connection portion on the base substrate is greater than a second distance greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

12. The display substrate according to claim 4, wherein: A length of the second via portion along the second direction is greater than a first length, and the first length is greater than or equal to 3.9 μm and less than or equal to 4.3 μm.

13. The display substrate according to claim 4, wherein: A distance between an edge of an orthographic projection of the first via hole on the base substrate and an edge of an orthographic projection of the first connection portion on the base substrate is greater than a third distance, and the third distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

14. The display substrate according to claim 4, wherein: The length of the first via hole along the first direction is greater than the second length, and the second length is greater than or equal to 3.8 μm and less than or equal to 4.2 μm.

15. The display substrate according to claim 6, wherein: A distance between a third edge of an orthographic projection of the fourth via portion on the substrate and a fourth edge of an orthographic projection of the fourth connection portion on the substrate is greater than a fourth distance, and the fourth distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm; The third edge and the fourth edge are opposite edges.

16. The display substrate according to claim 6, wherein: The shortest distance along the second direction between an edge of an orthographic projection of the third via portion on the base substrate and an edge of an orthographic projection of the fourth connection portion on the base substrate is greater than a fifth distance, and the fifth distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

17. The display substrate according to claim 6, wherein: A length of the fourth via portion along the first direction is greater than the third length, and the third length is greater than or equal to 3.9 μm and less than or equal to 4.3 μm.

18. The display substrate according to claim 5, wherein: The shortest distance along the first direction between an edge of an orthographic projection of the second via hole on the base substrate and an edge of an orthographic projection of the third connection portion on the base substrate is greater than a sixth distance, and the sixth distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

19. The display substrate according to claim 5, wherein: The length of the second via hole along the second direction is greater than a fourth length, and the fourth length is greater than or equal to 3.8 μm and less than or equal to 4.2 μm.

20. The display substrate according to claim 4, wherein: The length of the orthographic projection of the first via portion on the base substrate along the first direction is greater than the length of the orthographic projection of the second via portion on the base substrate along the first direction; or, A length of an orthographic projection of the first via portion on the base substrate along the first direction is smaller than a length of an orthographic projection of the second via portion on the base substrate along the first direction.

21. The display substrate according to claim 6, wherein: The length of the third via portion along the second direction is greater than the length of the fourth via portion along the second direction; or, A length of the third via portion along the second direction is smaller than a length of the fourth via portion along the second direction.

22. The display substrate according to claim 1, wherein: Also includes a base substrate and a gate line disposed on the base substrate; There is a first overlapping area between the orthographic projection of the gate line on the substrate and the orthographic projection of the first conductive sub-portion in the connection structure on the substrate; There is a second overlapping area between the orthographic projection of the gate line on the substrate and the orthographic projection of the second conductive sub-portion in the connection structure on the substrate; An area of ​​the first overlapping region is smaller than an area of ​​the second overlapping region.

23. The display substrate according to claim 1, wherein: It also includes a base substrate and pixel electrodes, data lines, gate lines and switch transistors arranged on the base substrate; The gate line comprises a first gate line portion and a second gate line portion which are interconnected; the first gate line portion is multiplexed as the gate of the switch transistor; The first electrode of the switch transistor is electrically connected to the data line; The second electrode of the switch transistor includes a switching portion, a first electrode portion and a second electrode portion; the switching portion is electrically connected to the pixel electrode, and the first electrode portion is arranged on the switching portion. A first side, wherein the second electrode portion is disposed on a second side of the transition portion, and the first side and the second side are opposite sides; The orthographic projection of the first electrode portion on the substrate at least partially overlaps with the orthographic projection of the first gate line portion on the substrate; An orthographic projection of the second electrode portion on the base substrate at least partially overlaps with an orthographic projection of the second gate line portion on the base substrate.

24. The display substrate according to any one of claims 1 to 8, wherein: It also includes a base substrate; the display substrate includes a first transparent conductive layer, a gate electrode layer, a source-drain electrode layer, and a second transparent conductive layer arranged in sequence in a direction away from the base substrate; The first conductive layer is the second transparent conductive layer, and the second conductive layer is the source-drain electrode layer.

25. A display device comprising the display substrate according to any one of claims 1 to 24.

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