Manufacturing method for semiconductor device

Abstract

Provided in the embodiments of the present disclosure is a manufacturing method for a semiconductor device. The manufacturing method comprises: forming a sacrificial area on the surface of a substrate; forming a laminated structure on the sacrificial area, wherein the laminated structure comprises a first semiconductor layer and a second semiconductor layer which are alternately stacked; removing the sacrificial area, so as to form a cavity between the substrate and the laminated structure; filling the cavity with an insulating layer; removing one of the first semiconductor layer and the second semiconductor layer; and forming a gate structure around the other one of the first semiconductor layer and the second semiconductor layer.

Description

Method for manufacturing semiconductor device Technical Field

[0001] The present disclosure belongs to, but is not limited to, the field of semiconductor manufacturing technology, and particularly relates to a method for manufacturing a semiconductor device. Background Art

[0002] With the continuous development of semiconductor manufacturing technology, the critical dimensions of semiconductor devices continue to shrink. However, the reduction in gate width leads to the so-called short-channel effects, which can cause drain-induced barrier lowering (DIBL), making it impossible for semiconductor devices to be turned off.

[0003] To address this challenge, Fin FETs and Gate-All-Around FETs (GAA FETs) have been proposed. In 3nm and higher process technologies, GAA FETs offer significant advantages over Fin FETs, such as better control of leakage current, smaller DIBL, higher performance, and greater device density.

[0004] As shown in FIG1 , a conventional GAA FET includes a substrate 11, a plurality of channel regions 12 formed on the substrate 11, a gate insulating layer (not shown) surrounding the channel regions 12, and a metal gate 13 surrounding the gate insulating layer. The channel regions 12 are surrounded on all sides by the metal gate 13, thereby achieving a smaller DIBL. However, further improvements to the GAA FET are still needed.

[0005] Summary of the Invention

[0006] The embodiments of the present disclosure provide a method for manufacturing a semiconductor device to solve the problem of poor high-frequency switching characteristics of semiconductor devices in the related art.

[0007] In order to solve the above technical problems, the present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0008] forming a sacrificial region on a surface of the substrate;

[0009] forming a stacked structure on the sacrificial region, the stacked structure comprising alternately stacked first semiconductor layers and second semiconductor layers;

[0010] removing the sacrificial region to form a cavity between the substrate and the stacked structure;

[0011] filling the cavity with an insulating layer;

[0012] removing one of the first semiconductor layer and the second semiconductor layer;

[0013] A gate structure is formed around the other of the first semiconductor layer and the second semiconductor layer.

[0014] In some implementations, forming a sacrificial region on the surface of the substrate includes:

[0015] Performing ion implantation on a predetermined area on the surface of the substrate;

[0016] Annealing is performed on the ion-implanted region to form the sacrificial region.

[0017] In some implementations, the ion implantation is performed for n-type doping, and the ion implantation dose is 1×10 15 / cm 2 to 5×10 16 / cm 2 .

[0018] In some implementations, the n-type dopant includes at least one of Sb, As, and P.

[0019] In some implementations, forming a stacked structure on the sacrificial region includes:

[0020] forming the first semiconductor layers and the second semiconductor layers alternately stacked on the surface of the substrate;

[0021] The alternately stacked first semiconductor layers and the second semiconductor layers are etched to obtain the stacked structure, and at least a portion of the sidewall of the sacrificial region is exposed.

[0022] In some implementations, etching the alternately stacked first semiconductor layers and the second semiconductor layers includes:

[0023] forming a hard mask layer above the alternately stacked first semiconductor layers and the second semiconductor layers, wherein a projection of the hard mask layer on the substrate corresponds to the sacrificial region;

[0024] The first semiconductor layer, the second semiconductor layer and the substrate are etched using the hard mask layer to form the stacked structure, and grooves are formed in the substrate on both sides of the stacked structure.

[0025] In some implementations, during the process of forming the grooves in the substrate on both sides of the stacked structure, at least a portion of the sidewalls of the sacrificial region are exposed.

[0026] In some implementations, forming a stacked structure on the sacrificial area further includes:

[0027] forming a protective layer covering the stacked structure and the substrate;

[0028] Anisotropic etching is performed on the protection layer and the substrate, the protection layer on the sidewall of the stacked structure is retained as a sidewall protection layer, and at least a portion of the sidewall of the sacrificial area is exposed.

[0029] In some implementations, forming a protection layer covering the stacked structure and the substrate includes:

[0030] forming the protective layer by an ALD process; or

[0031] The protective layer comprises a silicon nitride-based material; or

[0032] The protection layer includes at least one of silicon nitride, SiON, SiOCN or SiCN.

[0033] In some implementations, anisotropically etching the protective layer includes:

[0034] The anisotropic etching is performed by adopting a process gas with a high etching rate, high upper electrode radio frequency power and high lower electrode radio frequency power.

[0035] In some implementations, the process gas includes chlorine or fluorocarbon gas; or

[0036] The radio frequency power of the upper electrode ranges from 100W to 3000W, and the radio frequency power of the lower electrode ranges from 50W to 1000W.

[0037] In some implementations, the hard mask layer includes at least one of an oxide insulating layer and a nitride insulating layer; or

[0038] The hard mask layer includes a first hard mask layer and a second hard mask layer located over the first hard mask layer, the first hard mask layer includes silicon oxide, and the second hard mask layer includes silicon nitride.

[0039] In some implementations, removing the sacrificial area includes:

[0040] The sacrificial region is subjected to isotropic plasma etching.

[0041] In some implementations, performing isotropic plasma etching on the sacrificial region includes:

[0042] The sacrificial area is etched in a low-pressure environment without loading the lower electrode radio frequency power.

[0043] In some implementations, the low pressure environment is 5 mTorr to 800 mTorr.

[0044] In some implementations, the etching gas used in the isotropic plasma etching is an etching gas that enables an etching selectivity ratio between the sacrificial region and the substrate to be greater than a predetermined value.

[0045] In some implementations, the substrate is silicon, the sacrificial region is n-type heavily doped silicon, and the etching gas used in the isotropic plasma etching is chlorine;

[0046] An etching selectivity ratio between the sacrificial region and the substrate is greater than 200.

[0047] In some implementations, the first semiconductor layer and the second semiconductor layer are made of semiconductor materials having different lattice constants.

[0048] In some implementations, the first semiconductor layer and the second semiconductor layer include at least one of Si, Ge, SiGe, GeSn, SiGeSn, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP.

[0049] In some implementations, filling the cavity with an insulating layer includes:

[0050] Depositing the insulating layer around the stacked structure and on the surface of the substrate until the insulating layer below the stacked structure at the cavity is in contact with the insulating layer above the substrate at the cavity;

[0051] The insulating layer outside the cavity is removed.

[0052] In some implementations, depositing the insulating layer around the stacked structure and on the surface of the substrate includes:

[0053] The insulating layer is deposited using an atomic layer deposition process.

[0054] In some implementations, the method for manufacturing a semiconductor device further includes:

[0055] The insulating layer is annealed.

[0056] In some implementations, the method for manufacturing a semiconductor device further includes:

[0057] removing the sidewall protection layer and the hard mask layer;

[0058] The groove is filled to form a shallow trench isolation structure.

[0059] In some implementations, before removing one of the first semiconductor layer and the second semiconductor layer, the method further includes:

[0060] A source region and a drain region are respectively formed on both sides of the region of the stacked structure where the gate structure is to be formed.

[0061] In some implementations, the gate structure includes a gate dielectric layer disposed around the other of the first semiconductor layer and the second semiconductor layer and a gate electrode layer disposed around the gate dielectric layer;

[0062] The other of the first semiconductor layer and the second semiconductor layer surrounded by the gate structure is formed as a channel region of the semiconductor device.

[0063] In the manufacturing method of the semiconductor device of the embodiment of the present disclosure, by forming an insulating layer between the bottom gate structure of the semiconductor device and the substrate, the parasitic gate capacitance between the bottom gate structure and the substrate is suppressed, thereby improving the high-frequency switching characteristics of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] FIG1 shows a schematic diagram of a GAA FET in related art;

[0065] FIG2 is a schematic diagram showing one of the various stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0066] FIG3 is a schematic diagram showing one of the various stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0067] FIG4 is a schematic diagram showing one of the various stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0068] FIG5 is a schematic diagram showing one of the various stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0069] FIG6 is a schematic diagram showing one of the various stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0070] FIG7A is a schematic diagram showing one of the various stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0071] FIG7B shows a schematic cross-sectional view along the dotted line in FIG7A ;

[0072] FIG8A is a schematic isometric view illustrating one of the various stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0073] FIG8B shows a front view of FIG8A ;

[0074] FIG8C shows a schematic cross-sectional view along the dotted line in FIG8B ;

[0075] 9A is a schematic isometric view illustrating one of the various stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0076] FIG9B shows a front view of FIG9A ;

[0077] FIG9C shows a schematic cross-sectional view along the dotted line in FIG9B ;

[0078] FIG10A is a schematic isometric view illustrating one of the various stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0079] FIG10B shows a front schematic diagram of FIG10A ;

[0080] FIG10C shows a schematic cross-sectional view along the dotted line in FIG10B ;

[0081] FIG11 is a schematic diagram showing one of the various stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0082] FIG12 is a schematic isometric view of one of the various stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0083] FIG13A is a schematic diagram showing one of the various stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0084] FIG13B shows a schematic cross-sectional view along the dotted line in FIG13A ;

[0085] 14A is a schematic axial cross-sectional view showing one of the various stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0086] FIG. 14B shows a schematic front view of FIG. 14A . DETAILED DESCRIPTION

[0087] To make the objectives, technical solutions, and advantages of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without creative work are within the scope of protection of the present disclosure.

[0088] It should be understood by those skilled in the art that the embodiments of the present disclosure are merely illustrations of the structures and methods claimed in the present disclosure that can be implemented in various forms. In addition, each example given in conjunction with the various embodiments is intended to be illustrative rather than restrictive. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show the details of specific components. Therefore, the specific structural and functional details in the embodiments of the present disclosure should not be interpreted as restrictive, but merely as a representative basis for teaching those skilled in the art to adopt the methods and structures of the embodiments of the present disclosure in different ways. It should also be noted that identical and corresponding elements are represented by the same reference numerals.

[0089] In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present disclosure. However, it will be understood by those skilled in the art that the various embodiments of the present disclosure may be practiced without these specific details. In other cases, well-known structures or processing steps have not been described in detail to avoid obscuring the present disclosure.

[0090] For the purposes of the following description, the terms "upper," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall relate to the orientation of the structures and methods disclosed in the drawings of the specification. It will be understood that when an element as a layer, region, or substrate is referred to as being "on" another element, the element can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements between the two. It will also be understood that when an element is referred to as being "under" another element, the element can be directly under the other element or intervening elements may be present. Conversely, when an element is referred to as being "directly under" another element, there are no intervening elements between the two.

[0091] A GAA FET in related art is shown in FIG1 , which includes a substrate 11, a plurality of channel regions 12 formed on the substrate 11, a gate insulating layer (not shown) disposed around the channel regions 12, and a metal gate 13 disposed around the gate insulating layer. The inventors of the present disclosure have discovered that in this GAA FET structure, a parasitic gate capacitance is formed between the bottommost metal gate 13 and the substrate 11. When a turn-on or turn-off voltage is applied to the metal gate 13, the parasitic gate capacitance is charged, thereby affecting the turn-on or turn-off speed of the GAA FET and reducing the high-frequency switching characteristics of the GAA FET.

[0092] To solve this problem, a main concept proposed in the embodiments of the present disclosure is to set an insulating layer between the bottom metal gate 13 of the GAA FET in the related art and the substrate 11, so as to suppress the parasitic gate capacitance and improve the high-frequency switching characteristics of the GAA FET.

[0093] The technical solutions provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0094] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, which may include the following steps.

[0095] S110 , forming a sacrificial region on the surface of the substrate.

[0096] As shown in FIG3 , a sacrificial region 101 is formed on the surface of the substrate 100. The sacrificial region 101 herein refers to a sacrificial layer having a certain depth formed in the substrate 100, and the upper surface of the sacrificial layer is coplanar with the upper surface of the substrate 100. The presently disclosed embodiment does not impose any restrictions on the method for manufacturing the sacrificial layer. As long as there is a large etching selectivity between the sacrificial region 101 and the substrate 100, the sacrificial region 101 can be removed by selective etching in subsequent steps. As will be seen below, the position of the sacrificial region 101 corresponds to the position of the projection of the channel region of the semiconductor device on the substrate 100.

[0097] The substrate 100 includes a single crystal semiconductor layer on at least a portion of its surface. The substrate 100 may include a single crystal semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some embodiments, the substrate 100 may be made of crystalline Si. The substrate 100 may include one or more buffer layers (not shown) in its surface region. The buffer layer may be used to gradually change the lattice constant from the lattice constant of the substrate to the lattice constant of the source / drain region, for example, the lattice constant of the plurality of buffer layers gradually changes from the substrate to the source / drain region to reduce the difference in lattice constant between each adjacent two film layers (including the substrate and the adjacent buffer layer, each adjacent buffer layer, and the source / drain region and the adjacent buffer layer). The buffer layer can be formed of an epitaxially grown single crystal semiconductor material such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In some embodiments, substrate 100 can include a silicon germanium (SiGe) buffer layer epitaxially grown on a silicon substrate. Substrate 100 can also include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity).

[0098] In some implementations of the present disclosure, step S110 may include:

[0099] S111 , forming a photoresist pattern 102 on the substrate 100 using a mask, wherein the photoresist pattern 102 exposes a predetermined area on the surface of the substrate 100 , as shown in FIG2 . The predetermined area is also the area where the sacrificial area 101 will be formed.

[0100] S112 , performing ion implantation on a predetermined area on the surface of the substrate 100 .

[0101] As shown in FIG. 2 , ion implantation is performed in a predetermined area by shielding the photoresist pattern 102 to form a doped region, ie, a sacrificial region 101 . The sacrificial region 101 may be, for example, an n-type doped region.

[0102] In some embodiments, the ion implantation dose may be 1×10 15 / cm 2 to 5×10 16 / cm 2 The implanted impurities may be, for example, n-type dopants. This ion implantation forms a sacrificial region 101 in the substrate 100. The sacrificial region 101 is a heavily n-type doped region, thereby increasing the etching selectivity between the formed sacrificial region 101 and the substrate 100. Optionally, the n-type dopant may include at least one of Sb, As, and P.

[0103] In some embodiments, to improve the pattern accuracy of the sacrificial region 101, the photoresist pattern 102 may include two layers, namely, a double anti-reflective coating (DARC) located below (adjacent to the surface of the substrate 100) and a photoresist layer located above the DARC. Those skilled in the art will appreciate that the photoresist pattern 102 may also include more layers or a single layer.

[0104] S113 , removing the photoresist pattern 102 .

[0105] Various stripping processes may be used to remove the photoresist pattern 102 , and the present disclosure does not impose any limitation thereto.

[0106] S114 , performing annealing on the region after ion implantation to form a sacrificial region 101 .

[0107] After ion implantation, the substrate's lattice is damaged. To allow continued epitaxial growth on the substrate, the substrate needs to be annealed to recrystallize the damaged regions after ion implantation. In some embodiments, a rapid thermal annealing (RTA) process is used to perform the annealing.

[0108] S120 , forming a stacked structure on the sacrificial region, the stacked structure comprising alternately stacked first semiconductor layers and second semiconductor layers.

[0109] 7A and 7B , a stacked structure is formed on the sacrificial region 101. The stacked structure may include alternately stacked first semiconductor layers 110 and second semiconductor layers 120. In addition, a hard mask layer 130 is also formed on the stacked structure as a mask for etching the stacked structure.

[0110] The first semiconductor layer 110 and the second semiconductor layer 120 are made of materials with different lattice constants and may include one or more layers of Si, Ge, SiGe, GeSn, SiGeSn, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP.

[0111] In some embodiments, the first semiconductor layer 110 and the second semiconductor layer 120 are made of Si, a Si compound, SiGe, Ge, or a Ge compound. In some embodiments, the first semiconductor layer 110 is Si and the second semiconductor layer 120 is SiGe. In other embodiments, the first semiconductor layer 110 may also be SiGe, and the Ge content of the first semiconductor layer 110 and the second semiconductor layer 120 is different.

[0112] 7A and 7B illustrate three first semiconductor layers 110 and three second semiconductor layers 120, but the disclosed embodiments are not limited thereto. More or fewer first semiconductor layers 110 and second semiconductor layers 120 are feasible. In some embodiments, each of the first semiconductor layer 110 and the second semiconductor layer 120 is formed in a number of 2 to 20 layers. By adjusting the number of the first semiconductor layer 110 and / or the second semiconductor layer 120, the drive current of the GAA FET device can be adjusted.

[0113] The first semiconductor layer 110 and the second semiconductor layer 120 are epitaxially formed on the substrate 100. The thickness of the first semiconductor layer 110 and the thickness of the second semiconductor layer 120 may be the same or different. Moreover, the thickness of each layer in the first semiconductor layer 110 may be the same or different; the thickness of each layer in the second semiconductor layer 120 may be the same or different. The embodiments of the present disclosure do not impose any restrictions on this. In some embodiments, the thickness of the first semiconductor layer 110 is in the range of 2 nm to 20 nm. In some embodiments, the thickness of the second semiconductor layer 120 is in the range of 2 nm to 20 nm.

[0114] The hard mask layer 130 may be a single layer or multiple layers, and the embodiments of the present disclosure do not impose any limitation on this. In some embodiments, the hard mask layer 130 includes at least one of an oxide insulating layer and a nitride insulating layer. For example, the hard mask layer 130 may include a first hard mask layer 131 and a second hard mask layer 132 located above the first hard mask layer 131. The first hard mask layer 131 may include silicon oxide, for example, a pad oxide layer made of silicon oxide, and the pad oxide layer may be formed by thermal oxidation. The second hard mask layer 132 may include silicon nitride, for example, made of silicon nitride (SiN), and silicon nitride is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. CVD includes low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD). The hard mask layer 130 is patterned into a mask pattern by using a patterning process including photolithography and etching.

[0115] In some implementations of the embodiments of the present disclosure, the above step S120 may include:

[0116] S121 , forming alternately stacked first semiconductor layers 110 and second semiconductor layers 120 on the surface of the substrate 100 , as shown in FIG. 4 .

[0117] S122 , forming a hard mask layer 130 on the alternately stacked first semiconductor layers 110 and second semiconductor layers 120 , wherein a projection of the hard mask layer 130 on the substrate 100 corresponds to the sacrificial region 101 , as shown in FIG. 4 .

[0118] It should be noted that the entire hard mask layer 130, before patterning, covers the entire substrate 100. A photoresist pattern is then formed using a mask, and during patterning, the excess portions of the hard mask layer 130 are etched away to obtain the patterned hard mask layer 130 shown in FIG4 . The mask used in step S122 is the same as the mask used in step S111, but the photoresist used is different. In one embodiment, a positive photoresist is used in step S122, while a negative photoresist is used in step S111; in another embodiment, a negative photoresist is used in step S122, while a positive photoresist is used in step S111.

[0119] S123 , using the hard mask layer 130 , etching the first semiconductor layer 110 , the second semiconductor layer 120 and the substrate 100 to obtain a stacked structure, and forming grooves in the substrate 100 on both sides of the stacked structure.

[0120] As shown in FIG5 , in this step, after etching the alternately stacked first semiconductor layer 110 and the second semiconductor layer 120 is completed, etching may be continued on the underlying substrate 100 to form grooves in the substrate 100 on both sides of the stacked structure, thereby facilitating the subsequent formation of a shallow trench isolation (STI) structure.

[0121] In some embodiments of this step, at least a portion of the sidewalls of the sacrificial region 101 can be exposed during the process of forming recesses in the substrate 100 on both sides of the stacked structure. In subsequent processes, the sacrificial region 101 can be removed by selective lateral etching. However, in this embodiment, the lateral etching of the sacrificial region 101 can damage the channel regions in the first semiconductor layer 110 and the second semiconductor layer 120, thereby affecting the performance of the GAA FET device.

[0122] In some other embodiments of this step, during the process of forming the grooves in the substrate 100 on both sides of the stacked structure, the etching depth can be controlled, for example, by detecting the etching endpoint by optical emission spectroscopy (OES) so that the etching depth reaches a depth that just does not expose the sacrificial area 101. The subsequent steps are described below.

[0123] S124 , forming a protection layer 140 covering the stacked structure and the substrate 100 , as shown in FIG6 .

[0124] The protective layer 140 is used to protect the channel region from being laterally etched during the subsequent etching process of the sacrificial region 101. The protective layer 140 may include a silicon nitride-based material formed by CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes, such as silicon nitride, SiON, SiOCN, or SiCN, and combinations thereof. In some embodiments, the protective layer 140 is made of silicon nitride, for example, by an ALD process, thereby ensuring good density of the protective layer 140 to protect the channel region from being laterally etched during the subsequent etching process of the sacrificial region 101.

[0125] S125 , anisotropically etching the protection layer 140 and the substrate 100 , retaining the protection layer on the sidewall of the stacked structure as a sidewall protection layer 141 , and exposing at least a portion of the sidewall of the sacrificial region 101 , as shown in FIG. 7A and FIG. 7B .

[0126] In this step, a process gas with a high etching rate, high upper electrode RF power, and high lower electrode RF power can be used to perform the anisotropic etching, thereby etching only the protective layer 140 and a portion of the substrate 100 in the horizontal direction, retaining the sidewall protective layer 141 on the sidewalls of the stacked structure, and exposing at least a portion of the sidewalls of the sacrificial area 101, preferably, exposing the sidewalls of the entire sacrificial area 101, so as to facilitate more complete removal of the sacrificial area 101 in subsequent processes. Here, the protective layer 140 in the horizontal direction refers to the protective layer 140 laid in the horizontal direction or in an inclined direction close to the horizontal direction, such as the portion of the protective layer 140 covering the surface of the substrate 100 and the portion covering the hard mask layer 130.

[0127] The use of high lower electrode RF power can provide downward acceleration energy and direction for the plasma, and the use of high upper electrode RF power can generate more plasma. At the same time, the use of a process gas with a high etching rate can enhance the directionality of the anisotropic etching, so that the protective layer 140 and a portion of the substrate 100 in the horizontal direction can be etched away to expose at least a portion of the sidewall of the sacrificial area 101, while avoiding the protective layer 140 located on the sidewall of the stacked structure from being etched laterally as much as possible, thereby providing protection for the channel area in the subsequent etching process. It should be understood by those skilled in the art that the so-called upper electrode RF power generally refers to the RF power applied to the RF coil located at the top of the process chamber. In some embodiments, the RF coil can also be located on the side of the process chamber to ionize the process gas to generate plasma; the so-called lower electrode RF power generally refers to the RF power applied to the lower electrode assembly of the process chamber. The lower electrode assembly includes a wafer support device for generating an RF bias to improve the directionality of the plasma.

[0128] In some embodiments, the protective layer 140 is silicon nitride, the substrate 100 is silicon, and the process gas may include chlorine or a fluorocarbon gas. The fluorocarbon gas may be, for example, CF4 or CHF3. Of course, during the etching process, the process gas may also include a shielding gas to protect the sidewall protective layer 140. The shielding gas may include at least one of N2 and CH4. More specifically, the RF power of the upper electrode may range from 100W to 3000W, for example, and the RF power of the lower electrode may range from 50W to 1000W, for example.

[0129] S130 , removing the sacrificial region to form a cavity between the substrate and the stacked structure.

[0130] As shown in FIG. 8A to FIG. 8C , the sacrificial region 101 between the substrate 100 and the stacked structure may be removed by selective etching, thereby forming a cavity 103 .

[0131] In contrast to step S125, in this step, the substrate 100 needs to be isotropically etched to remove the sacrificial area 101. Therefore, in this step, no lower electrode RF power is loaded, and a lower upper electrode RF power is loaded. The upper electrode RF power in this step is lower than the upper electrode RF power in step S125. During the etching process, the sacrificial area 101 is etched under a low-pressure environment, that is, a lower chamber pressure is required, which is, for example, lower than the chamber pressure in step S125, to increase the free path of the etching ions, thereby completely removing the sacrificial area 101. Specifically, the chamber pressure used in the above step S130 is 5mTorr to 800mTorr.

[0132] In some embodiments, the etching gas used in the isotropic plasma etching in step S130 is an etching gas that enables an etching selectivity ratio between the sacrificial region 101 and the substrate 100 to be greater than a predetermined value, thereby ensuring that the sacrificial region 101 can be completely removed without damaging the structure of the semiconductor device. For example, if the substrate 100 is silicon and the sacrificial region 101 is n-type heavily doped silicon, in this case, chlorine gas can be selected as the etching gas to increase the etching selectivity ratio between n-type heavily doped silicon and silicon, and between n-type heavily doped silicon and silicon nitride. The etching selectivity ratio between n-type heavily doped silicon and silicon is greater than 200 (i.e., the predetermined value). Furthermore, the etching selectivity ratio is, for example, greater than (200-250):1, thereby ensuring that the sacrificial region 101 can be completely removed without damaging the structure of the semiconductor device. On this basis, in some embodiments, the sidewall protection layer 141 is silicon nitride, the uppermost second hard mask layer 132 in the hard mask layer 130 is silicon nitride, and the etching selectivity between n-type heavily doped silicon and silicon nitride is greater than 200. Furthermore, the etching selectivity is, for example, greater than (200-250): 1. It should be noted that in order to ensure that the sacrificial area 101 can be completely removed while substantially not etching the substrate 100, the sidewall protection layer 141, and the second hard mask layer 132, it is necessary to ensure that the etching selectivity between the sacrificial area 101 and the substrate 100 is greater than a predetermined value, and that the etching selectivity between the sacrificial area 101 and the sidewall protection layer 141, as well as the etching selectivity between the sacrificial area 101 and the second hard mask layer 132 are sufficiently large.

[0133] It should be understood that the embodiments of the present disclosure are not limited to this. The sacrificial area, substrate, sidewall protection layer and hard mask layer may also be made of other materials. Those skilled in the art can reasonably select the etching gas to be used based on the materials of the sacrificial area, substrate, sidewall protection layer and hard mask layer. As long as the etching selectivity between the sacrificial area 101 and the substrate 100, the etching selectivity between the sacrificial area 101 and the sidewall protection layer 141, and the etching selectivity between the sacrificial area 101 and the second hard mask layer 132 are large enough, they will not be elaborated here.

[0134] S140 , filling the cavity with an insulating layer.

[0135] As shown in Figures 10A to 10C , by filling the cavity with an insulating layer 151, an insulating layer 151 is formed between the bottommost gate structure of the subsequently formed GAA FET and the substrate 100. This suppresses the parasitic gate capacitance between the bottommost gate structure and the substrate, thereby improving the high-frequency switching characteristics of the semiconductor device. In some embodiments, the insulating layer 151 may be, for example, silicon nitride, silicon oxide, or silicon oxynitride. This disclosure does not impose any restrictions on the material or filling method of the insulating layer 151.

[0136] In some implementations of the present disclosure, step S140 may include:

[0137] S141 , depositing an insulating layer 150 around the stacked structure and on the surface of the substrate 100 until the insulating layer 150 below the stacked structure at the cavity 103 is aligned with the insulating layer 150 above the substrate 100 at the cavity 103 , as shown in FIG. 9A to FIG. 9C .

[0138] Those skilled in the art will appreciate that the horizontal line drawn between the insulating layer 150 below the laminated structure at the cavity 103 and the insulating layer 150 above the substrate 100 at the cavity 103 in FIG. 9A to FIG. 9C is merely for the purpose of illustrating more clearly that, in the disclosed embodiment, the insulating layer 150 is formed by continuously depositing the insulating layer 150 below the laminated structure at the cavity 103 and the insulating layer 150 above the substrate 100 at the cavity 103 so as to adhere to each other, and is not intended to limit the insulating layer 150 to being intentionally divided into two layers. That is, within the cavity 103, a portion of the insulating layer 150 gradually increases in thickness downward from the top of the cavity 103 (i.e., the lower surface of the laminated structure in the cavity 103), while another portion of the insulating layer 150 gradually increases in thickness upward from the bottom of the cavity 103 (i.e., the upper surface of the substrate 100 in the cavity 103). The opposing surfaces of the two portions of the insulating layer 150 gradually approach each other as the thickness increases until they adhere together.

[0139] In order to allow the process gas to be deposited deep into the cavity 103 , low-pressure CVD (LPCVD) or atomic layer deposition (ALD) processes can be used to form the insulating layer 150 . Furthermore, the ALD process is used to form the insulating layer 150 , so that the cavity 103 can be better filled.

[0140] Since the insulating layer 150 outside the cavity needs to be removed in subsequent processes and only the insulating layer 150 inside the cavity needs to be retained, in some embodiments, a large etching selectivity is required between the insulating layer 150 and the substrate 100 and between the insulating layer 150 and the sidewall protection layer 141, so that the insulating layer 150 outside the cavity can be selectively removed.

[0141] S142 , removing the insulating layer 150 outside the cavity 103 .

[0142] As shown in Figures 10A to 10C, the insulating layer 150 outside the cavity 103 can be removed by dry or wet etching. After the portion of the insulating layer 150 outside the cavity 103 is removed, the portion remaining only within the cavity 103 is the insulating layer 151. In some embodiments, the insulating layer 150 is silicon oxide, the sidewall protection layer 141 is silicon nitride, and the substrate 100 is silicon. This allows for a wide etching selectivity between the insulating layer 150 and the sidewall protection layer 141, and between the insulating layer 150 and the substrate 100, facilitating the removal of the insulating layer 150 outside the cavity 103.

[0143] In some implementations, the above step S140 may further include:

[0144] S143 , performing annealing treatment on the insulating layer 151 .

[0145] Annealing the insulating layer 151 can help reduce lattice defects in the insulating layer 151 , increase the density of the insulating layer 151 , and improve the high-voltage tolerance of the insulating layer 151 , thereby improving the reliability of the insulating layer 151 .

[0146] It should be noted that the annealing process in step S143 can be performed before or after removing the insulating layer outside the cavity in step S142, and the present disclosure does not impose any limitation on this. The annealing process can be performed using, for example, a rapid thermal annealing process or a laser annealing process.

[0147] In some implementations, after step S143, the following steps may also be included:

[0148] S144 , removing the sidewall protection layer 141 and the hard mask layer 130 , as shown in FIG. 11 .

[0149] In some embodiments, the sidewall protection layer 141 and the hard mask layer 130 have a large etching selectivity with the substrate 100 , the first semiconductor layer 110 , and the second semiconductor layer 120 , thereby facilitating removal of the sidewall protection layer 141 and the hard mask layer 130 .

[0150] S145: Fill the groove to form a shallow trench isolation structure 160, as shown in Figure 11. The shallow trench isolation structure 160 can achieve isolation between various GAA FETs.

[0151] In some implementations, before step S150, the following steps may also be included:

[0152] S146 , forming a source region and a drain region on both sides of the region of the stacked structure where the gate structure is to be formed, hereinafter referred to as source / drain region 200 , as shown in FIG12 .

[0153] Specifically, step S146 may include: forming a sacrificial gate in the region corresponding to the gate structure to be formed; doping the stacked structure on both sides of the sacrificial gate to form the source / drain regions 200; forming an isolation layer 210 and an isolation pad 220 on both sides of the sacrificial gate to cover the top and side portions of the source / drain regions 200, respectively; and removing the sacrificial gate to expose the channel region between the source / drain regions 200, thereby obtaining the semiconductor structure shown in FIG12. The above process steps are conventional in the art and will not be described in detail here.

[0154] S150 , removing one of the first semiconductor layer 110 and the second semiconductor layer 120 .

[0155] As shown in FIG. 13A and FIG. 13B , the first semiconductor layer 110 is removed, thereby forming a plurality of vacancies 111 in regions corresponding to the gate structures.

[0156] For Si, SiGe, or Ge-based GAA FETs, Si is typically used for n-channel GAA FETs, while SiGe or Ge is used for p-channel GAA FETs. In the case of SiGe p-channel GAA FETs, a higher Ge concentration can improve transistor performance. Those skilled in the art can remove the first semiconductor layer 110 and the second semiconductor layer 120 as needed.

[0157] S160 , forming a gate structure 121 around the other of the first semiconductor layer 110 and the second semiconductor layer 120 .

[0158] In some embodiments, the gate structure 121 includes a gate dielectric layer disposed around the other of the first semiconductor layer 110 and the second semiconductor layer 120, and a gate electrode layer disposed around the gate dielectric layer; and the other of the first semiconductor layer 110 and the second semiconductor layer 120 surrounded by the gate structure 121 forms the channel region of the semiconductor device. For example, as shown in Figures 14A and 14B, the gate structure 121 is formed around the second semiconductor layer 120, and the second semiconductor layer 120 surrounded by the gate structure 121 forms the channel region of a GAA FET. The gate structure 121 may include a gate dielectric layer and a gate electrode layer disposed around the second semiconductor layer 120.

[0159] In some embodiments, the gate dielectric layer may include one or more layers of dielectric materials such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. High-k dielectric materials may include, for example, H f O2、H f SiO, H f SiON, H f TaO、H f TiO, H f ZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (H f The gate dielectric layer may be formed by CVD, ALD, or any other suitable method. In an alternative embodiment, the gate dielectric layer may have a thickness in the range of about 1 nm to about 6 nm.

[0160] In some embodiments, the gate electrode layer may include one or more layers of a conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, alloys thereof, other suitable materials, and / or combinations thereof. The gate electrode layer may be formed by CVD, ALD, electroplating, or other suitable methods.

[0161] In some embodiments, the above process steps are conventional process steps in the art, and the gap between the two isolation layers 210 may also be filled by an insulating cover layer, which will not be described in detail here.

[0162] In the manufacturing method of the semiconductor device of the embodiment of the present disclosure, by forming an insulating layer between the bottom gate structure of the semiconductor device and the substrate, the parasitic gate capacitance between the bottom gate structure and the substrate is suppressed, thereby improving the high-frequency switching characteristics of the semiconductor device.

[0163] The above embodiments of the present disclosure focus on the differences between the various embodiments. As long as the different optimization features between the various embodiments are not contradictory, they can be combined to form a better embodiment. Considering the simplicity of the text, they will not be repeated here.

[0164] The foregoing is merely an embodiment of the present disclosure and is not intended to limit the present disclosure. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure are intended to be included within the scope of the claims of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, wherein: include: forming a sacrificial region on a surface of the substrate; forming a stacked structure on the sacrificial region, the stacked structure comprising first semiconductor layers and second semiconductor layers stacked alternately; removing the sacrificial region to form a cavity between the substrate and the stacked structure; filling an insulating layer in the cavity; removing one of the first semiconductor layer and the second semiconductor layer; A gate structure is formed around the other of the first semiconductor layer and the second semiconductor layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of a sacrificial area on the surface of the substrate comprises: Performing ion implantation on a preset area on the surface of the substrate; The ion-implanted region is annealed to form the sacrificial region.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The ion implantation is performed for n-type doping, and the dose of the ion implantation is 1×10 15 / cm 2 Up to 5×10 16 / cm 2 .

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The n-type dopant includes at least one of Sb, As, and P.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of a stacked structure on the sacrificial area comprises: Forming the first semiconductor layer and the second semiconductor layer alternately stacked on the surface of the substrate; The first semiconductor layers and the second semiconductor layers that are alternately stacked are etched to obtain the stacked structure, and at least a portion of the sidewall of the sacrificial region is exposed.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The etching of the alternately stacked first semiconductor layers and the second semiconductor layers comprises: forming a hard mask layer above the alternately stacked first semiconductor layers and the second semiconductor layers, wherein a projection of the hard mask layer on the substrate corresponds to the sacrificial region; The first semiconductor layer, the second semiconductor layer and the substrate are etched by using the hard mask layer to form the stacked structure, and grooves are formed in the substrate at both sides of the stacked structure.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: In the process of forming the grooves in the substrate at both sides of the stacked structure, at least a portion of the sidewalls of the sacrificial region are exposed.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: The forming of a stacked structure on the sacrificial area further comprises: forming a protective layer covering the stacked structure and the substrate; The protective layer and the substrate are anisotropically etched to retain the protective layer on the sidewall of the stacked structure as a sidewall protective layer, and to expose at least a portion of the sidewall of the sacrificial area.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The forming of a protective layer covering the stacked structure and the substrate comprises: The protective layer is formed by an ALD process; or The protective layer comprises a silicon nitride-based material; or The protection layer includes at least one of silicon nitride, SiON, SiOCN or SiCN.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: The anisotropic etching of the protective layer comprises: The anisotropic etching is performed by using a process gas with a high etching rate, high upper electrode radio frequency power and high lower electrode radio frequency power.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The process gas includes chlorine gas or fluorocarbon gas; or The radio frequency power of the upper electrode ranges from 100W to 3000W, and the radio frequency power of the lower electrode ranges from 50W to 1000W.

12. The method for manufacturing a semiconductor device according to claim 6, wherein: The hard mask layer includes at least one of an oxide insulating layer and a nitride insulating layer; or The hard mask layer includes a first hard mask layer and a second hard mask layer located above the first hard mask layer, the first hard mask layer includes silicon oxide, and the second hard mask layer includes silicon nitride.

13. The method for manufacturing a semiconductor device according to claim 1, wherein: The removing of the sacrificial area comprises: The sacrificial region is subjected to isotropic plasma etching.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The isotropic plasma etching of the sacrificial area comprises: The sacrificial area is etched in a low-pressure environment without loading the lower electrode radio frequency power.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The low pressure environment is 5 mTorr to 800 mTorr.

16. The method for manufacturing a semiconductor device according to claim 13, wherein: The etching gas used in the isotropic plasma etching is an etching gas that enables an etching selectivity ratio between the sacrificial region and the substrate to be greater than a predetermined value.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The substrate is silicon, the sacrificial region is n-type heavily doped silicon, and the etching gas used in the isotropic plasma etching is chlorine; An etching selectivity ratio between the sacrificial region and the substrate is greater than 200.

18. The method for manufacturing a semiconductor device according to claim 1, wherein: The first semiconductor layer and the second semiconductor layer are made of semiconductor materials having different lattice constants.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: The first semiconductor layer and the second semiconductor layer include at least one of Si, Ge, SiGe, GeSn, SiGeSn, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP.

20. The method for manufacturing a semiconductor device according to any one of claims 1 to 19, wherein: The step of filling the cavity with an insulating layer comprises: Depositing the insulating layer around the stacked structure and on the surface of the substrate until the insulating layer below the stacked structure at the cavity is attached to the insulating layer above the substrate at the cavity; The insulating layer outside the cavity is removed.

21. The method for manufacturing a semiconductor device according to claim 20, wherein: The step of depositing the insulating layer around the stacked structure and on the surface of the substrate comprises: The insulating layer is deposited using an atomic layer deposition process.

22. The method for manufacturing a semiconductor device according to claim 20, wherein: Also includes: The insulating layer is subjected to annealing treatment.

23. The method for manufacturing a semiconductor device according to claim 8, wherein: Also includes: removing the sidewall protection layer and the hard mask layer; The recess is filled to form a shallow trench isolation structure.

24. The method for manufacturing a semiconductor device according to claim 1, wherein: Before removing one of the first semiconductor layer and the second semiconductor layer, the method further includes: A source region and a drain region are respectively formed on both sides of the region of the stacked structure where the gate structure is to be formed.

25. The method for manufacturing a semiconductor device according to claim 1, wherein: The gate structure includes a gate dielectric layer disposed around the other of the first semiconductor layer and the second semiconductor layer and a gate electrode layer disposed around the gate dielectric layer; The other of the first semiconductor layer and the second semiconductor layer surrounded by the gate structure is formed as a channel region of the semiconductor device.

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