Arithmetic device, signal processing device, and signal processing circuit

Abstract

[Problem] To enable economizing on power and on surface area. [Solution] This arithmetic device comprises: a first capacitor connected between a first node and a reference voltage node; a plurality of second capacitors connected in series to a signal path between the first node and the second node; and a plurality of third capacitors which are respectively connected at one end to connection nodes of the first capacitor and the plurality of second capacitors. By means of a first digital signal, it is established whether to apply, to other ends of the plurality of third capacitors, a voltage corresponding to a second digital signal or a predetermined reference voltage. The second node outputs a voltage corresponding to a result of multiplying the first digital signal and the second digital signal.

Description

Arithmetic device, signal processing device, and signal processing circuit

[0001] The present disclosure relates to a computing device, a signal processing device, and a signal processing circuit.

[0002] Machine learning, such as deep learning, has been attracting attention. Machine learning requires repeated multiply-and-accumulate operations using neural networks, and efforts are underway to develop hardware that can perform such operations quickly, with a small footprint, and low power consumption. For example, a C-2C ladder structure has been proposed that can improve the energy efficiency of multi-bit multiply-and-accumulate operations and prevent area expansion even when the number of bits increases (see Non-Patent Document 1). Another technology has been proposed that generates input signals as digital pulse signals by charge distribution (see Non-Patent Document 2).

[0003] Hechen Wang et, al. “A 32.2 TOPS / W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference” VLSI 2022, C04-1Gicheol Shin et, al. “A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA / AD Conversions” ECCIRC 2021, Sungkyunkwan Univ.

[0004] However, in Non-Patent Document 1, a digital-to-analog converter (DAC) that converts a digital signal to an analog signal for performing a product-sum operation with a weighting coefficient set as a power of 2, and an analog-to-digital converter (ADC) that converts the multiplication result into a digital signal are required, which increases the circuit area and power consumption.

[0005] In Non-Patent Document 2, static random access memory (SRAM) cells are arranged in row and column directions, and multiple switches are provided between the SRAM columns in the column direction. These switches are then used to perform a multiply-and-accumulate operation using the SRAM cells. The need for multiple switches results in a complex configuration, and switch control is also cumbersome. Furthermore, Non-Patent Document 2 uses two multi-bit operation rows to perform a multiplication operation by allocating charge according to the input signal. Therefore, performing a multiplication-and-accumulation operation between two digital signals requires a number of multi-bit operation rows that is a multiple of two, resulting in poor area efficiency for the multiplication operation compared to performing a multiplication operation using a single multi-bit operation row.

[0006] Therefore, the present disclosure provides a calculation device, a signal processing device, and a signal processing circuit that are capable of saving power and space.

[0007] In order to solve the above problem, according to the present disclosure, there is provided an arithmetic device comprising: a first capacitor connected between a first node and a reference voltage node; a plurality of second capacitors connected in series to a signal path between the first node and a second node; and a plurality of third capacitors, each having one end connected to a connection node between the first capacitor and the plurality of second capacitors; wherein a first digital signal determines whether a voltage corresponding to a second digital signal or a predetermined reference voltage is applied to the other end of each of the plurality of third capacitors; and the second node outputs a voltage corresponding to a multiplication result of the first digital signal and the second digital signal.

[0008] One end of each of two or more third capacitors may be connected to each connection node on the signal path between the first node and the second capacitor adjacent to the first node, between two adjacent second capacitors, and between the second node and the second capacitor adjacent to the second node.

[0009] The second digital signal may have a plurality of bits, and each bit of the second digital signal may be used to set a voltage at the other end of each of the two or more third capacitors at a different one of the connection nodes.

[0010] A plurality of connection nodes may be provided on the signal path, and a voltage corresponding to the second digital signal or the predetermined reference voltage may be applied to the other end of each of the two or more third capacitors connected to each of the plurality of connection nodes, depending on the corresponding bit value of the same first digital signal.

[0011] The two or more third capacitors may have the same capacitance value, the sum of the capacitance values ​​of the two or more third capacitors may be equal to the capacitance value of the first capacitor, and the first digital signal may be a thermometer code.

[0012] The third capacitors may have capacitance values ​​that are different powers of two over the capacitance value of the first capacitor.

[0013] A voltage corresponding to the same bit value of the second digital signal may be applied to one end of each of the plurality of third capacitors, the other end of each of which is connected to the same connection node on the signal path, and voltages corresponding to different bit values ​​of the second digital signal may be applied to the other ends of the plurality of third capacitors, the other ends of which are connected to different connection nodes on the signal path.

[0014] The plurality of second capacitors may have the same capacitance value, and the capacitance value of the second capacitor may be twice the capacitance value of the first capacitor.

[0015] The digital signal processing device may include an array unit having a plurality of multipliers arranged in a first direction and a second direction that intersect with each other, and each of the plurality of multipliers may have the first capacitor, the plurality of second capacitors, and the plurality of third capacitors.

[0016] The present disclosure also provides a signal processing device comprising: a first capacitor connected between a first node and a reference voltage node; a plurality of second capacitors connected in series to a signal path between the first node and a second node; and a plurality of third capacitors, each having one end connected to a connection node between the first capacitor and the plurality of second capacitors, wherein a first digital signal is used to set whether a voltage corresponding to a second digital signal or a predetermined reference voltage is applied to the other end of each of the plurality of third capacitors, and the second node outputs a voltage corresponding to a multiplication result of the first digital signal and the second digital signal; and an imaging unit that outputs captured image data, wherein at least one of the first digital signal and the second digital signal is a signal based on the image data.

[0017] The present disclosure also provides a signal processing circuit including an analog arithmetic circuit that performs a first process of converting a first digital signal into a first analog signal, and that performs a second process of changing a second analog signal corresponding to a multiplication value of the converted first analog signal and a second digital signal based on a third digital signal for gain setting, thereby generating a third analog signal.

[0018] The digital signal processing device may include a plurality of the analog arithmetic circuits that perform the first processing and the second processing separately, a signal line that transmits a fourth analog signal having a signal level obtained by adding together the plurality of second analog signals or the plurality of third analog signals output from each of the plurality of analog arithmetic circuits, and an analog-to-digital conversion circuit that converts the fourth analog signal after the second processing into a fourth digital signal.

[0019] The second process may include a third process of simultaneously lowering the voltage level on the signal line based on a plurality of the first analog signals, and a fourth process of, after the third process, gradually raising the voltage on the signal line based on each of the plurality of third digital signals to generate the fourth analog signal.

[0020] The digital signal processing device may further include a control circuit that controls the plurality of analog arithmetic circuits, and the control circuit may cause the plurality of analog arithmetic circuits to perform the first process and the third process in parallel, and may cause the plurality of analog arithmetic circuits to perform the fourth process sequentially.

[0021] Each of the plurality of analog arithmetic circuits may include two or more first capacitors that accumulate electric charge according to the first digital signal, and a switch that switches between connecting the two or more first capacitors in parallel, or charging or discharging one or more of the two or more first capacitors according to the first digital signal, and leaving the remaining first capacitors in a floating state.

[0022] Each of the plurality of analog arithmetic circuits may have a plurality of second capacitors connected in series, each outputting a voltage that is one divided by a power of two, and may also have a ladder multiplication circuit having one end connected to the signal line.

[0023] The two or more first capacitors may be connected between two adjacent second capacitors among the plurality of second capacitors, the two or more first capacitors may have the same capacitance, and each of the plurality of second capacitors may have a capacitance that is at least twice that of the first capacitor.

[0024] The circuit may include a plurality of capacitor groups each having the two or more first capacitors, wherein one end of each of the two or more first capacitors in each of the plurality of capacitor groups is connected to the signal line, the two or more first capacitors in each of the plurality of capacitor groups have the same capacitance, and the capacitances of the two or more first capacitors in each of the plurality of capacitor groups may differ by a power of two.

[0025] The analog-to-digital conversion circuit may have a comparison circuit that determines whether the fourth analog signal on the signal line exceeds a predetermined threshold value, and a counter that performs a counting operation from when the analog-to-digital conversion operation starts until the comparison circuit determines that the predetermined threshold value has been exceeded, and output the fourth digital signal according to the count value of the counter.

[0026] The voltage level of the signal line that each of the analog arithmetic circuits changes through the second processing may be determined by the third digital signal.

[0027] 1 is a block diagram showing a first example of a arithmetic device according to a first embodiment of the present disclosure. FIG. 2 is a block diagram showing a first configuration example of a capacitance selection unit according to the first embodiment of the present disclosure. FIG. 3 is a circuit diagram showing a configuration of an inverter according to the first embodiment of the present disclosure. FIG. 4 is a block diagram showing a second configuration example of a capacitance selection unit according to the first embodiment of the present disclosure. FIG. 5 is a block diagram showing a second configuration example of a arithmetic device according to the first embodiment of the present disclosure. FIG. 6 is a block diagram showing a first configuration example of the arithmetic device of FIG. 3. FIG. 7 is a block diagram showing a second configuration example of the arithmetic device of FIG. 3. FIG. 8 is a block diagram showing a configuration of a signal processing device according to the first embodiment of the present disclosure. FIG. 9 is a schematic diagram showing a first modified example of a logic board. FIG. 10 is a schematic diagram showing a second modified example of a logic board. FIG. 11 is a block diagram showing a configuration of a arithmetic device according to a comparative example. FIG. 12 is a block diagram showing a configuration of a multiplier according to a comparative example. FIG. 13 is a block diagram showing a configuration of a capacitance selection unit according to a second embodiment of the present disclosure. FIG. 14 is a block diagram of a signal processing circuit according to a third embodiment of the present disclosure. FIG. 15 is a diagram showing a more detailed configuration of the signal processing circuit. FIG. 16 is a circuit diagram showing a specific configuration of a DAC according to a third embodiment of the present disclosure. FIG. 17 is a diagram explaining first processing according to a third embodiment of the present disclosure. FIG. 18 is a timing chart showing operation in the first processing of the DAC. FIG. 19 is a diagram showing a modified example of a first capacitor according to a third embodiment of the present disclosure. FIG. 19 is a circuit diagram showing an internal configuration of a ladder multiplier according to a third embodiment of the present disclosure. 10 is a circuit diagram of a multiplier having a basic structure. FIG. 11 is a circuit diagram showing the configuration of a multiplexer according to a third embodiment of the present disclosure. FIG. 12 is a timing chart showing the operation of a second process of a DAC. FIG. 13 is a diagram showing the output of a product-sum operation result of an analog arithmetic circuit. FIG. 14 is a waveform diagram showing the degree of voltage drop of a signal line according to a product-sum operation value. FIG. 15 is a diagram showing a third analog signal output operation of one analog arithmetic circuit. FIG. 16 is a diagram showing a third analog signal output operation of a plurality of analog arithmetic circuits. FIG. 17 is a waveform diagram showing a state in which the voltage of a signal line increases stepwise. FIG. 18 is a waveform diagram showing a voltage increase of a signal line during gain adjustment. FIG. 19 is a diagram showing a first example of a counter synchronization technique. FIG. 20 is a diagram showing a second example of a counter synchronization technique. FIG. 21 is a diagram showing a third example of a counter synchronization technique. FIG. 22 is a diagram showing a fourth example of a counter synchronization technique. FIG. 23 is a diagram showing a fifth example of a counter synchronization technique. FIG. 24 is a diagram showing a sixth example of a counter synchronization technique. FIG. 25 is a diagram showing a seventh example of a counter synchronization technique.1 is a block diagram showing the configuration of a memory circuit according to a third embodiment of the present disclosure. FIG. 2 is a flowchart showing the overall operation of a signal processing circuit according to the third embodiment of the present disclosure. FIG. 3 is a timing chart showing the overall operation of a signal processing circuit according to the third embodiment of the present disclosure. FIG. 4 is a circuit diagram showing the configuration of a memory element. FIG. 5 is a circuit diagram showing the configuration of a comparison circuit. FIG. 6 is a circuit diagram showing the configuration of a comparison bias circuit. FIG. 7 is a circuit diagram showing the configuration of a test circuit. FIG. 8 is a diagram showing a first example of a substrate structure of a signal processing circuit according to the third embodiment of the present disclosure. FIG. 9 is a diagram showing a second example of a substrate structure of a signal processing circuit according to the third embodiment of the present disclosure. FIG. 10 is a plan view of the first example of a signal processing circuit according to the third embodiment of the present disclosure. FIG. 11 is a plan perspective view showing a first example of a wiring structure of a ladder multiplier according to the third embodiment of the present disclosure. FIG. 12 is a plan view of a second example of a signal processing circuit according to the third embodiment of the present disclosure. FIG. 13 is a diagram showing a second example of a circuit structure of a ladder multiplier according to the third embodiment of the present disclosure. FIG. 14 is a plan perspective view showing a second example of a wiring structure of a ladder multiplier according to the third embodiment of the present disclosure. FIG. 15 is a diagram showing a configuration in which a plurality of array units of the same size are arranged. FIG. 16 is a diagram showing a configuration in which a plurality of array units of different sizes are arranged. FIG. 10 is a diagram showing the difference between a signal processing circuit according to a third embodiment of the present disclosure and a signal processing circuit according to a comparative example. FIG. 11 is a circuit diagram showing a ladder multiplier according to a fourth embodiment of the present disclosure. FIG. 12 is a planar perspective view showing a first example of a wiring structure of a ladder multiplier according to the fourth embodiment of the present disclosure. FIG. 13 is a planar perspective view showing a second example of a wiring structure of a ladder multiplier according to the fourth embodiment of the present disclosure. FIG. 14 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 15 is an explanatory diagram showing an example of the installation positions of an outside vehicle information detection unit and an imaging unit.

[0028] Hereinafter, embodiments of a calculation device, a signal processing device, and a signal processing circuit will be described with reference to the drawings. The following description will focus on the main components of the calculation device, the signal processing device, and the signal processing circuit, but the calculation device, the signal processing device, and the signal processing circuit may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0029] First Embodiment FIG. 1 is a block diagram showing a first example of a calculation device according to a first embodiment of the present disclosure. The calculation device in FIG. 1 is a multiplier. For this reason, hereinafter, it will be referred to as multiplier 1. A first digital signal A consisting of a plurality of bits and a second digital signal B consisting of a plurality of bits are input to multiplier 1. Multiplier 1 multiplies the first digital signal A and the second digital signal B and outputs the result as a voltage Vout. More precisely, this voltage is output as a charge resulting from the multiplication, and is output as voltage Vout due to parasitic capacitance of wiring, etc. FIG. 1 shows an example in which first digital signal A consists of i bits (A[0] to A[i-1]) and second digital signal B consists of j bits (B[0] to B[j-1]).

[0030] The multiplier 1 includes a first capacitor 11 , a plurality of second capacitors 12 , and a plurality of capacitance selection units 13 .

[0031] The first capacitor 11 is connected between a first node n1 of a signal path L and a reference voltage (e.g., ground voltage) node. The signal path L extends from the first node n1 to a second node n2, which is the output node of the multiplier 1. The first capacitor 11 has a predetermined unit capacitance (e.g., C).

[0032] The multiple second capacitors 12 are connected in series to the signal path L between the first node n1 and the second node n2. All of the multiple second capacitors 12 have the same capacitance value. More specifically, each of the multiple second capacitors 12 has a capacitance value (e.g., 2C) that is twice that of the first capacitor 11. In this specification, of the multiple second capacitors 12, the second capacitor 12 adjacent to the first capacitor 11 (and the first node n1) is referred to as the first-stage second capacitor 12, and the second capacitor 12 adjacent to the second node n2 is referred to as the final-stage second capacitor 12. A voltage Vout, which is the multiplication result of the first digital signal A and the second digital signal B, is output to the signal wiring 21 from the second node n2, which is one end of the final-stage second capacitor 12.

[0033] The plurality of capacitance selection sections 13 have one end connected to each connection node n3 of the first capacitor 11 and the plurality of second capacitors 12. More specifically, the connection node n3 is arranged between the first node n1 and the first-stage second capacitor 12, between two adjacent second capacitors 12, and between the second node n2 and the last-stage second capacitor 12, respectively.

[0034] A voltage corresponding to a corresponding bit value of the second digital signal B is input to the other end of each of the plurality of capacitance selection units 13. For example, a voltage corresponding to a least significant bit (LSB) B[0] of the second digital signal B is input to the other end of the capacitance selection unit 13 having one end connected to the connection node n3 between the first capacitor 11 and the second capacitor 12 of the first stage. Also, a voltage corresponding to a most significant bit (MSB) B[j-1] of the second digital signal B is input to the other end of the capacitance selection unit 13 having one end connected to the connection node n3 between the second capacitor 12 of the last stage and the second node n2.

[0035] Each capacitance selection unit 13 has two or more capacitors (third capacitors). The capacitance selection units 13 select whether or not to connect one end of each of the two or more third capacitors to each connection node n3 of the signal path L, based on the first digital signal A. More specifically, the capacitance selection units 13 have the same number of third capacitors as the number of bits of the first digital signal A.

[0036] The plurality of capacitance selection units 13 receive the same first digital signal A. That is, the two or more third capacitors included in each of the plurality of capacitance selection units 13 are switched, depending on the bit value of the same first digital signal A, as to whether or not to apply a voltage according to the corresponding bit value of the second digital signal B to the other end of the two or more third capacitors.

[0037] A voltage corresponding to the multiplication result of the first digital signal A and the second digital signal B is output to the second node n2 of the signal path L. The second node n2 of the signal path L is connected to the signal wiring 21, and the voltage signal corresponding to the multiplication result of the first digital signal A and the second digital signal B is transmitted from the second node n2 to the signal wiring 21.

[0038] 1, the capacitance values ​​of the plurality of capacitors provided in the capacitance selection unit 13 are the same, but a modified example in which the capacitance values ​​of the plurality of capacitors are different from one another is also possible. Below, a first example and a second example of the specific internal configuration of the capacitance selection unit 13 will be described in order.

[0039] 2A is a circuit diagram showing a first example of the internal configuration of the capacitance selection unit 13. Fig. 2A illustrates the internal configuration of the capacitance selection unit 13a of the (k+1)th connection node n3 from the left among the multiple connection nodes n3 of the signal path L.

[0040] As shown in Figure 2A, the capacitance selection unit 13a of the first example has a plurality of third capacitors 14, one end of which is connected to each connection node n3 of the signal path L, and a plurality of inverters 15, one end of which is connected to the other end of the plurality of third capacitors 14.

[0041] 2A shows an example in which each capacitance selection unit 13a has i (i is an integer equal to or greater than 2) third capacitors 14 and i inverters 15. In this case, the first digital signal A is an i-bit digital signal, and each bit of the first digital signal A corresponds to one of the inverters 15. More specifically, a voltage corresponding to each bit value of the first digital signal A is input to the power supply terminal of the corresponding inverter 15. In FIG. 2A , a voltage corresponding to the k+1-th bit value B[k] of the second digital signal B is input to each input terminal of the multiple inverters 15. The output terminal of the inverter 15 is connected to the third capacitor 14.

[0042] 2B is a circuit diagram showing a configuration of the inverter 15 according to the first embodiment of the present disclosure. The inverter 15 includes transistors 16 and 17. The transistor 16 is, for example, a PMOS (P-channel Metal-Oxide-Semiconductor) transistor. The transistor 17 is, for example, an NMOS (N-channel Metal-Oxide-Semiconductor) transistor.

[0043] The gates of the transistors 16 and 17 are connected to the input terminal p1 of the inverter 15. A voltage corresponding to the bit value B[k] of the second digital signal B is input to the gates of the transistors 16 and 17 via the input terminal p1. The source of the transistor 16 is connected to the power supply terminal p2 of the inverter 15, and a voltage corresponding to one of the bit values ​​of the first digital signal A is input from the power supply terminal p2. In the example of FIG. 2B , a voltage corresponding to the (h+1)th bit value A[h] of the first digital signal A is input to the source of the transistor 16. A GND (e.g., 0 V) ​​voltage is input to the source of the transistor 16 from the terminal p3. The drains of the transistors 16 and 17 are connected to the output terminal p4. The output terminal p4 outputs a voltage Vc to the third capacitor 14.

[0044] For example, when the bit value A[h] is 1, a high voltage is input to the power supply terminal of the inverter 15, and the voltage Vc becomes a voltage corresponding to the bit value B[k]. Conversely, when the bit value A[h] is 0, a low voltage is input to the power supply terminal of the corresponding inverter 15, and the voltage Vc becomes a predetermined reference voltage. In this specification, the state in which the inverter 15 outputs the voltage Vc corresponding to the bit value B[k] is called an enabled state, and the state in which the inverter 15 outputs the voltage Vc of the predetermined reference voltage is called a disabled state.

[0045] In this way, depending on the bit value of the first digital signal A, it is possible to set whether to apply a voltage corresponding to the bit value B[k] or a predetermined reference voltage to the third capacitor 14 used by the multiplier 1.

[0046] In this embodiment, the first digital signal A is a thermometer code. A thermometer code is a code in which the number of bits whose bit value is 1 increases (or decreases) by one. By using the first digital signal A as a thermometer code, it is possible to arbitrarily adjust the number of third capacitors 14, of which the voltage corresponding to the bit value of the second digital signal B is applied to the other end.

[0047] For example, if the number of bits of the first digital signal A is four, four third capacitors 14 are provided. Voltages corresponding to the bit values ​​of different bits of the first digital signal A are input to the power supply terminals of the four inverters 15 connected to these four third capacitors 14. Furthermore, a voltage corresponding to the value of the (k+1)th bit of the second digital signal B is input to all of the input terminals of these four inverters 15.

[0048] The capacitance of the four third capacitors 14 is ¼ times the capacitance value C of the first capacitor 11. Therefore, the combined capacitance of these four third capacitors 14 is C. As in this example, two or more third capacitors 14 have the same capacitance value. Furthermore, the sum of the capacitance values ​​of the two or more third capacitors 14 is equal to the capacitance value of the first capacitor 11.

[0049] When the inverter 15 is enabled, the other end of the third capacitor 14 is at a low voltage (ground voltage) or a high voltage (power supply voltage) depending on the value B[k] of the (k+1)th bit of the second digital signal B. The voltage level of the connection node n3 on one end side of the third capacitor 14 changes depending on whether the other end of the third capacitor 14 is at a low voltage or a high voltage. In the capacitance selection unit 13 to which the least significant bit of the second digital signal B is input, this voltage level is a value reflecting the multiplication result of the first digital signal A and the bit value B[0]. In the capacitance selection unit 13 to which bits other than the least significant bit are input, the multiplication result of the first digital signal A and the bit value B[k] is added to the multiplication result of the lower-order bits of the first digital signal A and the second digital signal B.

[0050] Alternatively, the second digital signal B may be input to the power supply terminal p2 of the inverter 15, and the first digital signal A may be input to the input terminal p1 of the inverter 15. In this case, the voltage corresponding to the bit value B[k] switches whether all of the inverters 15 in the capacitance selection unit 13a are enabled or not. The number of third capacitors 14 to which a high voltage is input switches according to each bit of the first digital signal A. Even in this case, the first digital signal A can adjust the number of third capacitors 14 to which the voltage of the bit value B[k] is reflected.

[0051] Fig. 2C is a circuit diagram showing a second example of the internal configuration of the capacitance selection unit 13. As shown in Fig. 2C, a capacitance selection unit 13b according to the second example has a configuration in which a capacitance initialization circuit 18 is further added to the capacitance selection unit 13a of Fig. 2A.

[0052] The capacitance initialization circuit 18 initializes the storage capacitances of the plurality of third capacitors 14 before the start of a new multiplication in the multiplier 1. The capacitance initialization circuit 18 has a transistor 19 connected between a reference voltage Vref node and a signal path L. The transistor 19 is, for example, an NMOS transistor. An INI signal is input to the gate of the transistor 19. When the INI signal becomes high level, the transistor 19 turns on, and charges corresponding to the reference voltage Vref are stored in the plurality of third capacitors 14.

[0053] A capacitance initialization circuit 18 may be provided for each connection node n3 of the signal path L, or one capacitance initialization circuit 18 may be provided for all connection nodes n3. The circuit configuration of the capacitance initialization circuit 18 shown in Fig. 2C is merely an example, and the accumulated capacitances of the plurality of third capacitors 14 may be initialized using a circuit configuration different from that shown in Fig. 2C.

[0054] 1, 2A, and 2C, the plurality of third capacitors 14 connected to each connection node n3 in FIG. 1 all have a combined capacitance value of C. As a result, the multiplier 1 in FIG. 1 has a C-2C ladder structure in which C (third capacitor 14) is connected between stages of a plurality of 2C (second capacitors 12) connected in series to the signal path L.

[0055] 1 , when any bit of the first digital signal A input to the multiplier 1 is 1, the inverter 15 corresponding to that bit is enabled, and a voltage is applied to the corresponding third capacitor 14. In this way, the first digital signal A is used to determine which of the multiple third capacitors 14 connected to each connection node n3 of the signal path L has a voltage corresponding to the corresponding bit value of the second digital signal B applied to its other end. Furthermore, each bit of the second digital signal B is used to set the voltage at the other end of each of the multiple third capacitors 14 connected to the corresponding connection node n3 of the signal path L.

[0056] In this way, the multiplier 1 shown in FIGS. 1, 2A, and 2C multiplies the first digital signal A by the second digital signal B for each bit, and outputs the multiplication results to the corresponding connection nodes n3 on the signal path L, from the least significant bit to the most significant bit.

[0057] The arithmetic device according to the first embodiment may be configured with a single multiplier 1 shown in FIG. 1 , or may have a function of performing a product-sum operation using a plurality of multipliers 1 shown in FIG. 1 . FIG. 3 is a block diagram showing a second example of the arithmetic device according to the first embodiment of the present disclosure. The arithmetic device 10 in FIG. 3 has a plurality of multipliers 1 having the same configuration as in FIG. 1 , and is characterized by performing a product-sum operation in which the multiplication results of the plurality of multipliers 1 are added together. More specifically, the arithmetic device 10 includes a product-sum array unit (array unit) 2, an analog-to-digital converter (ADC) 3, and a signal processing unit 4.

[0058] The product-sum array unit 2 has a plurality of multipliers 1 arranged in an array. Each multiplier 1 has the same configuration as in FIG. 1. The product-sum array unit 2 performs a product-sum operation, adding together the multiplication results of the plurality of multipliers 1. The result of the product-sum operation is sent to the analog-to-digital converter 3. The multiplication results of the plurality of multipliers 1 are transmitted over a common output wiring (specifically, signal wiring 21). Because the output nodes of the plurality of multipliers 1 (specifically, second node n2) are connected to this output wiring, the plurality of multiplication results are added on the output wiring by wired addition.

[0059] In this way, the product-sum array unit 2 can perform summation on the output wiring by connecting the output nodes of a plurality of multipliers 1 to a common output wiring, without providing a separate adder.

[0060] The product-sum array unit 2 performs multiple multiplications in parallel or sequentially using multiple multipliers 1. As the number of multipliers 1 provided in the product-sum array unit 2 increases, the number of multiplications that can be performed in parallel or sequentially can be increased, and the speed of product-sum calculations can be increased, but the circuit scale increases.

[0061] The arithmetic device 10 may include a storage unit 5. The storage unit 5 stores one of the first digital signal A or the second digital signal B (e.g., the first digital signal A). The multiple multipliers 1 in the product-sum array unit 2 read the first digital signal A from the storage unit 5 and also read the second digital signal B from an external device (e.g., a sensor). The multiple multipliers 1 may read both the first digital signal A and the second digital signal B from the storage unit 5. Alternatively, the multiple multipliers 1 may read both the first digital signal A and the second digital signal B from an external device.

[0062] The arithmetic unit 10 may include an integrator 6. The integrator 6 is connected to a plurality of multipliers 1, and adds or averages the multiplication results of the plurality of multipliers 1, and outputs the result to the analog-to-digital converter 3 as a product-sum operation value.

[0063] The arithmetic device 10 may include a gain calculator 7. The gain calculator 7 applies a gain to the multiplication result output from the product-sum array unit 2 or the product-sum calculation value output from the integrator 6, and outputs the full-scale adjusted value to the analog-to-digital converter 3.

[0064] The analog-to-digital converter 3 converts the signal input from the integrator 6 etc. into a digital signal and outputs it to the signal processing unit 4 .

[0065] The signal processing unit 4 performs predetermined signal processing based on the digital signal input from the analog-digital converter 3. The predetermined signal processing includes, for example, processing such as outputting digital values ​​less than or equal to 0 as 0 by ReLU (Rectified Linear Unit) calculation. Note that the specific signal processing performed by the signal processing unit 4 is arbitrary, and the signal processing unit 4 may be provided separately from the arithmetic device 10. In this case, the internal configuration of the arithmetic device 10 can be simplified.

[0066] Fig. 4A is a diagram showing a first configuration example of the arithmetic device 10. The arithmetic device 10a in Fig. 4A has a product-sum array unit 2 and a plurality of analog-to-digital converters 3. Fig. 4A does not show the signal processing unit 4. The product-sum array unit 2 has a plurality of multipliers 1 arranged in a first direction X and a second direction Y that intersect with each other.

[0067] An analog-to-digital converter 3 is arranged for each group of multipliers 1 arranged in the second direction Y. A signal wiring 21 is also arranged for each analog-to-digital converter 3. The signal wiring 21 is connected to the output nodes (second nodes n2) of the multiple multipliers 1 arranged in the second direction Y. As a result, the multiplication results of the multiple multipliers 1 are added on the signal wiring 21 to obtain a product-sum operation result. The signal wiring 21 is connected to the input node of the analog-to-digital converter 3. The analog-to-digital converter 3 converts the voltage on the signal wiring 21 (specifically, the voltage Vout generated by adding up the charges output by the multiple multipliers 1) into a digital signal.

[0068] The same first digital signal A may be input to a group of multipliers 1 arranged in the second direction Y from a storage unit 5 not shown in FIG. 4A.

[0069] 4B is a diagram showing a second configuration example of the arithmetic device 10. The arithmetic device 10b in FIG. 4B differs from the arithmetic device 10a in that it has a plurality of integrators 6.

[0070] 4A shows an example in which the multiplication results of a plurality of multipliers 1 are added together on the signal wiring 21 of the product-sum array unit 2, but in FIG. 4B , the multiplication results of a plurality of multipliers 1 are added together in an integrator 6, not on the signal wiring 21. One integrator 6 is provided for each signal wiring 21. The integrator 6 also adds the voltages on the signal wiring 21 according to the charge. More specifically, the integrator 6 receives the multiplication results from the multipliers 1 in the product-sum array unit 2 and outputs the integration result to the analog-to-digital converter 3. The integrator 6 has a capacitor 22, a switch 23, and an amplifier 24 connected in parallel between the product-sum array unit 2 and the analog-to-digital converter 3.

[0071] The output voltage of the integrator 6 is determined by the capacitance of the capacitor 22 and the sum of the charges output from the multiplier. The switch 23 is used to initialize the capacitor 22 by discharging the accumulated charge. When a new multiplication result is input via the signal line 21 with the switch 23 turned off, a voltage corresponding to the result of adding this to the result of the immediately preceding product-sum operation is output. The integrator 6 may also perform averaging of the multiplication results.

[0072] The analog-to-digital converter 3 in FIG. 4B converts the voltage that has been added or averaged by the integrator 6 into a digital signal, and outputs it to the signal processing unit 4 or the like at the subsequent stage.

[0073] The arithmetic device 10 in Fig. 3 can be applied to various applications such as image, character, and voice recognition, classification, and generation, but as an example, an example in which the arithmetic device 10 in Fig. 3 is applied to an image sensor will be described below. Fig. 5A is a block diagram showing the configuration of a signal processing device 30 according to the first embodiment of the present disclosure. The signal processing device 30 is, for example, an image sensor, and is used to output image data according to the luminance of incident light.

[0074] The signal processing device 30 has a laminated semiconductor structure in which a substrate 31 and a substrate 32 are stacked. The substrates 31 and 32 are semiconductor substrates each having a semiconductor layer. The substrate 31 has a light receiving unit 33. The light receiving unit 33 receives incident light and outputs a pixel signal according to the luminance of the incident light. A portion of the light receiving unit 33 may be disposed on the substrate 32. The substrate 31 is also called a light receiving substrate.

[0075] The substrate 32 has an arithmetic unit 10 and an image processing unit 34. The light receiving unit 33 and the image processing unit 34 are collectively referred to as an imaging unit. The image processing unit 34 performs predetermined signal processing on pixel signals output from the light receiving unit 33. The predetermined signal processing includes analog-to-digital conversion, which converts pixel signals into digital signals. The digital signals output by the image processing unit 34 are also referred to as image data. The arithmetic unit 10 performs a product-sum operation using the digital signals output from the image processing unit 34. At least one of the first digital signal A and the second digital signal B (for example, the second digital signal B) input to the product-sum array unit 2 in the arithmetic unit 10 is a digital signal output from the image processing unit 34. The substrate 32 is also referred to as a logic substrate.

[0076] 5A has a two-layer stacked semiconductor structure made up of substrates 31 and 32, but the configuration of the signal processing device 30 is not limited to this. For example, the light receiving unit 33 may be arranged separately on multiple substrates. Furthermore, at least one of the image processing unit 34 and the arithmetic unit 10 may be arranged separately on separate substrates, or the product-sum array unit 2, analog-to-digital converter 3, and signal processing unit 4 of the arithmetic unit 10 may be arranged separately on separate substrates. In other words, the signal processing device 30 may have a structure in which three or more substrates are stacked.

[0077] Furthermore, the substrate 32 may have a plurality of arithmetic units 10. Fig. 5B is a schematic diagram showing a first modified example of the substrate 32. The substrate 32a in Fig. 5B can perform two or more different arithmetic processes in parallel using a plurality of arithmetic units 10. For example, the plurality of arithmetic units 10 may each perform different multiply-accumulate operations in parallel, sequentially, or selectively.

[0078] The plurality of arithmetic units 10 may include arithmetic units 10 having different operation sizes. Fig. 5C is a schematic diagram showing a second modification of the board 32. The board 32b in Fig. 5C can use a plurality of arithmetic units 10 depending on the size of the data to be operated on.

[0079] 6 is a block diagram showing the configuration of a calculation device 80 according to a comparative example. The calculation device 80 differs from the calculation device 10 shown in FIG. 3 in that it includes a digital-to-analog converter (DAC) 81. The digital-to-analog converter 81 supplies a voltage Vf obtained by digital-to-analog converting the first digital signal A to a plurality of multipliers 1 in the product-sum array unit 2.

[0080] 7 is a block diagram showing the configuration of a multiplier 90 according to a comparative example. Instead of the first digital signal A, the multiplier 90 receives the voltage Vf from the digital-to-analog converter 81 as described above.

[0081] In the multiplier 1 of Fig. 1, one end of each of the plurality of third capacitors 14 is connected to each connection node n3 of the signal path L, but in the multiplier 90 of Fig. 7, one end of a single third capacitor 14 is connected to each connection node n3 of the signal path L. The capacitance of the third capacitor 14 is the same as the capacitance (e.g., C) of the first capacitor 11. Therefore, the multiplier 90 of Fig. 7 has a C-2C ladder structure similar to the multiplier 1 of Fig. 1.

[0082] An inverter 92 is provided for each capacitor 91. The inverter 92 has a structure similar to that of the inverter 15 in FIG. 2B. Bits B[0] to B[j-1] are input to the input terminals of the multiple inverters 92. Therefore, the input terminal of each inverter 92 becomes a low voltage (e.g., ground voltage) or a high voltage (e.g., DAC output voltage Vf), and each inverter 92 inverts and outputs the voltage at the input terminal. Therefore, the other ends of the multiple capacitors 91 are supplied with the DAC output voltage Vf or the low voltage.

[0083] 7 multiplies a first digital signal A by a second digital signal B, and outputs the multiplication result from a second node n2 to a signal wiring 21, similar to the multiplier 1 of FIG.

[0084] In the arithmetic device 80 according to the comparative example, a first digital signal A is converted into an analog voltage signal by a digital-to-analog converter 81, and the analog signal is input to the power supply terminals of a plurality of inverters 92. For this reason, the digital-to-analog converter 81 is essential in the arithmetic device 80 according to the comparative example. Since the area of ​​the digital-to-analog converter 81 increases as the number of bits of the first digital signal A increases, the multiplier 90 according to the comparative example has a larger circuit area and consumes more power than the multiplier 1 in FIG. 1 .

[0085] In contrast, the multiplier 1 according to the first embodiment of the present disclosure can directly input the first digital signal A to the power supply terminals of the plurality of inverters 15 without converting it into an analog voltage signal. Therefore, the arithmetic device 10 according to the first embodiment of the present disclosure does not require the digital-to-analog converter 81, and can reduce the area and power consumption compared to the arithmetic device 80 according to the comparative example.

[0086] As described above, the multiplier 1 according to the first embodiment of the present disclosure has a first capacitor 11 connected between a first node of a signal path L and a reference voltage (for example, a ground node), a plurality of second capacitors 12 connected in series between the first node n1 and a second node n2, one end of each of a plurality of third capacitors 14 connected to each connection node n3 of the signal path L, and a first digital signal A that switches between applying a voltage corresponding to a second digital signal B or a predetermined reference voltage to each of the other ends of the plurality of third capacitors 14, and a second digital signal B that is input to the other ends of the plurality of third capacitors 14. Therefore, a voltage corresponding to the multiplication result of the first digital signal A and the second digital signal B can be output from the second node n2. This eliminates the need to provide a digital-to-analog conversion circuit that converts the first digital signal A into an analog signal, thereby enabling the multiplier 1 to have reduced area and power consumption.

[0087] Second Embodiment The internal configuration of the capacitance selection section 13 shown in FIG. 1 is not necessarily limited to the circuit configuration shown in FIG. 2A or 2C, and various modifications are possible.

[0088] FIG. 8 is a circuit diagram showing the internal configuration of a capacitance selection unit 13c of the arithmetic device according to the second embodiment.

[0089] 2A, the capacitance selection unit 13c in Fig. 8 includes a plurality of third capacitors 14a, one end of which is connected to each connection node n3 of the signal path L, and a plurality of inverters 15, which are connected to the other ends of the plurality of third capacitors 14a. The difference between the capacitance selection unit 13c in Fig. 8 and the capacitance selection unit 13c in Fig. 2A is that the plurality of third capacitors 14a in Fig. 8 have capacitance values ​​that are each a different power of 2 divided by the capacitance value C of the first capacitor 11.

[0090] The capacitance selection unit 13c in Fig. 8 can switch the voltage level of the voltage Vf more finely than the capacitance selection unit 13a in Fig. 2A. Specifically, when the number of bits of the first digital signal A is i, the capacitance selection unit 13a in Fig. 2A can output the voltage Vf at i different voltage levels. On the other hand, the capacitance selection unit 13c in Fig. 8 can output the voltage Vf at 2 to the power of i different voltage levels.

[0091] In the first embodiment, it was necessary to convert the first digital signal A into a thermometer code, but in the second embodiment, it is not necessary to convert the first digital signal A into a thermometer code, and any bit string signal can be used as the first digital signal A. This eliminates restrictions on the first digital signal A. Therefore, in the second embodiment, the voltage level of the voltage Vf can be switched more finely, and the computing capacity of the computing device can be improved.

[0092] Third Embodiment In a third embodiment of the present disclosure, a signal processing circuit that has a configuration different from the arithmetic device 10 in FIG. 3 and that is capable of multi-bit product-sum calculations with reduced area and low power consumption will be described.

[0093] Fig. 9 is a block diagram of a signal processing circuit (signal processing device) 101 according to a third embodiment of the present disclosure. Fig. 10 is a diagram showing a more detailed configuration of the signal processing circuit 101. The signal processing circuit 101 in Fig. 9 performs analog product-sum operations and is used in neural networks, etc. The signal processing circuit 101 includes an array section 110 having a plurality of analog arithmetic circuits 102, a control circuit 103, a memory circuit 104, and a plurality of analog-to-digital converters (hereinafter, ADCs) 111.

[0094] Each of the multiple analog arithmetic circuits 102 extends in a first direction X of the array section 110. The multiple analog arithmetic circuits 102 are arranged in a second direction Y that intersects the first direction X. Each of the multiple analog arithmetic circuits 102 performs analog arithmetic processing to multiply a first digital signal by a second digital signal. More specifically, each of the multiple analog arithmetic circuits 102 performs a first processing to convert the first digital signal into a first analog signal, and a second processing to change the second analog signal, which corresponds to the multiplied value of the converted first analog signal and the second digital signal, based on a third digital signal for gain setting, to generate a third analog signal. Each analog arithmetic circuit 102 has a digital-to-analog converter (hereinafter, referred to as a DAC) 107 for performing the first processing, and a ladder multiplier 108 for performing the second processing.

[0095] As will be described later, the DAC 107 performs DA (Digital to Analog) conversion by utilizing some of the capacitors included in the ladder multiplier 108. The ladder multiplier 108 is also utilized for processing by the ADC 111. In this way, by utilizing the ladder multiplier 108 for various purposes, the circuit size can be reduced.

[0096] The ladder multiplier 108 included in each of the multiple analog arithmetic circuits 102 has a ladder structure in which multiple capacitors are connected in series and parallel. In this embodiment, the ladder structure is configured using multiple capacitors with two types of capacitance, 0.5C and 2C, so the analog arithmetic circuit 102 (and ladder multiplier 108) is expressed as 0.5C×2−2C. The detailed configuration of the analog arithmetic circuit 102 will be described later.

[0097] In this specification, the plurality of analog arithmetic circuits 102 arranged in the first direction X are referred to as arithmetic circuit rows, and the plurality of analog arithmetic circuits 102 arranged in the second direction Y are referred to as arithmetic circuit columns. That is, in the array section 110, a plurality of arithmetic circuit rows each extending in the first direction X are arranged in the second direction Y. Also, in the array section 110, a plurality of arithmetic circuit columns each extending in the second direction Y are arranged in the first direction X. A second analog signal indicating the multiplication result output from the plurality of analog arithmetic circuits 102 constituting the arithmetic circuit column is transmitted through a corresponding signal line VSL. The arithmetic circuit rows and arithmetic circuit columns in the array section 110 can be referred to as a first arithmetic circuit group and a second arithmetic circuit group (or simply arithmetic circuit groups), respectively.

[0098] As described above, each of the multiple analog arithmetic circuits 102 has a DAC 107. The DAC 107 converts a first digital signal into a first analog signal. The first digital signal is one of the digital signals used for multiplication. The DAC 107 outputs the first analog signal after DA conversion via data lines DSLp and DSLm. Note that multiple analog arithmetic circuits 102 belonging to different arithmetic circuit arrays may share one DAC 107.

[0099] The control circuit 103 controls the multiple analog arithmetic circuits 102. Specifically, the control circuit 103 inputs various signals including the first digital signal to the DAC 107 in the analog arithmetic circuit 102, and causes the DAC 107 and the ladder multiplier 108 to perform the first processing and the second processing described above.

[0100] The memory circuit 104 is arranged, for example, for each arithmetic circuit column. The memory circuit 104 stores a second digital signal used by the multiple analog arithmetic circuits 102 to perform multiplication and a third digital signal for setting gains used to perform the second processing. The memory circuit 104 supplies the second digital signal and the third digital signal to the multiple analog arithmetic circuits 102 arranged in the column direction via the transmission line MSL shown in FIG. 10 . The second digital signal is, for example, a weighting coefficient by which the first digital signal is multiplied. Note that the second digital signal is not necessarily limited to a weighting coefficient. The second digital signal is any digital signal that is multiplied by the first digital signal. Note that the memory circuit 104 may store different second digital signals and third digital signals for each of the multiple analog arithmetic circuits 102 arranged in the column direction. In other words, the analog arithmetic circuits 102 provided in the array section 110 may perform product-sum operations using different second digital signals and third digital signals. In this case, a separate memory circuit 104 may be provided for each analog arithmetic circuit 102.

[0101] Each of the plurality of ADCs 111 includes a comparison circuit 105 and a latch circuit 106. Each of the plurality of ADCs 111 is arranged for each arithmetic circuit array. A second analog signal indicating the multiplication result calculated by the plurality of analog arithmetic circuits 102 in the arithmetic circuit array is input to the corresponding ADC 111 via the corresponding signal line VSL. The ADC 111 performs AD (Analog to Digital) conversion to convert the second analog signal transmitted through the corresponding signal line VSL into a fourth digital signal.

[0102] The DACs 107 in the analog arithmetic circuits 102 perform the first processing in parallel to convert the corresponding first digital signals into first analog signals. The ladder multipliers 108 in the analog arithmetic circuits 102 multiply the first analog signals by the second digital signals and set the voltage level of the signal line VSL using the second analog signals corresponding to the multiplied values.

[0103] The second processing performed by the ladder multiplier 108 includes a processing (third processing) of multiplying the first analog signal by the second digital signal to generate a second analog signal, and a processing (fourth processing) of changing the second analog signal based on the third digital signal to generate a third analog signal. In the second processing, the voltage level of the signal line VSL is lowered based on the second analog signal (multiplied value), and then the voltage level of the signal line VSL is raised in stages based on the gain set by the third digital signal to generate a fourth analog signal. The comparator circuit 105 determines, for each stage, whether the fourth analog signal generated by the second processing exceeds a predetermined threshold.

[0104] The signal processing circuit 101 has a counter 121, a comparison bias circuit (CM_Bias) 122, a selection switch 123, and a test circuit (monitor circuit) 124 shown in FIG. 10. The counter 121 supplies a count value to the latch circuit 106. The comparison bias circuit 122 supplies a bias signal to the comparison circuit 105. The selection switch 123 switches whether or not the voltage of the signal line VSL is input to the ADC 111. A signal VSLINI is input to the gate of the selection switch 123. The test circuit 124 monitors the voltage level of the signal line VSL and checks whether or not an abnormality has occurred in the calculation result of the analog calculation circuit 102.

[0105] The signal processing circuit 101 may include a nonlinear calculator 112. The nonlinear calculator 112 performs nonlinear calculation processing on the fourth digital signal output from the ADC 111. A specific example of the nonlinear calculator 112 includes the counter 121 described above and a nonlinear calculation control circuit 125. The nonlinear calculation control circuit 125 nonlinearly controls the count value of the counter 121 according to the value of the fourth digital signal. Details of the processing by the nonlinear calculator 112 will be described later.

[0106] 11 is a circuit diagram showing a specific configuration of the DAC 107 in the analog arithmetic circuit 102. Two types of first digital signals ACTp and ACTm are input to the DAC 107, but in this embodiment, the first digital signal ACTm is set to a fixed low level, for example. Therefore, in this specification, ACTp may be referred to as the first digital signal.

[0107] The DAC 107 includes a first DAC processing unit 107a, a second DAC processing unit 107b, and a switch 130. The first DAC processing unit 107a generates a first analog signal by DA-converting the first digital signal ACTp and outputs the first analog signal to the data line DSLp. The data line DSLp is connected to a capacitor 141a in the ladder multiplier 108 via a multiplexer 144 (described later). For simplification, the multiplexer 144 is omitted from FIG. 11. The second DAC processing unit 107b is connected to a data line DSLm capable of performing charge redistribution with the data line DSLp, and the data line DSLm is connected to a capacitor 141b in the ladder multiplier 108 via a multiplexer 144 (not shown in FIG. 11). A switch 130 is connected between the data lines DSLp and DSLm. The switch 130 is switched on or off by an INSHORT signal. When the switch 130 is turned on, the data lines DSLp and DSLm are short-circuited, the capacitors 141a and 141b are connected in parallel, and the charges of the capacitors 141a and 141b are redistributed, so that the data lines DSLp and DSLm have the same voltage. When the switch 130 is turned off, the capacitors 141a and 141b are floating when the outputs of the inverters 134a and 134b are disabled, and the capacitors 141a and 141b are charging or discharging when the outputs are enabled. The data line DSLp has a voltage level corresponding to the charge stored in the capacitor 141a, and the data line DSLm has a voltage level corresponding to the charge stored in the capacitor 141b. In this specification, the capacitors 141a and 141b may be referred to as first capacitors.

[0108] The first DAC processing unit 107a has logic circuits 131a, 132a, 133a, and an inverter 134a. The logic circuits 131a, 132a, 133a are, for example, AND circuits. The logic circuit 131a receives a first digital signal ACTp and a MODE signal. The logic circuit 132a receives a Dslope[i]p signal and an inverted signal of the MODE signal. The Dslope[i]p signal is a control signal corresponding to the arithmetic circuit row with row number i. FIG. 11 shows an example in which the Dslope[0]p signal corresponding to the arithmetic circuit row with row number 0 is input. The logic circuit 133a receives an inverted signal of the output of the logic circuit 131a and an inverted signal of the output of the logic circuit 132a. The inverter 134a switches between enabling and disabling the output depending on the logic of the INCTRLp signal. For example, when the INCTRLp signal is at a high level, the inverter 134a outputs an inverted signal of the output signal of the logic circuit 133a.

[0109] The signal logic of the MODE signal switches depending on whether the analog arithmetic circuit 102 performs the first processing or the second processing. For example, when the MODE signal is at a high level, the first DAC processing unit 107a outputs a first analog signal CRow[0]p obtained by DA-converting the first digital signal ACTp. When the MODE signal is at a low level, the first DAC processing unit 107a first outputs a low-level first analog signal CRow[0]p, and then outputs a high-level first analog signal at a predetermined timing. As will be described later, when the MODE signal is at a low level, the timing at which the first analog signal CRow[0]p transitions to a high level differs for each arithmetic circuit row.

[0110] The second DAC processing unit 107b has a configuration similar to that of the first DAC processing unit 107a. Specifically, the second DAC processing unit 107b includes logic circuits 131b, 132b, and 133b, and an inverter 134b. The logic circuits 131b, 132b, and 133b, and the inverter 134b correspond to the logic circuits 131a, 132a, and 133a, and the inverter 134a of the first DAC processing unit 107a. The logic circuit 131b receives a first digital signal ACTm and a MODE signal. As described above, in this embodiment, the first digital signal ACTm is fixed to, for example, a low level. The logic circuit 132b receives a Dslope[i]m signal (Dslope[0]m signal in FIG. 11) and an inverted signal of the MODE signal. The inverter 134b switches whether or not the output is enabled depending on the INCTRLm signal corresponding to the INCTRLp signal.

[0111] Alternatively, the MODE signal and the Dslope[0] signal may be omitted, and the input signal to the inverter 134a may be generated based on the first digital signal ACT. In this case, the logic circuits 131a, 132a, and 133a may be omitted. Similarly, the MODE signal and the Dslope[0] signal may be omitted, and the input signal to the inverter 134b may be generated based on the first digital signal ACT.

[0112] The DAC 107 generates first analog signals CRow[i]p and CRow[i]m (CRow[0]p and CRow[0]m in FIG. 11) corresponding to the arithmetic circuit row with row number i, using the first DAC processing unit 107a, the second DAC processing unit 107b, and the switch 130. The first analog signals CRow[0]p and CRow[0]m are supplied to capacitors 141a and 141b, respectively.

[0113] 12 is a diagram illustrating a first process according to the third embodiment of the present disclosure. In the first process, the capacitors 141 a and 141 b are repeatedly charged, discharged, and short-circuited to generate a first analog signal at a signal level obtained by DA-converting the first digital signal.

[0114] First, the DAC 107 charges the capacitor 141a and discharges the capacitor 141b with the switch 130 turned off (step S1). The capacitor 141a is charged to, for example, the level of the power supply voltage VDD. The capacitor 141b is discharged to, for example, 0V.

[0115] Next, the DAC 107 turns on the switch 130 (step S2), which connects one end of the capacitors 141a and 141b to each other, and due to charge redistribution, the charged amounts of the capacitors 141a and 141b become the same, and one end of the capacitors 141a and 141b connected to the output node of the DAC 107 becomes 0.5 VDD.

[0116] The inverter 134a of the first DAC processing unit 107a outputs a signal having a signal logic corresponding to the signal logic of the first digital signal ACTp, or is in a floating state. The capacitor 141a charges when the output signal of the inverter 134a is at a high level, and discharges when the output signal of the inverter 134a is at a low level. Furthermore, the output of the inverter 134b of the second DAC processing unit 107b remains in a floating state once it becomes low level. Therefore, in this embodiment, the capacitor 141b may discharge, but does not charge. The switch 130 is periodically turned on during the period in which the analog arithmetic circuit 102 performs the second processing, thereby reallocating the charge between the capacitors 141a and 141b.

[0117] After step S2, when the first digital signal ACTp becomes high level, the capacitor 141a performs a charging operation and the capacitor 141b is set to a floating state (step S3). After that, the switch 130 is turned on, the capacitors 141a and 141b perform charge redistribution, and the voltage level at one end of the capacitors 141a and 141b becomes 0.75 VDD (step S4).

[0118] On the other hand, after step S2, when the first digital signal ACTp goes low, the capacitor 141a discharges and the capacitor 141b goes into a floating state (step S5). After that, the switch 130 turns on, the capacitors 141a and 141b redistribute their charges, and the voltage levels at the ends of the capacitors 141a and 141b go to 0.25 VDD (step S6).

[0119] The first digital signal ACTp is composed of multiple bits, and is input to the logic circuit 131a in order from the least significant bit, for example, to charge and discharge the capacitor 141a. Finally, when processing is completed up to the most significant bit of the first digital signal ACTp, first analog signals CRow[i]p and CRow[i]m obtained by DA-converting the first digital signal ACTp are output from one end of the capacitors 141a and 141b, which are output nodes of the DAC 107.

[0120] 13 is a timing chart showing the operation of the DAC 107 in the first process. Fig. 13 shows the timing of the MODE signal, INCTRLp signal, INCTRLm signal, INSHORT signal, first digital signals ACTp and ACTm, and first analog signals CRow[0]p and CRow[0]m. In the first process, the MODE signal is set to a high level.

[0121] The first digital signal ACTp is a digital signal composed of multiple bits, and is input to the first DAC processing unit 107a in order from the least significant bit. In the example of FIG. 13, the first digital signal ACTp is "011." At time t1, the least significant bit "1" of the first digital signal ACTp is input, and the INCTRLp signal and the INCTRLm signal transition to a high level. As described above, the first digital signal ACTm is fixed to a low level. As a result, the capacitor 141a is charged, and the capacitor 141b is discharged. As a result, one end of the capacitor 141a, which is the output node of the first DAC processing unit 107a (i.e., the first analog signal CRow[0]p), becomes VDD, and one end of the capacitor 141b, which is the output node of the second DAC processing unit 107b (i.e., the first analog signal CRow[0]m), becomes 0V.

[0122] At time t2, the INSHORT signal transitions to a high level, turning on the switch 130. As a result, similar to step S2 in Fig. 12, the charges of the capacitors 141a and 141b are redistributed, and one end of each of the capacitors 141a and 141b becomes 1 / 2 VDD.

[0123] At time t3, the second bit of the first digital signal ACTp is "1", and the INCTRLp signal goes high. As a result, the capacitor 141a charges, just as at time t1. As a result, one end of the capacitor 141a goes to VDD. At this time, the INCTRLm signal is low, and the output of the inverter 134b goes into a floating state. Therefore, the capacitor 141b does not charge or discharge and retains its charge, so one end of the capacitor 141b remains at 1 / 2 VDD. Note that the inverter 134b then continues to go into a floating state during the first processing period.

[0124] At time t4, the INSHORT signal goes high, the switch 130 turns on, and the charges of the capacitors 141a and 141b are redistributed. As a result, one end of each of the capacitors 141a and 141b becomes 3 / 4 VDD.

[0125] At time t5, the most significant bit "0" of the first digital signal ACTp is input, causing the INCTRLp signal to go high. This causes the output of the inverter 134a to go low, and the charge in the capacitor 141a is discharged through the inverter 134a. As a result, one end of the capacitor 141a drops to 0 V. At this time, because the output of the inverter 134b is in a floating state, the charge in the capacitor 141b is maintained, and one end of the capacitor 141b remains at 3 / 4 VDD.

[0126] At time t6, the INSHORT signal goes high, the switch 130 turns on, and the charges of the capacitors 141a and 141b are redistributed. As a result, one end of each of the capacitors 141a and 141b becomes 3 / 8 VDD.

[0127] As shown in FIG. 13, the input of each bit of the first digital signal ACTp and the ON operation of the switch 130 are performed alternately.

[0128] As described above, each time the INSHORT signal goes high, the charges of the two capacitors 141a and 141b are redistributed, and the same amount of charge is stored in the two capacitors 141a and 141b, resulting in the same voltage level at one end of the capacitor 141a and one end of the capacitor 141b. Because the INSHORT signal has gone high three times by time t6, the level of the first analog signal CRow[0]p (and CRow[0]m) is a multiple of 1 / 8. Furthermore, charges corresponding to the first digital signal ACTp are stored in the capacitors 141a and 141b. In the example of FIG. 13, charges corresponding to "011" are stored, so that one end of the capacitors 141a and 141b becomes 3 / 8 VDD.

[0129] The first capacitor, which is made up of multiple capacitors that redistribute charge, may include three or more capacitors. Fig. 14 is a diagram showing a modified example of a first capacitor according to the third embodiment of the present disclosure. Fig. 14 shows an example in which the first capacitor includes four capacitors 141c, 141d, 141e, and 141f. Capacitors 141c to 141e correspond to, for example, capacitor 141a in Fig. 12, and capacitor 141f corresponds to, for example, capacitor 141b. Furthermore, one end of each of capacitors 141c to 141f can be switched by switch 130 as to whether it is short-circuited or not.

[0130] 14A shows an example in which capacitor 141c is fully charged and capacitors 141d to 141f are fully discharged. The charging voltage when fully charged is VDD. In this state, when one end of each of capacitors 141c to 141f is shorted, charge is redistributed and the charging voltage of capacitors 141c to 141f becomes 0.25VDD.

[0131] 14B shows an example in which capacitors 141c and 141d are fully charged and capacitors 141e and 141f are fully discharged. In this state, when one end of each of capacitors 141c to 141f is shorted, charge is redistributed and the charging voltage of capacitors 141c to 141f becomes 0.5 VDD.

[0132] 14C shows an example in which capacitors 141c to 141e are fully charged and capacitor 141f is fully discharged. In this state, when one end of each of capacitors 141c to 141f is shorted, charge is redistributed and the charging voltage of capacitors 141c to 141f becomes 0.75 VDD.

[0133] In the example of FIG. 14, the voltage can be switched in increments of 0.25 VDD. Also, similar to the example of FIG. 13, the charging or discharging and short-circuiting of capacitors 141c to 141e can be repeated multiple times. The output of the inverter corresponding to capacitor 141f is continuously kept floating. This allows for high-resolution DA conversion. By increasing the number of capacitors, the voltage can be switched in even finer increments.

[0134] 15 is a circuit diagram showing the internal configuration of the ladder multiplier 108 in the analog arithmetic circuit 102 according to the third embodiment of the present disclosure. The ladder multiplier 108 includes a plurality of capacitors 141 a, a plurality of capacitors 141 b, a capacitor 142, a plurality of capacitors 143, a plurality of analog multiplexers (AMUX) 144, and a plurality of transistors 145. In this specification, the plurality of capacitors 143 are also collectively referred to as second capacitors.

[0135] Capacitor 142 has a predetermined unit capacitance C, and each of the plurality of capacitors 143 has a capacitance of 2C, which is twice that of capacitor 142. The plurality of capacitors 141a and the plurality of capacitors 141b each have a capacitance of 0.5C, which is half that of capacitor 142. Therefore, ladder multiplier 108 in FIG. 15 can be called a 0.5C×2−2C multiplier.

[0136] The ladder multiplier 108 has a ladder structure in which a plurality of capacitors 143 are connected in series to one signal path 146. One end of the signal path 146 is connected to one end of the capacitor 142, and the other end is connected to the signal line VSL. A pair of capacitors 141 a and 141 b is connected between the stages of the plurality of capacitors 143, between the capacitor 143 and the signal line VSL, and between the capacitor 143 and the capacitor 142, respectively.

[0137] One end of each of the plurality of sets of capacitors 141a and 141b is connected to a signal path 146, and the other end is connected to a corresponding multiplexer 144. A voltage corresponding to a corresponding bit value of the second digital signal W is input to each of the plurality of multiplexers 144. The first analog signals CRow[0]p and CRow[0]m output from the DAC 107 are also input to the plurality of multiplexers 144. The multiplexers 144 switch whether or not to input the first analog signals CRow[0]p and CRow[0]m to the other ends of the corresponding capacitors 141a and 141b based on the corresponding bit value of the second digital signal W. Note that, hereinafter, the first analog signals CRow[0]p and CRow[0]m may be collectively referred to as the first analog signal CRow[0].

[0138] The second digital signal W is input from the memory circuit 104 to the analog arithmetic circuit 102 via the transmission line MSL.

[0139] The transistors 145 switch whether or not the ladder multiplier 108 performs multiplication. The transistors 145 are connected between the stages of the plurality of capacitors 143, between the capacitors 143 on the signal path 146 and the signal line VSL, and between the capacitors 143 and 142. The xINIFLOAT signal is input to the gate of the transistor 145. When the transistor 145 is in the on state, it initializes the signal path 146 and the signal line VSL to, for example, the power supply voltage VDD. When each transistor 145 is in the on state, the ladder multiplier 108 does not perform multiplication, and the signal line VSL is set to the initial voltage Vinitial.

[0140] The ladder multiplier 108 has capacitors 141a and 141b, a multiplexer 144, and multiple bit multiplication units 147, each including a transistor 145 and a capacitor 143 or 142. While FIG. 15 illustrates an example in which the ladder multiplier 108 has four bit multiplication units 147, the ladder multiplier 108 may have any number of bit multiplication units 147, two or more. A voltage corresponding to a different bit value of the second digital signal is input to each bit multiplication unit 147. In the example of FIG. 15 , the least significant bit of the second digital signal is W[0], and the most significant bit is W[3]. The voltage of the least significant bit W[0] is input to the multiplexer 144 closer to the capacitor 142, and the voltage of the most significant bit W[3] is input to the multiplexer 144 closer to the signal line VSL.

[0141] The ladder multiplier 108 multiplies the first analog signal CRow[0] by the second digital signal W using a plurality of capacitors 141a, a plurality of capacitors 141b, a capacitor 142, and a plurality of capacitors 143 that constitute a plurality of bit multiplication units 147, and a signal path 146.

[0142] FIG. 16 is a circuit diagram of a multiplier 900 having a basic structure for explaining the operation of the ladder multiplier 108 described above. The multiplier 900 in FIG. 16 has a ladder structure that is a simplification of the ladder multiplier 108 in FIG. 15 , and includes a plurality of capacitors 901, a capacitor 142, a plurality of capacitors 143, a plurality of switches 902, and a signal path 146. In FIG. 16 , the capacitors 141 a and 141 b in FIG. 15 are replaced with a single capacitor 901. Also, in FIG. 16 , the plurality of multiplexers 144 in FIG. 15 are replaced with a plurality of switches 902. One end of the plurality of capacitors 901 is connected to the signal path 146, and the other end is connected to a corresponding switch 902. Each switch 902 switches whether the other end of the corresponding capacitor 901 is connected to the output line of the DAC 903 or grounded. The ladder multiplier 108 in FIG. 16 includes a capacitor 901 with a capacitance C and a capacitor 143 with a capacitance 2C.

[0143] The DAC 903 outputs a first analog signal Vref obtained by DA conversion of the first digital signal. The plurality of switches 902 switch between inputting the first analog signal Vref to the other end of the corresponding capacitor 901 or setting the other end to 0 V, depending on the corresponding bit value of the second digital signal.

[0144] Each of the plurality of capacitors 143 outputs a voltage that is 1 / power of 2. The output voltage Vout of the multiplier 900 in FIG. 16 is expressed by the following equation (1): In equation (1), the number of capacitors 901 on the signal path 146 in FIG. 16 is M (M is an integer equal to or greater than 2).

[0145] As shown in the above equation (1), the signal Vout output from the signal path 146 has a voltage level that corresponds to the result of multiplying the first analog signal Vref and the second digital signal W.

[0146] The ladder multiplier 108 in Fig. 15 outputs the signal expressed by equation (1) to the signal line VSL, similarly to Fig. 16. That is, the analog arithmetic circuit 102 in Fig. 15 outputs the multiplication result of the first analog signal CRow obtained by DA-converting the first digital signal and the second digital signal W to the signal line VSL.

[0147] The analog arithmetic circuit 102 according to the third embodiment of the present disclosure does not need to provide a separate DAC because it has a built-in DAC 107. The DAC 107 has a simple configuration including a switch 130 that redistributes the charges of the capacitors 141 a and 141 b in the ladder multiplier 108, and can convert the first digital signal into the first analog signal with a circuit size smaller than that of a normal DAC, thereby reducing the circuit size.

[0148] 17 is a circuit diagram showing a configuration of a multiplexer 144 according to a third embodiment of the present disclosure. The multiplexers 144 are provided corresponding to the capacitors 141a and 141b. In the case of the ladder multiplier 108 of FIG. 15, four multiplexers 144 are provided for the four pairs of capacitors 141a and 141b. Each multiplexer 144 has a first multiplexer 144a connected to the capacitor 141a and a second multiplexer 144b connected to the capacitor 141b. The first multiplexer 144a and the second multiplexer 144b receive the first analog signals CRow[0]p and CRow[0]m, respectively.

[0149] The first multiplexer 144a has a switch 151a and a transistor 152a. A voltage corresponding to the corresponding bit of the second digital signal W (W[0] in the example of FIG. 17) is input to one end of the switch 151a. A voltage corresponding to the bit xW[0] obtained by inverting the bit W[0] is input to the other end of the switch 151a. A voltage corresponding to the bit xW[0] is input to the gate of the transistor 152a.

[0150] The switch 151a is turned on when the bit W[0] is 1, and inputs the first analog signal CRow[0]p to the other end of the capacitor 141a. The transistor 152a is turned on when the bit W[0] is 0, and connects the other end of the capacitor 141a to the reference voltage VSS node.

[0151] The second multiplexer 144b has a structure similar to that of the first multiplexer 144a, and includes a switch 151b and a transistor 152b corresponding to the switch 151a and the transistor 152a, respectively.

[0152] 14, capacitors of a power of 2 may be provided instead of the capacitors 141a and 141b in the ladder multiplier 108. In this case, the capacitance of each capacitor must be set to 1 / (power of 2) of the unit capacitance C. In other words, each of the multiple capacitors 143 has a capacitance that is at least twice the capacitance of the capacitor of a power of 2.

[0153] FIG. 18 is a timing chart showing the operation of the DAC 107 in the second process. FIGS. 19A to 19F are diagrams illustrating the second process according to the third embodiment of the present disclosure. FIG. 18 shows the timing of the MODE signal, INCTRLp signal, INCTRLm signal, INSHORT signal, xINIFLOAT signal, Dslope[0]p signal, Dslope[0]m signal, Vdriver[0]p signal, Vdriver[0]m signal, and first analog signals CRow[0]p and CRow[0]m. In addition, in the second process, the INSHORT signal is set to a low level, and the switch 130 is turned off. The Vdriver[0]p signal is a NOR signal of the MODE signal and the Dslope[0]p signal. Similarly, the Vdriver[0]m signal is a NOR signal of the MODE signal and the Dslope[0]m signal.

[0154] Before time t11, the xINIFLOAT signal is at a high level, and transistor 145 in FIG. 15 is turned on, so that signal path 146 and signal line VSL are initialized to the power supply voltage level.

[0155] At time t11, the xINIFLOAT signal transitions to low level, turning off the transistor 145 in FIG. 15 . This enables the analog arithmetic circuit 102 to output a voltage corresponding to the multiplication result to the signal line VSL. Between the time before the xINIFLOAT signal transitions to low level and t11, the analog arithmetic circuit 102 performs the first processing described above to generate first analog signals CRow[0]p and CRow[0]m by DA conversion of the first digital signal. As shown in FIG. 15 , the first analog signals CRow[0]p and CRow[0]m are input to the other ends of the capacitors 141a and 141b via the multiplexer 144. This enables the ladder multiplier 108 to multiply the first analog signal CRow[0] by the second digital signal W, and prepares to generate the second analog signal.

[0156] At time t12, the MODE signal goes low, and the INCTRLp signal and INCTRLm go high. As a result, the first analog signals CRow[0]p and CRow[0]m output from the inverters 134a and 134b in Figure 11 have voltage levels that correspond to the logic of the Dslope[0]p signal and Dslope[0]m signal. At this point, the Dslope[0]p signal and Dslope[0]m signal are low, so the voltage levels of the first analog signals CRow[0]p and CRow[0]m drop to the ground level.

[0157] 19A is a diagram illustrating the operation of the analog arithmetic circuit 102 at time t12. In the analog arithmetic circuit 102, as the voltage levels of the first analog signals CRow[0]p and CRow[0]m decrease, the voltage level of the signal path 146 connected to one end of the plurality of capacitors 141a and 141b also decreases, and further, the voltage level of the signal line VSL connected to the signal path 146 also decreases. The voltage levels of the first analog signals CRow[0]p and CRow[0]m decrease by the voltage value of the first analog signal that was DA converted immediately before time t12, and therefore the voltage level of the signal line VSL decreases by the voltage amount obtained by changing Vref in equation (1) to (-Vref). In other words, the voltage level of the signal line VSL decreases from the initial voltage Vinitial by the voltage amount corresponding to the multiplication result.

[0158] 9 and 10 , multiple analog arithmetic circuits 102 are connected to one signal line VSL, and at time t12, the multiple analog arithmetic circuits 102 operate in parallel to lower the voltage level of the signal line VSL. As a result, the signal line VSL reaches a voltage level corresponding to the sum of the multiplication results of all the analog arithmetic circuits 102, i.e., the result of the product-sum operation. This operation performs the third process, which is the multiplication of the first digital signal converted into the first analog signal Crow by the second digital signal W.

[0159] Therefore, the voltage level of the signal line VSL at time t12 (i.e., the second analog signal Vvsla) is expressed by the following equation (2): In equation (2), N is the number of analog arithmetic circuits 102, α is a voltage degradation coefficient due to the parasitic capacitance of the signal line VSL, and Vmul[i] is the output voltage Vout of the signal path 146 of the i-th analog arithmetic circuit 102, and is expressed by equation (3): CRow[i] in equation (3) is the first analog signal that has been DA converted by the DAC 107 in the i-th analog arithmetic circuit 102 immediately before time t12, and M is the number of pairs of capacitors 141a and 141b.

[0160] 19B is a waveform diagram showing the degree of voltage drop on the signal line VSL according to the sum-of-products operation value. The vertical axis of FIG. 19B represents the voltage V on the signal line VSL, and the horizontal axis represents time t. FIG. 19B shows a waveform w1 when the sum-of-products operation value is large and a waveform w2 when the sum-of-products operation value is small. As described in FIG. 18 , at time t12, the MODE signal goes low, and the INCTRLp signal and the INCTRLm signal input to the enable terminals of the inverters 134a and 134b both go high. Therefore, the first analog signals CRow[i]p and CRow[i]m output from the inverters 134a and 134b both go low, and the voltage levels of the signal path 146 and the signal line VSL are reduced by an amount corresponding to the multiplication results of the multiple analog arithmetic circuits 102.

[0161] The Vdriver[i]p signal and the Vdriver[i]m signal are signals indicating that the analog arithmetic circuit 102 of row number i is in the process of lowering the voltage level of the signal line VSL. As described above, at time t12, multiple analog arithmetic circuits 102 lower the voltage level of the signal line VSL in parallel, so the Vdriver[0:N-1]p signal and the Vdriver[0:N-1]m signal become high level.

[0162] At time t12, the multiple analog arithmetic circuits 102 simultaneously reduce the voltage level of the corresponding signal path 146 in accordance with the multiplication result. Therefore, the greater the sum-of-products operation value, which is the sum of the multiplication results of the analog arithmetic circuits 102, the greater the reduction in the voltage level of the signal line VSL. In the example of FIG. 19B , the voltage level of the signal line VSL is lower in the waveform w1, in which the sum-of-products operation value of the multiple analog arithmetic circuits 102 is large, than in the waveform w2, in which the sum-of-products operation value is small. In the waveform w1, the signal line VSL becomes a voltage reduced from the initial voltage Vinitial of the signal line by a voltage αΣVmul[i]_high corresponding to the sum-of-products operation value, and in the waveform w2, the voltage is reduced from the initial voltage Vinitial by a voltage αΣVmul[i]_low corresponding to the sum-of-products operation value.

[0163] In this specification, the process in which the multiple analog arithmetic circuits 102 simultaneously reduce the voltage level on the signal line VSL based on the multiple first analog signals CRow[i] is also referred to as a third process.

[0164] 18 , the Dslope[0]p signal goes high, causing the signal level of the first analog signal CRow[0]p to rise. This causes the voltage level of the signal path 146 of the analog arithmetic circuit 102 with row number 0 to rise by one step. Accordingly, the voltage level of the third analog signal output from the ladder multiplier 108 also rises by one step, and the voltage level of the fourth analog signal on the signal line VSL also rises by one step. At time t14, the Dslope[0]m signal goes high, causing the signal level of the first analog signal CRow[0]m to rise. This causes the voltage level of the third analog signal output from the ladder multiplier 108 in the analog arithmetic circuit 102 with row number 0 to rise by another step, and accordingly, the voltage level of the fourth analog signal on the signal line VSL also rises by another step. In this way, the voltage level of the fourth analog signal on the signal line VSL is raised in two stages by sequentially raising the signal levels of the first analog signals CRow[0]p and CRow[0]m corresponding to the analog arithmetic circuit 102 of row number 0. Note that the Dslope[0]m signal may be set to high level at the same time as the Dslope[0]p signal becomes high level, thereby raising the voltage level of the fourth analog signal on the signal line VSL in one stage.

[0165] FIG. 19C illustrates the operation of the analog arithmetic circuit 102 of row number 0 at time t14. Note that FIG. 19C (and FIG. 19D , described later) illustrates an example in which the Dslope[0]p signal and the Dslope[0]m signal are simultaneously set to high level, and the voltage level of the fourth analog signal on the signal line VSL is increased by one step. In the analog arithmetic circuit 102 of row number 0, as the levels of the first analog signals CRow[0]p and CRow[0]m increase, the voltage level of the third analog signal Vg[0] output from the ladder multiplier 108 of row number 0 also increases by one step. Accordingly, the voltage level of the fourth analog signal Vvslb on the signal line VSL also increases by one step. The amount of voltage increase of the third analog signal Vg[0] and the fourth analog signal Vvslb by one step is controlled by the third digital signal G for gain setting input to the multiplexer 144. The third digital signal G has the same number of bits as the second digital signal W, and each bit of the third digital signal G is input to a corresponding multiplexer 144 of the ladder multiplier 108. When the bit value of the third digital signal G is 0, the other end of the corresponding capacitors 141 a and 141 b is set to 0 V, and when the bit value is 1, the other end of the corresponding capacitors 141 a and 141 b becomes the voltage level of the first analog signals CRow[i]p and CRow[i]m.

[0166] As described above, at time t14, the voltage levels of the first analog signals CRow[i]p and CRow[i]m become high, and therefore, when the corresponding bit value of the third digital signal G is 1, the voltage level of the third analog signal Vg[0] output from the ladder multiplier 108 increases. On the other hand, when the bit value is 0, the voltage level of the third analog signal Vg[0] is maintained.

[0167] As described above, the voltage boost width of the third analog signal Vg[0] output from the ladder multiplier 108 and the fourth analog signal Vvslb on the signal line VSL can be adjusted by the value of each bit of the third digital signal G.

[0168] Thereafter, by sequentially increasing the signal levels of the first analog signals CRow[i]p and CRow[i]m in the i-th analog calculation circuits 102 from the first onwards, the voltage level of the fourth analog signal Vvslb on the signal line VSL increases by one step at a time.

[0169] 19D is a diagram showing the operation of the multiple analog arithmetic circuits 102 after time t14. As the voltage level of the third analog signal Vg[i] output from the ladder multiplier 108 in the multiple analog arithmetic circuits 102 increases by one step at a time, the voltage level of the fourth analog signal Vvslb on the signal line VSL also increases by one step at a time.

[0170] As described above, the multiple analog arithmetic circuits 102 sequentially increase the voltage level of the third analog signal Vg[i] based on the multiple input third digital signals G. In this way, the process in which the multiple analog arithmetic circuits 102 increase the voltage level of the signal line VSL in stages to generate the fourth analog signal Vvslb is also referred to as a fourth process in this specification.

[0171] 19C and 19D, a comparator circuit 105 is connected to the signal line VSL. The comparator circuit 105 compares the voltage level of the fourth analog signal Vvslb on the signal line VSL with the initial voltage Vinitial and outputs a Vcm signal indicating the comparison result. When the voltage level of the fourth analog signal Vvslb becomes higher than the initial voltage Vinitial, the comparator circuit 105 transitions the Vcm signal from high to low, for example.

[0172] The latch circuit 106 latches (holds) the count value Cc indicating the count value of the counter 121 at the timing when the Vcm signal transitions from high level to low level, and outputs the held data as a fourth digital signal Dc.

[0173] The comparator circuit 105 outputs a high-level Vcm signal until the voltage level of the fourth analog signal Vvslb exceeds the initial voltage Vinitial, and the latch circuit 106 does not perform a latch operation. Therefore, the fourth digital signal Dc is not generated until the voltage level of the fourth analog signal Vvslb exceeds the initial voltage Vinitial.

[0174] 19E is a waveform diagram showing the stepwise increase of the fourth analog signal Vvslb on the signal line VSL due to the second processing. The voltage level of the fourth analog signal Vvslb on the signal line VSL is increased stepwise from a state where it has decreased to Vinitial-αΣVmul[i] by sequentially increasing the first analog signals CRow[i]p and CRow[i]m in the multiple analog arithmetic circuits 102. As described above, the increase in the voltage level of the fourth analog signal Vvslb (and the third analog signal Vg[i]) is controlled by the bit value of the third digital signal G. In this specification, the increase in the voltage level of the fourth analog signal Vvslb is referred to as the gain of the second processing.

[0175] 18, at time t13, the Dslope[0]p signal goes high, causing the Vdriver[0]p signal to go low, and the voltage level of the fourth analog signal Vvslb on the signal line VSL increases by the voltage step Vg[0]p. Then, at time t14, the Vdriver[0]m signal goes low, and the voltage level of the fourth analog signal Vvslb on the signal line increases by the voltage step Vg[0]m. Similarly, at times t13 and t14, the voltage level of the third analog signal Vg[0] increases by the voltage steps Vg[0]p and Vg[0]m.

[0176] As shown in FIG. 19E, the fourth analog signal Vvslb has a voltage level obtained by adding a plurality of third analog signals Vg[i] in stages to the voltage level of the second analog signal Vvsla.

[0177] The counter 121 counts up the count value Cc in synchronization with the timing at which the voltage level of the fourth analog signal Vvslb on the signal line VSL increases stepwise, for example.

[0178] At time t21, when the voltage level of the fourth analog signal Vvslb on the signal line VSL reaches the voltage Vinitial, the Vcm signal output from the comparator circuit 105 transitions from high to low, and the latch circuit 106 latches the count value Cc at that time and outputs the latched count value Cc as the fourth digital signal Dc. After that, the voltage level of the fourth analog signal Vvslb on the signal line VSL continues to rise by one step at a time until the first analog signals CRow[i]p and CRow[i]m in all of the analog arithmetic circuits 102 have risen (time t22), but the fourth digital signal Dc does not change.

[0179] 19C to 19E, the ADC 111 (i.e., the comparison circuit 105 and the latch circuit 106) converts the fourth analog signal Vvslb after the second processing into a fourth digital signal Dc. That is, the ADC 111 can AD convert the product-sum calculation results of the multiple analog calculation circuits 102.

[0180] 19F is a waveform diagram showing the voltage rise of the signal line VSL when the gain of the fourth analog signal Vvslb is adjusted. The gain of the fourth analog signal Vvslb can be adjusted by adjusting the bit value of each bit of the third digital signal G. For example, when the voltage level of the second analog signal Vvsla (Vvsla_low) is Vinitial-αΣVmul[i]_low, the level of the fourth analog signal Vvslb (Vvslb_low) reaches the voltage Vinitial at time t31, which is earlier than the above-mentioned time t21.

[0181] By reducing the bit string of the third digital signal G, it is possible to reduce the voltage increase width of the third analog signal Vg[i] generated by the analog arithmetic circuit 102, and the time at which the voltage level of the fourth analog signal Vvslb on the signal line VSL reaches the initial voltage Vinitial can be delayed from time t31. For example, the time at which the voltage level of the fourth analog signal Vvslb_low reaches the voltage Vinitial can be set to the same time t21 as above.

[0182] As a comparative example of the second processing according to the third embodiment of the present disclosure, an example in which a reference signal generation circuit is provided can be considered. The reference signal generation circuit generates a reference signal that changes over time and inputs it to the comparison circuit 105. The comparison circuit 105 compares, for example, the second analog signal Vvsla with the reference signal, and when the voltage level of the reference signal reaches the voltage level of the second analog signal Vvsla, causes the latch circuit 106 to latch the count value Cc and generate the fourth digital signal Dc. This makes it possible to generate the fourth digital signal Dc by AD-converting the product-sum calculation results of the multiple analog calculation circuits 102.

[0183] In the above comparative example, a reference signal generation circuit is required, which increases the area of ​​the signal processing circuit 101. Furthermore, the reference signal generation circuit generates a reference signal whose voltage level changes, which increases power consumption. In contrast, in the third embodiment of the present disclosure, the signal levels of the first analog signals CRow[i]p and CRow[i]m in the multiple analog arithmetic circuits 102 are sequentially increased to gradually increase the voltage level of the fourth analog signal Vvslb on the signal line VSL. Therefore, the comparator circuit 105 only needs to compare the voltage level of the fourth analog signal Vvslb with the initial voltage Vinitial, which has a fixed voltage level. This allows for a reduction in circuit size and suppression of power consumption.

[0184] In the above example, the count value Cc of the counter 121 is counted up in synchronization with the timing at which the voltage level of the fourth analog signal Vvslb on the signal line VSL increases stepwise. However, several variations are possible for the timing at which the count value Cc of the counter 121 is counted up. FIG. 20A is a diagram showing a first example of a synchronization method for the counter 121. The first example is the synchronization method for the counter 121 described in FIG. 19E and other figures. In the first example, as shown in FIG. 20A , the count value Cc of the counter 121 is counted up in synchronization with the timing at which the voltage level of the fourth analog signal Vvslb (and the third analog signal Vg[i]) on the signal line VSL increases stepwise.

[0185] FIG. 20B illustrates a second example of a synchronization method for the counter 121. FIG. 20C illustrates a third example of a synchronization method for the counter 121. In the second example, as shown in FIG. 20B , the count value Cc of the counter 121 is incremented twice each time the voltage level of the fourth analog signal Vvslb on the signal line VSL increases by one step. That is, the count period of the counter 121 in the second example is half the period in which the voltage level of the fourth analog signal Vvslb increases. In the third example, as shown in FIG. 20C , the count value Cc of the counter 121 is incremented four times each time the voltage level of the fourth analog signal Vvslb on the signal line VSL increases by one step. That is, the count period of the counter 121 in the third example is one-quarter of the period in which the voltage level of the fourth analog signal Vvslb increases.

[0186] The second and third examples may be generalized to set the count period of the counter 121 to a power of 2 or a power of 2 divided by the period in which the voltage level of the fourth analog signal Vvslb increases. According to the second and third examples, the output of the fourth digital signal Dc can be adjusted.

[0187] 20A to 20C show an example in which the voltage of the fourth analog signal Vvslb on the signal line VSL increases stepwise by the same voltage step, but the voltage step may also change by a power of two or a power of two divided by two.

[0188] 20D is a diagram showing a fourth example of the synchronization method for the counter 121. In the fourth example, as shown in FIG. 20D, the voltage level of the fourth analog signal Vvslb increases stepwise in voltage increments that are powers of 2, and the count value Cc of the counter 121 counts up in accordance with the change in the voltage level of the fourth analog signal Vvslb.

[0189] Fig. 20E is a diagram showing a fifth example of a synchronization method for the counter 121. In the fifth example, as shown in Fig. 20F, the voltage level of the fourth analog signal Vvslb on the signal line VSL increases stepwise in voltage increments represented by the Fibonacci sequence, and the count value Cc of the counter 121 counts up in accordance with the change in the voltage level of the fourth analog signal Vvslb.

[0190] It is also possible to combine the second or third example with the fourth or fifth example. Furthermore, the time interval at which the voltage width of the fourth analog signal Vvslb on the signal line VSL changes does not necessarily have to be constant, and the time interval may change periodically or irregularly.

[0191] 20F is a diagram showing a sixth example of a synchronization technique for the counter 121. In the sixth example, as shown in FIG. 20F, the counter 121 starts counting up after a predetermined period has elapsed since the voltage level of the fourth analog signal Vvslb on the signal line VSL began to change stepwise. Alternatively, the counter 121 may be configured to perform counting up only when the voltage level of the fourth analog signal Vvslb is within a predetermined voltage range.

[0192] In the sixth example, even if the level of the fourth analog signal Vvslb reaches the voltage Vinitial before the counter 121 starts counting up, the count value Cc latched by the latch circuit 106 is 0, and the value of the fourth digital signal Dc is also 0. That is, in the sixth example, a rectified linear unit (ReLU) calculation can be realized, in which 0 is continuously output before the start of the counting up operation. The ReLU calculation may be performed downstream of the ADC 111. For example, a nonlinear calculation circuit may be provided downstream of the ADC 111, which outputs the fourth digital signal Dc as is if the fourth digital signal Dc is a positive value and outputs 0 if the fourth digital signal Dc is a negative value. The sixth example may be combined with at least one of the first to fifth examples described above.

[0193] FIG. 20G illustrates a seventh example of a synchronization technique for the counter 121. In the first to sixth examples, the voltage level of the signal line VSL is initialized to the initial voltage Vinitial and the count value Cc of the counter 121 is initialized each time a multiply-add operation is completed. However, in the seventh example, as shown in FIG. 20G, even when a multiply-add operation is completed and the signal line VSL is initialized to the initial voltage Vinitial, the count value of the counter 121 is not initialized but is maintained. This allows the counter 121 to cumulatively add the results of multiple multiply-add operations and generate a cumulatively added fourth digital signal. The seventh example may be combined with at least one of the first to sixth examples described above.

[0194] 21 is a block diagram showing a configuration of a storage circuit 104 according to a third embodiment of the present disclosure. The storage circuit 104 includes, for example, a static random access memory (SRAM). The storage circuit 104 includes a logic circuit (I / O Logic) 161 that controls the operation of the storage circuit 104, a gain storage circuit (SRAM for Gain) 162 that stores a third digital signal G for each analog arithmetic circuit 102, a weighting coefficient storage circuit (SRAM for Weight) 163 that stores a second digital signal W for each analog arithmetic circuit 102, and an output circuit 164 that outputs the second digital signal W and the third digital signal G to the corresponding analog arithmetic circuits 102.

[0195] 22 is a flowchart showing the overall processing operation of the signal processing circuit 101 according to the third embodiment of the present disclosure. First, the signal processing circuit 101 writes, for example, a second digital signal W representing a weighting coefficient and a third digital signal G representing a gain to the storage circuit 104 (step S21). The timing for writing the second digital signal W and the third digital signal G to the storage circuit 104 is arbitrary. The second digital signal W and the third digital signal G may be written to the storage circuit 104 when the signal processing circuit 101 is manufactured or shipped, or the settings of the second digital signal W and the third digital signal G may be changed by the user at will after shipment.

[0196] 15 , and initializes each node on the signal path 146 of the ladder multipliers 108 in the plurality of analog arithmetic circuits 102 to, for example, the power supply voltage level (step S22). The analog arithmetic circuit 102 also reads a second digital signal W representing a weighting coefficient from the storage circuit 104 (step S23). The read second digital signal W is input to the multiplexer 144. Next, with the signal line VSL set to the initial voltage Vinitial, the analog arithmetic circuit 102 performs a first process to generate a first analog signal CRow[i] (step S24).

[0197] The transistor 145 is turned off, and the initialization of the ladder multipliers 108 in the analog arithmetic circuits 102 and the signal line VSL is canceled (step S25). As a result, the multiplication of the first analog signal CRow[i] and the second digital signal W is performed in parallel in each of the ladder multipliers 108 in the multiple analog arithmetic circuits 102. As a result, a voltage Vout indicating the multiplication result is generated in each ladder multiplier 108. In addition, a second analog signal Vvsla based on the product-sum calculation results of the multiple analog arithmetic circuits 102 is transferred to the signal line VSL, and the voltages of the signal line VSL are simultaneously pulled down.

[0198] Next, the analog arithmetic circuit 102 reads out the third digital signal G for gain setting from the memory circuit 104 (step S26). Depending on the value of the third digital signal G, the voltage increase width by which the voltage level of the signal line VSL is increased stepwise can be variably controlled.

[0199] Next, the signal processing circuit 101 determines whether or not to perform a special calculation (step S27). The special calculation is, for example, a nonlinear calculation such as the ReLU calculation shown in FIG. 20F. When performing a special calculation, the special calculation setting is performed as necessary (step S28). When performing a ReLU calculation, the nonlinear calculation control circuit 125 delays the timing at which the counter 121 starts counting up. Furthermore, when adding the result of the previous product-sum calculation shown in FIG. 20G, the nonlinear calculation control circuit 125 performs processing such as holding the count value of the counter 121 without resetting it.

[0200] The signal processing circuit 101 performs the fourth process (step S29) when no special calculation is performed or after the special calculation setting in step S28 is completed. The multiple analog calculation circuits 102 gradually increase the voltage of the signal line VSL using the third digital signal G, and the counter 121 performs a count-up operation. The comparison circuit 105 compares the voltage level of the fourth analog signal on the signal line VSL with the initial voltage Vinitial. When the Vm signal, which is the output signal of the comparison circuit 105, is inverted, the latch circuit 106 latches the count value Cc of the counter 121 to generate a fourth digital signal Dc. That is, the ADC 111 performs AD conversion to generate a fourth digital signal Dc based on the result of the product-sum calculation in step S25 (step S30).

[0201] Next, the signal processing circuit 101 determines whether or not to end the calculation (step S31). If the calculation is to be continued, the signal processing circuit 101 determines whether or not to update the second digital signal W and the third digital signal G in the storage circuit 104 (step S32). If the second digital signal W and the third digital signal G are to be updated, the processing from step S31 onwards is performed again. If the signals are not to be updated, the processing from step S32 onwards is performed again.

[0202] 23 is a timing chart showing the overall operation of the signal processing circuit 101 according to the third embodiment of the present disclosure. Until time t41 in FIG. 23, the first analog signal CRow[i] is input to one end of each of the capacitors 141a and 141b in FIG. 15. Meanwhile, because the transistor 145 is on, the voltage levels of the other ends of the capacitors 141a and 141b continue to be initialized to a predetermined voltage level (e.g., the level of the power supply voltage VDD). This prevents the ladder multiplier 108 from starting a multiplication operation.

[0203] At time t41 in FIG. 23 , the transistor 145 is turned off, and the ladder multiplier 108 is ready for a multiplication operation (step S25 in FIG. 22 ). At time t42, the MODE signal is turned off, and the second process is initiated (step S29 in FIG. 22 ). At time t43, the second process is completed, and a fourth digital signal indicating the result of the product-sum operation is output from the latch circuit 106 (step S30 in FIG. 22 ). If step S31 in FIG. 22 is YES, before the analog arithmetic circuits 102 start a new multiplication, the xINIFLOAT signal is set to a high level to turn on the transistor 145, and the voltage levels of the analog arithmetic circuits 102 and the signal line VSL are initialized to a predetermined voltage level (e.g., the level of the power supply voltage VDD) (step S22 in FIG. 22 ). The operations up to time t43 are then repeated.

[0204] The operation before time t41 is the same as that in the timing chart of Fig. 13. The operation from time t41 to time t43 in Fig. 23 is the same as that in the timing chart of Fig. 18.

[0205] The memory circuit 104 in FIG. 9 is composed of multiple bits and stores the second digital signal W and the third digital signal G. The weighting coefficient memory circuit 163 and the gain memory circuit 162 in the memory circuit 104 each have a number of memory elements 170 that store the bit values ​​of the second digital signal W and the third digital signal G. FIG. 24A is a circuit diagram of one memory element 170 in the memory circuit 104. The memory element 170 includes logic circuits 171, 172, and 173. The logic circuit 171 outputs, for example, a NOR signal of the SET signal and the output signal of the logic circuit 172. The logic circuit 172 outputs, for example, a NAND signal of the XRESET signal and the output signal of the logic circuit 171. The logic circuit 173 outputs, for example, an inverted output signal of the logic circuit 171. The SET signal is a data bit to be stored in the memory element 170. The XRESET signal is a signal that erases the data bits stored in the memory element 170, and erasure is performed when the signal is at a low level. Note that Fig. 24A is an example of the circuit configuration of the memory element 170, and various modifications are applicable.

[0206] 24B is a circuit diagram showing the configuration of the comparison circuit 105. The comparison circuit 105 has transistors 181, 182, 183, and 184 connected in series between a node of the power supply voltage VDD and a ground node. The transistors 181 and 182 are, for example, PMOS transistors, and the transistors 183 and 184 are, for example, NMOS transistors. A voltage Vbp1 that passes a bias current is input to the gate of the transistor 181. For example, bias signals Vbp2 and Vbm from the comparison bias circuit 122 are input to the gates of the transistors 182 and 183, respectively. A fourth analog signal Vvslb is input to the gate of the transistor 184. A binary signal Vcm indicating the comparison result between the fourth analog signal Vvslb and the initial voltage Vinitial is output from the connection node of the transistors 182 and 183.

[0207] 24C is a diagram showing the configuration of the comparison bias circuit 122. The comparison bias circuit 122 includes a switch 191, transistors 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, and 209, and capacitors 210 and 211. The transistors 192, 193, 195, 198, 201, 204, 205, 207, and 209 are, for example, NMOS transistors. The transistors 194, 196, 197, 199, 200, 202, 203, 206, and 208 are, for example, PMOS transistors.

[0208] Transistors 193 and 195 form a current mirror circuit, and by controlling the current flowing between the drain and source of transistor 193, the current flowing between the drain and source of transistors 195 and 194 can be controlled, thereby controlling the voltage levels of bias signals Vbp and Vbm.

[0209] 24D is a circuit diagram showing the configuration of the test circuit 124 shown in FIG. 10. The test circuit 124 is provided to monitor the voltage level on the signal line VSL. The test circuit 124 makes it easier to identify the location of a fault in the signal processing circuit 101.

[0210] The test circuit 124 monitors, for example, the second analog signal Vvsla. When an abnormality in the fourth digital signal Dc is discovered in a downstream device or the like, the location of the abnormality in the signal processing circuit 101 can be easily identified by referring to the test results of the test circuit 124. When the second analog signal Vvsla is abnormal, it can be determined that an abnormality has occurred in the first processing and the product-sum calculations of the multiple analog arithmetic circuits 102. When no abnormality is found in the second analog signal Vvsla, it can be determined that an abnormality has occurred in the second processing and AD. As described above, the location of the abnormality can be isolated using the test circuit 124.

[0211] The test circuit 124 includes a transfer gate 221 and transistors 222, 223, 224, 225, 226, and 227. The transistors 223, 224, and 225 are, for example, PMOS transistors, and the transistors 222, 226, and 227 are, for example, NMOS transistors. The transfer gate 221 receives a selection signal SEL and an inverted signal xSEL of the selection signal SEL at its gate. The transfer gate 221 opens when a high-level selection signal SEL is input, and captures the Vbmon signal. When the selection signal SEL is high, the transistor 222 is turned off. Therefore, the transistor 223, which functions as a current source, passes a current corresponding to the voltage level of the Vbmon signal. The voltage of the signal line VSL is input to the gate of the transistor 224. A current corresponding to the voltage level of the signal line VSL flows between the source and drain of the transistor 224. Since transistors 226 and 227 form a current mirror circuit, a current proportional to the source-drain current of transistor 224 flows between the source and drain of transistor 225. The gate voltage of transistor 225 has a voltage level corresponding to the voltage of signal line VSL. Therefore, by monitoring the gate voltage of transistor 225, the voltage level of signal line VSL can be detected.

[0212] 25A is a diagram showing a first example of a substrate structure of a signal processing circuit 101 according to a third embodiment of the present disclosure. The analog arithmetic circuit 102 (ladder multiplier 108) and the memory circuit 104 are arranged, for example, on different layers of the same substrate. Specifically, the memory circuit 104 is arranged on a first layer Ly1, and the analog arithmetic circuit 102 is arranged on a second layer Ly2.

[0213] The analog arithmetic circuit 102 and the memory circuit 104 may be arranged on different substrates. Furthermore, the signal processing circuit 101 may have a structure in which a substrate on which the analog arithmetic circuit 102 is arranged and a substrate on which the memory circuit 104 is arranged are stacked.

[0214] The multiplexer 144 is arranged, for example, in the same layer as the memory circuit 104. In the example of Fig. 25A, the first multiplexer 144a and the second multiplexer 144b are integrated and arranged in the same region of the same layer.

[0215] 25B is a diagram illustrating a second example of a substrate structure of the signal processing circuit 101 according to the third embodiment of the present disclosure. Fig. 25B differs from Fig. 25A in that the first multiplexer 144a and the second multiplexer 144b are arranged separately from each other. In the example of Fig. 25B, the first multiplexer 144a and the second multiplexer 144b are arranged to face each other with the memory circuit 104 interposed therebetween.

[0216] 26A is a plan view of a first example of a signal processing circuit 101 according to a third embodiment of the present disclosure, showing an example in which a memory circuit 104 and a ladder multiplier 108 are arranged close to each other in the planar direction.

[0217] FIG. 26B is a diagram showing the circuit structure of the ladder multiplier 108 of FIG. 26A. The circuit structure of FIG. 26B is similar to that of FIG. 15. FIG. 26B shows an example in which capacitors 141a, 141b, and 143, a signal path 146, and data lines DSLp and DSLm are arranged in a plane. FIG. 26C is a planar perspective view showing the wiring structure of the ladder multiplier 108 of FIG. 26B. In FIG. 26C, for example, multiple wiring layers 146a constituting the signal path 146 are arranged to surround multiple data lines DSLp and multiple data lines DSLm, respectively. Insulating layers 230 are arranged between two adjacent wiring layers 146a, between the wiring layer 146a and the data line DSLp, and between the wiring layer 146a and the data line DSLm. The capacitor 141a is arranged between the wiring layer 146a and the data line DSLp. The capacitor 141b is disposed between the wiring layer 146a and the data line DSLm. The capacitor 143 is disposed between adjacent wiring layers 146a. The capacitors 141a, 141b, 143 and the wiring layer 146a are disposed on the second layer Ly2 in FIG. 25A.

[0218] 27A is a plan view of a second example of a signal processing circuit 101 according to a third embodiment of the present disclosure. Fig. 27A shows an example in which a ladder multiplier 108 is divided into two regions 108a and 108b. The regions 108a and 108b are arranged with the memory circuit 104 sandwiched between them.

[0219] 27B is a diagram showing the circuit structure of the ladder multiplier 108 of FIG. 27A. FIG. 27B shows an example in which the capacitor 141a in the ladder multiplier 108 is arranged in the region 108a of FIG. 27A, and the capacitor 141b is arranged in the region 108b. FIG. 27C is a planar perspective view showing the wiring structure of the ladder multiplier 108 of FIG. 27B. FIG. 27C shows an example in which the data lines DSLp and DSLm are arranged opposite each other with the wiring of the signal path 146 in between. Accordingly, the capacitors 141a and 141b are arranged opposite each other with the wiring layer 146a in between.

[0220] The signal processing circuit 101 may include a plurality of array units 110. Fig. 28A is a diagram showing a configuration in which a plurality of array units 110 of the same size are arranged. The plurality of array units 110 are arranged in at least one of a first direction X or a second direction Y (in the example of Fig. 28A, the second direction Y). The plurality of array units 110 each have the same number of analog arithmetic circuits 102. The signal processing circuit 101 can improve the arithmetic speed by, for example, performing arithmetic operations in parallel using the plurality of array units 110.

[0221] FIG. 28B is a diagram showing a configuration in which multiple array units 110 of different sizes are arranged. FIG. 28B illustrates a small-sized array unit 110a and a large-sized array unit 110b. In the example of FIG. 28B, the array units 110a and 110b are arranged in the second direction Y. The array unit 110b has a larger number of analog arithmetic circuits 102 arranged therein than the array unit 110a. The array unit 110a is used, for example, in a mobile network (MobileNet) and performs lightweight, high-speed calculations such as depthwise separable convolution. The array unit 110b is used for advanced calculations such as a fully convolutional network (FCN).

[0222] Fig. 29 is a diagram showing the difference between the signal processing circuit 101 according to the third embodiment of the present disclosure and a signal processing circuit 920 according to a comparative example. Fig. 29A illustrates the signal processing circuit 920 according to the comparative example, and Fig. 29B illustrates the signal processing circuit 101 according to the third embodiment of the present disclosure.

[0223] The signal processing circuit 920 has a product-sum operation circuit 921 configured, for example, with the multiplier 900 of Fig. 16. The product-sum operation circuit 921 does not have a DA conversion function for converting a digital signal into an analog signal for use in the product-sum operation, nor an AD conversion function for converting the result of the analog product-sum operation into a digital signal. Therefore, the signal processing circuit 920 requires a DAC 903, a gain setting circuit 922, and an ADC 923, which increases the circuit area.

[0224] In contrast, the array unit (product-sum operation circuit) 110 according to the third embodiment of the present disclosure can perform DA conversion of the first digital signal ACTp by the first processing, and can perform AD conversion of the fourth analog signal Vvslb by the second processing. Therefore, the signal processing circuit 101 does not require the DAC 903, the gain setting circuit 922, and the ADC 923, and can therefore have a smaller area than the signal processing circuit 920.

[0225] As described above, the signal processing circuit 101 according to the third embodiment of the present disclosure includes a plurality of analog arithmetic circuits 102 and an ADC 111. Each analog arithmetic circuit 102 includes a DAC 107 and a ladder multiplier 108. The DAC 107 performs a first process of DA conversion of the first digital signal ACTp into the first analog signal CRow[i] by using the capacitors 141a and 141b in the ladder multiplier 108 to reallocate capacitance. The ladder multiplier 108 performs a second process of changing the second analog signal Vvsla, which is generated by multiplying the first analog signal CRow[i] by the second digital signal W, based on the third digital signal G used for gain setting, to generate the third analog signal Vg[0]. The voltage level of the signal line VSL, to which the multiple analog arithmetic circuits 102 are connected, is first lowered from an initial voltage Vinitial based on the multiple second analog signals Vvsla, and then gradually raised based on the third analog signals Vg[0] generated by each ladder multiplier 108 to generate a fourth analog signal Vvslb. The comparator circuit 105 in the ADC 111 compares the voltage level of the fourth analog signal Vvslb with the initial voltage Vinitial and generates a Vcm signal indicating the comparison result. The latch circuit 106 in the ADC 111 latches the count value Cc of the counter 121 and generates a fourth digital signal Dc when the Vcm signal transitions from high to low.

[0226] According to the third embodiment of the present disclosure, some of the capacitors 141a and 141b constituting the ladder multiplier 108 in each analog arithmetic circuit 102 are reused to DA convert the first digital signal ACTp into the first analog signal CRow[i], thereby reducing the circuit size of the DAC 107 and enabling the signal processing circuit 101 to be made smaller than if a dedicated DAC were provided.

[0227] Furthermore, by switching the input of the multiplexer 144 connected to the ladder multiplier 108 in each analog arithmetic circuit 102 from the second digital signal W to the third digital signal G, the gain during AD conversion can be changed, and the resolution during AD conversion of the sum-of-products result signal can be made variable.

[0228] The voltage level on the signal line VSL can be changed according to the result of the product-sum operation, and the fluctuation in the voltage level of the signal line VSL falls within a certain range from the initial voltage Vinitial, thereby reducing power consumption.

[0229] The signal processing circuit 101 may omit either the first processing or the second processing. For example, the first processing may be omitted and a DAC 903 or the like may be provided. Furthermore, the second processing may be omitted and an ADC 923 or the like may be provided.

[0230] Alternatively, the first process may be realized by applying the first or second embodiment of the present disclosure. That is, the multiplier in Fig. 1 and the capacitance selection units 13a to 13c in Fig. 2A to 2C or 8 may be applied to the ladder multiplier 108 in Fig. 15 etc.

[0231] (Fourth Embodiment) Figure 30 is a circuit diagram showing a ladder multiplier 108c according to a fourth embodiment of the present disclosure. The ladder multiplier 108c in Figure 30 differs from the ladder multiplier 108 in Figure 15 in that it does not have capacitors 142 and 143. In addition, the ladder multiplier 108c has capacitors 141g and 141h corresponding to the capacitors 141a and 141b in Figure 30, respectively. One capacitor 141g and one capacitor 141h adjacent to capacitor 141g constitute one capacitor group 240.

[0232] The ladder multiplier 108c has a plurality of capacitor groups 240. Capacitors 141g and 141h belonging to the same capacitor group 240 have the same capacitance. Furthermore, in each of the different capacitor groups 240, the capacitances of the capacitors 141g and 141h differ by a power of 2. In the example of FIG. 30 , capacitors 141g and 141h with a capacitance of 0.5C, capacitors 141g and 141h with a capacitance of C, capacitors 141g and 141h with a capacitance of 2C, and capacitors 141g and 141h with a capacitance of 4C are arranged.

[0233] A multiplexer 144 is provided for each capacitor group 240. A voltage corresponding to each bit of the second digital signal W is input to each multiplexer 144 in accordance with the order of the capacitance of the corresponding capacitor group 240. Specifically, a voltage corresponding to the least significant bit of the second digital signal W is input to the multiplexer 144 connected to the capacitor group 240 with the smallest capacitance, and a voltage corresponding to the most significant bit of the second digital signal W is input to the multiplexer 144 connected to the capacitor group 240 with the largest capacitance.

[0234] 15, the ladder multiplier 108c is used for the first processing, the multiplication of the second digital signal W and the first analog signal CRow[i], and the second processing. In addition, the ladder multiplier 108c can perform a product-sum operation similar to that shown in the above-mentioned equation (3), and can output a second analog signal Vvsla similar to that shown in equation (2) to the signal line VSL.

[0235] Fig. 31A is a planar perspective view showing a first example of the wiring structure of ladder multiplier 108c. Fig. 31B is a planar perspective view showing a second example of the wiring structure of ladder multiplier 108c. The wiring structures of Fig. 31A and Fig. 31B correspond to the wiring structures of Fig. 26C and Fig. 27C, respectively.

[0236] In the analog arithmetic circuit 102 of FIG. 15, the capacitance of the capacitors 141a and 141b must be precisely adjusted relative to the capacitors 142 and 143. On the other hand, the ladder multiplier 108c of FIG. 30 does not require this adjustment, and is characterized by being less susceptible to noise caused by errors in the capacitance of each capacitor. Furthermore, the ladder multiplier 108c of FIG. 30 does not need to be arranged in ascending order of capacitance from the right side of FIG. 30. Therefore, the degree of freedom in circuit layout is higher than that of the analog arithmetic circuit 102 of FIG. 15. As described above, the multiplexer 144 needs to receive the bits of the second digital signal W corresponding to the capacitance of the capacitor group 240 connected thereto.

[0237] As in the third embodiment of the present disclosure, the capacitance selection sections 13a to 13c in FIGS. 2A to 2C or 8 may be applied to the capacitor group 240 in FIG. 30.

[0238] (Application Examples) The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, construction machinery, or agricultural machinery (tractor).

[0239] 32 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied. The vehicle control system 7000 includes a plurality of electronic control units connected via a communication network 7010. In the example shown in FIG. 32 , the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an outside-vehicle information detection unit 7400, an inside-vehicle information detection unit 7500, and an integrated control unit 7600. The communication network 7010 connecting these multiple control units may be an in-vehicle communication network conforming to any standard, such as a Controller Area Network (CAN), a Local Interconnect Network (LIN), a Local Area Network (LAN), or FlexRay (registered trademark).

[0240] Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a memory unit that stores the programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various controlled devices. Each control unit includes a network I / F for communicating with other control units via a communication network 7010, and a communication I / F for communicating with devices or sensors inside and outside the vehicle via wired or wireless communication. Figure 32 illustrates the functional configuration of the integrated control unit 7600, including a microcomputer 7610, a general-purpose communication I / F 7620, a dedicated communication I / F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I / F 7660, an audio / video output unit 7670, an in-vehicle network I / F 7680, and a memory unit 7690. Other control units also include a microcomputer, a communication I / F, a memory unit, and the like.

[0241] The drivetrain control unit 7100 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 7100 functions as a control device for a drive force generating device for generating drive force for the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating braking force for the vehicle. The drivetrain control unit 7100 may also function as a control device for an ABS (Antilock Brake System) or an ESC (Electronic Stability Control), etc.

[0242] A vehicle state detection unit 7110 is connected to the drivetrain control unit 7100. The vehicle state detection unit 7110 includes at least one of a gyro sensor that detects the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, or a sensor that detects the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine rotation speed, the rotation speed of the wheels, etc. The drivetrain control unit 7100 performs arithmetic processing using signals input from the vehicle state detection unit 7110, and controls the internal combustion engine, the drive motor, the electric power steering device, the brake device, etc.

[0243] The body system control unit 7200 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 7200. The body system control unit 7200 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0244] The battery control unit 7300 controls the secondary battery 7310, which is the power supply source for the drive motor, in accordance with various programs. For example, information such as battery temperature, battery output voltage, or remaining battery capacity is input to the battery control unit 7300 from a battery device equipped with the secondary battery 7310. The battery control unit 7300 performs arithmetic processing using these signals, and controls the temperature regulation of the secondary battery 7310 or a cooling device or the like equipped in the battery device.

[0245] The outside vehicle information detection unit 7400 detects information outside the vehicle equipped with the vehicle control system 7000. For example, at least one of an imaging unit 7410 and an outside vehicle information detection unit 7420 is connected to the outside vehicle information detection unit 7400. The imaging unit 7410 includes at least one of a time-of-flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The outside vehicle information detection unit 7420 includes at least one of an environmental sensor for detecting the current weather or climate, or a surrounding information detection sensor for detecting other vehicles, obstacles, pedestrians, etc. around the vehicle equipped with the vehicle control system 7000.

[0246] The environmental sensor may be, for example, at least one of a raindrop sensor that detects rain, a fog sensor that detects fog, a sunshine sensor that detects the degree of sunshine, and a snow sensor that detects snowfall. The surrounding information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. The imaging unit 7410 and the outside vehicle information detection unit 7420 may each be provided as an independent sensor or device, or may be provided as a device in which multiple sensors or devices are integrated.

[0247] Here, Figure 33 shows an example of the installation positions of the imaging unit 7410 and the vehicle exterior information detection unit 7420. The imaging units 7910, 7912, 7914, 7916, and 7918 are provided, for example, at least one of the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 7900. The imaging unit 7910 provided on the front nose and the imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 7900. The imaging units 7912 and 7914 provided on the side mirrors mainly acquire images of the sides of the vehicle 7900. The imaging unit 7916 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900. The imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0248] 33 shows an example of the imaging ranges of the imaging units 7910, 7912, 7914, and 7916. Imaging range a indicates the imaging range of the imaging unit 7910 provided on the front nose, imaging ranges b and c indicate the imaging ranges of the imaging units 7912 and 7914 provided on the side mirrors, respectively, and imaging range d indicates the imaging range of the imaging unit 7916 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 7910, 7912, 7914, and 7916, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained.

[0249] The outside vehicle information detection units 7920, 7922, 7924, 7926, 7928, and 7930 provided on the front, rear, sides, corners, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, ultrasonic sensors or radar devices. The outside vehicle information detection units 7920, 7926, and 7930 provided on the front nose, rear bumper, back door, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, LIDAR devices. These outside vehicle information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, obstacles, etc.

[0250] Returning to FIG. 32 , the explanation will be continued. The outside-vehicle information detection unit 7400 causes the imaging unit 7410 to capture an image outside the vehicle and receives the captured image data. The outside-vehicle information detection unit 7400 also receives detection information from the connected outside-vehicle information detection unit 7420. If the outside-vehicle information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the outside-vehicle information detection unit 7400 emits ultrasonic waves or electromagnetic waves and receives information on the received reflected waves. Based on the received information, the outside-vehicle information detection unit 7400 may perform object detection processing or distance detection processing for people, vehicles, obstacles, signs, or text on the road surface. Based on the received information, the outside-vehicle information detection unit 7400 may also perform environmental recognition processing for recognizing rainfall, fog, road conditions, etc. Based on the received information, the outside-vehicle information detection unit 7400 may also calculate the distance to an object outside the vehicle.

[0251] The outside vehicle information detection unit 7400 may also perform image recognition processing or distance detection processing to recognize people, vehicles, obstacles, signs, or characters on the road surface based on the received image data. The outside vehicle information detection unit 7400 may perform processing such as distortion correction or alignment on the received image data, and may also generate an overhead image or a panoramic image by combining image data captured by different image capturing units 7410. The outside vehicle information detection unit 7400 may also perform viewpoint conversion processing using image data captured by different image capturing units 7410.

[0252] The interior information detection unit 7500 detects information inside the vehicle. A driver state detection unit 7510 that detects the driver's state is connected to the interior information detection unit 7500, for example. The driver state detection unit 7510 may include a camera that captures an image of the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sound from within the vehicle cabin. The biosensor is provided, for example, on the seat or steering wheel, and detects the biometric information of a passenger sitting in the seat or the driver gripping the steering wheel. The interior information detection unit 7500 may calculate the driver's level of fatigue or concentration based on the detection information input from the driver state detection unit 7510, or may determine whether the driver is dozing off. The interior information detection unit 7500 may perform processing such as noise canceling on the collected audio signal.

[0253] The integrated control unit 7600 controls the overall operation of the vehicle control system 7000 according to various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 may be implemented by a device that can be operated by a passenger, such as a touch panel, a button, a microphone, a switch, or a lever. Data obtained by voice recognition of a voice input through a microphone may be input to the integrated control unit 7600. The input unit 7800 may be, for example, a remote control device using infrared or other radio waves, or an externally connected device such as a mobile phone or a personal digital assistant (PDA) that can operate the vehicle control system 7000. The input unit 7800 may be, for example, a camera, in which case the passenger can input information using gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on information input by the passenger using the input unit 7800 and outputs the input signal to the integrated control unit 7600. Passengers and the like operate this input unit 7800 to input various data to the vehicle control system 7000 and to instruct processing operations.

[0254] The storage unit 7690 may include a ROM (Read Only Memory) that stores various programs executed by the microcomputer, and a RAM (Random Access Memory) that stores various parameters, calculation results, sensor values, etc. The storage unit 7690 may also be realized by a magnetic storage device such as an HDD (Hard Disc Drive), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.

[0255] The general-purpose communication I / F 7620 is a general-purpose communication I / F that mediates communication with various devices present in the external environment 7750. The general-purpose communication I / F 7620 may implement a cellular communication protocol such as GSM (Global System of Mobile communications), WiMAX (registered trademark), LTE (Long Term Evolution), or LTE-Advanced (LTE-A), or other wireless communication protocols such as a wireless LAN (also referred to as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). The general-purpose communication I / F 7620 may connect to a device (e.g., an application server or a control server) present on an external network (e.g., the Internet, a cloud network, or an operator-specific network) via, for example, a base station or an access point. In addition, the general-purpose communication I / F 7620 may connect to a terminal located near the vehicle (e.g., a terminal of a driver, pedestrian, or store, or an MTC (Machine Type Communication) terminal) using, for example, P2P (Peer To Peer) technology.

[0256] The dedicated communication I / F 7630 is a communication I / F that supports a communication protocol designed for use in vehicles. The dedicated communication I / F 7630 may implement a standard protocol such as WAVE (Wireless Access in Vehicle Environment), which is a combination of a lower layer IEEE 802.11p and an upper layer IEEE 1609, DSRC (Dedicated Short Range Communications), or a cellular communication protocol. The dedicated communication I / F 7630 typically performs V2X communication, which is a concept including one or more of vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0257] The positioning unit 7640 receives, for example, GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites) to perform positioning and generate position information including the latitude, longitude, and altitude of the vehicle. Note that the positioning unit 7640 may identify the current position by exchanging signals with a wireless access point, or may obtain position information from a terminal such as a mobile phone, PHS, or smartphone that has a positioning function.

[0258] The beacon receiving unit 7650 receives, for example, radio waves or electromagnetic waves transmitted from radio stations or the like installed on the road, and acquires information such as the current location, congestion, road closures, required travel time, etc. The function of the beacon receiving unit 7650 may be included in the dedicated communication I / F 7630 described above.

[0259] The in-vehicle device I / F 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle. The in-vehicle device I / F 7660 may establish wireless connections using wireless communication protocols such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB). Furthermore, the in-vehicle device I / F 7660 may establish a wired connection such as USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface), or MHL (Mobile High-Definition Link) via a connection terminal (and a cable, if necessary) not shown. The in-vehicle device 7760 may include, for example, at least one of a mobile device or a wearable device owned by a passenger, or an information device carried into or attached to the vehicle. The in-vehicle device 7760 may also include a navigation device that searches for a route to an arbitrary destination. The in-vehicle device I / F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.

[0260] The in-vehicle network I / F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I / F 7680 transmits and receives signals in accordance with a predetermined protocol supported by the communication network 7010.

[0261] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 in accordance with various programs based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. For example, the microcomputer 7610 may calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the acquired information inside and outside the vehicle, and output control commands to the drivetrain control unit 7100. For example, the microcomputer 7610 may perform cooperative control aimed at realizing functions of an Advanced Driver Assistance System (ADAS), including vehicle collision avoidance or impact mitigation, following driving based on the following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc. In addition, the microcomputer 7610 may perform cooperative control for the purpose of autonomous driving, in which the vehicle travels autonomously without relying on driver operation, by controlling a driving force generating device, a steering mechanism, a braking device, etc. based on information acquired about the vehicle's surroundings.

[0262] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and objects such as surrounding structures and people, and create local map information including information about the vicinity of the vehicle's current location, based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. Furthermore, the microcomputer 7610 may predict dangers, such as a vehicle collision, the approach of a pedestrian, or entry into a closed road, based on the acquired information, and generate a warning signal. The warning signal may be, for example, a signal for generating a warning sound or turning on a warning lamp.

[0263] The audio / image output unit 7670 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying vehicle occupants or the outside of the vehicle of information. In the example of FIG. 32 , an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are illustrated as output devices. The display unit 7720 may include, for example, at least one of an on-board display and a head-up display. The display unit 7720 may have an AR (Augmented Reality) display function. The output device may also be other devices, such as headphones, a wearable device such as an eyeglass-type display worn by the occupant, a projector, or a lamp. When the output device is a display device, the display device visually displays results obtained by various processes performed by the microcomputer 7610 or information received from other control units in various formats, such as text, images, tables, and graphs. When the output device is an audio output device, the audio output device converts audio signals, such as reproduced audio data or acoustic data, into analog signals and audibly outputs the analog signals.

[0264] In the example shown in FIG. 32 , at least two control units connected via the communication network 7010 may be integrated into a single control unit. Alternatively, each control unit may be composed of multiple control units. Furthermore, the vehicle control system 7000 may include another control unit not shown. In the above description, some or all of the functions performed by one of the control units may be performed by another control unit. In other words, as long as information is transmitted and received via the communication network 7010, predetermined arithmetic processing may be performed by one of the control units. Similarly, a sensor or device connected to one of the control units may be connected to another control unit, and multiple control units may transmit and receive detection information to and from each other via the communication network 7010.

[0265] In the vehicle control system 7000 described above, the signal processing circuit 101 according to the present embodiment described with reference to Fig. 9 can be applied to the imaging unit 7410 of the application example shown in Fig. 32. For example, by applying the signal processing circuit 101 according to the present embodiment to the image processing of the imaging unit 7410, it is possible to realize image processing calculations with low power consumption.

[0266] The present technology may be configured as follows: (1) A computing device including: a first capacitor connected between a first node and a reference voltage node; a plurality of second capacitors connected in series to a signal path between the first node and a second node; and a plurality of third capacitors, each having one end connected to a connection node between the first capacitor and the plurality of second capacitors, wherein a first digital signal determines whether a voltage corresponding to a second digital signal or a predetermined reference voltage is applied to the other end of each of the plurality of third capacitors, and the second node outputs a voltage corresponding to a multiplication result of the first digital signal and the second digital signal. (2) The computing device according to (1), wherein one end of each of two or more third capacitors is connected to each connection node on the signal path between the first node and the second capacitor adjacent to the first node, between two adjacent second capacitors, and between the second node and the second capacitor adjacent to the second node. (3) The arithmetic device according to (2), wherein the second digital signal has a plurality of bits, and each bit of the second digital signal is used to set a voltage at the other end of the two or more third capacitors at a different connection node. (4) The arithmetic device according to (3), wherein a plurality of connection nodes are provided on the signal path, and a voltage corresponding to the second digital signal or the predetermined reference voltage is applied to the other end of each of the two or more third capacitors connected to the plurality of connection nodes, depending on the corresponding bit value of the same first digital signal. (5) The arithmetic device according to any one of (2) to (4), wherein the two or more third capacitors have the same capacitance value. (6) The arithmetic device according to (5), wherein a sum of the capacitance values ​​of the two or more third capacitors is equal to the capacitance value of the first capacitor. (7) The arithmetic device according to (5) or (6), wherein the first digital signal is a thermometer code. (8) The arithmetic device according to any one of (2) to (4), wherein the third capacitors have capacitance values ​​that are one-to-one times a power of two of the capacitance value of the first capacitor.(9) The arithmetic device according to any one of (2) to (8), wherein a voltage corresponding to the same bit value of the second digital signal is applied to one end of each of the plurality of third capacitors, the other end of each of which is connected to the same connection node on the signal path, and voltages corresponding to different bit values ​​of the second digital signal are applied to the other ends of each of the plurality of third capacitors, the other ends of which are connected to different connection nodes on the signal path. (10) The arithmetic device according to (9), wherein the plurality of second capacitors have the same capacitance value. (11) The arithmetic device according to (10), wherein the capacitance value of the second capacitor is twice the capacitance value of the first capacitor. (12) The arithmetic device according to any one of (1) to (11), comprising: an array unit having a plurality of multipliers arranged in a first direction and a second direction intersecting each other, wherein each of the plurality of multipliers has the first capacitor, the plurality of second capacitors, and the plurality of third capacitors. (13) The arithmetic device according to (12), wherein the array unit has signal wiring to which the second nodes of two or more of the multipliers arranged in the first direction or the second direction are connected, and the signal wiring has a voltage corresponding to a value obtained by adding together the multiplication results of the two or more multipliers or an average value. (14) The arithmetic device according to (13), further comprising an analog-to-digital converter connected to the signal wiring and converting a voltage on the signal wiring into a digital signal. (15) The arithmetic device according to (12), wherein the array unit has signal wiring to which the second nodes of two or more of the multipliers arranged in the first direction or the second direction are connected, and further comprising: an integrator that adds up signals output to the signal wiring; and an analog-to-digital converter that converts a voltage output from the integrator into a digital signal. (16) The arithmetic device according to (14) or (15), further comprising a signal processing unit that performs predetermined signal processing based on a digital signal of a product-sum operation value obtained by adding together the multiplication results of the multiple multipliers, output from the analog-to-digital converter. (17) The arithmetic device according to (16), wherein the array section, the analog-to-digital converter, and the signal processing section are divided and arranged on two or more stacked semiconductor substrates.(18) The arithmetic device according to any one of (12) to (17), further comprising: a storage unit that stores at least one of the first digital signal and the second digital signal, and the plurality of multipliers read out at least one of the first digital signal and the second digital signal stored in the storage unit and perform multiplication. (19) The arithmetic device according to any one of (1) to (18), further comprising: a capacitance initialization circuit that initializes accumulated charges of the plurality of third capacitors before multiplication of the first digital signal and the second digital signal. (20) A signal processing device comprising: an arithmetic unit; and an imaging unit that outputs captured image data, wherein the arithmetic unit has: a first capacitor connected between a first node and a reference voltage node, a plurality of second capacitors connected in series to a signal path between the first node and a second node, and a plurality of third capacitors, one end of each of which is connected to a connection node between the first capacitor and the plurality of second capacitors, wherein a first digital signal is used to set whether to apply a voltage corresponding to a second digital signal or a predetermined reference voltage to the other end of each of the plurality of third capacitors, wherein the second node outputs a voltage corresponding to a multiplication result of the first digital signal and the second digital signal, and at least one of the first digital signal and the second digital signal is a signal based on the image data. (21) A signal processing circuit comprising: an analog arithmetic circuit that performs first processing to convert the first digital signal into a first analog signal, and second processing to change the second analog signal, which corresponds to the multiplication value of the converted first analog signal and the second digital signal, based on a third digital signal for setting a gain, to generate the third analog signal. (22) The signal processing circuit according to (21), comprising: a plurality of the analog arithmetic circuits each performing the first processing and the second processing separately; a signal line for transmitting a fourth analog signal having a signal level obtained by adding together the second analog signals or the third analog signals output from each of the analog arithmetic circuits; and an analog-to-digital conversion circuit for converting the fourth analog signal after the second processing into a fourth digital signal.(23) The signal processing circuit according to (22), wherein the second processing includes a third processing of simultaneously lowering a voltage level on the signal line based on the plurality of first analog signals, and a fourth processing of, after the third processing, gradually raising the voltage of the signal line based on each of the plurality of third digital signals to generate the fourth analog signal. (24) The signal processing circuit according to (23), further comprising a control circuit that controls the plurality of analog arithmetic circuits, wherein the control circuit causes the plurality of analog arithmetic circuits to perform the first processing and the third processing in parallel and causes the plurality of analog arithmetic circuits to perform the fourth processing sequentially. (25) The signal processing circuit according to (24), wherein the control circuit initializes the plurality of fourth analog signals output from the plurality of analog arithmetic circuits to a predetermined voltage level before starting a new multiplication of the first digital signal and the second digital signal. (26) The signal processing circuit according to any one of (22) to (25), wherein each of the plurality of analog arithmetic circuits includes two or more first capacitors that accumulate charge according to the first digital signal, and a switch that switches between connecting the two or more first capacitors in parallel, or charging or discharging one or more of the two or more first capacitors according to the first digital signal and leaving the remaining first capacitors in a floating state. (27) The signal processing circuit according to (26), wherein each of the plurality of analog arithmetic circuits includes a plurality of second capacitors that are connected in series and each output a voltage that is one divided by a power of two, and includes a ladder multiplication circuit having one end connected to the signal line. (28) The signal processing circuit according to (27), wherein the two or more first capacitors are connected between two adjacent second capacitors among the plurality of second capacitors, the two or more first capacitors have the same capacitance, and each of the plurality of second capacitors has a capacitance that is at least twice that of the first capacitor.(29) The signal processing circuit according to (26), comprising a plurality of capacitor groups each having the two or more first capacitors, wherein one end of each of the two or more first capacitors in each of the plurality of capacitor groups is connected to the signal line, the two or more first capacitors in each of the plurality of capacitor groups have the same capacitance, and the capacitances of the two or more first capacitors in each of the plurality of capacitor groups differ by powers of 2. (30) The signal processing circuit according to any one of (26) to (29), comprising a memory unit that stores the second digital signal, and wherein at least some of the capacitors including the first capacitors included in the plurality of analog arithmetic circuits are arranged on a second layer different from a first layer on which the memory unit is arranged. (31) The signal processing circuit according to (30), wherein at least some of the capacitors including the first capacitor included in the plurality of analog arithmetic circuits have a plurality of wiring layers arranged on the second layer, and an insulating layer arranged between the plurality of wiring layers. (32) The signal processing circuit according to any one of (22) to (31), wherein each of the plurality of analog arithmetic circuits extends in a first direction and comprises an array unit having the plurality of analog arithmetic circuits arranged in a second direction intersecting the first direction. (33) The signal processing circuit according to (32), wherein the plurality of array units are arranged in at least one of the first direction or the second direction, and the plurality of array units have the same number of the plurality of analog arithmetic circuits, or at least some of the plurality of array units have a different number of the plurality of analog arithmetic circuits from the remaining array units. (34) The signal processing circuit according to any one of (22) to (33), wherein the analog-to-digital conversion circuit has a comparison circuit that determines whether the fourth analog signal on the signal line exceeds a predetermined threshold. (35) The signal processing circuit according to (34), wherein the analog-to-digital conversion circuit has a counter that counts from the start of an analog-to-digital conversion operation until the comparison circuit determines that the predetermined threshold has been exceeded, and outputs the fourth digital signal according to the count value of the counter.(36) The signal processing circuit according to (35), wherein a period during which each of the plurality of analog arithmetic circuits sequentially performs the second processing to change the voltage level of the signal line is the same as or different from a count period of the counter. (37) The signal processing circuit according to any one of (22) to (36), wherein the voltage level of the signal line changed by each of the plurality of analog arithmetic circuits through the second processing is determined by the third digital signal. (38) The signal processing circuit according to any one of (22) to (37), comprising a nonlinear arithmetic circuit that performs nonlinear arithmetic processing on the fourth digital signal output from the analog-to-digital conversion circuit. (39) The signal processing circuit according to (38), wherein the nonlinear arithmetic circuit outputs the fourth digital signal as is if the fourth digital signal has a positive value, and outputs 0 if the fourth digital signal has a negative value. (40) The signal processing circuit according to any one of (22) to (39), comprising a monitor circuit that monitors the voltage level of the signal line.

[0267] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0268] 1, 90 Multiplier, 2 Product-sum array unit, 3 Analog-to-digital converter, 4 Signal processing unit, 5 Memory unit, 6 Integrator, 7 Gain calculator, 10, 10a, 10b, 80 Arithmetic unit, 11 First capacitor, 12 Second capacitor, 13, 13a, 13b, 13c Capacitance selection unit, 14, 14a Third capacitor, 15, 92 Inverter, 18 Capacitance initialization circuit, 16, 17, 19 Transistor, 21 Signal wiring, 22, 91 Capacitor, 23 Switch, 24 Amplifier, 30 Signal processing device, 31, 32, 32a, 32b Substrate, 33 Light receiving unit, 34 Image processing unit, 81 Digital-to-analog converter, 101, 920 Signal processing circuit, 102 Analog calculation circuit, 103 Control circuit, 104 Memory circuit, 105 Comparison circuit, 106 Latch circuit, 107, 903 DAC, 107a First DAC processing unit, 107b Second DAC processing unit, 108, 108c Ladder multiplier, 108a, 108b Area, 110, 110a, 110b Array unit, 111, 923 ADC, 112 Nonlinear arithmetic unit, 121 Counter, 122 Comparison bias circuit, 123 Selection switch, 124 Test circuit, 125 Nonlinear arithmetic control circuit, 130, 151a, 151b, 191, 902 Switch, 131a, 131b, 132a, 132b, 133a, 133b, 171, 172, 173 Logic circuit, 134a, 134b Inverters, 141a, 141b, 141c, 141d, 141e, 141f, 141g, 141h, 142, 143, 210, 211, 901: Capacitor, 144: Multiplexer, 144a: First multiplexer, 144b: Second multiplexer, 145, 152a, 152b, 181, 182, 183, 184, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 222, 223, 224, 225, 226, 227: Transistor, 146: Signal path, 146a: Wiring layer, 147 Bit multiplication unit, 161 logic circuit, 162 gain memory circuit, 163 weighting coefficient memory circuit, 164 output circuit, 170 memory element, 221 transfer gate, 230 insulating layer, 240 capacitor group, 900 multiplier, 921 product-sum calculation circuit, 922 gain setting circuit

Claims

1. An arithmetic device comprising: a first capacitor connected between a first node and a reference voltage node; a plurality of second capacitors connected in series to a signal path between the first node and a second node; and a plurality of third capacitors, one end of each of which is connected to a connection node between the first capacitor and each of the plurality of second capacitors; wherein a first digital signal is used to determine whether a voltage corresponding to a second digital signal or a predetermined reference voltage is applied to the other end of each of the plurality of third capacitors; and the second node outputs a voltage corresponding to a result of multiplication of the first digital signal and the second digital signal.

2. The arithmetic device according to claim 1, wherein one end of each of two or more of the third capacitors is connected to each of connection nodes on the signal path between the first node and the second capacitor adjacent to the first node, between two adjacent second capacitors, and between the second node and the second capacitor adjacent to the second node.

3. The arithmetic device according to claim 2, wherein the second digital signal has a plurality of bits, and each bit of the second digital signal is used to set a voltage at the other end of each of the two or more third capacitors at a different connection node.

4. The arithmetic device according to claim 3, wherein a plurality of said connection nodes are provided on said signal path, and a voltage corresponding to said second digital signal or said predetermined reference voltage is applied to the other end of each of said two or more third capacitors connected to each of said plurality of connection nodes, depending on a corresponding bit value of the same said first digital signal.

5. The arithmetic device according to claim 2, wherein the two or more third capacitors have the same capacitance value, and a sum of the capacitance values ​​of the two or more third capacitors is equal to the capacitance value of the first capacitor.

6. The arithmetic device according to claim 2, wherein the third capacitors have capacitance values ​​that are each a power of two divided by a capacitance value of the first capacitor.

7. The arithmetic device according to claim 2, wherein a voltage corresponding to the same bit value of the second digital signal is applied to the other ends of the plurality of third capacitors, each having one end connected to the same connection node on the signal path, and voltages corresponding to different bit values ​​of the second digital signal are applied to the other ends of the plurality of third capacitors, each having one end connected to different connection nodes on the signal path.

8. The arithmetic device according to claim 7, wherein the plurality of second capacitors have the same capacitance value, and the capacitance value of the second capacitor is twice the capacitance value of the first capacitor.

9. The arithmetic device according to claim 1, comprising an array section having a plurality of multipliers arranged in a first direction and a second direction intersecting each other, each of the plurality of multipliers having the first capacitor, the plurality of second capacitors, and the plurality of third capacitors.

10. A signal processing device comprising: an arithmetic unit; and an imaging unit that outputs captured image data, wherein the arithmetic unit has a first capacitor connected between a first node and a reference voltage node, a plurality of second capacitors connected in series to a signal path between the first node and a second node, and a plurality of third capacitors, each having one end connected to a connection node of the first capacitor and the plurality of second capacitors, wherein a first digital signal determines whether a voltage corresponding to a second digital signal or a predetermined reference voltage is applied to the other end of each of the plurality of third capacitors, wherein the second node outputs a voltage corresponding to a multiplication result of the first digital signal and the second digital signal, and at least one of the first digital signal and the second digital signal is a signal based on the image data.

11. A signal processing circuit comprising an analog arithmetic circuit that performs a first process of converting a first digital signal into a first analog signal, and that performs a second process of changing a second analog signal corresponding to a multiplied value of the converted first analog signal and a second digital signal based on a third digital signal for gain setting, to generate a third analog signal.

12. The signal processing circuit according to claim 11, comprising: a plurality of said analog arithmetic circuits each performing said first processing and said second processing separately; a signal line for transmitting a fourth analog signal having a signal level obtained by adding together a plurality of said second analog signals or a plurality of said third analog signals output from each of said plurality of analog arithmetic circuits; and an analog-to-digital conversion circuit for converting said fourth analog signal after said second processing into a fourth digital signal.

13. The signal processing circuit of claim 12, wherein the second processing includes a third processing for simultaneously lowering a voltage level on the signal line based on a plurality of the first analog signals, and a fourth processing for, after the third processing, gradually raising the voltage of the signal line based on each of a plurality of the third digital signals to generate the fourth analog signal.

14. The signal processing circuit according to claim 13, further comprising a control circuit for controlling said plurality of analog arithmetic circuits, said control circuit causing said plurality of analog arithmetic circuits to perform said first processing and said third processing in parallel, and causing said plurality of analog arithmetic circuits to perform said fourth processing sequentially.

15. The signal processing circuit according to claim 12, wherein each of the plurality of analog arithmetic circuits comprises: two or more first capacitors that accumulate electric charge according to the first digital signal; and a switch that switches between connecting the two or more first capacitors in parallel, or charging or discharging one or more of the two or more first capacitors according to the first digital signal, and leaving the remaining first capacitors in a floating state.

16. The signal processing circuit according to claim 15, wherein each of the plurality of analog arithmetic circuits has a plurality of second capacitors connected in series, each of which outputs a voltage that is one divided by a power of two, and also has a ladder multiplication circuit having one end connected to the signal line.

17. The signal processing circuit according to claim 16, wherein the two or more first capacitors are connected between two adjacent second capacitors among the plurality of second capacitors, the two or more first capacitors have the same capacitance, and each of the plurality of second capacitors has a capacitance at least twice that of the first capacitor.

18. The signal processing circuit according to claim 15, comprising a plurality of capacitor groups each having the two or more first capacitors, one end of each of the two or more first capacitors in each of the plurality of capacitor groups is connected to the signal line, the two or more first capacitors in each of the plurality of capacitor groups have the same capacitance, and the capacitances of the two or more first capacitors in each of the plurality of capacitor groups differ by a power of two.

19. The signal processing circuit according to claim 12, wherein the analog-to-digital conversion circuit has a comparison circuit that determines whether or not the fourth analog signal on the signal line has exceeded a predetermined threshold value, and a counter that performs a counting operation from when an analog-to-digital conversion operation starts until the comparison circuit determines that the predetermined threshold value has been exceeded, and outputs the fourth digital signal according to the count value of the counter.

20. The signal processing circuit according to claim 12, wherein the voltage level of the signal line that each of the plurality of analog arithmetic circuits changes through the second processing is determined by the third digital signal.

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