Driving substrate and display panel

Abstract

The embodiments of the present application disclose a driving substrate and a display panel. A transition part of an active layer is arranged between a first contact part and a channel of the active layer, a first part of a gate overlapping the channel, and a second part of the gate overlapping the transition part; the first part of the gate is used for completely blocking doping ions, and the second part of the gate is used for transmitting some of the doping ions; a first electrode is connected to the first contact part, and a second electrode is connected to the second contact part.

Description

Drive substrate and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving substrate and a display panel. Background Art

[0002] Thin film transistors (TFTs) are widely used in liquid crystal display devices, organic light emitting diode display devices, and the like. In addition, they can also be used in micro LED display devices, electronic paper, and the like.

[0003] In a TFT, a high electric field is generated between the channel and drain regions, generating hot carriers in this region. This hot carrier effect causes fluctuations in the TFT's threshold voltage (Vth). This phenomenon can be mitigated by creating a lightly doped drain (LDD) region, which creates a resistive transition between the channel and drain regions.

[0004] During research and practice on existing technologies, the inventors of this application discovered that in top-gate TFTs, the top gate is typically used as a mask, the source and drain regions are formed by plasma treatment of an oxide semiconductor, and the LDD region is formed by contacting a SiN film. In other words, the channel length is determined by the length of the top gate. SUMMARY OF THE INVENTION

[0005] Embodiments of the present application provide a driving substrate and a display panel, which can narrow the channel length of the active layer.

[0006] The embodiment of the present application provides a driving substrate, which includes:

[0007] substrate;

[0008] A thin film transistor structure, wherein the thin film transistor structure is disposed on the substrate, and the thin film transistor structure comprises:

[0009] an active layer, the active layer being disposed on the substrate, the active layer comprising a first contact portion, a transition portion, a channel, and a second contact portion, the transition portion being disposed between the first contact portion and the channel, the second contact portion being disposed on a side of the channel away from the first contact portion, the resistance value of the first contact portion being smaller than the resistance value of the transition portion, and the resistance value of the transition portion being smaller than the resistance value of the channel;

[0010] a gate insulating layer, the gate insulating layer being disposed on the active layer;

[0011] a gate, the gate being disposed on the gate insulating layer, the gate comprising a first portion and a second portion connected to the first portion, the first portion being overlapped with the channel, the second portion being overlapped with the transition portion, the first portion being configured to completely block dopant ions, and the second portion being configured to partially transmit the dopant ions;

[0012] A first electrode and a second electrode, the first electrode is connected to the first contact portion, and the second electrode is connected to the second contact portion.

[0013] Optionally, in some embodiments of the present application, the density of the first part is greater than the density of the second part.

[0014] Optionally, in some embodiments of the present application, the thickness of the first part is greater than the thickness of the second part.

[0015] Optionally, in some embodiments of the present application, the gate is a single-film structure.

[0016] Optionally, in some embodiments of the present application, the gate includes a first metal layer and a second metal layer, the first metal layer is arranged on the gate insulating layer, the first metal layer blocks the channel and the transition portion, and the second metal layer is arranged on a side of the first metal layer away from the gate insulating layer, the second metal layer blocks the channel.

[0017] Optionally, in some embodiments of the present application, the thickness of the first metal layer is less than the thickness of the second metal layer.

[0018] Optionally, in some embodiments of the present application, the gate includes a first metal layer and a second metal layer, the first metal layer is arranged on the gate insulating layer, the first metal layer only blocks the channel, and the second metal layer is arranged on a side of the first metal layer away from the gate insulating layer, the second metal layer blocks the channel and the transition portion.

[0019] Optionally, in some embodiments of the present application, the thickness of the first portion is greater than or equal to 250 nanometers, and the thickness of the second portion is less than or equal to 100 nanometers and greater than or equal to 10 nanometers.

[0020] Optionally, in some embodiments of the present application, the mass ratio of the doping ions in the first contact portion is greater than the mass ratio of the doping ions in the transition portion.

[0021] Optionally, in some embodiments of the present application, the first electrode is used to connect the light-emitting device, the channel is directly connected to the second contact portion, or another transition portion is connected between the channel and the second contact portion.

[0022] Accordingly, an embodiment of the present application further provides a display panel, comprising the driving substrate described in any one of the above embodiments and a light-emitting device disposed on the driving substrate, wherein the driving substrate comprises:

[0023] substrate;

[0024] A thin film transistor structure, wherein the thin film transistor structure is disposed on the substrate, and the thin film transistor structure comprises:

[0025] an active layer, the active layer being disposed on the substrate, the active layer comprising a first contact portion, a transition portion, a channel, and a second contact portion, the transition portion being disposed between the first contact portion and the channel, the second contact portion being disposed on a side of the channel away from the first contact portion, the resistance value of the first contact portion being smaller than the resistance value of the transition portion, and the resistance value of the transition portion being smaller than the resistance value of the channel;

[0026] a gate insulating layer, the gate insulating layer being disposed on the active layer;

[0027] a gate, the gate being disposed on the gate insulating layer, the gate comprising a first portion and a second portion connected to the first portion, the first portion being overlapped with the channel, the second portion being overlapped with the transition portion, the first portion being configured to completely block dopant ions, and the second portion being configured to partially transmit the dopant ions;

[0028] A first electrode and a second electrode, the first electrode is connected to the first contact portion, and the second electrode is connected to the second contact portion.

[0029] Optionally, in some embodiments of the present application, the density of the first part is greater than the density of the second part.

[0030] Optionally, in some embodiments of the present application, the thickness of the first part is greater than the thickness of the second part.

[0031] Optionally, in some embodiments of the present application, the gate is a single-film structure.

[0032] Optionally, in some embodiments of the present application, the gate includes a first metal layer and a second metal layer, the first metal layer is arranged on the gate insulating layer, the first metal layer blocks the channel and the transition portion, and the second metal layer is arranged on a side of the first metal layer away from the gate insulating layer, the second metal layer blocks the channel.

[0033] Optionally, in some embodiments of the present application, the thickness of the first metal layer is less than the thickness of the second metal layer.

[0034] Optionally, in some embodiments of the present application, the gate includes a first metal layer and a second metal layer, the first metal layer is arranged on the gate insulating layer, the first metal layer only blocks the channel, and the second metal layer is arranged on a side of the first metal layer away from the gate insulating layer, the second metal layer blocks the channel and the transition portion.

[0035] Optionally, in some embodiments of the present application, the thickness of the first portion is greater than or equal to 250 nanometers, and the thickness of the second portion is less than or equal to 100 nanometers and greater than or equal to 10 nanometers.

[0036] Optionally, in some embodiments of the present application, the mass ratio of the doping ions in the first contact portion is greater than the mass ratio of the doping ions in the transition portion.

[0037] Optionally, in some embodiments of the present application, the first electrode is used to connect the light-emitting device, the channel is directly connected to the second contact portion, or another transition portion is connected between the channel and the second contact portion. Beneficial effects

[0038] An embodiment of the present application provides a driving substrate, comprising a substrate and a thin-film transistor structure, the thin-film transistor structure being disposed on the substrate and comprising an active layer, a gate insulating layer, a gate, a first electrode, and a second electrode. The active layer is disposed on the substrate and comprises a first contact portion, a transition portion, a channel, and a second contact portion, the transition portion being disposed between the first contact portion and the channel, the second contact portion being disposed on a side of the channel away from the first contact portion, the resistance of the first contact portion being smaller than the resistance of the transition portion, and the resistance of the transition portion being smaller than the resistance of the channel; the gate insulating layer being disposed on the active layer; the gate being disposed on the gate insulating layer and comprising a first portion and a second portion connected to the first portion, the first portion being disposed overlapping the channel, the second portion being disposed overlapping the transition portion, the first portion being configured to completely block dopant ions, and the second portion being configured to partially transmit the dopant ions; the first electrode being connected to the first contact portion, and the second electrode being connected to the second contact portion.

[0039] This embodiment uses a first portion of the gate to block the channel, while a second portion blocks the transition portion. This allows some dopant ions to penetrate through the second portion and enter the transition portion during ion implantation, while the dopant ions corresponding to the channel region are completely blocked by the first portion. Therefore, this embodiment uses the gate as a mask to achieve doping of the transition portion below the mask. Compared to existing techniques using the gate as a mask, this embodiment can achieve a narrower channel and improve the stability of the thin-film transistor threshold voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a schematic structural diagram of a drive substrate provided in a first embodiment of the present application;

[0041] FIG2 is a schematic diagram of step B12 of the method for preparing a drive substrate provided in the first embodiment of the present application;

[0042] 3 is a schematic diagram of step B13 of the method for preparing a drive substrate provided in the first embodiment of the present application;

[0043] FIG4 is a schematic structural diagram of a drive substrate provided in a second embodiment of the present application;

[0044] FIG5 is a schematic structural diagram of a drive substrate provided in a third embodiment of the present application;

[0045] FIG6 is a schematic structural diagram of a drive substrate provided in a fourth embodiment of the present application;

[0046] FIG7 is a schematic structural diagram of a drive substrate provided in a fifth embodiment of the present application;

[0047] FIG8 is a schematic structural diagram of a display panel provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0048] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0049] The embodiments of the present application provide a drive substrate and a display panel. It should be noted that the drive substrate can be used in liquid crystal display panels, organic light-emitting diode display panels, micro-light-emitting diode display panels, or electronic paper, among others. This is described in detail below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments.

[0050] 1 , a first embodiment of the present application provides a driving substrate 100 , which includes a substrate 11 and a thin film transistor structure 12 . The thin film transistor structure 12 is disposed on the substrate 11 .

[0051] The thin film transistor structure 12 includes an active layer 121 , a gate insulating layer 122 , a gate 123 , a first electrode 124 and a second electrode 125 .

[0052] Active layer 121 is disposed on substrate 11. Active layer 121 includes a first contact portion 12a, a transition portion 12b, a channel 12c, and a second contact portion 12d. Transition portion 12b is disposed between first contact portion 12a and channel 12c. Second contact portion 12d is disposed on a side of channel 12c away from first contact portion 12a. The resistance of first contact portion 12a is lower than that of transition portion 12b. The resistance of transition portion 12b is lower than that of channel 12c.

[0053] The gate insulating layer 122 is disposed on the active layer 121 . The gate 123 is disposed on the gate insulating layer 122 .

[0054] The gate 123 includes a first portion g1 and a second portion g2 connected to the first portion g1. The first portion g1 overlaps the channel 12c. The second portion g2 overlaps the transition portion 12b. The first portion g1 is configured to completely block dopant ions. The second portion g2 is configured to partially transmit the dopant ions.

[0055] The first electrode 124 is connected to the first contact portion 12a, and the second electrode 125 is connected to the second contact portion 12d.

[0056] In this embodiment, the first portion g1 of the gate 123 shields the channel 12c, while the second portion g2 shields the transition portion 12b. This allows some dopant ions to penetrate through the second portion g2 and enter the transition portion 12b during ion implantation, while the dopant ions corresponding to the channel 12c region are completely blocked by the first portion g1. Therefore, this embodiment uses the gate 123 as a mask to achieve doping of the transition portion 12b below the mask. Compared to existing techniques using the gate as a mask, this embodiment allows the channel 12c to be narrower, thereby improving the stability of the thin-film transistor threshold voltage.

[0057] Optionally, in the first embodiment, the thickness of the first portion g1 is greater than the thickness of the second portion g2. It is understood that as the thickness of the film increases, the film's ability to block dopant ions improves. Therefore, in this embodiment, the thinner second portion g2 can achieve sub-film ion doping, while the thicker first portion g1 can completely block dopant ions.

[0058] Optionally, the gate 123 is a single-layer structure.

[0059] It should be noted that the gate 123 is a single-layer structure, and the first portion g1 and the second portion g2 can be made of the same material or different materials.

[0060] When the first portion g1 and the second portion g2 of the gate 123 are made of the same material, the first portion g1 and the second portion g2 can be formed using a halftone or grayscale mask. The gate 123 of the first embodiment has a single-layer structure, which simplifies the manufacturing process of the gate 123.

[0061] When the first portion g1 and the second portion g2 of the gate 123 are made of different materials, the first portion g1 and the second portion g2 are formed separately.

[0062] Optionally, the thickness of the first portion g1 is greater than or equal to 250 nanometers, and the thickness of the second portion g2 is less than or equal to 100 nanometers and greater than or equal to 10 nanometers.

[0063] It is understood that in driver substrates used in panels, the gate 123 is typically fabricated using physical vapor deposition (PVD), resulting in a relatively high density. Therefore, in typical manufacturing processes, when the thickness of the first portion g1 is greater than 250 nanometers, dopant ions can be prevented from penetrating through the first portion g1. A thickness of the second portion g2 of less than 100 nanometers ensures dopant ion penetration and improves doping efficiency. A thickness of the second portion g2 of greater than 10 nanometers prevents the resistance of the transition portion 12b from becoming too low and converging with the first contact portion 12a. Consequently, when the resistance of the transition portion 12b converges with that of the first contact portion 12a, the stability of the thin-film transistor threshold voltage is reduced.

[0064] Alternatively, the thickness of the first portion g1 may be 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, or 1000 nm. The thickness of the second portion g2 may be 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, 30 nm, 20 nm, or 10 nm.

[0065] Optionally, the material of the gate 123 can be copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), nickel (Ni), zinc (Zn), chromium (Cr), an alloy containing any of the above metals, or an alloy combining any of the above metals.

[0066] Optionally, the gate insulating layer 122 is formed of a plurality of inorganic layers stacked in an alternating manner. For example, the gate insulating layer 122 may be formed as a double layer formed by stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide, or as a multilayer formed by alternatingly stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide. However, the present disclosure is not limited thereto, and the gate insulating layer 122 may be formed as a single inorganic layer including the above-mentioned insulating materials.

[0067] Alternatively, the material of the active layer 121 may be formed of single crystal silicon, polycrystalline silicon (poly-Si), or an oxide semiconductor. The oxide semiconductor may include an oxide based on titanium, hafnium, zirconium, aluminum, tantalum, germanium, zinc, gallium, tin, or indium, and a composite oxide thereof (such as indium gallium zinc oxide, indium zinc oxide, zinc tin oxide, indium gallium oxide, indium tin oxide, indium zirconium oxide, indium zirconium zinc oxide, indium zirconium tin oxide, indium zirconium gallium oxide, indium aluminum oxide, indium zinc aluminum oxide, indium tin aluminum oxide, indium aluminum gallium oxide, indium tantalum oxide, indium tantalum zinc oxide, indium tantalum tin oxide, indium tantalum gallium oxide, indium germanium oxide, indium germanium zinc oxide, indium germanium tin oxide, indium germanium gallium oxide, titanium indium zinc oxide, and hafnium indium zinc oxide).

[0068] Optionally, the mass ratio of the doping ions in the first contact portion 12a is greater than the mass ratio of the doping ions in the transition portion 12b. This configuration makes the resistance value of the first contact portion 12a smaller than the resistance value of the transition portion 12b.

[0069] In addition, the mass ratio of the doping ions in the second contact portion 12 d is greater than the mass ratio of the doping ions in the transition portion 12 b , so that the resistance value of the second contact portion 12 d is smaller than the resistance value of the transition portion 12 b .

[0070] Optionally, in the first embodiment, the first electrode 124 is used to connect the light-emitting device, and the channel 12c is directly connected to the second contact portion 12d.

[0071] Optionally, the driving substrate 100 may further include a buffer layer 126 , which is disposed between the active layer 121 and the substrate 11 .

[0072] Optionally, the drive substrate 100 may further include an interlayer dielectric layer 127 and a passivation layer 128. The interlayer dielectric layer 127 covers the gate 123, the active layer 121, and the substrate 11. A first electrode 124 and a second electrode 125 are disposed on the interlayer dielectric layer 127. The first electrode 124 is connected to the first contact portion 12a, and the second electrode 125 is connected to the second contact portion 12d. The passivation layer 128 covers the first electrode 124 and the second electrode 125.

[0073] In some embodiments, the driving substrate 100 may also omit the interlayer dielectric layer 127 , that is, the first electrode 124 is directly formed on the first contact portion 12 a , and the second electrode 125 is directly formed on the second contact portion 12 d .

[0074] The manufacturing process of the driving substrate 100 of the first embodiment is as follows:

[0075] In step B11 , a buffer layer 126 , a semiconductor layer 12 k , a gate insulating layer 122 and a gate 123 are sequentially formed on the substrate 11 .

[0076] The first portion g1 and the second portion g2 are formed using a halftone mask. The thickness of the first portion g1 is greater than that of the second portion g2. The semiconductor layer 12k includes a channel region corresponding to the first portion g1, a transition portion corresponding to the second portion g2, and a first electrode region and a second electrode region exposed outside the gate 123.

[0077] Then go to step B12.

[0078] Referring to FIG. 2 , step B12, the first and second electrode regions of the semiconductor layer 12k are subjected to a conductorization process using the gate electrode 123 as a mask. Optionally, the first and second electrode regions of the semiconductor layer 12k can be bombarded with Ar to form a high concentration of oxygen vacancies, thereby achieving conductorization. In this case, the sheet resistance of the first and second electrode regions of the semiconductor layer 12k is between 300 ohms and 3000 ohms, for example, 300 ohms, 1000 ohms, 2000 ohms, or 3000 ohms.

[0079] Then go to step B13.

[0080] 3 , step B13 , continuing to use the gate 123 as a mask, ion implantation is performed on the first electrode region, the second electrode region, and the transition region of the semiconductor layer 12 k to form the first contact portion 12 a , the via portion 12 b , the channel 12 c , and the second contact portion 12 d .

[0081] Optionally, the doping ions may be B or P, etc. The doping concentration is between E17 and E22, for example, E17, E18, E19, E20, E21 or E22.

[0082] Then, the process proceeds to step B14 , where a first electrode 124 and a second electrode 125 are formed on the substrate. The first electrode 124 is connected to the first contact portion 12 a , and the second electrode 125 is connected to the second contact portion 12 d .

[0083] This completes part of the preparation process of the driving substrate 100 of the first embodiment.

[0084] 4 , the driving substrate 100 of the second embodiment is different from that of the first embodiment in that another transition portion 12 b is connected between the trench 12 c and the second contact portion 12 d .

[0085] That is, compared with the driving substrate 100 of the first embodiment, the gate 123 of the driving substrate 100 of the second embodiment has two second portions g2 to cover the two transition portions 12 b in a one-to-one correspondence.

[0086] Compared with the first embodiment, the second embodiment adopts two transition portions 12 b to further narrow the length of the channel 12 c and improve the stability of the threshold voltage of the thin film transistor.

[0087] 5 , the driving substrate 100 of the third embodiment is different from any of the above embodiments in that the density of the first portion g1 is greater than the density of the second portion g2 .

[0088] Optionally, the thickness of the first portion g1 may be equal to the thickness of the second portion g2. The density of the film layer can be adjusted by adjusting the parameters of the vapor deposition process, such as the bombardment energy or the deposition rate, etc., which will not be elaborated here.

[0089] Referring to FIG. 6 , the drive substrate 100 of the fourth embodiment differs from any of the above embodiments in that the gate 123 includes a first metal layer 23a and a second metal layer 23b. The first metal layer 23a is disposed on the gate insulating layer 122. The first metal layer 23a shields the channel 12c and the transition portion 12b. The second metal layer 23b is disposed on a side of the first metal layer 23a away from the gate insulating layer 122. The second metal layer 23b shields the channel 12c.

[0090] Optionally, the first metal layer 23 a is disposed between the second metal layer 23 b and the gate insulating layer 122 , thereby improving adhesion between the gate 123 and the gate insulating layer 122 .

[0091] Optionally, the thickness of the first metal layer 23a is less than the thickness of the second metal layer 23b. Within a certain thickness limit, since the conductivity of the first metal layer 23a is less than that of the second metal layer 23b, providing a thicker second metal layer 23b can increase the conductivity of the gate 123 and improve the effect of the first portion g1 in blocking the penetration of dopant ions. Providing a thinner first metal layer 23a to allow some dopant ions to pass through, and the larger area of ​​the first metal layer 23a, can meet the requirement of improving the adhesion of the gate 123.

[0092] Optionally, the first metal layer 23a includes at least one of molybdenum and titanium, and the second metal layer 23b includes at least one of copper and aluminum.

[0093] For example, when the material of the first metal layer 23a is titanium or molybdenum-titanium alloy, the thickness of the first metal layer 23a may be between 10 nanometers and 50 nanometers, such as 10 nanometers, 20 nanometers, 30 nanometers, 40 nanometers or 50 nanometers.

[0094] When the second metal layer 23b is made of copper or aluminum, the thickness of the second metal layer 23b is between 350 nanometers and 1000 nanometers, for example, 350 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers, 800 nanometers, 900 nanometers, or 1000 nanometers. If the second metal layer 23b is densified using a strengthening process, the required thickness of the second metal layer 23b can be further reduced. Furthermore, the thickness of the second metal layer 23b is less than 1000 nanometers to prevent the gate 123 from being too thick, which would result in an excessively high ground surface.

[0095] In some embodiments, the gate 123 may also be a three-layer stacked structure, such as Ti / Al / Ti, Mo / Al / Mo, Ti / Cu / Ti, Mo / Cu / Mo, Mo&Ti / Al / Mo&Ti, or Mo&Ti / Cu / Mo&Ti.

[0096] Referring to FIG. 7 , the drive substrate 100 of the fifth embodiment differs from any of the aforementioned embodiments in that the gate 123 includes a first metal layer 23a and a second metal layer 23b. The first metal layer 23a is disposed on the gate insulating layer 122. The first metal layer 23a only blocks the channel 12c. The second metal layer 23b is disposed on a side of the first metal layer 23a away from the gate insulating layer 122. The second metal layer 23b blocks the channel 12c and the transition portion 12b.

[0097] This embodiment uses a multi-layer gate 123 to facilitate controlling the thickness of the first portion g1 and the second portion g2 , thereby achieving precise control of the resistance value of the transition portion 12 b .

[0098] It should be noted that, in this embodiment, the thickness of the first metal layer 23 a should not be too large, as a too large thickness may lead to the risk of the second metal layer 23 b covering the first metal layer 23 a being broken.

[0099] Please refer to FIG. 8 . Accordingly, the embodiment of the present application further provides a display panel 1000 , which includes the driving substrate 100 according to any one of the above embodiments.

[0100] Optionally, the display panel 1000 may be a liquid crystal display panel, an organic light emitting diode display panel, a micro light emitting diode display panel, or a quantum dot light emitting diode display panel.

[0101] As shown in FIG8 , this embodiment is illustrated by taking the display panel 1000 as a micro light emitting diode panel as an example.

[0102] The display panel 1000 further includes a light emitting device 200 disposed on the driving substrate 100 .

[0103] The structure of the driving substrate 100 of the display panel 1000 of this embodiment is similar to or the same as the structure of the driving substrate 100 of any of the above embodiments, and will not be described in detail here.

[0104] In the display panel 1000 of this embodiment, the first portion g1 of the gate 123 shields the channel 12c, while the second portion g2 shields the transition portion 12b. This allows some dopant ions to penetrate through the second portion g2 and enter the transition portion 12b during ion implantation, while the dopant ions corresponding to the channel 12c region are completely blocked by the first portion g1. Therefore, this embodiment uses the gate 123 as a mask to achieve doping of the transition portion 12b below the mask. Compared to conventional techniques that use the gate as a mask, this embodiment allows the channel 12c to be narrower, thereby improving the stability of the thin-film transistor threshold voltage.

[0105] The above is a detailed introduction to a driving substrate and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A driving substrate, comprising: substrate; A thin film transistor structure, wherein the thin film transistor structure is disposed on the substrate, and the thin film transistor structure comprises: an active layer, the active layer being arranged on the substrate, the active layer comprising a first contact portion, a transition portion, a channel, and a second contact portion, the transition portion being arranged between the first contact portion and the channel, the second contact portion being arranged on a side of the channel away from the first contact portion, the resistance value of the first contact portion being smaller than the resistance value of the transition portion, and the resistance value of the transition portion being smaller than the resistance value of the channel; a gate insulating layer, the gate insulating layer being disposed on the active layer; A gate, the gate being disposed on the gate insulating layer, the gate comprising a first portion and a second portion connected to the first portion, the first portion being overlapped with the channel, the second portion being overlapped with the transition portion, the first portion being used to completely block doping ions, and the second portion being used to partially transmit the doping ions; A first electrode and a second electrode, wherein the first electrode is connected to the first contact portion, and the second electrode is connected to the second contact portion.

2. The driving substrate according to claim 1, wherein: The density of the first portion is greater than the density of the second portion.

3. The driving substrate according to claim 2, wherein: The thickness of the first portion is greater than the thickness of the second portion.

4. The driving substrate according to claim 3, wherein: The gate is a single-layer structure.

5. The driving substrate according to claim 3, wherein: The gate includes a first metal layer and a second metal layer, the first metal layer is arranged on the gate insulating layer, the first metal layer blocks the channel and the transition portion, and the second metal layer is arranged on a side of the first metal layer away from the gate insulating layer, the second metal layer blocks the channel.

6. The driving substrate according to claim 5, wherein: The thickness of the first metal layer is smaller than the thickness of the second metal layer.

7. The driving substrate according to claim 3, wherein: The gate includes a first metal layer and a second metal layer, the first metal layer is arranged on the gate insulating layer, the first metal layer only blocks the channel, and the second metal layer is arranged on a side of the first metal layer away from the gate insulating layer, the second metal layer blocks the channel and the transition portion.

8. The driving substrate according to claim 3, wherein: The thickness of the first portion is greater than or equal to 250 nanometers, and the thickness of the second portion is less than or equal to 100 nanometers and greater than or equal to 10 nanometers.

9. The driving substrate according to claim 1, wherein: A mass ratio of the doping ions to the first contact portion is greater than a mass ratio of the doping ions to the transition portion.

10. The driving substrate according to claim 1, wherein: The first electrode is used to connect the light emitting device, the channel is directly connected to the second contact portion, or another transition portion is connected between the channel and the second contact portion.

11. A display panel comprising a driving substrate and a light emitting device disposed on the driving substrate, wherein the driving substrate comprises: substrate; A thin film transistor structure, wherein the thin film transistor structure is disposed on the substrate, and the thin film transistor structure comprises: an active layer, the active layer being arranged on the substrate, the active layer comprising a first contact portion, a transition portion, a channel, and a second contact portion, the transition portion being arranged between the first contact portion and the channel, the second contact portion being arranged on a side of the channel away from the first contact portion, the resistance value of the first contact portion being smaller than the resistance value of the transition portion, and the resistance value of the transition portion being smaller than the resistance value of the channel; a gate insulating layer, the gate insulating layer being disposed on the active layer; A gate, the gate being disposed on the gate insulating layer, the gate comprising a first portion and a second portion connected to the first portion, the first portion being overlapped with the channel, the second portion being overlapped with the transition portion, the first portion being used to completely block doping ions, and the second portion being used to partially transmit the doping ions; A first electrode and a second electrode, wherein the first electrode is connected to the first contact portion, and the second electrode is connected to the second contact portion.

12. The display panel according to claim 11, wherein: The density of the first portion is greater than the density of the second portion.

13. The display panel according to claim 11, wherein: The thickness of the first portion is greater than the thickness of the second portion.

14. The display panel according to claim 13, wherein: The gate is a single-layer structure.

15. The display panel according to claim 13, wherein: The gate includes a first metal layer and a second metal layer, the first metal layer is arranged on the gate insulating layer, the first metal layer blocks the channel and the transition portion, and the second metal layer is arranged on a side of the first metal layer away from the gate insulating layer, the second metal layer blocks the channel.

16. The display panel according to claim 15, wherein: The thickness of the first metal layer is smaller than the thickness of the second metal layer.

17. The display panel according to claim 13, wherein: The gate includes a first metal layer and a second metal layer, the first metal layer is arranged on the gate insulating layer, the first metal layer only blocks the channel, and the second metal layer is arranged on a side of the first metal layer away from the gate insulating layer, the second metal layer blocks the channel and the transition portion.

18. The display panel according to claim 13, wherein: The thickness of the first portion is greater than or equal to 250 nanometers, and the thickness of the second portion is less than or equal to 100 nanometers and greater than or equal to 10 nanometers.

19. The display panel according to claim 11, wherein: A mass ratio of the doping ions to the first contact portion is greater than a mass ratio of the doping ions to the transition portion.

20. The display panel according to claim 11, wherein: The first electrode is used to connect the light emitting device, the channel is directly connected to the second contact portion, or another transition portion is connected between the channel and the second contact portion.

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