Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises: an array substrate (1) and an opposing substrate (2) which are arranged opposite each other; a plurality of data lines (15), which are located on the array substrate (1) and extend in a first direction (X); a plurality of pixel electrodes (14), which are located on the array substrate (1), wherein at least one of the plurality of pixel electrodes (14) comprises a plurality of sub-pixel electrode portions (P0) arranged in the first direction (X); a first electrode (12), which is located on the array substrate (1), wherein the first electrode (12) comprises a plurality of first hollowed-out portions (L1), and the orthographic projection of each first hollowed-out portion (L1) on the array substrate (1) is located within the orthographic projection of each sub-pixel electrode portion (P0) on the array substrate (1); and a common electrode (22), which is located on the opposing substrate (2).

Description

Display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the Intellectual Property Office of the People's Republic of China on June 14, 2023, with application number 202310702904.8 and invention name "Display Panel and Display Device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a display panel and a display device. Background Art

[0004] Photo-alignment technology (UV2A) takes its name from the multiplication of ultraviolet (UV) light with the VA method of LCD panels. This technology uses UV light to precisely manipulate the alignment of liquid crystal molecules, significantly improving light transmittance. The key to UV2A is the use of a special polymer material as an alignment film, precisely controlling the tilt of liquid crystal molecules along the direction of the UV light. Its accuracy is measured in picometers (one trillionth of a meter). The advantage of UV2A lies in the simple structure of the LCD panel, free of protrusions and slits. This "dream of LCD technicians" was explored as early as 30 years ago. Today, with the three conditions of new materials, production equipment, and a sophisticated processing process, this dream has become a reality. The simple structure of the LCD panel not only improves production efficiency but also offers numerous advantages in image quality.

[0005] Compared with the UV2A pixel design, ultra-fine photo alignment (SUVA) is an upgraded version of UV2A. The SUVA pixel design can have better response time and color shift characteristics.

[0006] Summary of the Invention

[0007] The present disclosure provides a display panel and a display device. The display panel includes:

[0008] An array substrate and an opposing substrate arranged opposite to each other;

[0009] A plurality of data lines are located on the array substrate and extend along a first direction;

[0010] A plurality of pixel electrodes are located on the array substrate, at least one of the plurality of pixel electrodes comprises: a plurality of sub-pixel electrode portions arranged along the first direction;

[0011] A first electrode is located on the array substrate, the first electrode includes a plurality of first hollow portions, and an orthographic projection of the first hollow portion on the array substrate is located within the orthographic projection of the sub-pixel electrode portion on the array substrate;

[0012] The common electrode is located on the opposite substrate.

[0013] In a possible implementation manner, the first electrode is located on a side of the pixel electrode away from the opposite substrate.

[0014] In a possible implementation manner, the first electrode and the common electrode are loaded with the same signal.

[0015] In one possible embodiment, the multiple sub-pixel electrode portions include: two sub-pixel electrode groups distributed along the first direction, the sub-pixel electrode group includes two sub-pixel electrode portions, the sub-pixel electrode portion has multiple slit structures extending along the same direction, and the slit structures of two adjacent sub-pixel electrode portions included in the sub-pixel electrode group extend in different directions.

[0016] In a possible implementation manner, an axis extending perpendicular to the first direction is present between two sub-pixel electrode portions of the same sub-pixel electrode group;

[0017] The two first hollow portions corresponding to the same sub-pixel electrode group are symmetrical about the axis.

[0018] In a possible implementation manner, the first hollow portion is located in a central area of ​​an orthographic projection of the array substrate, and overlaps with the central area of ​​an orthographic projection of the sub-pixel electrode portion of the array substrate.

[0019] In a possible implementation manner, the orthographic projection of the first hollow portion on the array substrate is circular or elliptical.

[0020] In a possible implementation manner, the orthographic projection of the first hollow portion on the array substrate is a rectangle, and at least one side of the rectangle is parallel to an outer edge of the sub-pixel electrode portion.

[0021] In a possible implementation, the first hollow portion includes a first edge extending along the first direction;

[0022] The extension lines of the first sides of the two first hollow portions corresponding to the same sub-pixel electrode group overlap.

[0023] In a possible implementation, in the same pixel electrode, an extension line of at least one of the first sides of the first hollow portions corresponding to two sub-pixel electrode groups does not overlap.

[0024] In a possible implementation manner, the orthographic projection of the first hollow portion on the array substrate is a hexagon, and at least one side of the hexagon is parallel to an outer edge of the sub-pixel electrode portion.

[0025] In a possible implementation manner, at least one side of the hexagon is parallel to an extension direction of the slit structure of the sub-pixel electrode portion.

[0026] In a possible implementation manner, at least one side of the hexagon is perpendicular to an extension direction of the slit structure of the sub-pixel electrode portion.

[0027] In a possible embodiment, the orthographic projection of the first hollow portion on the array substrate is a right-angled trapezoid, at least one side of the right-angled trapezoid is parallel to the outer edge of the sub-pixel electrode portion, and the hypotenuse of the right-angled trapezoid intersects the extension direction of the slit structure.

[0028] In a possible implementation, the right-angled side of the right-angled trapezoid extends along the first direction, and the hypotenuse of the right-angled trapezoid is perpendicular to the extending direction of the slit structure.

[0029] In a possible implementation manner, top sides of the first hollow portions of two right-angled trapezoids corresponding to the same sub-pixel electrode group are arranged close to each other.

[0030] In a possible implementation manner, the bottom sides of the first hollow portions of two right-angled trapezoids corresponding to the same sub-pixel electrode group are arranged close to each other.

[0031] In a possible implementation manner, the extended lines of the right-angled sides of the first hollow portions of two right-angled trapezoids corresponding to the same sub-pixel electrode group coincide with each other.

[0032] In a possible implementation, in the same pixel electrode, the extension lines of the right-angled sides of the trapezoidal first hollow portions corresponding to the two sub-pixel electrode groups do not overlap.

[0033] In a possible embodiment, the orthographic projection of the first hollow portion on the array substrate is X-shaped, and the first hollow portion includes: a first sub-hollow portion extending along a third direction, and a second sub-hollow portion extending along a fourth direction, and the first sub-hollow portion and the second sub-hollow portion are arranged crosswise.

[0034] In a possible embodiment, the extension direction of one of the first sub-hollow portion and the second sub-hollow portion is parallel to the extension direction of the slit structure of the sub-pixel electrode portion, and the extension direction of the other sub-hollow portion is perpendicular to the extension direction of the slit structure of the sub-pixel electrode portion.

[0035] In a possible implementation manner, the two first hollow portions corresponding to the same sub-pixel electrode group are an integrated structure.

[0036] In a possible implementation manner, the two first hollow portions corresponding to the same sub-pixel electrode group are separated structures.

[0037] In a possible implementation manner, the slit structures are evenly distributed throughout the sub-pixel electrode portion.

[0038] In a possible implementation manner, the slit structure is distributed only in a partial area of ​​the sub-pixel electrode portion, and the sub-pixel electrode portion further includes a block structure.

[0039] In a possible implementation manner, in the two sub-pixel electrode groups of the same pixel electrode, the block structures are distributed at different positions;

[0040] In the two sub-pixel electrode portions of the same sub-pixel electrode group, the block structure is an integrated structure.

[0041] In a possible implementation manner, an orthographic projection of the first hollow portion on the array substrate at least partially overlaps with an orthographic projection of the block structure on the array substrate.

[0042] In a possible implementation, the plurality of sub-pixel electrode portions include: a first sub-pixel electrode portion, a second sub-pixel electrode portion, a third sub-pixel electrode portion, and a fourth sub-pixel electrode portion sequentially arranged along the first direction;

[0043] The extension direction of the slit structure of the first sub-pixel electrode portion is the same as the extension direction of the slit structure of the third sub-pixel electrode portion, and the extension direction of the slit structure of the second sub-pixel electrode portion is the same as the extension direction of the slit structure of the fourth sub-pixel electrode portion.

[0044] In a possible implementation, the display panel further includes a plurality of gate lines located on the array substrate, and the plurality of gate lines extend along the second direction;

[0045] An orthographic projection of the gate line on the array substrate and an orthographic projection of a gap between the second sub-pixel electrode portion and the third sub-pixel electrode portion on the array substrate have an overlapping area.

[0046] In a possible implementation, the gate line includes a first gate line hollow; an orthographic projection of the first gate line hollow on the array substrate overlaps with an orthographic projection of a portion of the data line on the array substrate.

[0047] In a possible implementation manner, the pixel electrode further includes: a connecting portion connecting the second sub-pixel electrode portion and the third sub-pixel electrode portion;

[0048] The gate line further includes a second gate line hollow, and an orthographic projection of the second gate line hollow on the array substrate at least partially overlaps with an orthographic projection of the connecting portion on the array substrate.

[0049] In a possible implementation manner, extension lines of the connecting portions of two adjacent pixel electrodes in the first direction do not overlap.

[0050] In a possible implementation, the first electrode further includes: a second hollow portion, wherein the orthographic projection of the second hollow portion on the array substrate covers the orthographic projection of the connecting portion on the array substrate.

[0051] In a possible implementation, the array substrate includes: a first substrate;

[0052] There is a boundary between two adjacent sub-pixel electrode portions in the pixel electrode; the orthographic projection of at least part of the first hollow portion on the first substrate has an overlapping area with the orthographic projection of the boundary on the first substrate.

[0053] In a possible implementation, the plurality of sub-pixel electrode portions of the pixel electrode include: a first sub-pixel electrode portion, a second sub-pixel electrode portion, a third sub-pixel electrode portion, and a fourth sub-pixel electrode portion sequentially arranged along the first direction;

[0054] The first hollow portion is provided in a region where at least one of the first sub-pixel electrode portion, the second sub-pixel electrode portion, the third sub-pixel electrode portion, and the fourth sub-pixel electrode portion is located.

[0055] In a possible implementation, the plurality of first hollow portions include: a first type of hollow portion located in a region where the first sub-pixel electrode portion is located, a second type of hollow portion located in a region where the second sub-pixel electrode portion is located, a third type of hollow portion located in a region where the third sub-pixel electrode portion is located, and a fourth type of hollow portion located in a region where the fourth sub-pixel electrode portion is located;

[0056] The first type of hollow portion and the second type of hollow portion are an integrated structure, and an orthographic projection of the first substrate and an orthographic projection of the boundary between the first sub-pixel electrode portion and the second sub-pixel electrode portion on the first substrate have an overlapping area;

[0057] The third type hollow portion and the fourth type hollow portion are an integrated structure, and have an overlapping area in the orthographic projection of the first substrate with the orthographic projection of the boundary between the third sub-pixel electrode portion and the fourth sub-pixel electrode portion on the first substrate.

[0058] In a possible embodiment, the second type of hollow portion and the third type of hollow portion are an integrated structure, and have an overlapping area in the orthographic projection of the first substrate with the boundary between the second sub-pixel electrode portion and the third sub-pixel electrode portion in the orthographic projection of the first substrate.

[0059] In a possible implementation, the plurality of first hollow portions include: a second type of hollow portion located in the region where the second sub-pixel electrode portion is located, and a third type of hollow portion located in the region where the third sub-pixel electrode portion is located;

[0060] The second type of hollow portion and the third type of hollow portion are an integrated structure, and have an overlapping area in the orthographic projection of the first substrate with the orthographic projection of the boundary between the second sub-pixel electrode portion and the third sub-pixel electrode portion on the first substrate.

[0061] In a possible implementation manner, the sub-pixel electrode portion has a plurality of slit structures extending in the same direction;

[0062] An extension direction of the slit structure in the first sub-pixel electrode portion is parallel to an extension direction of the slit structure in the third sub-pixel electrode portion, and an extension direction of the slit structure in the second sub-pixel electrode portion is parallel to an extension direction of the slit structure in the fourth sub-pixel electrode portion.

[0063] In a possible implementation manner, an extension direction of the first hollow portion is parallel to an extension direction of the slit structure in the sub-pixel electrode portion where the first hollow portion is located.

[0064] In a possible implementation, the orthographic projection of the first hollow portion on the first substrate is a rectangle, and the rectangle includes a first outer edge extending along the first direction and a second outer edge extending along the second direction.

[0065] In a possible embodiment, the boundary between the first sub-pixel electrode portion and the second sub-pixel electrode portion has a first slit extending along the second direction; the boundary between the third sub-pixel electrode portion and the fourth sub-pixel electrode portion has a second slit extending along the second direction.

[0066] In a possible implementation manner, the boundary portion between the second sub-pixel electrode portion and the third sub-pixel electrode portion has a connecting electrode extending along the second direction.

[0067] In a possible implementation manner, the orthographic projection of the first electrode on the substrate covers the orthographic projection of the data line on the substrate.

[0068] In a possible implementation, the display panel further includes a plurality of gate lines located on the array substrate, and the plurality of gate lines extend along the second direction;

[0069] An orthographic projection of the gate line on the first substrate and an orthographic projection of a gap between two adjacent pixel electrodes on the first substrate have an overlapping area;

[0070] The orthographic projection of the first electrode on the first substrate covers at least a portion of the orthographic projection of the gate line on the first substrate.

[0071] In a possible implementation manner, the gate line includes: a gate line main portion extending along the first direction, and a gate electrode extending from one side of the gate line main portion;

[0072] The first electrode includes: a third hollow portion; an orthographic projection of the third hollow portion on the first substrate covers at least a portion of an orthographic projection of the gate on the first substrate.

[0073] In a possible implementation, the array substrate further includes: a first common line extending along the second direction, wherein an orthographic projection of the first common line on the first substrate overlaps an orthographic projection of a gap between two adjacent pixel electrodes on the first substrate;

[0074] The first common trace includes: a first common main portion extending along the second direction, and a first common extension portion extending from the first common main portion toward one side of the gate line;

[0075] The orthographic projection of the third hollow portion on the first substrate covers at least a portion of the orthographic projection of the first common extension portion on the first substrate.

[0076] In a possible implementation, the display panel further includes: a first transistor electrode electrically connected to the data line, and a second transistor electrode;

[0077] The second electrode of the transistor includes: a second electrode first portion extending along the second direction, and a second electrode second portion extending from the second electrode first portion along the first direction;

[0078] At least part of the orthographic projection of the second portion of the second pole on the first substrate has an overlapping area with the orthographic projection of the first common extension portion on the first substrate; the orthographic projection of the second portion of the second pole on the first substrate has an overlapping area with the orthographic projection of the gate on the first substrate.

[0079] In one possible implementation, the second pole first portion includes: a second pole first sub-portion and a second pole second sub-portion extending along the second direction; a width of the second pole second sub-portion in the first direction is smaller than a width of the second pole second sub-portion in the first direction;

[0080] An orthographic projection of the second sub-portion of the second pole on the first substrate and an orthographic projection of the first common extension portion on the first substrate have an overlapping area.

[0081] In a possible implementation, the data line is located on a side of the first electrode away from the pixel electrode; the array substrate further includes: a first insulating layer located between the data line and the first electrode, the first insulating layer including a color resist layer.

[0082] In a possible implementation, the first insulating layer includes: a transition layer located on a side of the color resist layer facing the first electrode.

[0083] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] FIG1 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0085] FIG2A is a schematic top view of an array substrate according to an embodiment of the present disclosure;

[0086] FIG2B is a schematic diagram of a single film layer of the gate line in FIG2A;

[0087] FIG2C is a schematic diagram of a single film layer of the data line in FIG2A ;

[0088] FIG2D is a schematic diagram of a single film layer of the active layer in FIG2A;

[0089] FIG2E is a schematic diagram of a single film layer of the first insulating layer in FIG2A ;

[0090] FIG2F is a schematic diagram of a single film layer of the first electrode in FIG2A ;

[0091] FIG2G is a schematic diagram of a single film layer of the second insulating layer in FIG2A ;

[0092] FIG2H is a schematic diagram of a single film layer of the pixel electrode in FIG2A ;

[0093] FIG2I is a schematic diagram of the black matrix corresponding to FIG2A ;

[0094] FIG2J is an optical simulation diagram corresponding to FIG2A ;

[0095] FIG3A is a second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0096] FIG3B is a schematic diagram of a single film layer of the first electrode in FIG3A ;

[0097] FIG3C is an optical simulation diagram corresponding to FIG3A ;

[0098] FIG4A is a third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0099] FIG4B is a schematic diagram of a single film layer of the first electrode in FIG4A ;

[0100] FIG4C is an optical simulation diagram corresponding to FIG4A ;

[0101] FIG5A is a fourth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0102] FIG5B is a schematic diagram of a single film layer of the first electrode in FIG5A ;

[0103] FIG5C is an optical simulation diagram corresponding to FIG5A ;

[0104] FIG6A is a fifth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0105] FIG6B is a schematic diagram of a single film layer of the first electrode in FIG6A ;

[0106] FIG6C is a schematic diagram of a single film layer of the pixel electrode in FIG6A ;

[0107] FIG6D is an optical simulation diagram corresponding to FIG6A ;

[0108] FIG7A is a sixth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0109] FIG7B is a schematic diagram of a single film layer of the first electrode in FIG7A ;

[0110] FIG7C is an optical simulation diagram corresponding to FIG7A ;

[0111] FIG8A is a seventh schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0112] FIG8B is a schematic diagram of a single film layer of the first electrode in FIG8A ;

[0113] FIG8C is an optical simulation diagram corresponding to FIG8A ;

[0114] FIG9A is an eighth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0115] FIG9B is a schematic diagram of a single film layer of the first electrode in FIG9A ;

[0116] FIG9C is an optical simulation diagram corresponding to FIG9A ;

[0117] FIG10A is a ninth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0118] FIG10B is a schematic diagram of a single film layer of the first electrode in FIG10A;

[0119] FIG10C is an optical simulation diagram corresponding to FIG10A;

[0120] FIG11A is a tenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0121] FIG11B is a schematic diagram of a single film layer of the first electrode in FIG11A ;

[0122] FIG11C is a schematic diagram of a single film layer of the pixel electrode in FIG11A ;

[0123] FIG11D is an optical simulation diagram corresponding to FIG11A ;

[0124] FIG12A is an eleventh schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0125] FIG12B is a schematic diagram of a single film layer of the gate line corresponding to FIG12A;

[0126] FIG13A is a twelfth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0127] FIG13B is a schematic diagram of a single film layer of the gate line corresponding to FIG13A;

[0128] FIG14 is an equivalent circuit diagram provided by an embodiment of the present disclosure;

[0129] FIG15A is a schematic diagram of an array substrate including a plurality of sub-pixels provided in an embodiment of the present disclosure;

[0130] FIG15B is a schematic diagram of a single film layer where the gate lines are located in FIG15A;

[0131] FIG15C is a schematic diagram of a single film layer where the data line is located in FIG15A;

[0132] FIG15D is a schematic diagram of a single film layer where the first electrode is located in FIG15A;

[0133] FIG15E is a schematic diagram of a single film layer where the pixel electrode is located in FIG15A;

[0134] FIG15F is a partial enlarged schematic diagram of FIG15C;

[0135] FIG16A is one of the schematic diagrams of a sub-pixel provided in an embodiment of the present disclosure;

[0136] FIG16B is a schematic diagram of a single film layer where the gate lines are located in FIG16A;

[0137] FIG16C is a schematic diagram of a single film layer where the data line is located in FIG16A;

[0138] FIG16D is a schematic diagram of a single film layer where the first electrode is located in FIG16A;

[0139] FIG16E is a schematic diagram of a single film layer where the pixel electrode is located in FIG16A;

[0140] FIG16F is a schematic diagram of FIG16E without part numbers;

[0141] FIG16G is a color resistance diagram corresponding to FIG16A ;

[0142] FIG16H is a schematic diagram of the black matrix corresponding to FIG16A ;

[0143] FIG17A is a second schematic diagram of a sub-pixel provided in an embodiment of the present disclosure;

[0144] FIG17B is a schematic diagram of a single film layer of the first electrode in FIG17A;

[0145] FIG18A is a third schematic diagram of a sub-pixel provided in an embodiment of the present disclosure;

[0146] FIG18B is a schematic diagram of a single film layer of the first electrode in FIG18A;

[0147] FIG19A is a fourth schematic diagram of a sub-pixel provided in an embodiment of the present disclosure;

[0148] FIG19B is a schematic diagram of a single film layer of the first electrode in FIG19A;

[0149] FIG20A is a fifth schematic diagram of a sub-pixel provided in an embodiment of the present disclosure;

[0150] FIG20B is a schematic diagram of a single film layer of the first electrode in FIG20A;

[0151] FIG21A is a sixth schematic diagram of a sub-pixel provided by an embodiment of the present disclosure;

[0152] FIG21B is a schematic diagram of a single film layer of the first electrode in FIG21A;

[0153] FIG22A is a seventh schematic diagram of a sub-pixel provided in an embodiment of the present disclosure;

[0154] FIG22B is a schematic diagram of a single film layer of the first electrode in FIG22A ;

[0155] FIG23A is an eighth schematic diagram of a sub-pixel provided by an embodiment of the present disclosure;

[0156] FIG23B is a schematic diagram of a single film layer of the first electrode in FIG23A;

[0157] FIG24 is a second schematic cross-sectional view of a display panel provided by an embodiment of the present disclosure;

[0158] FIG25 is a third schematic cross-sectional view of a display panel provided in an embodiment of the present disclosure;

[0159] FIG26 is a fourth schematic cross-sectional view of a display panel provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0160] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0161] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0162] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0163] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0164] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0165] High-resolution products, such as 8K and 16K display products, are the main direction of subsequent products. However, the current 8K products using vertical alignment liquid crystal (VA) have problems with low transmittance and poor color deviation.

[0166] In view of this, referring to Figures 1, 2A-2J, 3A-3C, 4A-4C, 5A-5C, 6A-6D, 7A-7C, 8A-8C, 9A-9C, 10A-10C, 11A-11D, and 12A-12B, Figure 2A is one of the top views of the array substrate provided in an embodiment of the present disclosure, Figure 2B is a single-film schematic diagram of the gate line in Figure 2A, Figure 2C is a single-film schematic diagram of the data line in Figure 2A, Figure 2D is a single-film schematic diagram of the active layer in Figure 2A, Figure 2E is a single-film schematic diagram of the first insulating layer in Figure 2A, Figure 2F is a single-film schematic diagram of the first electrode in Figure 2A, and Figure 2G is a second insulating layer in Figure 2A. 2H is a schematic diagram of a single film layer of the pixel electrode in FIG2A , FIG2I is a schematic diagram of the black matrix corresponding to FIG2A , FIG2J is an optical simulation diagram corresponding to FIG2A , FIG3A is a second schematic diagram of a top view of an array substrate provided in an embodiment of the present disclosure, FIG3B is a schematic diagram of a single film layer of the first electrode in FIG3A , FIG3C is an optical simulation diagram corresponding to FIG3A , FIG4A is a third schematic diagram of a top view of an array substrate provided in an embodiment of the present disclosure, FIG4B is a schematic diagram of a single film layer of the first electrode in FIG4A , FIG4C is an optical simulation diagram corresponding to FIG4A , FIG5A is a fourth schematic diagram of a top view of an array substrate provided in an embodiment of the present disclosure, FIG5B is a schematic diagram of a single film layer of the first electrode in FIG5A , and FIG5C is an optical simulation diagram corresponding to FIG5A , Figure 6A is the fifth schematic top view of the array substrate provided in the embodiment of the present disclosure, Figure 6B is a schematic diagram of a single film layer of the first electrode in Figure 6A, Figure 6C is a schematic diagram of a single film layer of the pixel electrode in Figure 6A, Figure 6D is an optical simulation diagram corresponding to Figure 6A, Figure 7A is the sixth schematic top view of the array substrate provided in the embodiment of the present disclosure, Figure 7B is a schematic diagram of a single film layer of the first electrode in Figure 7A, Figure 7C is an optical simulation diagram corresponding to Figure 7A, Figure 8A is the seventh schematic top view of the array substrate provided in the embodiment of the present disclosure, Figure 8B is a schematic diagram of a single film layer of the first electrode in Figure 8A, Figure 8C is an optical simulation diagram corresponding to Figure 8A, Figure 9A is the eighth schematic top view of the array substrate provided in the embodiment of the present disclosure, Figure 9B is a schematic diagram of a single film layer of the first electrode in Figure 9A 9C is an optical simulation diagram corresponding to FIG9A , FIG10A is a ninth schematic top view of an array substrate provided in an embodiment of the present disclosure, FIG10B is a schematic diagram of a single film layer of the first electrode in FIG10A , FIG10C is an optical simulation diagram corresponding to FIG10A , FIG11A is a tenth schematic top view of an array substrate provided in an embodiment of the present disclosure, FIG11B is a schematic diagram of a single film layer of the first electrode in FIG11A , FIG11C is a schematic diagram of a single film layer of the pixel electrode in FIG11A , FIG11D is an optical simulation diagram corresponding to FIG11A , FIG12A is an eleventh schematic top view of an array substrate provided in an embodiment of the present disclosure, and FIG12B is a schematic diagram of a single film layer of a gate line corresponding to FIG12A ; an embodiment of the present disclosure provides a display panel, comprising:

[0167] An array substrate 1 and an opposing substrate 2 are arranged opposite to each other;

[0168] A plurality of data lines 15 are located on the array substrate 1 and extend along a first direction X;

[0169] A plurality of pixel electrodes 14 are located on the array substrate 1 , and at least one pixel electrode 14 among the plurality of pixel electrodes 14 includes: a plurality of sub-pixel electrode portions P0 arranged along a first direction X;

[0170] A first electrode 12 is located on the array substrate 1. The first electrode 12 includes a plurality of first hollow portions L1. The orthographic projections of the first hollow portions L1 on the array substrate 1 are located within the orthographic projections of the sub-pixel electrode portions P0 on the array substrate 1. Specifically, the first hollow portions L1 and the sub-pixel electrode portions P0 may correspond one-to-one, that is, a first hollow portion L1 is provided in the region corresponding to each sub-pixel electrode portion P0.

[0171] The common electrode 22 is located on the opposite substrate 2 .

[0172] In the embodiment of the present disclosure, for a display panel in a VA display mode in which an array substrate 1 is provided with a pixel electrode 14 and an opposing substrate 2 is provided with a common electrode 22, a first electrode 12 having a first hollow portion L1 is further provided on the array substrate. When displaying, at a position without the first hollow portion L1, the first electrode 12 and the pixel electrode 14 form a capacitor, which affects or divides a portion of the voltage between the pixel electrode 14 and the common electrode 22, so that the voltage at the position without the first hollow portion L1 is lower than the voltage at the position with the first hollow portion L1, thereby making the brightness at the position without the first hollow portion L1 lower than the brightness at the position with the first hollow portion L1, forming areas with different brightness within the same sub-pixel electrode portion P0, thereby realizing eight domains with different brightness. display effect, high-resolution display can be achieved, and the shape of the first hollow portion L1 can be of many kinds, which can easily achieve different proportions of light and dark areas; in addition, within the same pixel electrode 14, the pressure difference between the position with the first hollow portion L1 and the position without the first hollow portion L1 is different, which can make the liquid crystal twist more uniform, reduce the dark lines corresponding to the pixel electrode 14, reduce the width of the black matrix, and improve the transmittance of the display panel; in addition, in addition to the vertical electric field formed by the pixel electrode 14 and the common electrode 22 in the array substrate, the pixel electrode 14 and the first electrode 12 will form a horizontal electric field, which can increase the deflection direction of the liquid crystal and improve the color deviation problem of the display panel; in addition, corresponding to each sub-pixel, only one transistor is used to achieve the above effects, and the pixel structure of the display panel is simple and easy to implement.

[0173] It should be noted that in Figures 2F, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, and 11B, in order to clearly illustrate the shape of the first hollow portion L1, the first hollow portion L1 and the second hollow portion L2 are represented by patterns with filling points; the area outside the first hollow portion L1 and the second hollow portion L2 serves as the effective area of ​​the first electrode 12, that is, the area outside the first hollow portion L1 and the second hollow portion L2 is the area with the physical first electrode 12, and the first hollow portion L1 and the second hollow portion L2 with filling points are the hollowed-out areas.

[0174] In a possible embodiment, in combination with Figures 1 and 2A-2J, the array substrate 1 may include: a first substrate 11, a plurality of gate lines 16 extending along the second direction Y on one side of the first substrate 11; the data line 15 may be located on the side of the gate line 16 facing away from the first substrate 11, the first electrode 12 may be located on the side of the data line 15 facing away from the gate line 16, the pixel electrode 14 may be located on the side of the first electrode 12 facing away from the data line 15, a gate insulating layer may be provided between the layer where the gate line 16 is located and the layer where the data line 15 is located, an active layer may be provided between the gate insulating layer and the data line 15 (the active layer may include an active pattern 17, and the active layer material may be amorphous silicon, low-temperature polycrystalline silicon, metal oxide, etc., which is not limited here), a first insulating layer 18 may be provided between the data line 15 and the first electrode 12, and a second insulating layer 13 may be provided between the first electrode 12 and the pixel electrode 14.

[0175] In one possible embodiment, as shown in FIG2I , the display panel may further be provided with a black matrix 23. The orthographic projection of the black matrix 23 on the array substrate 1 may cover the orthographic projection of the gate line 16 on the array substrate, and cover the orthographic projection of the data line 15 on the array substrate 1. Specifically, the counter substrate may include a second substrate 21, and the black matrix 23 may be located between the second substrate 21 and the common electrode 22.

[0176] In one possible embodiment, as shown in FIG1 , the first electrode 12 is located on the side of the pixel electrode 14 away from the opposing substrate 2. In this public embodiment, the first electrode 12 is located on the side of the pixel electrode 14 away from the opposing substrate 2, which can isolate the first overlapping capacitance Cgp between the pixel electrode 14 and the gate line 16 and the second overlapping capacitance Cpd between the pixel electrode 14 and the data line 15, thereby greatly reducing the risk of crosstalk. At the same time, due to the presence of the first electrode 12, the distance between the pixel electrodes can be reduced, so that the pixel electrode 14 overlaps with the gate line 16, and the pixel electrode 14 overlaps with the data line 15, thereby reducing the risk of liquid crystal light leakage, thereby reducing the width of the black matrix, increasing the pixel aperture ratio, and improving the pixel transmittance.

[0177] In a possible implementation, the first electrode 12 and the common electrode 22 are loaded with the same signal. That is, the first electrode 12 is also loaded with a common signal.

[0178] In a possible embodiment, referring to Figures 2A-2J, 3A-3C, 4A-4C, 5A-5C, 6A-6D, 7A-7C, 8A-8C, 9A-9C, 10A-10C, and 11A-11D, the multiple sub-pixel electrode portions P0 include: two sub-pixel electrode groups P00 distributed along a first direction X, the sub-pixel electrode group P00 includes two sub-pixel electrode portions P0, the sub-pixel electrode portion P0 has multiple slit structures S extending in the same direction, and the slit structures S of two adjacent sub-pixel electrode portions P0 included in the sub-pixel electrode group P00 extend in different directions.

[0179] In a possible embodiment, referring to Figures 2A-2J, 3A-3C, 4A-4C, 5A-5C, 6A-6D, 7A-7C, 8A-8C, 9A-9C, 10A-10C, and 11A-11D, the plurality of sub-pixel electrode portions P0 include: a first sub-pixel electrode portion P1, a second sub-pixel electrode portion P2, a third sub-pixel electrode portion P3, and a fourth sub-pixel electrode portion P4 arranged in sequence along the first direction X; an extension direction of the slit structure S of the first sub-pixel electrode portion P1 is the same as an extension direction of the slit structure S of the third sub-pixel electrode portion P3, and an extension direction of the slit structure S of the second sub-pixel electrode portion P2 is the same as an extension direction of the slit structure S of the fourth sub-pixel electrode portion P4.

[0180] In a possible embodiment, the angle formed by the extension direction of the slit structure S of the first sub-pixel portion P1 and the second direction Y can be 40° to 50°, for example, 45°; the angle formed by the extension direction of the slit structure S of the second sub-pixel portion P2 and the second direction Y can be 130° to 140°, for example, 135°.

[0181] In one possible embodiment, referring to Figures 2A-2J, 3A-3C, 4A-4C, 5A-5C, 6A-6D, 7A-7C, 8A-8C, 9A-9C, 10A-10C, and 11A-11D, the orthographic projection of the gate line 16 on the array substrate 1 overlaps with the orthographic projection of the gap between the second sub-pixel electrode portion P2 and the third sub-pixel electrode portion P3 on the array substrate 1. That is, the gate line 16 is located in the gap between the two sub-pixel electrode groups P00 of the same pixel electrode 14.

[0182] Specifically, the area defined by the intersection of the gate line 16 and the data line 15 can be used as the area where the pixel electrode 14 is located, and the sub-pixel electrode portion P0 is in the area where the pixel electrode 14 is located. At this time, the first hollow portion L1 of the first electrode 12 overlaps with the sub-pixel electrode portion P0 in the area where the pixel electrode 14 is located.

[0183] In one possible embodiment, referring to Figures 2A-2J, 3A-3C, 4A-4C, 5A-5C, 6A-6D, 7A-7C, 8A-8C, 9A-9C, 10A-10C, and 11A-11D, the pixel electrode 14 further includes a connecting portion P5 connecting the second sub-pixel electrode portion P2 and the third sub-pixel electrode portion P4. The two sub-pixel electrode groups P00 of the same pixel electrode 14 are connected via the connecting portion P5. Specifically, the connecting portion P5 may be located on the same layer as the pixel electrode 14.

[0184] Specifically, in combination with Figures 2A to 2J, the layer where the data line 15 is located may also include a first electrode 151 of a transistor (optionally, the data line is multiplexed as the first electrode 151 of the transistor), and a second electrode 152 of a transistor; the orthographic projection of the connection portion P5 on the array substrate 1 may have an overlapping area with the orthographic projection of the second electrode 152 of the transistor on the array substrate 1, so that the pixel electrode 14 is connected to the second electrode 152 of the transistor through the via.

[0185] Specifically, in combination with Figures 2A to 2J, the first electrode 12 also includes: a second hollow portion L2, the orthographic projection of the second hollow portion L2 on the array substrate 1 at least partially covers the orthographic projection of the connection portion P5 on the array substrate 1, optionally, the orthographic projection of the second hollow portion L2 on the array substrate 1 completely covers the orthographic projection of the connection portion P5 on the array substrate 1; the first insulating layer also includes a first via K1, and the second insulating layer also includes a second via K2; the orthographic projection of the connection portion P5 on the array substrate 1, the orthographic projection of the second via K2 on the array substrate 1, the orthographic projection of the second hollow portion L2 on the array substrate 1, the orthographic projection of the first via K1 on the array substrate 1, and the orthographic projection of the second pole 152 of the transistor on the array substrate 1 all have overlapping areas, so that the connection portion P5 is connected to the second pole 152 of the transistor through the second via K2, the second hollow portion L2, and the first via K1 in sequence.

[0186] Specifically, as shown in Figures 13A and 13B , the extension lines of the connection portions P5 of two adjacent pixel electrodes 14 in the first direction X do not overlap. That is, in the first direction X, the connection portions P5 of two adjacent pixel electrodes 14 are staggered, so that the same data line 15 can be connected to pixel electrodes 14 in different columns. Specifically, for example, in Figure 13A , the second data line 15 from the left is connected to the first pixel electrode 14 on the right side above, and is also connected to the pixel electrode 14 on the left side below. The two connected pixel electrodes 14 are located in different columns.

[0187] In one possible implementation, as shown in Figures 12A and 12B , the gate line 16 includes a first gate line hollow 161; the orthographic projection of the first gate line hollow 161 on the array substrate 1 overlaps with the orthographic projection of a portion of the data line 15 on the array substrate 1. In the disclosed embodiment, the gate line 16 is hollowed out in the area where it overlaps with the data line 15 to prevent overlap capacitance between the two, which could affect signal transmission between the gate line 16 and the data line 15.

[0188] In one possible embodiment, as shown in Figures 12A and 12B, the gate line 16 further includes a second gate line hollow 162, the orthographic projection of the second gate line hollow 162 on the array substrate 1 at least partially overlapping with the orthographic projection of the connection portion P5 on the array substrate 1. In the disclosed embodiment, the gate line 16 is hollowed out in the area overlapping with the connection portion P5 to prevent overlapping capacitance between the gate line 16 and the pixel electrode 14, which could affect signal transmission on the gate line 16.

[0189] In a possible embodiment, referring to Figures 2A-2J, 3A-3C, 4A-4C, 5A-5C, 6A-6D, 7A-7C, 8A-8C, 9A-9C, 10A-10C, and 11A-11D, the first gate line hollow 161 and the second gate line hollow 162 can also be an integrated structure, that is, a connecting groove is opened on the gate line 16, which serves as the first gate line hollow 161 and the second gate line hollow 162 at the same time.

[0190] It should be noted that Figures 3A-3C, 4A-4C, 5A-5C, 6A-6D, 7A-7C, 8A-8C, 9A-9C, 10A-10C, and 11A-11D only illustrate the stacking diagram of the array substrate and the single film layer diagram of the first electrode 12 or the pixel electrode 14. For other film layer patterns of the array substrate, they can be shown in Figures 2A-2I, and the embodiments of the present disclosure will no longer be repeated.

[0191] In a possible embodiment, referring to Figures 2A-2J, 3A-3C, 4A-4C, 5A-5C, 6A-6D, 7A-7C, 8A-8C, 9A-9C, 10A-10C, and 11A-11D, an axis k extending perpendicular to the first direction X is present between two sub-pixel electrode portions P0 of the same sub-pixel electrode group P00; the two first hollow portions L1 corresponding to the same sub-pixel electrode group P00 are symmetrical about the axis k.

[0192] In one possible implementation, referring to Figures 2A, 3A, 4A, 5A, 7A, and 8A, the first hollow portion L1 is located at the center of the orthographic projection of the array substrate 1 and coincides with the center of the orthographic projection of the sub-pixel electrode portion P0 on the array substrate 1. Specifically, the first hollow portion L1 is located at the center of the orthographic projection of the array substrate 1 and coincides with the center of the orthographic projection of the sub-pixel electrode portion P0 on the array substrate 1.

[0193] In a possible implementation, referring to FIG. 3A to FIG. 3C and FIG. 4A to FIG. 4C , the orthographic projection of the first hollow portion L1 on the array substrate 1 is circular or elliptical.

[0194] In one possible embodiment, referring to Figures 5A-5C and 6A-6D, the orthographic projection of the first hollow portion L1 on the array substrate 1 is a rectangle, and at least one side of the rectangle is parallel to the outer edge of the sub-pixel electrode portion P0. Specifically, for example, as shown in Figures 5A-5C and 6A-6D, the side of the rectangle extending along the first direction X is parallel to the side of the sub-pixel electrode portion P0 extending along the first direction X, that is, both extend along the first direction X; and the side of the rectangle extending along the second direction Y is parallel to the side of the sub-pixel electrode portion P0 extending along the second direction Y, that is, both extend along the second direction Y.

[0195] It should be noted that the outer edge of the sub-pixel electrode portion P0 can be the actual outer edge of the pixel electrode, or it can be the extension line of the branch electrode end of the pixel electrode (for example, the pixel electrode is comb-shaped, and the outer edge of the sub-pixel electrode portion P0 can be the extension line of the branch electrode end).

[0196] In one possible embodiment, referring to Figures 5A-5C and 6A-6D, the first hollow portion L1 includes a first side L10 extending along the first direction X; the extension lines of the first sides L10 of the two first hollow portions L1 corresponding to the same sub-pixel electrode group P00 coincide with each other. For example, as shown in Figures 5A and 6A, the extension line of the first side L10 of the first hollow portion L1 corresponding to the first sub-pixel electrode portion P1 coincides with the extension line of the first side L10 of the first hollow portion L1 corresponding to the second sub-pixel electrode portion P2; and the extension line of the first side L10 of the first hollow portion L1 corresponding to the third sub-pixel electrode portion P3 coincides with the extension line of the first side L10 of the first hollow portion L1 corresponding to the fourth sub-pixel electrode portion P4.

[0197] In one possible embodiment, as shown in Figures 6A to 6D , in the same pixel electrode 14, the extension lines of at least one first side L10 of the first hollow portion L1 corresponding to the two sub-pixel electrode groups P00 do not overlap. For example, as shown in Figure 6A , the extension line of the first side L10 on the right side of the first hollow portion L1 of the upper sub-pixel electrode group P00 does not overlap with the extension line of the first side L10 on the left side of the first hollow portion L1 of the lower sub-pixel electrode group P00; and the extension line of the first side L10 on the right side of the first hollow portion L1 of the upper sub-pixel electrode group P00 does not overlap with the extension line of the first side L10 on the right side of the first hollow portion L1 of the lower sub-pixel electrode group P00.

[0198] In a possible implementation, referring to FIG. 7A to FIG. 7C and FIG. 8A to FIG. 8C , the orthographic projection of the first hollow portion L1 on the array substrate 1 is a hexagon, and at least one side of the hexagon is parallel to the outer edge of the sub-pixel electrode portion P0 .

[0199] In a possible implementation, referring to FIG. 7A to FIG. 7C , at least one side of the hexagon is parallel to the extension direction of the slit structure S of the sub-pixel electrode portion P0 .

[0200] In a possible implementation, referring to FIG. 7A to FIG. 7C and FIG. 8A to FIG. 8C , at least one side of the hexagon is perpendicular to the extension direction of the slit structure S of the sub-pixel electrode portion P0 .

[0201] In one possible embodiment, referring to Figures 9A-9C, 10A-10C, and 11A-11C, the orthographic projection of the first hollow portion L1 on the array substrate 1 is a right-angled trapezoid, at least one side of the right-angled trapezoid is parallel to the outer edge of the sub-pixel electrode portion P0, and the hypotenuse of the right-angled trapezoid intersects the extension direction of the slit structure S. For example, the bottom side, top side, and right-angled sides of the right-angled trapezoid are parallel to the corresponding outer edges of the sub-pixel electrode portion P0, and the hypotenuse of the right-angled trapezoid is perpendicular to the extension direction of the slit structure S.

[0202] In a possible embodiment, referring to FIG. 9A-FIG . 9C , FIG. 10A-FIG . 10C , and FIG. 11A-FIG . 11C , the right-angled sides of the right-angled trapezoid extend along the first direction X, and the hypotenuse of the right-angled trapezoid is perpendicular to the extension direction of the slit structure S.

[0203] It is understandable that due to limitations in process precision, the right angle of the first hollow portion L1 may be difficult to achieve, and the right angle position may have a certain curvature, that is, the position corresponding to the right angle of the first hollow portion L1 may also be arc-shaped, which is the right angle referred to in the embodiment of the present disclosure within the range of process error.

[0204] In one possible embodiment, as shown in Figures 9A-9C and 11A-11C, the top sides of the two right-angled trapezoidal first hollow portions L1 corresponding to the same sub-pixel electrode group P00 are disposed adjacent to each other. That is, the top sides of the two right-angled trapezoidal first hollow portions L1 corresponding to the same sub-pixel electrode group P00 are disposed opposite each other.

[0205] In one possible embodiment, as shown in Figures 10A-10C , the bases of the two right-angled trapezoidal first hollow portions L1 corresponding to the same sub-pixel electrode group P00 are disposed adjacent to each other. That is, the bases of the two right-angled trapezoidal first hollow portions L1 corresponding to the same sub-pixel electrode group P00 are disposed opposite to each other.

[0206] In one possible embodiment, referring to Figures 9A-9C, 10A-10C, and 11A-11C, the extended lines of the right-angled sides of the first hollow portions L1 of the two right-angled trapezoids corresponding to the same sub-pixel electrode group P00 overlap. Specifically, as shown in Figures 10A-10C and 11A-11C, the extended lines of the right-angled sides of the first hollow portions L1 of the two right-angled trapezoids corresponding to the same sub-pixel electrode group P00 overlap, and the two trapezoids may be merged together to form a single, integrated hole.

[0207] In one possible embodiment, referring to Figures 9A-9C, 10A-10C, and 11A-11C, in the same pixel electrode 14, the extension lines of the right-angled sides of the trapezoidal first hollow portion L1 corresponding to the two sub-pixel electrode groups P00 do not overlap. For example, as shown in Figure 9B, in the same pixel electrode 14, the extension line of the right-angled side of the trapezoidal first hollow portion L1 corresponding to the upper sub-pixel electrode group P00 does not overlap with the extension line of the right-angled side of the trapezoidal first hollow portion L1 corresponding to the lower sub-pixel electrode group P00. Specifically, in the same pixel electrode 14, the right-angled side of the trapezoidal first hollow portion L1 corresponding to the upper sub-pixel electrode group P00 is disposed adjacent to the right edge of the pixel electrode 14, while the right-angled side of the trapezoidal first hollow portion L1 corresponding to the lower sub-pixel electrode group P00 is disposed adjacent to the left edge of the pixel electrode 14.

[0208] In one possible embodiment, as shown in Figures 2A and 2F , the orthographic projection of the first hollow portion L1 on the array substrate 1 is X-shaped. The first hollow portion L1 includes a first sub-hollow portion L01 extending along a third direction G, and a second sub-hollow portion L02 extending along a fourth direction H. The first sub-hollow portion L01 and the second sub-hollow portion L02 are intersectingly disposed. Specifically, the first sub-hollow portion L01 is perpendicular to the second sub-hollow portion L02.

[0209] In one possible embodiment, referring to Figures 2A and 2F , the extension direction of one of the first sub-hollow portion L01 and the second sub-hollow portion L02 is parallel to the extension direction of the slit structure S of the sub-pixel electrode portion P0 in which it is located, while the extension direction of the other sub-hollow portion is perpendicular to the extension direction of the slit structure of the sub-pixel electrode portion in which it is located. For example, in the region where the first sub-pixel electrode portion P1 is located, the extension direction of the first sub-hollow portion L01 is parallel to the extension direction of the slit structure S, and the extension direction of the second sub-hollow portion L02 is perpendicular to the extension direction of the slit structure S; in the region where the second sub-pixel electrode portion P2 is located, the extension direction of the first sub-hollow portion L01 is perpendicular to the extension direction of the slit structure S, and the extension direction of the second sub-hollow portion L02 is parallel to the extension direction of the slit structure S.

[0210] In a possible implementation, referring to FIG. 6A to FIG. 6D , FIG. 10A to FIG. 10C , and FIG. 11A to FIG. 11D , the two first hollow portions L1 corresponding to the same sub-pixel electrode group P00 are an integrated structure.

[0211] In a possible implementation, referring to Figures 2A-2J, 3A-3C, 4A-4C, 5A-5C, 7A-7C, 8A-8C, and 9A-9C, the two first hollow portions L1 corresponding to the same sub-pixel electrode group P00 are separated structures.

[0212] In a possible embodiment, as shown in Figures 2A-2J, Figures 3A-3C, Figures 4A-4C, Figures 5A-5C, Figures 7A-7C, Figures 8A-8C, Figures 9A-9C, Figures 10A-10C, and Figures 12A-12B, the slit structure S is uniformly distributed in the entire sub-pixel electrode portion.

[0213] In one possible implementation, as shown in Figures 6A-6D and 11A-11D, the slit structure S is distributed only in a portion of the sub-pixel electrode portion P0, and the sub-pixel electrode portion P0 also includes a block structure F. That is, there are no slits within the block structure F. In the disclosed embodiment, the slit structure S is distributed only in a portion of the sub-pixel electrode portion P0, and the sub-pixel electrode portion P0 also includes a block structure F. This can increase the pixel brightness and transmittance in the area where the block structure F is located. At the same time, it can produce a variety of brightness distributions within the pixel, creating a visual effect with more than 8 domains.

[0214] In a possible embodiment, referring to Figures 6A-6D and 11A-11D, the distribution positions of the block structure F are different in the two sub-pixel electrode groups P00 of the same pixel electrode 14; specifically, for example, as shown in Figures 6A-6D and 11A-11D, the block structure F corresponding to the upper sub-pixel electrode group P00 is arranged against the right edge of the pixel electrode 14, and the block structure F corresponding to the lower sub-pixel electrode group P00 is arranged against the left edge of the pixel electrode 14; in the two sub-pixel electrode parts P0 of the same sub-pixel electrode group P00, the block structure F is an integrated structure. Specifically, for example, as shown in Figures 6A-6D and 11A-11D, the block structures F corresponding to the two sub-pixel electrode parts P0 in the upper sub-pixel electrode group P00 are an integrated structure.

[0215] In one possible embodiment, referring to Figures 6A-6D and 11A-11D, the orthographic projection of the first hollow portion L1 on the array substrate 1 at least partially overlaps with the orthographic projection of the block structure F on the array substrate 1. Specifically, for example, in conjunction with Figure 6A, the orthographic projection of the first hollow portion L1 on the array substrate 1 covers the orthographic projection of the block structure F on the array substrate 1. Specifically, the orthographic projection of the widest portion of the block structure F on the array substrate 1 can be disposed within the orthographic projection of the first hollow portion L1 on the array substrate 1. Specifically, for another example, as shown in Figure 11A, the orthographic projection of the first hollow portion L1 on the array substrate 1 partially overlaps with the orthographic projection of the block structure F on the array substrate 1.

[0216] In a possible embodiment, referring to FIG6A , a maximum length d1 of the orthographic projection of the block structure F on the array substrate 1 in the second direction Y is less than or equal to a maximum length d2 of the orthographic projection of the first hollow portion L1 on the array substrate 1 in the second direction Y; a maximum length d3 of the orthographic projection of the block structure F on the array substrate 1 in the first direction X is less than or equal to a maximum length d4 of the orthographic projection of the first hollow portion L1 on the array substrate 1 in the first direction X; in a possible embodiment, referring to FIG11A , a maximum length d1 of the orthographic projection of the block structure F on the array substrate 1 in the second direction Y is greater than or equal to a maximum length d2 of the orthographic projection of the first hollow portion L1 on the array substrate 1 in the second direction Y; a maximum length d3 of the orthographic projection of the block structure F on the array substrate 1 in the first direction X is greater than or equal to a maximum length d4 of the orthographic projection of the first hollow portion L1 on the array substrate 1 in the first direction X.

[0217] In one possible embodiment, referring to Figures 6A-6D and 11A-11D, within the same sub-pixel electrode group P00, the block structures F of different sub-pixel electrode portions P0 may be an integrally connected structure. Specifically, referring to Figure 6A, the block structure F may be a right triangle, and within the same sub-pixel electrode group P00, the right-angled sides of two block structures F of different sub-pixel electrode portions P0 coincide with each other; specifically, referring to Figure 11A, the block structure F may be a right trapezoid, and within the same sub-pixel electrode group P00, the two right-angled trapezoidal block structures F of different sub-pixel electrode portions P0 are arranged with their bases close to each other, that is, the bases of the two right-angled trapezoidal block structures F of different sub-pixel electrode portions P0 coincide with each other.

[0218] In a possible implementation, within the same sub-pixel electrode group P00 , the block structures F of different sub-pixel electrode portions P0 may also be separated from each other.

[0219] In one possible embodiment, referring to FIG. 11A to FIG. 11D , the block structure F may have a shape similar to that of the first hollow portion L1. For example, as shown in FIG. 11A , the shape of the first hollow portion L1 is a right-angled trapezoid, and the shape of the block structure F is also a right-angled trapezoid. Specifically, the block structure F may have a shape similar to that of the first hollow portion L1, but be arranged differently. For example, as shown in FIG. 11A , the bottom side of the first hollow portion L1 partially overlaps with the top side of the block structure F, the top side of the first hollow portion L1 partially overlaps with the bottom side of the block structure F, the right-angled side of the first hollow portion L1 at least partially overlaps with the right-angled side of the block structure F, and the hypotenuse of the first hollow portion L1 is arranged to intersect with the hypotenuse of the block structure F. Specifically, for example, the hypotenuse of the first hollow portion L1 is perpendicular to the hypotenuse of the block structure F.

[0220] Specifically, for example, referring to FIG11A , the block structure F is a right-angled trapezoid, and the orthographic projection of an acute angle corresponding to the long bottom side of the block structure F on the array substrate 1 does not overlap with the orthographic projection of the first hollow portion L1 on the array substrate 1; the orthographic projection of the right angle corresponding to the long bottom side of the block structure F on the array substrate 1 and the orthographic projection of the first hollow portion L1 on the array substrate 1 at least partially overlap.

[0221] In one possible embodiment, as shown in Figures 6A-6D, the block structure F may have a different shape from the first hollow portion L1. For example, as shown in Figure 6A, the first hollow portion L1 is rectangular, and the block structure F is triangular. Specifically, the block structure F may be in the shape of a right triangle. Specifically, as shown in Figure 6A, at least one right-angled side of the right-angled triangle block structure F coincides with at least one side of the rectangular first hollow portion L1; and the hypotenuse of the right-angled triangle block structure F coincides with the diagonal of the rectangular first hollow portion L1.

[0222] Specifically, in combination with Figures 2J, 3C, 4C, 5C, 6D, 7C, 8C, 9C, 10C, and 11D, when the first hollow portion L1 is arc-shaped, there will be areas of disorderly arrangement of the liquid crystal, and irregular dark lines will appear; when the edge of the first hollow portion L1 is parallel to the extension direction of the slit structure S, the dark lines will be aggravated and the transmittance will be reduced, as shown in Figures 2J and 7C; among the above figures, the transmittance of Figures 8C, 9C, and 10C is better.

[0223] Specifically, as shown in FIG14, an equivalent circuit diagram corresponding to a pixel electrode provided by an embodiment of the present disclosure is provided, wherein S is the data line on the left side of the pixel, that is, the signal line for transmitting the data signal to the current pixel electrode 14, that is, the data line electrically connected to the current pixel electrode 14, S is the data line on the right side of the pixel, and is also the data line of the horizontally adjacent pixels. The pixel circuit may include: a transistor, and the sub-pixel electrode group on each side of the gate line can form a first capacitor Cpd, a second capacitor Cgp, a liquid crystal capacitor Clc, a third capacitor Cpd, and a fourth capacitor Cpcom; wherein the overlapping area of ​​the pixel electrode 14 and the data line 15 can form a first capacitor Cpd The overlapping area of ​​the pixel electrode 14 and the gate line 16 can form a second capacitor Cgp, the pixel electrode 14 and the common electrode 22 can form a liquid crystal capacitor Clc, a third capacitor Cpd can be formed between the pixel electrode 14 and the adjacent data line 15, and a fourth capacitor Cpcom can be formed between the pixel electrode 14 and the first electrode 12. In addition, Cpp(n+1) can be formed between the first sub-pixel electrode portion P1 of the current pixel electrode 14 and the fourth sub-pixel electrode portion P4 of the previous pixel electrode 14, and Cpp(n-1) can be formed between the fourth sub-pixel electrode portion P4 of the current pixel electrode 14 and the first sub-pixel electrode portion P1 of the next pixel electrode 14. Among them, the position where the first hollow portion L1 is provided (that is, the area where the first electrode 12 is dug out) is bright, which is equivalent to the absence of Cpcom; while the position where the first hollow portion L1 is not provided is dark, which is equivalent to the presence of Cpcom.

[0224] In a possible embodiment, referring to Figures 15A to 15F and Figures 16A to 16H, Figure 15A is a schematic diagram of an array substrate including a plurality of sub-pixels provided in an embodiment of the present disclosure, Figure 15B is a schematic diagram of a single film layer of the layer where the gate line is located in Figure 15A, Figure 15C is a schematic diagram of a single film layer of the layer where the data line is located in Figure 15A, Figure 15D is a schematic diagram of a single film layer of the layer where the first electrode is located in Figure 15A, Figure 15E is a schematic diagram of a single film layer of the layer where the pixel electrode is located in Figure 15A, Figure 15F is a partially enlarged schematic diagram of Figure 15C, Figure 16A is a schematic diagram of a sub-pixel provided in an embodiment of the present disclosure, Figure 16B is a schematic diagram of a single film layer of the layer where the gate line is located in Figure 16A, and Figure 16C is a schematic diagram of a single film layer in the layer where the data line is located in Figure 16A, Figure 16D is a schematic diagram of a single film layer in the layer where the first electrode is located in Figure 16A, Figure 16E is a schematic diagram of a single film layer in the layer where the pixel electrode is located in Figure 16A, Figure 16F is a schematic diagram of Figure 16E without some labels, Figure 16G is a color resistance schematic diagram corresponding to Figure 16A, and Figure 16H is a black matrix schematic diagram corresponding to Figure 16A. The array substrate includes: a first substrate 11; a boundary portion PJ between two adjacent sub-pixel electrode portions P0 in the pixel electrode 14; at least part of the first hollow portion L1 is an orthographic projection on the first substrate 11, and has an overlapping area with the orthographic projection of the boundary portion PJ between the two adjacent sub-pixel electrode portions P0 on the first substrate 11.

[0225] In the embodiment of the present disclosure, for a display panel in a VA display mode in which the array substrate 1 is provided with a pixel electrode 14 and the counter substrate 2 is provided with a common electrode 22, a first electrode 12 having a first hollow portion L1 is further provided on the array substrate, so that different electric fields are formed in the area where the pixel electrode 14 is located with and without the first hollow portion L1, resulting in inconsistent degrees of liquid crystal deflection, forming a multi-domain effect, achieving a wide viewing angle compensation effect, and improving VA wide viewing angle color deviation; at the same time, the first hollow portion L1 is provided to reduce the storage capacitance Cst formed between the first electrode 12 and the pixel electrode 14, reduce the load, and optimize the charging rate or image quality; moreover, the orthographic projection of at least part of the first hollow portion L1 on the first substrate 11 has an overlapping area with the orthographic projection of the boundary portion PJ between two adjacent sub-pixel electrode portions P0 on the first substrate 11, that is, the first electrode 12 has a window at the boundary position of the adjacent sub-pixel electrode portions P0, which can make the dark lines of the display panel smaller and the transmittance higher during display.

[0226] Optionally, the pixel electrode 14 may not be provided with a slit, that is, the pixel electrode 14 is provided as a whole block structure, and the first electrode 12 is provided with a hollow structure. The hollow structure provided by the first electrode 12 is used to reduce the storage capacitance formed between the first electrode 12 and the pixel electrode 14, thereby improving the charging rate.

[0227] In the disclosed embodiment, the first electrode 12 can shield data signals and gate line signals, remove at least part of the common wiring of the array substrate, and thereby reduce the shading range around the data lines and gate lines, greatly improving the aperture ratio.

[0228] In one possible embodiment, as shown in Figures 15A-15F and 16A-16H , the multiple sub-pixel electrode portions P0 of the pixel electrode 14 include: a first sub-pixel electrode portion P1, a second sub-pixel electrode portion P2, a third sub-pixel electrode portion P3, and a fourth sub-pixel electrode portion P4, arranged sequentially along a first direction X. A first hollow portion L1 is provided in the region where at least one of the first sub-pixel electrode portion P1, the second sub-pixel electrode portion P2, the third sub-pixel electrode portion P3, and the fourth sub-pixel electrode portion P4 is located. Referring to Figure 15D , adjacent rows of first electrodes 12 are electrically connected via a connecting electrode portion LJ.

[0229] In a possible embodiment, referring to Figures 17A-17B, 19A-19B, 20A-20B, 21A-21B, and 22A-22B, the plurality of first hollow portions L1 include: a first type of hollow portion L11 located in the region where the first sub-pixel electrode portion P1 is located, a second type of hollow portion L12 located in the region where the second sub-pixel electrode portion P2 is located, a third type of hollow portion L13 located in the region where the third sub-pixel electrode portion P3 is located, and a fourth type of hollow portion L14 located in the region where the fourth sub-pixel electrode portion P4 is located;

[0230] The first type hollow portion L11 and the second type hollow portion L12 are an integrated structure, and their orthographic projection on the first substrate 11 overlaps with the orthographic projection on the first substrate 11 of the boundary portion PJ between the first sub-pixel electrode portion P1 and the second sub-pixel electrode P2;

[0231] The third type hollow portion L13 and the fourth type hollow portion L14 are an integrated structure, and their orthographic projection on the first substrate 11 has an overlapping area with the orthographic projection of the boundary PJ between the third sub-pixel electrode portion P3 and the fourth sub-pixel electrode portion P4 on the first substrate 11.

[0232] In the embodiment of the present disclosure, a first hollow portion L1 can be provided in the area where each sub-pixel electrode portion P0 is located, and each area where the sub-pixel electrode portion P0 is located can have areas with different degrees of liquid crystal deflection, thereby having more multi-domain display areas; and at least two first hollow portions L1 can be connected as an integrated structure, which can simplify the pattern shape of the first electrode having the first hollow portion L1 and simplify the production process of the array substrate.

[0233] In a possible embodiment, referring to Figures 18A-18B and Figures 19A-19B, the second type of hollow portion L12 and the third type of hollow portion L13 are an integrated structure, and their orthographic projection on the first substrate 11 has an overlapping area with the orthographic projection of the boundary portion PJ between the second sub-pixel electrode portion P2 and the third sub-pixel electrode P3 on the first substrate 11.

[0234] Specifically, for example, as shown in Figure 17A, the first type of hollow portion L11 and the second type of hollow portion L12 are an integrated structure, the third type of hollow portion L13 and the fourth type of hollow portion L14 are an integrated structure, and the second type of hollow portion L12 and the third type of hollow portion L13 can be disconnected and unconnected structures; specifically, for example, as shown in Figure 19A, the first type of hollow portion L11, the second type of hollow portion L12, the third type of hollow portion L13, and the fourth type of hollow portion L14 can be an integrated structure, which can reduce the load and improve the charging rate of the display panel.

[0235] In a possible embodiment, the first hollow portion L1 may be provided only in the area where part of the sub-pixel electrode portion P0 is located, referring to Figures 18A-18B and Figures 23A-23B, and the multiple first hollow portions L1 include: a second type of hollow portion L12 located in the area where the second sub-pixel electrode portion P2 is located, and a third type of hollow portion L13 located in the area where the third sub-pixel electrode portion P3 is located; the second type of hollow portion L12 and the third type of hollow portion L13 are an integrated structure, and their orthographic projection on the first substrate 11 has an overlapping area with the orthographic projection of the boundary portion PJ between the second sub-pixel electrode portion P2 and the third sub-pixel electrode P3 on the first substrate 11.

[0236] In one possible embodiment, the sub-pixel electrode portion P0 has multiple slit structures S extending in the same direction; the extension direction of the slit structure S in the first sub-pixel electrode portion P1 is parallel to the extension direction of the slit structure S in the third sub-pixel electrode portion P3, and the extension direction of the slit structure S in the second sub-pixel electrode portion P2 is parallel to the extension direction of the slit structure S in the fourth sub-pixel electrode portion P4.

[0237] In a possible embodiment, the angle formed by the extension direction of the slit structure S of the first sub-pixel portion P1 and the second direction Y can be 40° to 50°, for example, 45°; the angle formed by the extension direction of the slit structure S of the second sub-pixel portion P2 and the second direction Y can be 130° to 140°, for example, 135°.

[0238] In a possible embodiment, referring to Figures 20A-20B, 21A-21B, 22A-22B, and 23A-23B, the extension direction of the first hollow portion L1 is parallel to the extension direction of the slit structure S in the sub-pixel electrode portion P0 in which it is located. By setting the first hollow portion L1 to be adjusted according to the shape of the slit structure S in the sub-pixel electrode portion P0 and / or the pixel electrode 14, the shape, size, and dimensions of the first hollow portion L1 are adjusted to achieve the best comprehensive effect of improving color deviation, charging rate, and transmittance.

[0239] Specifically, as shown in Figures 20A-20B, the area where each sub-pixel electrode portion P0 is located is provided with a first hollow portion L1, and the first type of hollow portion L11 located in the area where the first sub-pixel electrode portion P1 is located is an integrally connected structure with the second type of hollow portion L12 located in the area where the second sub-pixel electrode portion P2 is located; the extension direction of the first type of hollow portion L11 located in the area where the first sub-pixel electrode portion P1 is located is parallel to the extension direction of the slit structure S in the area of ​​the first sub-pixel electrode portion P1; the extension direction of the second type of hollow portion L12 located in the area where the second sub-pixel electrode portion P2 is located is parallel to the extension direction of the slit structure S in the area of ​​the second sub-pixel electrode portion P2; the first type of hollow portion L11 and the second type of hollow portion L12 are an integrally connected structure, forming a "V"-shaped pattern. Similarly, the extension direction of the third type of hollow portion L13 located in the area where the third sub-pixel electrode portion P3 is located is parallel to the extension direction of the slit structure S within the area of ​​the third sub-pixel electrode portion P3; the extension direction of the fourth type of hollow portion L14 located in the area where the fourth sub-pixel electrode portion P4 is located is parallel to the extension direction of the slit structure S within the area of ​​the fourth sub-pixel electrode portion P4; the third type of hollow portion L13 and the fourth type of hollow portion L14 are an integrated connection structure, forming a "V"-shaped pattern.

[0240] Specifically, as shown in Figures 20A and 20B, the extension direction of the first type of hollow portion L11 can be parallel to the extension direction of one of the diagonals of the first sub-pixel electrode portion P1, and the length of the first type of hollow portion L11 along the extension direction of the diagonal is less than the length of the diagonal; the extension direction of the second type of hollow portion L12 can be parallel to the extension direction of one of the diagonals of the second sub-pixel electrode portion P2, and the length of the second type of hollow portion L12 along the extension direction of the diagonal is less than the length of the diagonal; the extension direction of the third type of hollow portion L13 can be parallel to the extension direction of one of the diagonals of the third sub-pixel electrode portion P3, and the length of the third type of hollow portion L13 along the extension direction of the diagonal is less than the length of the diagonal; the extension direction of the fourth type of hollow portion L14 can be parallel to the extension direction of one of the diagonals of the fourth sub-pixel electrode portion P4, and the length of the fourth type of hollow portion L14 along the extension direction of the diagonal is less than the length of the diagonal.

[0241] Specifically, as shown in Figures 21A-21B and Figures 22A-22B, the area where each sub-pixel electrode portion P0 is located is provided with a first hollow portion L1, and the first type of hollow portion L11, the second type of hollow portion L12, the third type of hollow portion L13, and the fourth type of hollow portion L14 are an integrated connection structure; the extension direction of the first type of hollow portion L11 located in the area where the first sub-pixel electrode portion P1 is located is parallel to the extension direction of the slit structure S in the area of ​​the first sub-pixel electrode portion P1; the extension direction of the second type of hollow portion L12 located in the area where the second sub-pixel electrode portion P2 is located is parallel to the extension direction of the slit structure S in the area of ​​the second sub-pixel electrode portion P2. The extension direction of the slit structure S in the electrode portion P2 area is parallel; the extension direction of the third type of hollow portion L13 located in the area where the third sub-pixel electrode portion P3 is located is parallel to the extension direction of the slit structure S in the area of ​​the third sub-pixel electrode portion P3; the extension direction of the fourth type of hollow portion L14 located in the area where the fourth sub-pixel electrode portion P4 is located is parallel to the extension direction of the slit structure S in the area of ​​the fourth sub-pixel electrode portion P4; the first type of hollow portion L11, the second type of hollow portion L12, the third type of hollow portion L13, and the fourth type of hollow portion L14 are an integrated connection structure, forming a "W" shaped pattern.

[0242] Specifically, as shown in FIG21A-FIG21B, the extension direction of the first type hollow portion L11 may be parallel to the extension direction of one of the diagonals of the first sub-pixel electrode portion P1, and the length of the first type hollow portion L11 along the extension direction of the diagonal is less than the length of the diagonal; the second type hollow portion L12 The extension direction of the third type of hollow portion L13 may be parallel to the extension direction of one of the diagonals of the second sub-pixel electrode portion P2, and the length of the second type of hollow portion L12 in the extension direction along the diagonal is equal to the length of the diagonal; optionally, the projection of the second type of hollow portion L12 on the first substrate 11 covers one of the diagonals of the second sub-pixel electrode portion P2; the extension direction of the third type of hollow portion L13 may be parallel to the extension direction of one of the diagonals of the third sub-pixel electrode portion P3, and the length of the third type of hollow portion L13 in the extension direction along the diagonal is equal to the length of the diagonal, optionally, the projection of the third type of hollow portion L13 on the first substrate 11 covers one of the diagonals of the third sub-pixel electrode portion P3; the extension direction of the fourth type of hollow portion L14 may be parallel to the extension direction of one of the diagonals of the fourth sub-pixel electrode portion P4, and the length of the fourth type of hollow portion L14 in the extension direction along the diagonal is less than the length of the diagonal.

[0243] Specifically, as shown in Figures 21A and 21B, the extension direction of the first type of hollow portion L11 can be parallel to the extension direction of one of the diagonals of the first sub-pixel electrode portion P1, and the length of the first type of hollow portion L11 along the extension direction of the diagonal is equal to the length of the diagonal. Optionally, the projection of the first type of hollow portion L11 on the first substrate 11 covers the diagonal of the first sub-pixel electrode portion P1; the extension direction of the second type of hollow portion L12 can be parallel to the extension direction of one of the diagonals of the second sub-pixel electrode portion P2, and the length of the second type of hollow portion L12 along the extension direction of the diagonal is equal to the length of the diagonal. Optionally, the projection of the second type of hollow portion L12 on the first substrate 11 covers the second sub-pixel electrode The extension direction of the third type of hollow portion L13 can be parallel to the extension direction of one of the diagonals of the third sub-pixel electrode portion P3, and the length of the third type of hollow portion L13 along the extension direction of the diagonal is equal to the length of the diagonal. Optionally, the projection of the third type of hollow portion L13 on the first substrate 11 covers the diagonal of the third sub-pixel electrode portion P3. The extension direction of the fourth type of hollow portion L14 can be parallel to the extension direction of one of the diagonals of the fourth sub-pixel electrode portion P4, and the length of the fourth type of hollow portion L14 along the extension direction of the diagonal is equal to the length of the diagonal. Optionally, the projection of the fourth type of hollow portion L14 on the first substrate 11 covers the diagonal of the fourth sub-pixel electrode portion P4. Referring to Figures 21A and 22A, increasing the length of the first hollow portion L1 can improve the charging rate of the display panel.

[0244] Specifically, as shown in Figures 23A and 23B, only the area where the second sub-pixel electrode portion P2 and the third sub-pixel electrode portion P3 are located is provided with the first hollow portion L1, and the second type of hollow portion L12 located in the area where the second sub-pixel electrode portion P2 is located is an integrally connected structure with the third type of hollow portion L13 located in the area where the third sub-pixel electrode portion P3 is located; the extension direction of the second type of hollow portion L12 located in the area where the second sub-pixel electrode portion P2 is located is parallel to the extension direction of the slit structure S in the area of ​​the second sub-pixel electrode portion P2; the extension direction of the third type of hollow portion L13 located in the area where the third sub-pixel electrode portion P3 is located is parallel to the extension direction of the slit structure S in the area of ​​the third sub-pixel electrode portion P3; the second type of hollow portion L12 and the third type of hollow portion L13 are an integrally connected structure, forming a "V"-shaped pattern.

[0245] Specifically, as shown in Figures 23A-23B, the extension direction of the second type of hollow portion L12 can be parallel to the extension direction of one of the diagonals of the second sub-pixel electrode portion P2, and the length of the second type of hollow portion L12 along the extension direction of the diagonal is less than the length of the diagonal; the extension direction of the third type of hollow portion L13 can be parallel to the extension direction of one of the diagonals of the third sub-pixel electrode portion P3, and the length of the third type of hollow portion L13 along the extension direction of the diagonal is less than the length of the diagonal.

[0246] In a possible embodiment, referring to Figures 16A-16D, 17A-17B, 18A-18B, and 19A-19B, the positive projection shape of the first hollow portion L1 on the first substrate 11 is a rectangle, and the rectangle includes: a first outer edge w1 extending along the first direction X, and a second outer edge w2 extending along the second direction Y.

[0247] In a possible embodiment, as shown in Figure 16F, the junction portion PJ between the first sub-pixel electrode portion P1 and the second sub-pixel electrode portion P2 has a first slit SW1 extending along the second direction Y; the junction portion PJ between the third sub-pixel electrode portion P3 and the fourth sub-pixel electrode portion P4 has a second slit SW2 extending along the second direction Y.

[0248] In a possible implementation, as shown in FIG. 16F , a boundary portion PJ between the second sub-pixel electrode portion P2 and the third sub-pixel electrode portion P3 has a connecting electrode PD extending along the second direction Y.

[0249] In one possible embodiment, as shown in Figures 15A-15F and 16A-16F, the orthographic projection of the first electrode 12 on the first substrate 11 covers the orthographic projection of the data line 15 on the first substrate 11. This shields the signal of the data line 15, improving the problem of conventional technology that requires additional shielding structures in the area where the data line 15 is located, resulting in a low aperture ratio of the display panel.

[0250] In one possible embodiment, as shown in Figures 15A-15F and 16A-16F, the display panel further includes a plurality of gate lines 16 located on the array substrate, the plurality of gate lines 16 extending along the second direction Y. The orthographic projections of the gate lines 16 on the first substrate 11 overlap with the orthographic projections of the gaps between two adjacent pixel electrodes 14 on the first substrate 11. The orthographic projections of the first electrodes 12 on the first substrate 11 cover at least a portion of the orthographic projections of the gate lines 16 on the first substrate 11. This shields the signals of the gate lines 16, improving the conventional technique of requiring additional shielding structures in the area where the gate lines 16 are located, which results in a low aperture ratio of the display panel.

[0251] In one possible embodiment, as shown in Figures 16A-16F , the gate line 16 includes a gate line main portion 163 extending along a first direction X, and a gate electrode 164 extending from one side of the gate line main portion 163. The first electrode 12 includes a third hollow portion L3. The orthographic projection of the third hollow portion L3 on the first substrate 11 covers at least a portion of the orthographic projection of the gate electrode 164 on the first substrate 11. This prevents the first electrode 12 from affecting the transistors and thus affecting the normal display of the display panel.

[0252] In one possible embodiment, as shown in Figures 16A-16F, the array substrate further includes: a first common line 5 extending along the second direction Y, wherein the orthographic projection of the first common line 5 on the first substrate 11 overlaps with the orthographic projection of the gap between two adjacent pixel electrodes 14 on the first substrate 11; the first common line 5 includes: a first common main portion 51 extending along the second direction Y, and a first common extension portion 52 extending from the first common main portion 51 toward the gate line 16; and the orthographic projection of the third hollow portion L3 on the first substrate 11 covers at least a portion of the orthographic projection of the first common extension portion 52 on the first substrate 11. Optionally, the first common line 5 is electrically connected to the first electrode 12, or the first common line 5 and the first electrode 12 transmit the same signal. Optionally, the orthographic projections of the first common line 5 and the pixel electrode 14 in a direction perpendicular to the first substrate 11 at least partially overlap, and the two can form a storage capacitor.

[0253] In a possible embodiment, referring to FIG16C or FIG15F , the display panel further includes: a transistor first electrode 151 electrically connected to the data line 15, and a transistor second electrode 152; the transistor second electrode 152 includes: a second electrode first portion 1521 extending along the second direction Y, and a second electrode second portion 1522 extending from the second electrode first portion 1521 along the first direction X; at least a portion of the orthographic projection of the second electrode second portion 1522 on the first substrate 11 has an overlapping area with the orthographic projection of the first common extension portion 52 on the first substrate 11; the orthographic projection of the second electrode second portion 1522 on the first substrate 11 has an overlapping area with the orthographic projection of the gate 164 on the first substrate 11.

[0254] In a possible embodiment, referring to FIG16C or FIG15F , the second pole first portion 1521 includes: a second pole first sub-portion TB1 and a second pole second sub-portion TB2 extending along the second direction Y; a width a1 of the second pole second sub-portion TB1 in the first direction X is smaller than a2 of the second pole second sub-portion TB2 in the first direction X; and an orthographic projection of the second pole second sub-portion TB2 on the first substrate 11 has an overlapping area with the orthographic projection of the first common extension portion 52 on the first substrate 11.

[0255] In one possible embodiment, as shown in Figures 24, 25, and 26, the data line 15 is located on the side of the first electrode 12 facing away from the pixel electrode 14. The array substrate further includes a first insulating layer 18 located between the data line 15 and the first electrode 12. The first insulating layer 18 includes a color resist layer 24. In the disclosed embodiment, the conventional first insulating layer 18 can be replaced by a color resist layer, saving one insulating layer manufacturing process and effectively reducing the display panel manufacturing cost.

[0256] In one possible embodiment, as shown in Figures 25 and 26 , the first insulating layer 18 includes a transition layer 180 located on the side of the color resist layer 24 facing the first electrode 12. In the disclosed embodiment, when the color resist layer replaces the first insulating layer, saving one insulating layer process step to reduce costs, to enhance the adhesion of the first electrode 12 above the color resist layer 24 and prevent crystallization of the first electrode 12 on the surface of the color resist layer 24, the transition layer 180 may be located on the side of the color resist layer 24 facing the first electrode 12 to improve the adhesion of the first electrode 12 and alleviate crystallization of the first electrode 12.

[0257] Optionally, the transition layer 180 may be an insulating layer, and the transition layer 180 may include silicon nitride and / or silicon oxide.

[0258] In a possible implementation, referring to FIG. 25 and FIG. 26 , a gate insulating layer 19 may be further disposed between the data line 15 and the first substrate 11 .

[0259] Based on the same inventive concept, the present disclosure also provides a display device including the display panel provided in the present disclosure. The implementation of the display device can refer to the above-mentioned display panel embodiment, and the repeated parts will not be repeated.

[0260] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0261] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0262] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A display panel, wherein: include: An array substrate and a counter substrate arranged opposite to each other; A plurality of data lines are located on the array substrate and extend along a first direction; A plurality of pixel electrodes are located on the array substrate, and at least one of the plurality of pixel electrodes comprises: a plurality of sub-pixel electrode portions arranged along the first direction; A first electrode, located on the array substrate, the first electrode comprising a plurality of first hollow portions, the orthographic projection of the first hollow portions on the array substrate being located within the orthographic projection of the sub-pixel electrode portion on the array substrate; The common electrode is located on the opposite substrate.

2. The display panel according to claim 1, wherein: The first electrode is located at a side of the pixel electrode away from the opposite substrate.

3. The display panel according to claim 1 or 2, wherein: The first electrode and the common electrode are loaded with the same signal.

4. The display panel according to any one of claims 1 to 3, wherein: The multiple sub-pixel electrode portions include: two sub-pixel electrode groups distributed along the first direction, the sub-pixel electrode group includes two sub-pixel electrode portions, the sub-pixel electrode portion has a plurality of slit structures extending along the same direction, and the slit structures of two adjacent sub-pixel electrode portions included in the sub-pixel electrode group extend in different directions.

5. The display panel according to claim 4, wherein: An axis extending perpendicular to the first direction is provided between two sub-pixel electrode portions of the same sub-pixel electrode group; The two first hollow portions corresponding to the same sub-pixel electrode group are symmetrical about the axis.

6. The display panel according to claim 5, wherein: The first hollow portion is located in a central area of ​​the orthographic projection of the array substrate, and overlaps with the sub-pixel electrode portion in a central area of ​​the orthographic projection of the array substrate.

7. The display panel according to claim 6, wherein: The orthographic projection of the first hollow portion on the array substrate is circular or elliptical.

8. The display panel according to claim 6, wherein: The orthographic projection of the first hollow portion on the array substrate is a rectangle, and at least one side of the rectangle is parallel to the outer edge of the sub-pixel electrode portion.

9. The display panel according to claim 8, wherein: The first hollow portion includes a first edge extending along the first direction; The extension lines of the first sides of two first hollow portions corresponding to the same sub-pixel electrode group overlap.

10. The display panel according to claim 9, wherein: In the same pixel electrode, an extension line of at least one of the first sides of the first hollowed-out portions corresponding to two sub-pixel electrode groups does not overlap.

11. The display panel according to claim 6, wherein: The orthographic projection of the first hollow portion on the array substrate is a hexagon, and at least one side of the hexagon is parallel to the outer edge of the sub-pixel electrode portion.

12. The display panel according to claim 11, wherein: At least one side of the hexagon is parallel to an extending direction of the slit structure of the sub-pixel electrode portion.

13. The display panel according to claim 11 or 12, wherein: At least one side of the hexagon is perpendicular to an extending direction of the slit structure of the sub-pixel electrode portion.

14. The display panel according to claim 5, wherein: The orthographic projection of the first hollow portion on the array substrate is a right-angled trapezoid, at least one side of the right-angled trapezoid is parallel to the outer edge of the sub-pixel electrode portion, and the hypotenuse of the right-angled trapezoid intersects with the extension direction of the slit structure.

15. The display panel according to claim 14, wherein: The right-angled side of the right-angled trapezoid extends along the first direction, and the hypotenuse of the right-angled trapezoid is perpendicular to the extending direction of the slit structure.

16. The display panel according to claim 14 or 15, wherein: The top sides of the first hollowed-out parts of two right-angled trapezoids corresponding to the same sub-pixel electrode group are arranged close to each other.

17. The display panel according to claim 14 or 15, wherein: The bottom sides of the first hollowed-out parts of two right-angled trapezoids corresponding to the same sub-pixel electrode group are arranged close to each other.

18. The display panel according to any one of claims 14 to 17, wherein: The extended lines of the right-angled sides of the first hollowed-out parts of the two right-angled trapezoids corresponding to the same sub-pixel electrode group overlap.

19. The display panel according to any one of claims 14 to 18, wherein: In the same pixel electrode, the extended lines of the right-angled sides of the trapezoidal first hollowed-out portions corresponding to the two sub-pixel electrode groups do not overlap.

20. The display panel according to claim 6, wherein: The orthographic projection of the first hollow portion on the array substrate is X-shaped, and the first hollow portion includes: a first sub-hollow portion extending along a third direction, and a second sub-hollow portion extending along a fourth direction, and the first sub-hollow portion and the second sub-hollow portion are arranged crosswise.

21. The display panel according to claim 20, wherein: An extension direction of one of the first sub-hollow portion and the second sub-hollow portion is parallel to an extension direction of the slit structure of the sub-pixel electrode portion, and an extension direction of the other sub-hollow portion is perpendicular to an extension direction of the slit structure of the sub-pixel electrode portion.

22. The display panel according to any one of claims 1 to 21, wherein: The two first hollow portions corresponding to the same sub-pixel electrode group are an integrated structure.

23. The display panel according to any one of claims 1 to 22, wherein: The two first hollow portions corresponding to the same sub-pixel electrode group are separated structures.

24. The display panel according to any one of claims 4 to 23, wherein: The slit structures are evenly distributed throughout the sub-pixel electrode portion.

25. The display panel according to any one of claims 4 to 23, wherein: The slit structure is distributed only in a partial area of ​​the sub-pixel electrode portion, and the sub-pixel electrode portion also includes a block structure.

26. The display panel according to claim 25, wherein: In the two sub-pixel electrode groups of the same pixel electrode, the block structures are distributed at different positions; In the two sub-pixel electrode portions of the same sub-pixel electrode group, the block structure is an integrated structure.

27. The display panel according to claim 25 or 26, wherein: The orthographic projection of the first hollow portion on the array substrate at least partially overlaps with the orthographic projection of the block structure on the array substrate.

28. The display panel according to any one of claims 4 to 27, wherein: The plurality of sub-pixel electrode portions include: a first sub-pixel electrode portion, a second sub-pixel electrode portion, a third sub-pixel electrode portion, and a fourth sub-pixel electrode portion sequentially arranged along the first direction; An extension direction of the slit structure of the first sub-pixel electrode portion is the same as an extension direction of the slit structure of the third sub-pixel electrode portion, and an extension direction of the slit structure of the second sub-pixel electrode portion is the same as an extension direction of the slit structure of the fourth sub-pixel electrode portion.

29. The display panel according to claim 28, wherein: The display panel further comprises a plurality of gate lines located on the array substrate, and the plurality of gate lines extend along a second direction; The orthographic projection of the gate line on the array substrate has an overlapping area with the orthographic projection of the gap between the second sub-pixel electrode portion and the third sub-pixel electrode portion on the array substrate.

30. The display panel according to claim 29, wherein: The gate line includes a first gate line hollow; an orthographic projection of the first gate line hollow on the array substrate overlaps with an orthographic projection of a portion of the data line on the array substrate.

31. The display panel according to claim 30, wherein: The pixel electrode further includes: a connecting portion connecting the second sub-pixel electrode portion and the third sub-pixel electrode portion; The gate line further includes a second gate line hollowing out, wherein an orthographic projection of the second gate line hollowing out on the array substrate at least partially overlaps with an orthographic projection of the connecting portion on the array substrate.

32. The display panel according to claim 31, wherein: Extension lines of the connection portions of two adjacent pixel electrodes in the first direction do not overlap.

33. The display panel according to claim 31 or 32, wherein: The first electrode further includes: a second hollow portion, wherein the orthographic projection of the second hollow portion on the array substrate covers the orthographic projection of the connecting portion on the array substrate.

34. The display panel according to any one of claims 1 to 3, wherein: The array substrate comprises: a first substrate; There is a boundary between two adjacent sub-pixel electrode portions in the pixel electrode; the orthographic projection of at least part of the first hollow portion on the first substrate is parallel to the orthographic projection of the boundary on the first substrate. The projections have overlapping areas.

35. The display panel according to claim 34, wherein: The plurality of sub-pixel electrode portions of the pixel electrode include: a first sub-pixel electrode portion, a second sub-pixel electrode portion, a third sub-pixel electrode portion, and a fourth sub-pixel electrode portion sequentially arranged along the first direction; The first hollow portion is disposed in a region where at least one of the first sub-pixel electrode portion, the second sub-pixel electrode portion, the third sub-pixel electrode portion, and the fourth sub-pixel electrode portion is located.

36. The display panel according to claim 35, wherein: The plurality of first hollow portions include: a first type of hollow portion located in the region where the first sub-pixel electrode portion is located, a second type of hollow portion located in the region where the second sub-pixel electrode portion is located, a third type of hollow portion located in the region where the third sub-pixel electrode portion is located, and a fourth type of hollow portion located in the region where the fourth sub-pixel electrode portion is located; The first type of hollow portion and the second type of hollow portion are an integrated structure, and have an overlapping area in the orthographic projection of the first substrate and the orthographic projection of the boundary between the first sub-pixel electrode portion and the second sub-pixel electrode portion in the first substrate; The third type of hollow portion and the fourth type of hollow portion are an integrated structure, and have an overlapping area in the orthographic projection of the first substrate with the boundary between the third sub-pixel electrode portion and the fourth sub-pixel electrode portion in the orthographic projection of the first substrate.

37. The display panel according to claim 36, wherein: The second type of hollow portion and the third type of hollow portion are an integrated structure, and have an overlapping area in the orthographic projection of the first substrate with the boundary portion between the second sub-pixel electrode portion and the third sub-pixel electrode portion in the orthographic projection of the first substrate.

38. The display panel according to claim 35, wherein: The plurality of first hollow portions include: a second type of hollow portion located in the area where the second sub-pixel electrode portion is located, and a third type of hollow portion located in the area where the third sub-pixel electrode portion is located; The second type of hollow portion and the third type of hollow portion are an integrated structure, and have an overlapping area in the orthographic projection of the first substrate with the boundary portion between the second sub-pixel electrode portion and the third sub-pixel electrode portion in the orthographic projection of the first substrate.

39. The display panel according to any one of claims 35 to 38, wherein: The sub-pixel electrode portion has a plurality of slit structures extending in the same direction; An extension direction of the slit structure in the first sub-pixel electrode portion is parallel to an extension direction of the slit structure in the third sub-pixel electrode portion, and an extension direction of the slit structure in the second sub-pixel electrode portion is parallel to an extension direction of the slit structure in the fourth sub-pixel electrode portion.

40. The display panel according to claim 39, wherein: An extension direction of the first hollow portion is parallel to an extension direction of the slit structure in the sub-pixel electrode portion where the first hollow portion is located.

41. The display panel according to any one of claims 35 to 39, wherein: The orthographic projection shape of the first hollow portion on the first substrate is a rectangle, and the rectangle includes: a first outer edge extending along the first direction, and a second outer edge extending along the second direction.

42. The display panel according to any one of claims 35 to 41, wherein: The boundary between the first sub-pixel electrode portion and the second sub-pixel electrode portion has a first slit extending along the second direction; the boundary between the third sub-pixel electrode portion and the fourth sub-pixel electrode portion has a second slit extending along the second direction.

43. The display panel according to claim 42, wherein: The boundary portion between the second sub-pixel electrode portion and the third sub-pixel electrode portion has a connecting electrode extending along the second direction.

44. The display panel according to any one of claims 35 to 43, wherein: The orthographic projection of the first electrode on the substrate covers the orthographic projection of the data line on the substrate.

45. The display panel according to any one of claims 35 to 44, wherein: The display panel further comprises a plurality of gate lines located on the array substrate, and the plurality of gate lines extend along a second direction; The orthographic projection of the gate line on the first substrate and the orthographic projection of the gap between two adjacent pixel electrodes on the first substrate have an overlapping area; The orthographic projection of the first electrode on the first substrate covers at least a portion of the orthographic projection of the gate line on the first substrate.

46. ​​The display panel according to claim 45, wherein: The gate line comprises: a gate line main portion extending along the first direction, and a gate extending from one side of the gate line main portion; The first electrode comprises: a third hollow portion; the third hollow portion is located on the positive side of the first substrate The projection covers at least a portion of the positive projection of the gate on the first substrate.

47. The display panel according to claim 46, wherein: The array substrate further comprises: a first common wiring extending along the second direction, wherein an orthographic projection of the first common wiring on the first substrate and an orthographic projection of a gap between two adjacent pixel electrodes on the first substrate have an overlapping area; The first common wiring includes: a first common main portion extending along the second direction, and a first common extension portion extending from the first common main portion toward one side of the gate line; The orthographic projection of the third hollow portion on the first substrate covers at least a portion of the orthographic projection of the first common extension portion on the first substrate.

48. The display panel according to claim 47, wherein: The display panel further includes: a first transistor electrode electrically connected to the data line, and a second transistor electrode; The second electrode of the transistor comprises: a second electrode first portion extending along a second direction, and a second electrode second portion extending from the second electrode first portion along the first direction; At least part of the orthographic projection of the second portion of the second pole on the first substrate has an overlapping area with the orthographic projection of the first common extension portion on the first substrate; the orthographic projection of the second portion of the second pole on the first substrate has an overlapping area with the orthographic projection of the gate on the first substrate.

49. The display panel according to claim 48, wherein: The second pole first portion includes: a second pole first sub-portion and a second pole second sub-portion extending along the second direction; the width of the second pole second sub-portion in the first direction is smaller than the width of the second pole second sub-portion in the first direction; An orthographic projection of the second sub-portion of the second pole on the first substrate has an overlapping area with an orthographic projection of the first common extension portion on the first substrate.

50. The display panel according to any one of claims 35 to 49, wherein: The data line is located at a side of the first electrode away from the pixel electrode; the array substrate further comprises: a first insulating layer located between the data line and the first electrode, the first insulating layer comprising a color resist layer.

51. The display panel according to claim 50, wherein: The first insulating layer includes: a transition layer located on a side of the color resist layer facing the first electrode.

52. A display device, wherein: Comprising a display panel as described in any one of claims 1-51.

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