Display panel and manufacturing method therefor, and display apparatus

Abstract

A display panel and a manufacturing method therefor, and a display apparatus. The display panel comprises: a base substrate (100); a transistor device layer (200); at least one metal layer, arranged on the side of the transistor device layer (200) away from the base substrate (100) and comprising a plurality of metal wirings (01) extending in a first direction (Y); a first insulating layer (405), arranged on the side surface of the at least one metal layer away from the base substrate (100); a first electrode layer (501), arranged on the side surface of the first insulating layer (405) away from the base substrate (100), the first electrode layer (501) comprising a plurality of first electrode blocks; and a pixel definition layer (600), comprising a plurality of first limiting dams (601) extending in the first direction (Y) and a plurality of second limiting dams (602) extending in a second direction (X), wherein the orthographic projections of the metal wirings (01) on the base substrate (100) are located within the orthographic projections of the first limiting dams (601) on the base substrate (100), the thickness of at least one metal layer among the at least one metal layer is greater than the thickness of the first insulating layer (405), and the thickness of the metal layer is at least 0.5 μm greater than the thickness of the first insulating layer (405).

Description

Display panel, manufacturing method, and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202310723461.0 filed on June 16, 2023, entitled “Display panel, manufacturing method, and display device.” The entire contents of this Chinese patent application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0004] The methods for fabricating the organic functional thin film layers of organic light-emitting diodes (OLEDs) are divided into vacuum thermal deposition and solution-casting methods. Solution-casting methods are further subdivided into spin coating, inkjet printing, and screen printing.

[0005] Inkjet printing uses a solvent to melt the organic OLED material, then prints the material directly onto the substrate surface to form the light-emitting functional layer. However, due to the inherent characteristics of the printing technology, the resulting light-emitting functional layer can suffer from factors such as the coffee ring effect, which can affect film quality and lead to uneven light emission.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

[0007] Summary of the Invention

[0008] The present disclosure aims to provide a display panel and a manufacturing method thereof, and a display device to improve the coffee ring effect.

[0009] To achieve the above-mentioned purpose, the present invention adopts the following technical solutions:

[0010] According to a first aspect of the present disclosure, there is provided a display panel, comprising:

[0011] substrate;

[0012] A transistor device layer is provided on one side of the base substrate;

[0013] at least one metal layer, disposed on a side of the transistor device layer away from the substrate, and comprising a plurality of metal traces extending along a first direction;

[0014] A first insulating layer is provided on a surface of the at least one metal layer away from the base substrate;

[0015] A first electrode layer is provided on a surface of the first insulating layer away from the base substrate, the first electrode layer comprising a plurality of first electrode blocks;

[0016] a pixel definition layer comprising a plurality of first defining dams extending along the first direction and a plurality of second defining dams extending along the second direction, wherein the plurality of first defining dams and the plurality of second defining dams intersect to define a plurality of pixel openings, wherein in a direction perpendicular to the base substrate, the pixel openings correspond one-to-one to the first electrode blocks;

[0017] The orthographic projection of the metal trace on the substrate is located within the orthographic projection of the first limiting dam on the substrate;

[0018] The thickness of at least one metal layer among the at least one metal layer is greater than that of the first insulating layer, and the thickness of the metal layer is at least 0.5 μm greater than that of the first insulating layer.

[0019] In an exemplary embodiment of the present disclosure, the metal trace has a first surface close to the substrate substrate and a second surface away from the substrate substrate, and a side wall connecting the first surface and the second surface, and a first angle is formed between the side wall of the metal trace and the first surface of the metal trace, and the first angle of at least some of the multiple metal traces is 70°-90°.

[0020] In an exemplary embodiment of the present disclosure, the at least one metal layer comprises:

[0021] A first metal layer is provided on a side of the transistor device layer away from the substrate, and the plurality of metal traces are distributed in the first metal layer;

[0022] The first angle of the metal traces distributed in the first metal layer is 70°-90°.

[0023] In an exemplary embodiment of the present disclosure, the at least one metal layer comprises:

[0024] A first metal layer is provided on a side of the transistor device layer away from the substrate, and at least part of the plurality of metal traces are distributed in the first metal layer;

[0025] a second metal layer, disposed on a side of the first metal layer away from the substrate, wherein at least some of the plurality of metal traces are distributed in the second metal layer;

[0026] The first angle of the metal traces distributed in the first metal layer is 70°-90° and / or the first angle of the metal traces distributed in the second metal layer is 70°-90°.

[0027] In an exemplary embodiment of the present disclosure, an orthographic projection of the metal traces distributed in the first metal layer on the substrate does not overlap with an orthographic projection of the metal traces distributed in the second metal layer on the substrate.

[0028] In an exemplary embodiment of the present disclosure, the thickness of at least one metal layer among the at least one metal layer is not less than 0.7 μm.

[0029] In an exemplary embodiment of the present disclosure, the single metal layer in the at least one metal layer includes a first sub-metal layer and a second sub-metal layer stacked in a direction away from the substrate;

[0030] The thickness of the first sub-metal layer is greater than that of the second sub-metal layer, and the thickness of the first sub-metal layer is not less than 0.5 μm.

[0031] In an exemplary embodiment of the present disclosure, the single metal layer in the at least one metal layer further includes a third sub-metal layer, and the third sub-metal layer is provided on a side of the first sub-metal layer close to the base substrate;

[0032] The thickness of the first sub-metal layer is greater than the thickness of the third sub-metal layer.

[0033] In an exemplary embodiment of the present disclosure, the thickness of the first insulating layer is no greater than 0.2 μm.

[0034] In an exemplary embodiment of the present disclosure, the plurality of metal traces include a target metal trace, and a shortest distance between an edge of an orthographic projection of the target metal trace on the substrate and an edge of an orthographic projection of a corresponding first defining dam on the substrate is no greater than 2 μm;

[0035] The first included angle of the target metal trace is 70°-90°, and the thickness of the target metal trace is not less than 0.7 μm.

[0036] In an exemplary embodiment of the present disclosure, the base substrate includes a display area and a dummy area located at the periphery of the display area;

[0037] The plurality of first electrode blocks include a plurality of normal electrodes located in the display area and a plurality of dummy electrodes located in the dummy area, the normal electrodes are electrically connected to the transistor device layer, and the dummy electrodes are electrically insulated from the transistor device layer;

[0038] The orthographic projection of the metal traces distributed in the second metal layer on the substrate is located in the virtual area.

[0039] In an exemplary embodiment of the present disclosure, no organic material layer is included between the at least one metal layer and the first electrode layer.

[0040] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0041] a light-emitting functional layer, disposed on a side of the first electrode layer away from the base substrate, and at least partially located within the pixel opening;

[0042] A second electrode layer is provided on a surface of the pixel definition layer and the light-emitting functional layer that is away from the base substrate;

[0043] The second electrode layer is connected to the metal layer closest to the second electrode layer among the at least one metal layer through a first via hole in the second defining dam.

[0044] In an exemplary embodiment of the present disclosure, the metal layer closest to the second electrode layer among the at least one metal layer is a third metal layer;

[0045] The metal traces distributed in the third metal layer have a connection block, and the connection block is located at the intersection of the first limiting dam and the second limiting dam;

[0046] The size of the connecting block in the second direction is larger than the size of other areas of the metal trace in the second direction;

[0047] The orthographic projection of the connecting block on the base substrate is located within the orthographic projection of the first via hole on the base substrate.

[0048] In an exemplary embodiment of the present disclosure, the thickness of the third metal layer is not less than 0.7 μm.

[0049] In an exemplary embodiment of the present disclosure, the third metal layer includes a first sub-metal layer and a second sub-metal layer stacked in a direction away from the substrate;

[0050] The thickness of the first sub-metal layer is greater than that of the second sub-metal layer, and the thickness of the first sub-metal layer is not less than 0.5 μm.

[0051] In an exemplary embodiment of the present disclosure, the hardness of the first sub-metal layer is less than the hardness of the second sub-metal layer.

[0052] In an exemplary embodiment of the present disclosure, the number of metal layers in the at least one metal layer is multiple, wherein the metal layer located on a side of the third metal layer close to the base substrate and closest to the third metal layer is the fourth metal layer;

[0053] The metal traces distributed in the third metal layer are connected to the metal traces distributed in the fourth metal layer through vias.

[0054] In an exemplary embodiment of the present disclosure, the display panel includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and the red sub-pixel, the green sub-pixel, and the blue sub-pixel are arranged in sequence along the first direction;

[0055] The connection block is located between the red sub-pixel and the green sub-pixel, or between the blue sub-pixel and the green sub-pixel.

[0056] In an exemplary embodiment of the present disclosure, the second limiting dam located between the red sub-pixel and the green sub-pixel, and the second limiting dam located between the blue sub-pixel and the green sub-pixel have sizes in the first direction that are larger than the size of the second limiting dam located between the red sub-pixel and the blue sub-pixel in the first direction.

[0057] In an exemplary embodiment of the present disclosure, the plurality of first defining dams include a plurality of first sub-defining dams and a plurality of second sub-defining dams, the first sub-defining dams and the second sub-defining dams both extend along a first direction, the second sub-defining dams are located on one side of the first sub-defining dams along a second direction, the first sub-defining dams and the second sub-defining dams both have a bottom end proximal to the base substrate and a top end distal to the base substrate, and a distance between the bottom end and the top end of the first sub-defining dams is smaller than a distance between the bottom end and the top end of the second sub-defining dams;

[0058] The orthographic projection of the metal trace on the substrate is located within the orthographic projection of the second sub-definition dam on the substrate.

[0059] According to a second aspect of the present disclosure, a method for manufacturing a display panel is provided, comprising:

[0060] providing a substrate;

[0061] forming a transistor device layer on one side of the base substrate;

[0062] forming at least one metal layer on a side of the transistor device layer away from the substrate, wherein the at least one metal layer includes a plurality of metal traces extending along a first direction;

[0063] forming a first insulating layer on a surface of the at least one metal layer away from the base substrate;

[0064] forming a first electrode layer on a surface of the first insulating layer away from the base substrate, wherein the first electrode layer includes a plurality of first electrode blocks;

[0065] forming a pixel definition layer, the pixel definition layer comprising a plurality of first definition dams extending along the first direction and a plurality of second definition dams extending along the second direction, the plurality of first definition dams and the plurality of second definition dams intersecting each other to define a plurality of pixel openings, wherein in a direction perpendicular to the substrate, the pixel openings correspond one-to-one to the first electrode blocks;

[0066] The orthographic projection of the metal trace on the substrate is located within the orthographic projection of the first limiting dam on the substrate;

[0067] The thickness of at least one metal layer among the at least one metal layer is greater than that of the first insulating layer, and the thickness of the metal layer is at least 0.5 μm greater than that of the first insulating layer.

[0068] According to a third aspect of the present disclosure, a display device is provided, comprising the display panel as described in the first aspect.

[0069] The display panel provided by the present disclosure includes a base substrate, a transistor device layer, at least one metal layer, a first insulating layer, a first electrode layer, and a pixel definition layer. The at least one metal layer includes multiple metal traces extending along a first direction, the pixel definition layer includes a first defining dam extending along the first direction, the orthographic projections of the metal traces on the base substrate are located within the orthographic projections of the first defining dam on the base substrate, and at least one of the at least one metal layer has a thickness at least 0.5 μm greater than that of the first insulating layer. Thus, the thicker metal traces help form a larger slope angle, which, when combined with the thinner first insulating layer, allows the first defining dam to also form a larger slope angle, thereby helping to mitigate the ink slope phenomenon, improve the coffee ring effect, and enhance the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the accompanying drawings.

[0071] FIG1 is a schematic diagram of light intensity distribution of a display panel in the related art;

[0072] FIG2 is a schematic diagram of a planar structure of a display panel in an exemplary embodiment of the present disclosure;

[0073] FIG3 is an exemplary layout diagram of the first metal layer of a display panel in an exemplary embodiment of the present disclosure;

[0074] FIG4 is an example layout diagram of a pixel definition layer of a display panel in an exemplary embodiment of the present disclosure;

[0075] FIG5 is a cross-sectional view in the AA direction in FIG2;

[0076] FIG6 is a cross-sectional view in the direction BB in FIG2;

[0077] FIG7 is an exemplary layout diagram of the second metal layer of the display panel in an exemplary embodiment of the present disclosure;

[0078] FIG8 is an exemplary layout diagram of the stacking of the first metal layer and the second metal layer of the display panel in an exemplary embodiment of the present disclosure;

[0079] FIG9 is a schematic cross-sectional view of a first metal layer and a second metal layer of a display panel in an exemplary embodiment of the present disclosure;

[0080] FIG10 is a schematic cross-sectional view of a first metal layer and a second metal layer of a display panel in another exemplary embodiment of the present disclosure;

[0081] FIG11 is a schematic diagram of a planar structure of a display panel in another exemplary embodiment of the present disclosure;

[0082] FIG12 is a cross-sectional view in the CC direction of FIG11;

[0083] FIG13 is a schematic diagram of a planar structure of a display panel in another exemplary embodiment of the present disclosure;

[0084] FIG14 is a cross-sectional view in the EE direction in FIG13;

[0085] FIG15 is a schematic diagram of light intensity distribution of a display panel in an exemplary embodiment of the present disclosure;

[0086] FIG. 16 is a schematic diagram of a single metal layer structure in an exemplary embodiment of the present disclosure.

[0087] The main elements in the figure are marked as follows: 1-substrate; 2-pixel definition layer; 3-hole injection layer; 100-substrate substrate; 110-display area; 111-dummy area; 120-peripheral area; 01-metal trace; 011-connection block; 02-connection trace; 200-transistor device layer; 201-active layer; 202-first gate insulation layer; 203-first gate metal layer; 204-interlayer dielectric layer; 205-source and drain layer; 300-planarization layer; 401-first metal layer; 402-second metal layer; 403-third metal layer; 404-fourth metal layer; 405-first insulation layer; 406- Second insulating layer; 01a-first sub-metal layer; 01b-second sub-metal layer; 01c-third sub-metal layer; 501-first electrode layer; 5011-normal electrode; 5012-virtual electrode; 502-light-emitting functional layer; 503-second electrode layer; 600-pixel definition layer; 601-first defining dam; 6011-first sub-defining dam; 6012-second sub-defining dam; 602-second defining dam; 6021-first via hole; 603-pixel opening. DETAILED DESCRIPTION

[0088] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of the embodiments of the present disclosure.

[0089] In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

[0090] The described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, materials, etc. can be adopted. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the main technical ideas of the present disclosure.

[0091] When a structure is “on” another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is “directly” disposed on the other structure, or that the structure is “indirectly” disposed on the other structure via another structure.

[0092] The terms "a," "an," and "the" are used to indicate the presence of one or more elements / components; the terms "including" and "having" are used to indicate an open-ended inclusiveness and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc. The terms "first," "second," etc. are used merely as labels and do not limit the quantity of the items to which they refer.

[0093] As shown in FIG1 , in the related art, inkjet printing technology is applied to the production and preparation of OLED display panels due to its advantages of high production efficiency and low material cost. The display panel includes a substrate 1 and a pixel definition layer 2 provided on one side of the substrate 1. The inkjet printing technology is to drop inkjet droplets into the pixel area defined by the pixel definition layer 2, and then perform a drying process to solidify the inkjet droplets to form a film layer such as a hole injection layer 3. However, although this method is simple to manufacture, during the drying process of the inkjet droplets, the evaporation rate at the edge position is greater than the evaporation rate at the middle position, causing an outward capillary flow to be generated inside the inkjet droplets, carrying the suspended particles to the edge position, and depositing them into a ring at the edge position, resulting in a thickness at the edge position greater than that at the middle position, resulting in a coffee ring effect, thereby interfering with the microcavity effect, especially when the display panel also includes a light extraction layer 4, the light extraction layer 4 is usually located on the side of the cathode layer of the light-emitting device away from the substrate 1, and the light intensity distribution is uneven, affecting the display quality of the OLED display panel.

[0094] As shown in Figures 2 to 6, the present disclosure provides a display panel comprising a base substrate 100, a transistor device layer 200, at least one metal layer, a first insulating layer 405, and a first electrode layer 501. The transistor device layer 200 is disposed on one side of the base substrate 100; the at least one metal layer is disposed on a side of the transistor device layer 200 away from the base substrate 100 and includes a plurality of metal traces 01 extending along a first direction Y; the first insulating layer 405 is disposed on a surface of the at least one metal layer away from the base substrate 100; the first electrode layer 501 is disposed on a surface of the first insulating layer 405 away from the base substrate 100 and includes a plurality of first electrode blocks; and a pixel definition layer 600 comprises a plurality of first defining dams 601 extending along the first direction Y and a plurality of second defining dams 602 extending along the second direction X. The plurality of first defining dams 601 and the plurality of second defining dams 602 intersect to define a plurality of pixel openings 603, which expose each of the first electrode blocks in a one-to-one correspondence. The orthographic projection of the metal trace 01 on the base substrate 100 is located within the orthographic projection of the first limiting dam 601 on the base substrate 100; the thickness of at least one metal layer in the at least one metal layer is greater than the thickness of the first insulating layer 405, and the thickness of the metal layer is at least 0.5 μm greater than the thickness of the first insulating layer 405.

[0095] The display panel provided by the present disclosure includes a base substrate 100, a transistor device layer 200, at least one metal layer, a first insulating layer 405, a first electrode layer 501, and a pixel definition layer 600. The at least one metal layer includes a plurality of metal traces 01 extending along a first direction Y. The pixel definition layer 600 includes a first defining dam 601 extending along the first direction Y. The orthographic projections of the metal traces 01 on the base substrate 100 are located within the orthographic projections of the first defining dam 601 on the base substrate 100. Furthermore, the thickness of at least one of the at least one metal layer is at least 0.5 μm greater than the thickness of the first insulating layer 405. Thus, the thicker metal traces 01 help form a larger slope angle. Combined with the thinner first insulating layer 405, the first defining dam 601 also forms a larger slope angle, thereby helping to mitigate the ink slope phenomenon, improve the coffee ring effect, and enhance the display quality of the display panel.

[0096] The components of the display panel provided by the present disclosure will be described in detail below with reference to the accompanying drawings and specific embodiments:

[0097] As shown in Figures 2 to 6, embodiments of the present disclosure provide a display panel, which can be an OLED (Organic Light-Emitting Diode) display panel or a QLED (Quantum Dot Light Emitting Diode) display panel. The display panel provided by the present disclosure includes a base substrate 100, a transistor device layer 200, at least one metal layer, a first insulating layer 405, a first electrode layer 501, and a pixel definition layer 600.

[0098] The base substrate 100 may be a base substrate 100 of an inorganic material or a base substrate 100 of an organic material. For example, in one embodiment of the present disclosure, the material of the base substrate 100 may be a glass material such as soda-lime glass, quartz glass, sapphire glass, or a metal material such as stainless steel, aluminum, nickel, etc. In another embodiment of the present disclosure, the material of the base substrate 100 may be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof. The substrate 100 may also be a flexible substrate 100. For example, in one embodiment of the present disclosure, the material of the substrate 100 may be polyimide (PI). The substrate 100 may also be a composite of multiple layers. For example, in one embodiment of the present disclosure, the substrate 100 may include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence. In some embodiments of the present disclosure, the substrate 100 includes a display area 110 and a virtual area 111 located outside the display area 110. The display area 110 is used to display images.

[0099] As shown in Figures 2 and 5, the transistor device layer 200 is provided on one side of the base substrate 100. The transistor device layer 200 may include devices such as transistors and capacitors for forming pixel circuits. The pixel circuit is used to drive the light-emitting devices such as organic light-emitting diodes or quantum dot light-emitting diodes of the display panel to emit light. The pixel circuit can be a 7T1C, 7T2C, 6T1C or 6T2C pixel circuit, and its structure is not particularly limited here. Among them, nTmC means that a pixel circuit includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C").

[0100] In some embodiments of the present disclosure, the transistor device layer 200 may be composed of a multilayer film structure. For example, if the transistor in the driving circuit is a top-gate thin-film transistor, the transistor device layer 200 includes an active layer 201, a first gate insulating layer 202, a first gate metal layer 203, an interlayer dielectric layer 204, and a source / drain layer 205.

[0101] An active layer 201 is disposed on one side of the substrate 100; a first gate insulating layer 202 is disposed on a side of the active layer 201 away from the substrate 100, and covers the active layer 201; a first gate metal layer 203 is disposed on a side of the first gate insulating layer 202 away from the substrate 100, and is used to form the gate of the transistor. An interlayer dielectric layer 204 is disposed on a side of the first gate metal layer 203 away from the substrate 100, and covers the first gate metal layer 203; a source / drain layer 205 is disposed on a side of the interlayer dielectric layer 204 away from the substrate 100, and is used to form the source and drain of the transistor, which are connected to the active layer 201.

[0102] In other embodiments, the transistor device layer 200 may further include a second gate insulating layer and a second gate metal layer. In such embodiments, the second gate insulating layer and the second gate metal layer are disposed between the first gate metal layer 203 and the source / drain layer 205. The first gate metal layer 203 is used to form the first plate of the capacitor and the gate of the transistor T; the second gate insulating layer is disposed on the side of the first gate metal layer 203 away from the substrate 100, and the second gate insulating layer covers the first gate metal layer 203; the second gate metal layer is disposed on the side of the first gate insulating layer 202 away from the substrate 100 and is disposed opposite the first plate, and the second gate metal layer is used to form the second plate of the capacitor; the interlayer dielectric layer 204 is disposed on the side of the second gate metal layer away from the substrate 100, and the interlayer dielectric layer 204 covers the second gate metal layer.

[0103] In some embodiments of the present disclosure, the display panel further includes a planarization layer 300 disposed between the transistor device layer 200 and at least one metal layer. Specifically, the planarization layer 300 is disposed on a side of the source / drain layer 205 away from the base substrate 100 .

[0104] As shown in Figures 2 to 6, at least one metal layer is disposed on a side of the transistor device layer 200 away from the substrate 100 and includes a plurality of metal traces 01 extending along a first direction Y. The at least one metal layer can be one, two, three, or more metal layers. The multiple metal traces 01 can be distributed across one, two, three, or more metal layers. As shown in Figure 9, when the at least one metal layer includes multiple metal layers, a second insulating layer 406 is disposed between two adjacent metal layers.

[0105] The first insulating layer 405 is disposed on a surface of the at least one metal layer away from the base substrate 100. The first insulating layer 405 can be made of an inorganic material, such as silicon nitride, silicon oxide, or silicon oxynitride. The thickness of at least one of the at least one metal layer is greater than the thickness of the first insulating layer 405, and the thickness of the metal layer is at least 0.5 μm greater than the thickness of the first insulating layer 405. Specifically, the thickness can be at least 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, 0.8 μm, 0.85 μm, 0.9 μm, etc.

[0106] For example, if the at least one metal layer includes one metal layer, the thickness of the metal layer is at least 0.5 μm greater than the thickness of the first insulating layer 405. For another example, if the at least one metal layer includes two metal layers, the thickness of at least one of the two metal layers is at least 0.5 μm greater than the thickness of the first insulating layer 405. Similarly, if the at least one metal layer includes three metal layers, the thickness of at least one of the three metal layers is at least 0.5 μm greater than the thickness of the first insulating layer 405.

[0107] The first electrode layer 501 is disposed on a surface of the first insulating layer 405 that is away from the substrate, such that the first insulating layer 405, which is relatively thin, is located between the first electrode layer 501 and the at least one metal layer. The first electrode layer 501 includes a plurality of first electrode blocks. The first electrode blocks can serve as anodes for light-emitting devices such as organic light-emitting diodes (OLEDs) or quantum dot light-emitting diodes (QDs).

[0108] As shown in FIG11 , in some embodiments of the present disclosure, the plurality of first electrode blocks include a plurality of normal electrodes 5011 located in the display area 110 and a plurality of dummy electrodes 5012 located in the dummy area 111. The normal electrodes 5011 are electrically connected to the transistor device layer 200, while the dummy electrodes 5012 are electrically insulated from the transistor device layer 200. In other words, the organic light-emitting diodes or quantum dot light-emitting diodes containing the dummy electrodes 5012 do not emit light. The dummy electrodes 5012 located in the dummy area 111 can serve as a process reference area for forming the normal electrodes 5011 and also help balance the display effect at the edge of the display area 110 of the display panel.

[0109] As shown in Figures 2, 4, and 5, the pixel definition layer 600 includes a plurality of first defining dams 601 extending along a first direction Y and a plurality of second defining dams 602 extending along a second direction X. The plurality of first defining dams 601 and the plurality of second defining dams 602 intersect to define a plurality of pixel openings 603. In a direction perpendicular to the substrate 100, each pixel opening 603 corresponds one-to-one with a first electrode block. The first direction Y and the second direction X form an angle. The first direction Y can be a column direction, and the second direction X can be a row direction, but is not limited to such. The orthographic projection of the pixel openings 603 onto the substrate 100 can have various shapes, such as a circle, an ellipse, or a closed curved edge. The material of the pixel definition layer 600 can include materials such as fluorinated resin. The materials of the first defining dams 601 and the second defining dams 602 can be different.

[0110] In the present disclosure, the thickness relationship between at least one metal layer and the first insulating layer 405 is defined, and the at least one metal layer is maintained to have a thicker thickness, which helps to form a larger slope angle during etching, while the first insulating layer 405 has a thinner thickness. While the insulating layer of this thickness has an insulating effect, it helps to maintain the larger slope angle formed by the aforementioned at least one metal layer, thereby providing a structural basis for the subsequent first limiting dam 601 to form a larger slope angle.

[0111] In some embodiments of the present disclosure, at least one of the at least one metal layer has a thickness of no less than 0.7 μm. The thickness of the first insulating layer 405 is no greater than 0.2 μm. Specifically, at least one of the at least one metal layer has a thickness of 0.7 μm-1 μm. The thickness of the first insulating layer 405 is 0.05-0.2 μm, such as 0.05 μm, 0.1 μm, 0.15 μm, or 0.2 μm.

[0112] In some embodiments of the present disclosure, metal trace 01 has a first surface proximate to substrate 100, a second surface distal to substrate 100, and sidewalls connecting the first and second surfaces. A first angle α is formed between the sidewalls of metal trace 01 and the first surface of metal trace 01. For at least some of the multiple metal traces 01, the first angle α is between 70° and 90°. It should be noted that the first angle α is the slope angle of metal trace 01. For at least some of the multiple metal traces 01, the slope angle is between 70° and 90°.

[0113] For example, the multiple metal traces 01 include a target metal trace. The shortest distance D between the edge of the orthographic projection of the target metal trace on the substrate 100 and the edge of the orthographic projection of the corresponding first defining dam 601 on the substrate 100 is no greater than 2 μm. The first angle α of the target metal trace is between 70° and 90°. In other words, the metal trace 01 closest to the edge of the corresponding first defining dam 601 is the target metal trace. The first angle α of the target metal trace is between 70° and 90°, and the thickness of the target metal trace is no less than 0.7 μm. This ensures that at least one target metal trace among the multiple metal traces 01 can elevate the first defining dam 601 and form a larger slope angle.

[0114] It should be noted that, in the actual manufacturing process, the window size of the mask for forming the target metal trace and the window size of the mask for forming the pixel definition layer can be set to be substantially equal. In this case, the shortest distance D between the edge of the orthographic projection on the substrate 100 and the edge of the orthographic projection of the corresponding first definition dam 601 on the substrate 100 is related to the exposure bias (photo bias) and etching bias (etch bias) during the process. For example, D = |ZXY|, where X is the exposure bias (photo bias) of the target metal trace, Y is the etching bias (etch bias) of the target metal trace after exposure, and Z is the exposure bias of the first definition dam.

[0115] When forming the metal trace 01, a metal material layer may be first deposited and then patterned to form a metal layer including the metal trace 01. When patterning the metal material layer, dry etching or wet etching may be used, depending on the material properties of the metal material.

[0116] The single metal layer in the at least one metal layer can be made of a single metal or a composite metal. For example, in some embodiments, the single metal layer in the at least one metal layer is made of a single metal such as molybdenum (Mo), titanium (Ti), or aluminum (Al). Wet etching of the molybdenum metal film layer facilitates forming a larger slope angle, while dry etching of the titanium and aluminum metal layers facilitates forming a larger slope angle. Therefore, when the metal layers are made of different metal materials, different etching processes can be used accordingly.

[0117] As shown in FIG14 , in some other embodiments, the single metal layer in the at least one metal layer includes a first sub-metal layer 01a and a second sub-metal layer 01b stacked in a direction away from the base substrate 100; the thickness of the first sub-metal layer 01a is greater than the thickness of the second sub-metal layer 01b, and the thickness of the first sub-metal layer 01a is not less than 0.5 μm. The thickness of the first sub-metal layer 01a can be 0.5 μm-0.8 μm, and the thickness of the second sub-metal layer 01b can be 0.05 μm-0.2 μm. The material of the first sub-metal layer 01a can be selected from aluminum (Al) metal material. The thicker aluminum metal layer mainly serves to raise the height so that the formed metal line has a larger slope angle. The second sub-metal layer 01b can be selected from molybdenum (Mo) or titanium (Ti) metal material. In this type of embodiment, a dry etching process is preferably used to form the metal trace 01.

[0118] Furthermore, the single metal layer in the at least one metal layer further includes a third sub-metal layer 01c. The third sub-metal layer 01c is disposed on a side of the first sub-metal layer 01a closer to the base substrate 100. The thickness of the first sub-metal layer 01a is greater than that of the third sub-metal layer 01c. The thickness of the third sub-metal layer 01c can range from 0.05 μm to 0.2 μm. The third sub-metal layer 01c can be made of molybdenum (Mo) or titanium (Ti).

[0119] As shown in Figures 6 and 15, further, in the present disclosure, no organic material layer is included between the at least one metal layer and the first electrode layer 501. In the prior art, the thickness of the organic material layer in the display panel is usually relatively thick. Such organic material layer may level the height difference formed by the metal trace 01, so that the slope angle formed by the metal trace 01 cannot effectively affect the slope angle of the first limiting dam 601. In the present disclosure, no organic material layer is provided between the at least one metal layer and the first electrode layer 501, but only a thin first insulating layer 405 (inorganic material layer) is provided. In this way, the metal trace 01 can fully utilize the cushioning effect of the first limiting dam 601, and the larger slope angle of the metal trace 01 can cause the first limiting dam 601 to also form a larger slope angle, thereby reducing ink climbing, thereby improving the coffee ring effect, improving the light intensity distribution of the light-emitting device, and improving the display quality of the display panel.

[0120] As shown in Figures 5, 15 and 16, the display panel also includes a light-emitting functional layer 502 and a second electrode layer 503. The light-emitting functional layer 502 is arranged on the side of the first electrode layer 501 away from the base substrate 100, and the light-emitting functional layer 502 is at least partially located in the pixel opening 603. The light-emitting functional layer 502 is a multi-layer structure. In the direction away from the base substrate 100, the light-emitting functional layer 502 includes a hole injection layer, a hole transport layer, a light-emitting material layer, and an electron transport layer. Visible light can be generated by allowing holes and electrons to recombine into excitons in the light-emitting material layer, and the excitons radiate photons. The specific light-emitting principle will not be described in detail here. The light-emitting material layer can be an organic light-emitting material layer or a quantum dot light-emitting material layer. In some embodiments, the light-emitting functional layer 502 may further include an electron injection layer, which is arranged on the side of the electron transport layer away from the base substrate 100.

[0121] Some or all of the film layers in the light-emitting functional layer 502 may be formed using an inkjet printing process. Preferably, some of the film layers in the light-emitting functional layer 502 are formed using an inkjet printing process, while others are formed using an evaporation process. For example, the hole injection layer, hole transport layer, and light-emitting material layer are formed using an inkjet printing process, while the electron transport layer and electron injection layer are formed using an evaporation process. The printed film layers are positioned within the pixel openings 603, while the evaporation-deposited film layers may cover the surface of the pixel definition layer 600 that is away from the base substrate 100.

[0122] The second electrode layer 503 is disposed on a surface of the pixel definition layer 600 and the light-emitting functional layer 502 away from the substrate 100. The second electrode layer 503 can be formed by sputtering and can be made of a transparent material such as indium zinc oxide (IZO).

[0123] The display panel also includes a light extraction layer 600, disposed on the side of the second electrode layer 503 facing away from the base substrate 100. This layer significantly improves the light extraction pattern of the display device, allowing light previously confined within the device to escape the display panel, resulting in higher light extraction efficiency. The light extraction layer 600, combined with the at least one metal layer configuration disclosed herein, can more effectively adjust the light intensity distribution of the light-emitting device, improving the uneven light intensity distribution of the light-emitting device.

[0124] The display panel further includes an encapsulation layer, which covers the surface of the second electrode layer 503 facing away from the base substrate 100 and can be used to prevent external water and oxygen from corroding the light-emitting device.

[0125] In some embodiments of the present disclosure, encapsulation can be achieved by thin-film encapsulation (TFE). Specifically, the encapsulation layer may include a first inorganic layer, an organic layer, and a second inorganic layer, wherein the first inorganic layer covers the surface of the second electrode layer 503 facing away from the base substrate 100, the organic layer may be provided on the surface of the first inorganic layer facing away from the base substrate 100, and the boundary of the organic layer is limited to the inner side of the boundary of the first inorganic layer, and the second inorganic layer covers the organic layer and the first inorganic layer not covered by the organic layer. The second inorganic layer can block the intrusion of water and oxygen, and flattening can be achieved by the flexible organic layer. The materials of the first and second inorganic layers are Si3N4, SiO2, SiC, TiO2, Al2O3, etc., which have the function of blocking water and oxygen. A thin film of 0.03μm-1μm can be formed by chemical vapor deposition (CVD), sputtering, atomic force deposition (ALD), etc.

[0126] As shown in FIG4 , in some embodiments of the present disclosure, the plurality of first defining dams 601 include a plurality of first sub-defining dams 6011 and a plurality of second sub-defining dams 6012. The first sub-defining dams 6011 and the second sub-defining dams 6012 both extend along a first direction Y. The second sub-defining dam 6012 is located to one side of the first sub-defining dam 6011 along a second direction X. The first sub-defining dam 6011 and the second sub-defining dam 6012 both have a bottom end proximal to the substrate 100 and a top end distal to the substrate 100. The distance between the bottom and top ends of the first sub-defining dam 6011 is smaller than the distance between the bottom and top ends of the second sub-defining dam 6012. The orthographic projection of the metal trace O1 on the substrate 100 is located within the orthographic projection of the second sub-defining dam 6012 on the substrate 100. The distance between the bottom and top ends of the first sub-defining dam 6011 can be 0.2 μm to 0.6 μm, and the distance between the bottom and top ends of the second sub-defining dam 6012 can be 1.5 μm to 2 μm. The first sub-defining dams 6011 and the second sub-defining dams 6012 can be arranged in various ways, such as one second sub-defining dam 6012 can be arranged every m first sub-defining dams 6011, where m can be a positive integer, such as 2≤m≤10. The distance between the bottom and top of the second sub-defining dams 602 can be 1.5μm-2μm.

[0127] As shown in FIG13 , in the present disclosure, the display panel includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, which are arranged sequentially along a first direction Y. Multiple red sub-pixels R are arranged along a second direction X, i.e., sub-pixels in the same row have the same color. The top material of the first sub-defining dam 6011 may include a lyophilic material, such as a lyophilic photoresist or a lyophilic inorganic film, to ensure that sub-pixels of the same color in the same row between two adjacent second sub-defining dams 6012 can be connected. The top material of the second delimiting dam 602 may include a lyophobic material, such as a lyophobic photoresist, to prevent interference between sub-pixels of different colors.

[0128] In the present disclosure, the at least one metal layer may include one, two or more metal layers. The following describes in detail the configuration of the at least one metal layer in the present disclosure in conjunction with different embodiments.

[0129] As shown in Figures 2 to 6, in one embodiment of the present disclosure, at least one metal layer includes a first metal layer 401, which is disposed on a side of the transistor device layer 200 away from the substrate 100. Multiple metal traces 01 are distributed within the first metal layer 401. The first angle α of the metal traces 01 distributed within the first metal layer 401 is between 70° and 90°. The thickness of the first metal layer 401 is between 0.7 μm and 1 μm. The shortest distance D between the edge of the orthographic projection of the metal trace 01 on the substrate 100 and the edge of the orthographic projection of the corresponding first defining dam 601 on the substrate 100 is no greater than 2 μm.

[0130] As shown in FIG16 , the first metal layer 401 can be made of a single metal such as molybdenum (Mo), titanium (Ti), or aluminum (Al), or a composite metal. For example, the first metal layer 401 includes a first sub-metal layer 01a and a second sub-metal layer 01b stacked in a direction away from the base substrate 100 . The thickness of the first sub-metal layer 01a is greater than that of the second sub-metal layer 01b , and the thickness of the first sub-metal layer 01a is not less than 0.5 μm. The thickness of the first sub-metal layer 01a can be 0.5 μm to 0.8 μm, such as 0.5 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, etc. The thickness of the second sub-metal layer 01b can be 0.05 μm to 0.2 μm, such as 0.05 μm, 0.08 μm, 0.1 μm, 0.15 μm, 0.18 μm, etc. The material of the first sub-metal layer 01a can be aluminum (Al). Furthermore, the first metal layer 401 includes a third sub-metal layer 01c, which is disposed on a side of the first sub-metal layer 01a closer to the base substrate 100. The thickness of the first sub-metal layer 01a is greater than that of the third sub-metal layer 01c. The thickness of the third sub-metal layer 01c can range from 0.05 μm to 0.2 μm. The third sub-metal layer 01c can be made of molybdenum (Mo) or titanium (Ti).

[0131] In this type of embodiment, the metal traces 01 distributed in the first metal layer 401 can be used as data lines, power lines, etc., for transmitting data signals or power voltages VDD / VSS.

[0132] As shown in Figures 5 and 6, the first insulating layer 405 is provided on a surface of the first metal layer 401 away from the base substrate 100. The thickness of the first insulating layer 405 is no greater than 0.2 μm. Specifically, the thickness of the first insulating layer 405 is 0.05-0.2 μm, such as 0.05 μm, 0.1 μm, 0.15 μm, or 0.2 μm. The material of the first insulating layer 405 can be an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0133] As shown in Figures 7 to 10 and 16, in another embodiment of the present disclosure, the at least one metal layer includes two metal layers, namely a first metal layer 401 and a second metal layer 402. The first metal layer 401 is disposed on a side of the transistor device layer 200 away from the substrate 100, and at least some of the multiple metal traces 01 are distributed in the first metal layer 401. The second metal layer 402 is disposed on a side of the first metal layer 401 away from the substrate 100, and at least some of the multiple metal traces 01 are distributed in the second metal layer 402. The first included angle α of the metal traces 01 distributed in the first metal layer 401 is 70°-90° and / or the first included angle α of the metal traces 01 distributed in the second metal layer 402 is 70°-90°.

[0134] The thickness of the first metal layer 401 and / or the second metal layer 402 is 0.7 μm to 1 μm. Preferably, the thickness of both the first metal layer 401 and the second metal layer 402 is 0.7 μm to 1 μm. The plurality of metal traces 01 include a target metal trace. The shortest distance D between the edge of the orthographic projection of the target metal trace on the substrate 100 and the edge of the orthographic projection of the corresponding first limiting dam 601 on the substrate 100 is no greater than 2 μm. The target metal trace can be distributed in the first metal layer 401 and / or the second metal layer 402.

[0135] The first metal layer 401 and the second metal layer 402 can be made of a single metal such as molybdenum (Mo), titanium (Ti), or aluminum (Al), or a composite metal. For example, the first metal layer 401 and the second metal layer 402 each include a first sub-metal layer 01a and a second sub-metal layer 01b stacked in a direction away from the base substrate 100. The thickness of the first sub-metal layer 01a is greater than that of the second sub-metal layer 01b, and the thickness of the first sub-metal layer 01a is not less than 0.5 μm. The thickness of the first sub-metal layer 01a can be 0.5 μm to 0.8 μm, such as 0.5 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, etc. The thickness of the second sub-metal layer 01b can be 0.05 μm to 0.2 μm, such as 0.05 μm, 0.08 μm, 0.1 μm, 0.15 μm, 0.18 μm, etc. The material of the first sub-metal layer 01a can be selected from aluminum (Al). Furthermore, both the first metal layer 401 and the second metal layer 402 further include a third sub-metal layer 01c, which is disposed on the side of the first sub-metal layer 01a closer to the base substrate 100. The thickness of the first sub-metal layer 01a is greater than that of the third sub-metal layer 01c. The thickness of the third sub-metal layer 01c can range from 0.05 μm to 0.2 μm. The third sub-metal layer 01c can be selected from molybdenum (Mo) or titanium (Ti).

[0136] Preferably, as shown in FIG10 , the orthographic projection of the metal trace 01 distributed in the first metal layer 401 on the substrate 100 does not overlap with the orthographic projection of the metal trace 01 distributed in the second metal layer 402 on the substrate 100 to avoid parasitic capacitance between the two.

[0137] In this type of embodiment, the metal traces 01 distributed in the first metal layer 401 and the second metal layer 402 can be used as data lines, power lines, etc., for transmitting data signals or power supply voltages VDD / VSS. Furthermore, the metal traces 01 distributed in the second metal layer 402 can also serve as gate drive circuit (GOA) signal lines, such as STU, VGH, VGL, RST, and other DC signal traces.

[0138] The first insulating layer 405 is disposed on a surface of the second metal layer 402 away from the base substrate 100. The thickness of the first insulating layer 405 is no greater than 0.2 μm. Specifically, the thickness of the first insulating layer 405 is 0.05-0.2 μm, such as 0.05 μm, 0.1 μm, 0.15 μm, or 0.2 μm. The material of the first insulating layer 405 can be an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0139] As shown in Figures 11 and 12, in this type of embodiment, the orthographic projection of the metal trace 01 distributed in the first metal layer 401 on the substrate 100 is located in the display area 110 and the virtual area 111, while the orthographic projection of the metal trace 01 distributed in the second metal layer 402 on the substrate 100 can be located in the display area 110 and the virtual area 111, or only in the virtual area 111, and the present disclosure does not specifically limit this. Preferably, the orthographic projection of the metal trace 01 distributed in the second metal layer 402 on the substrate 100 is located in the virtual area 111. In this case, the metal trace 01 distributed in the second metal layer 402 serves as a gate drive circuit (GOA) signal line, such as a DC signal trace such as STU, VGH, VGL, and RST.

[0140] Furthermore, in this type of embodiment, the second metal layer 402 may further include a connection line 02, which extends along the second direction X and can be in contact with and connected to the metal trace 01. The orthographic projection of the connection line 02 on the base substrate 100 is located in the virtual area 111 and can also serve as a gate drive circuit (GOA) signal line, which is not specifically limited in this disclosure.

[0141] As shown in Figures 13 and 14, in another embodiment of the present disclosure, the second electrode layer 503 is connected to the metal layer closest to the second electrode layer 503 among the at least one metal layer through a first via 6021 in the second defining dam 602. The metal layer connected to the second electrode layer 503 through the via hole can serve as a cathode auxiliary electrode layer, connected in parallel with the second electrode layer 503, to reduce resistance and lower impedance.

[0142] Specifically, the metal layer closest to the second electrode layer 503 among the at least one metal layer is the third metal layer 403. The metal trace 01 distributed in the third metal layer 403 has a connecting block 011, which is located at the intersection of the first limiting dam 601 and the second limiting dam 602. The size of the connecting block 011 in the second direction X is larger than the size of other areas of the metal trace 01 in the second direction X. The orthographic projection of the connecting block 011 on the substrate 100 is located within the orthographic projection of the first via 6021 on the substrate 100. The orthographic projection of the connecting block 011 on the substrate 100 can be square, rectangular, or other polygonal. A gap exists between the edge of the orthographic projection of the first via 6021 on the substrate 100 and the edge of the orthographic projection of the connecting block 011 on the substrate 100, and the gap is greater than zero.

[0143] Furthermore, the thickness of the third metal layer 403 is not less than 0.7 μm. The third metal layer 403 includes a first sub-metal layer 01a and a second sub-metal layer 01b stacked in a direction away from the base substrate 100. The thickness of the first sub-metal layer 01a is greater than that of the second sub-metal layer 01b, and the thickness of the first sub-metal layer 01a is not less than 0.5 μm. The hardness of the first sub-metal layer 01a is less than that of the second sub-metal layer 01b. When etching to form the connecting block 011 in the third metal layer 403, the orthographic projection of the first sub-metal layer 01a on the base substrate 100 in the connecting block 011 will be located within the orthographic projection of the second sub-metal layer 01b on the base substrate 100. This type of connecting block 011 can isolate the film layers in the light-emitting functional layer 502 subsequently formed by the evaporation process, providing a structural foundation for achieving the connection between the second electrode layer 503 and the third metal layer 403. At this time, the second electrode layer 503 may be formed by a sputtering process, and the formed second electrode layer 503 will be connected to the sidewall of the connection block 011 , thereby achieving parallel connection between the second electrode layer 503 and the third metal layer 403 .

[0144] The third metal layer 403 may further include a third sub-metal layer 01c, which is disposed on the side of the first sub-metal layer 01a closer to the base substrate 100. The thickness of the first sub-metal layer 01a is greater than that of the third sub-metal layer 01c. The thickness of the third sub-metal layer 01c may be 0.05 μm to 0.2 μm. The material of the first sub-metal layer 01a may be aluminum (Al). The second sub-metal layer 01b and the third sub-metal layer 01c may be molybdenum (Mo) or titanium (Ti).

[0145] Furthermore, the at least one metal layer comprises multiple metal layers, wherein the metal layer located on the side of the third metal layer 403 closest to the substrate 100 and closest to the third metal layer 403 is the fourth metal layer 404. The metal traces 01 distributed in the third metal layer 403 are connected to the metal traces 01 distributed in the fourth metal layer 404 via holes to further reduce resistance. Preferably, the conductivity of the fourth metal layer 404 is greater than that of the third metal layer 403. For example, the fourth metal layer 404 can be made of highly conductive metals such as Cu and Ag. The third metal layer 403 can be made of Ti / Al / Ti.

[0146] In this type of embodiment, the connection block 011 is located between the red sub-pixel R and the green sub-pixel G, or between the blue sub-pixel B and the green sub-pixel G. The dimensions of the second defining dam 602 located between the red sub-pixel R and the green sub-pixel G, and the second defining dam 602 located between the blue sub-pixel B and the green sub-pixel G in the first direction Y are both larger than the dimensions of the second defining dam 602 located between the red sub-pixel R and the blue sub-pixel B in the first direction Y. For example, the dimensions of the second defining dam 602 located between the red sub-pixel R and the green sub-pixel G, and the second defining dam 602 located between the blue sub-pixel B and the green sub-pixel G in the first direction Y are 1.2-1.5 times the dimensions of the second defining dam 602 located between the red sub-pixel R and the green sub-pixel G in the first direction Y.

[0147] As shown in FIG. 2 to FIG. 6 , the present disclosure further provides a method for manufacturing a display panel, comprising:

[0148] Step S100, providing a base substrate 100;

[0149] Step S200 , forming a transistor device layer 200 on one side of the base substrate 100 ;

[0150] Step S300 , forming at least one metal layer on a side of the transistor device layer 200 away from the base substrate 100 , wherein the at least one metal layer includes a plurality of metal traces 01 extending along a first direction Y;

[0151] Step S400 , forming a first insulating layer 405 on a surface of at least one metal layer away from the base substrate 100 ;

[0152] Step S500 , forming a first electrode layer 501 on a surface of the first insulating layer 405 away from the base substrate, wherein the first electrode layer 501 includes a plurality of first electrode blocks;

[0153] Step S600: forming a pixel definition layer 600. The pixel definition layer 600 includes a plurality of first definition dams 601 extending along a first direction Y and a plurality of second definition dams 602 extending along a second direction X. The plurality of first definition dams 601 and the plurality of second definition dams 602 intersect to define a plurality of pixel openings 603. In a direction perpendicular to the base substrate 100, the pixel openings 603 correspond one-to-one to the first electrode blocks.

[0154] The orthographic projection of the metal trace 01 on the base substrate 100 is located within the orthographic projection of the first limiting dam 601 on the base substrate 100;

[0155] The thickness of at least one metal layer in the at least one metal layer is greater than the thickness of the first insulating layer 405 , and the thickness of the metal layer is at least 0.5 μm greater than the thickness of the first insulating layer 405 .

[0156] The present disclosure further provides a display device including a display panel. The display panel may be any of the display panels described above. The specific structure and beneficial effects thereof may be referenced above with respect to the display panel embodiments, and are not further described herein. The display device of the present disclosure may be an electronic device such as a mobile phone, a tablet computer, or a television, and these are not listed here.

[0157] It should be noted that although the steps of the method of the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additional or alternative steps, such as omitting certain steps, combining multiple steps into one step, and / or decomposing a step into multiple steps, should all be considered part of this disclosure.

[0158] It should be understood that the present disclosure is not limited in its application to the detailed structure and arrangement of the components set forth in this specification. The present disclosure is capable of other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All of these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. A display panel, in, include: substrate substrate; A transistor device layer is provided on one side of the base substrate; At least one metal layer, disposed on a side of the transistor device layer away from the substrate, comprising a plurality of metal traces extending along a first direction; A first insulating layer is provided on a surface of the at least one metal layer away from the base substrate; A first electrode layer is provided on a surface of the first insulating layer away from the base substrate, and the first electrode layer includes a plurality of first electrode blocks; a pixel definition layer, comprising a plurality of first defining dams extending along the first direction and a plurality of second defining dams extending along the second direction, wherein the plurality of first defining dams and the plurality of second defining dams intersect each other to define a plurality of pixel openings, and in a direction perpendicular to the substrate, the pixel openings correspond one-to-one to the first electrode blocks; Wherein, the orthographic projection of the metal trace on the substrate is located within the orthographic projection of the first limiting dam on the substrate; At least one of the at least one metal layer has a thickness greater than that of the first insulating layer, and the thickness of the metal layer is at least 0.5 μm greater than that of the first insulating layer.

2. The display panel according to claim 1, in, The metal routing has a first surface close to the substrate, a second surface away from the substrate, and a side wall connecting the first surface and the second surface. A first angle is formed between the side wall of the metal routing and the first surface of the metal routing. The first angle of at least some of the multiple metal routings is 70°-90°.

3. The display panel according to claim 1, in, The at least one metal layer comprises: A first metal layer is provided on a side of the transistor device layer away from the substrate, and the plurality of metal traces are distributed in the first metal layer; The first angle of the metal traces distributed in the first metal layer is 70°-90°.

4. The display panel according to claim 1, in, The at least one metal layer comprises: A first metal layer is provided on a side of the transistor device layer away from the substrate, and at least part of the plurality of metal traces are distributed in the first metal layer; A second metal layer is provided on a side of the first metal layer away from the base substrate, and at least part of the plurality of metal traces are distributed in the second metal layer; The first angle of the metal routing lines distributed in the first metal layer is 70°-90° and / or the first angle of the metal routing lines distributed in the second metal layer is 70°-90°.

5. The display panel according to claim 4, in, The orthographic projection of the metal wiring distributed in the first metal layer on the substrate does not overlap with the orthographic projection of the metal wiring distributed in the second metal layer on the substrate.

6. The display panel according to claim 1, in, At least one of the at least one metal layer has a thickness of not less than 0.7 μm.

7. The display panel according to claim 1, in, The single metal layer in the at least one metal layer comprises a first sub-metal layer and a second sub-metal layer stacked in a direction away from the substrate; The thickness of the first sub-metal layer is greater than that of the second sub-metal layer, and the thickness of the first sub-metal layer is not less than 0.5 μm.

8. The display panel according to claim 7, in, The single metal layer in the at least one metal layer further includes a third sub-metal layer, and the third sub-metal layer is arranged on a side of the first sub-metal layer close to the base substrate; The thickness of the first sub-metal layer is greater than the thickness of the third sub-metal layer.

9. The display panel according to claim 1, in, The thickness of the first insulating layer is no more than 0.2 μm.

10. The display panel according to claim 2, in, The plurality of metal traces include a target metal trace, and the shortest distance between an edge of an orthographic projection of the target metal trace on the substrate and an edge of an orthographic projection of a corresponding first limiting dam on the substrate is no greater than 2 μm; The first angle of the target metal wiring is 70°-90°, and the thickness of the target metal wiring is not less than 0.7 μm.

11. The display panel according to claim 4, in, The base substrate comprises a display area and a virtual area located outside the display area; The plurality of first electrode blocks include a plurality of normal electrodes located in the display area and a plurality of virtual electrodes located in the virtual area, the normal electrodes are electrically connected to the transistor device layer, and the virtual electrodes are electrically insulated from the transistor device layer; The orthographic projection of the metal traces distributed in the second metal layer on the substrate is located in the virtual area.

12. The display panel according to claim 1, in, No organic material layer is included between the at least one metal layer and the first electrode layer.

13. The display panel according to claim 1, in, The display panel further includes: A light-emitting functional layer is provided on a side of the first electrode layer away from the base substrate, and at least a part of the light-emitting functional layer is located in the pixel opening; A second electrode layer is provided on a surface of the pixel definition layer and the light emitting functional layer which is away from the base substrate; The second electrode layer is connected to the metal layer closest to the second electrode layer among the at least one metal layer through a first via hole in the second defining dam.

14. The display panel according to claim 13, in, The metal layer closest to the second electrode layer among the at least one metal layer is a third metal layer; The metal wiring distributed in the third metal layer has a connection block, and the connection block is located at the intersection of the first limiting dam and the second limiting dam; The size of the connecting block in the second direction is larger than the size of other areas of the metal wiring in the second direction; The orthographic projection of the connection block on the base substrate is located within the orthographic projection of the first via hole on the base substrate.

15. The display panel according to claim 14, in, The thickness of the third metal layer is not less than 0.7 μm.

16. The display panel according to claim 15, in, The third metal layer includes a first sub-metal layer and a second sub-metal layer stacked in a direction away from the substrate; The thickness of the first sub-metal layer is greater than that of the second sub-metal layer, and the thickness of the first sub-metal layer is not less than 0.5 μm.

17. The display panel according to claim 7 or 16, in, The hardness of the first sub-metal layer is less than the hardness of the second sub-metal layer.

18. The display panel according to claim 14, in, The number of metal layers in the at least one metal layer is multiple layers, wherein the metal layer located on the side of the third metal layer close to the base substrate and closest to the third metal layer is the fourth metal layer; The metal routing lines distributed in the third metal layer are connected to the metal routing lines distributed in the fourth metal layer through via holes.

19. The display panel according to claim 14, in, The display panel comprises a red sub-pixel, a green sub-pixel and a blue sub-pixel, and the red sub-pixel, the green sub-pixel and the blue sub-pixel are arranged in sequence along the first direction; The connection block is located between the red sub-pixel and the green sub-pixel, or between the blue sub-pixel and the green sub-pixel.

20. The display panel according to claim 19, in, The second defining dam located between the red sub-pixel and the green sub-pixel and the second defining dam located between the blue sub-pixel and the green sub-pixel have sizes in the first direction that are greater than the size of the second defining dam located between the red sub-pixel and the blue sub-pixel in the first direction.

21. The display panel according to claim 1, in, The plurality of first defining dams include a plurality of first sub-defining dams and a plurality of second sub-defining dams, the first sub-defining dams and the second sub-defining dams both extend along a first direction, the second sub-defining dams are located at one side of the first sub-defining dams along a second direction, the first sub-defining dams and the second sub-defining dams both have a bottom end close to the substrate and a top end away from the substrate, and a distance between the bottom end and the top end of the first sub-defining dams is smaller than a distance between the bottom end and the top end of the second sub-defining dams; The orthographic projection of the metal trace on the substrate is located within the orthographic projection of the second sub-definition dam on the substrate.

22. A method for manufacturing a display panel, in, include: providing a substrate base plate; forming a transistor device layer on one side of the base substrate; Forming at least one metal layer on a side of the transistor device layer away from the substrate, wherein the at least one metal layer includes a plurality of metal traces extending along a first direction; A first insulating layer is formed on a surface of the at least one metal layer away from the substrate. layer; forming a first electrode layer on a surface of the first insulating layer away from the base substrate, wherein the first electrode layer comprises a plurality of first electrode blocks; forming a pixel definition layer, the pixel definition layer comprising a plurality of first definition dams extending along the first direction and a plurality of second definition dams extending along the second direction, the plurality of first definition dams and the plurality of second definition dams intersecting each other to define a plurality of pixel openings, and in a direction perpendicular to the substrate, the pixel openings correspond one-to-one to the first electrode blocks; Wherein, the orthographic projection of the metal trace on the substrate is located within the orthographic projection of the first limiting dam on the substrate; At least one of the at least one metal layer has a thickness greater than that of the first insulating layer, and the thickness of the metal layer is at least 0.5 μm greater than that of the first insulating layer.

23. A display device, in, Comprising a display panel as described in any one of claims 1-21.

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