Display panel and display apparatus

Abstract

The present application discloses a display panel and a display apparatus. The display panel comprises a first metal layer and an anode layer which are stacked on a base substrate. The first metal layer comprises a first signal line, a second signal line, and a third signal line which are arranged at equal intervals. The orthographic projection of the second signal line on the base substrate at least partially overlaps with the anode layer.

Description

Display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310706609.X filed in China on June 14, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] Organic light-emitting diode (OLED) display panels have gained widespread application due to their advantages, including self-luminescence, low driving voltage, and fast response speed. OLED display panels generally consist of multiple pixel units, each of which includes a light-emitting element and pixel circuitry connected to the light-emitting element. The light-emitting element includes an anode, a light-emitting layer located above the anode, and a cathode located above the light-emitting layer. Therefore, the flatness of the anode of a light-emitting element affects the color separation of the light-emitting element.

[0005] However, since the pixel circuit below the anode has relatively complex electronic components (such as transistors, storage capacitors, etc.) and wiring structures, the flatness of the anode is not very ideal. Therefore, current display panels and display devices still need to be improved.

[0006] Summary of the Invention

[0007] The present application provides a display panel and a method for manufacturing the same.

[0008] In a first aspect of the present application, a display panel is provided, comprising a first metal layer and an anode layer stacked on a base substrate, wherein the first metal layer comprises a first signal line, a second signal line, and a third signal line arranged at equal intervals; and an orthographic projection of the second signal line on the base substrate at least partially overlaps with the anode layer.

[0009] In some embodiments, the display panel has first pixel circuits and second pixel circuits alternately arranged along a first direction, and the first pixel circuits and the second pixel circuits are symmetrically arranged along a second direction;

[0010] The anode layer includes a first anode corresponding to the first sub-pixel and a second anode corresponding to the second sub-pixel; the first anode is symmetrical about a first boundary of the first pixel circuit, the second anode is symmetrical about a second boundary of the second pixel circuit, and the first boundary of the first pixel circuit is parallel to the second boundary of the second pixel circuit;

[0011] The second signal line includes a first part corresponding to the first pixel circuit and a second part corresponding to the second pixel circuit. In the orthographic projection of the first part and the second part on the substrate, the part located in the first sub-pixel area is symmetrical about the first boundary of the first pixel circuit, and the part located in the second sub-pixel area is symmetrical about the second boundary of the second pixel circuit.

[0012] In some embodiments, the distance between the first signal line and the second signal line is greater than or equal to 2.5 μm, or the distance between the second signal line and the third signal line is greater than or equal to 2.5 μm, and the widths of the first signal line, the second signal line, and the third signal line are independently greater than or equal to 2 μm.

[0013] In some embodiments, the display panel also includes a second metal layer, the second metal layer having a first auxiliary metal line, the orthographic projection of the first auxiliary metal line on the base substrate at least partially overlaps with the orthographic projection of the anode on the base substrate, and the overlapping area between the first auxiliary metal line and the projection of the third signal line on the base substrate is less than 20% of the projection of the third signal line on the base substrate.

[0014] In some embodiments, the first auxiliary metal line is arranged at a projected position of a first boundary of the first pixel circuit, and the first auxiliary metal line is symmetrical about the first boundary of the first pixel circuit, or the first auxiliary metal line is arranged on a second boundary of the second pixel circuit, and the first auxiliary metal line is symmetrical about the second boundary of the second pixel circuit.

[0015] In some embodiments, the width of the first auxiliary metal line is greater than or equal to 2 μm.

[0016] In some embodiments, the anode layer further includes a third anode corresponding to a third sub-pixel, an orthographic projection of the third anode on the substrate partially overlaps with the first pixel circuit and the second pixel circuit, respectively, and the third anode has a symmetry axis extending along the first direction;

[0017] The projection of the first signal line in the third anode region is an integrated structure.

[0018] In some embodiments, the substrate further includes a first reset power line, a second reset power line, and a third reset power line, and the first reset power line, the second reset power line, and the third reset power line are mesh-connected.

[0019] In some embodiments, the second metal layer further includes a second auxiliary metal line and a third auxiliary metal line, and the orthographic projections of the second auxiliary metal line and the third auxiliary metal line on the substrate have at least partial overlaps with the orthographic projection of the third anode on the substrate; the second auxiliary metal line and the third auxiliary metal line are symmetrically distributed along the second direction.

[0020] In some embodiments, the display panel further includes first to third gate layers stacked sequentially on the base substrate, the first to third gate layers are all located between the base substrate and the first metal layer, and the projection of the third gate layer within the projection area of ​​the third anode and the projection of the second metal layer within the projection area of ​​the third anode are symmetrical along the first direction.

[0021] In some embodiments, the display panel further includes a pixel defining layer, the pixel defining layer having first to third openings, the first opening corresponding to the first anode, the second opening corresponding to the second anode, and the third opening corresponding to the third anode.

[0022] The first opening and the second opening include three via holes within the projection area of ​​the base substrate, and the third opening includes 1.5 via holes within the projection area of ​​the base substrate.

[0023] In some embodiments, the first signal line is a driving power line of the display panel, the second signal line is an auxiliary driving power line, and the third signal line is a data signal line of the display panel.

[0024] In some embodiments, the first metal layer is a second source-drain electrode layer, and the second metal layer is a first source-drain electrode layer.

[0025] In some embodiments, the pixel circuit comprises:

[0026] a first transistor, wherein a gate of the first transistor is connected to a first reset signal line, a first electrode of the first transistor is connected to a first reset power line, and a second electrode of the first transistor is connected to a third node;

[0027] a second transistor, wherein a gate of the second transistor is connected to a first gate signal line included in the display panel, a first electrode of the second transistor is connected to the first node, and a second electrode of the second transistor is connected to the third node;

[0028] a third transistor, wherein a gate of the third transistor is connected to the first node, a first electrode of the third transistor is connected to the second node, and a second electrode of the third transistor is connected to the third node;

[0029] a fourth transistor, wherein a gate of the fourth transistor is connected to a second gate signal line included in the display panel, a first electrode of the fourth transistor is connected to a data signal line included in the display panel, and a second electrode of the fourth transistor is connected to the second node;

[0030] a fifth transistor, wherein a gate of the fifth transistor is connected to the light emitting control signal line, a first electrode of the fifth transistor is connected to a driving power line included in the display panel, and a second electrode of the fifth transistor is connected to the second node;

[0031] a sixth transistor, wherein a gate of the sixth transistor is connected to the light-emitting control signal line, a first electrode of the sixth transistor is connected to the third node, and a second electrode of the sixth transistor is connected to the light-emitting unit;

[0032] a seventh transistor, wherein a gate of the seventh transistor is connected to a second gate signal line included in the display panel, a first electrode of the seventh transistor is connected to a second reset power line, and a second electrode of the seventh transistor is connected to the light-emitting unit;

[0033] an eighth transistor, wherein a gate of the eighth transistor is connected to the second reset signal line, a first electrode of the eighth transistor is connected to a third reset power line included in the display panel, and a second electrode of the eighth transistor is connected to the second node;

[0034] A storage capacitor, one end of which is connected to the driving power line, and the other end of which is connected to the first node.

[0035] In a second aspect of the present application, a display device is provided, which includes the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0037] FIG1 is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present application;

[0038] FIG2 is a schematic diagram of a partial structure of another display panel provided in an embodiment of the present application;

[0039] FIG3 is a schematic diagram of a partial structure of the first source and drain layer corresponding to FIG2 ;

[0040] FIG4 is a schematic diagram of a partial structure of the second source and drain layer corresponding to FIG2 ;

[0041] FIG5 is an equivalent circuit diagram of a pixel circuit provided in an embodiment of the present application;

[0042] FIG6 is a timing diagram corresponding to FIG5;

[0043] FIG7 is a cross-sectional view of an AA (or BB) region provided in an embodiment of the present application;

[0044] FIG8 is another cross-sectional view of the AA (or BB) region provided in an embodiment of the present application;

[0045] FIG9 is a schematic diagram of a circuit structure provided in an embodiment of the present application;

[0046] FIG10 is a schematic diagram of a circuit structure provided in an embodiment of the present application;

[0047] FIG11 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, and an oxide layer of a display panel provided in an embodiment of the present application;

[0048] 12 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, and a third gate layer of a display panel provided by an embodiment of the present application;

[0049] 13 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first source-drain electrode layer, and a second source-drain electrode layer of a display panel provided by an embodiment of the present application;

[0050] 14 is a partial superposition diagram of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first source-drain electrode layer, a second source-drain electrode layer, an anode layer, and a pixel defining layer of a display panel provided in an embodiment of the present application;

[0051] FIG15 is a cross-sectional view of a CC region provided in an embodiment of the present application;

[0052] FIG16 is a schematic diagram of a partial structure of a first source and drain layer provided in an embodiment of the present application;

[0053] 17 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, and a first source and drain electrode layer of another display panel provided by an embodiment of the present application;

[0054] FIG18 is a partial schematic diagram of a first source and drain layer of another display panel provided in an embodiment of the present application;

[0055] FIG19 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first source-drain electrode layer, and a second source-drain electrode layer of another display panel provided by an embodiment of the present application;

[0056] FIG20 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first source-drain electrode layer, a second source-drain electrode layer, an anode layer, and a pixel defining layer of another display panel provided by an embodiment of the present application;

[0057] 21 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, and a first source and drain electrode layer of another display panel provided by an embodiment of the present application;

[0058] 22 and 23 are schematic diagrams of partial superposition of a via hole and an opening of a pixel defining layer of a display panel in the related art;

[0059] 24 and 25 are schematic diagrams of partial superposition of a via hole and an opening of a pixel defining layer of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] In the following, only certain exemplary embodiments are briefly described. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present application, and different embodiments may be combined in any manner without conflict. Therefore, the drawings and description are to be regarded as illustrative in nature and not restrictive.

[0061] The transistors used in all embodiments of the present application can be field-effect transistors or other devices with the same characteristics. According to their functions in the circuit, the transistors used in the embodiments of the present application are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present application, the source is referred to as the first electrode and the drain is referred to as the second electrode, or the drain is referred to as the first electrode and the source is referred to as the second electrode. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end is the source, and the signal output end is the drain. In addition, the switching transistors used in the embodiments of the present application may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is low and turned off when the gate is high, and the N-type switching transistor is turned on when the gate is high and turned off when the gate is low. In addition, the multiple signals in each embodiment of the present application correspond to effective potentials and invalid potentials. The effective potential and invalid potential only represent that the potential of the signal has two state quantities, and do not mean that the effective potential or invalid potential has a specific value in the full text.

[0062] 1 is a partial structural diagram of a display panel provided in an embodiment of the present application. The display panel 10 may include a base substrate 101 and a plurality of pixel units 102 .

[0063] At least one of the plurality of pixel units 102 includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, each of which includes a pixel circuit and a light-emitting element. The pixel circuits in the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to a gate signal line, a data signal line, and a light-emitting signal line. The pixel circuits are configured to receive a data voltage transmitted by the data signal line under the control of the gate signal line and the light-emitting signal line, and output a corresponding current to the light-emitting element. The light-emitting elements of the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to the pixel circuits of the sub-pixels in which they are located. The light-emitting elements are configured to emit light of corresponding brightness in response to the current output by the pixel circuits of the sub-pixels in which they are located.

[0064] In a feasible embodiment, FIG2 is a schematic diagram of a partial structure of another display panel provided in an embodiment of the present application. As shown in FIG2 , a plurality of pixel circuits arranged along a first direction X, less one pixel circuit, include: a plurality of first pixel circuits 1021 arranged along a second direction Y, and a plurality of second pixel circuits 1022 arranged along a second direction y. The first direction X and the second direction Y are perpendicular, for example, the first direction X is a pixel row direction, and the second direction Y is a pixel column direction. The plurality of first pixel circuits 1021 and the second pixel circuits 1022 are alternately arranged along the first direction, and each of the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022 includes a first boundary and a second boundary extending along the second direction.

[0065] In a feasible embodiment, a pixel unit may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In some embodiments, the shape of the sub-pixels in the pixel unit may be a rectangle, a rhombus, a pentagon, or a hexagon. The pixel units may be arranged horizontally, vertically, or in a herringbone pattern. Figure 2 shows the positions of the first sub-pixel, the second sub-pixel, and the third sub-pixel arranged in a herringbone pattern. Among them, the first sub-pixel 1031 is a red sub-pixel, the second sub-pixel 1032 is a blue sub-pixel, and the third sub-pixel 1033 is a green sub-pixel.

[0066] It should be understood that the first pixel circuit 1021 and the second pixel circuit 1022 do not necessarily correspond to the first sub-pixel and the second sub-pixel, that is, the first pixel circuit 1021 and the first sub-pixel 1031 connected thereto do not necessarily correspond to each other. In other words, the first pixel circuit 1021 can be a pixel circuit for controlling the first sub-pixel 1031, or a pixel circuit for controlling the third sub-pixel 1033, or a control circuit for other pixels, which is determined by the layout design of the pixel circuit and is not specifically limited in this application.

[0067] In a feasible embodiment, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 5 is an equivalent circuit diagram of a pixel circuit provided in an embodiment of the present application. As shown in Figure 5, the pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor Cst.

[0068] The gate of the seventh transistor T7 can be connected to the first reset signal line Reset_H, the first electrode of the seventh transistor T7 can be connected to the second reset power line Vinit2, and the second electrode of the seventh transistor T7 can be connected to the light emitting unit. The seventh transistor T7 can also be called a reset transistor.

[0069] The gate of the fourth transistor T4 can be connected to the first gate signal line Gate_P, the first electrode of the fourth transistor T4 can be connected to the data signal line Data, and the second electrode of the fourth transistor T4 can be connected to the second node N2. That is, the fourth transistor T4 can be a data writing transistor in the pixel circuit.

[0070] The gate of the fifth transistor T5 can be connected to the light emission control signal line EM, the first electrode of the fifth transistor T5 can be connected to the driving power line VDD, and the second electrode of the fifth transistor T5 can be connected to the second node N2. Since the gate of the fifth transistor T5 is connected to the light emission control signal EM, the fifth transistor T5 can also be called a light emission control transistor.

[0071] The gate of the first transistor T1 may be connected to the second reset signal line Reset_P, the first electrode of the first transistor T1 may be connected to the first reset power line Vinit1, and the second electrode of the first transistor T1 may be connected to the third node N3. The first transistor T1 may also be called a reset transistor.

[0072] The gate of the sixth transistor T6 can be connected to the light-emitting control signal line EM, the first electrode of the sixth transistor T6 can be connected to the third node N3, and the second electrode of the fifth transistor can be connected to the light-emitting unit. Since the gate of the sixth transistor T6 is connected to the light-emitting control signal line EM, the sixth transistor T6 can also be called a light-emitting control transistor.

[0073] The gate of the second transistor T2 is connected to the second gate signal line Gate_N, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1. The second transistor T2 may also be called a compensation transistor.

[0074] The gate of the third transistor T3 may be connected to the first node N1, the first electrode of the third transistor T3 may be connected to the second node N2, and the second electrode of the third transistor T3 may be connected to the third node N3. The third transistor T3 may also be called a driving transistor.

[0075] The gate of the eighth transistor T8 can be connected to the first reset signal line Reset_H. That is, the gate of the eighth transistor T8 and the gate of the seventh transistor T7 share the first reset signal line Reset_H. The first electrode of the eighth transistor T8 can be connected to the third reset power line Vinit3, and the second electrode of the eighth transistor T8 can be connected to the second node N2. The eighth transistor T8 can also be called a reset transistor.

[0076] One end of the storage capacitor Cst can be connected to the driving power line VDD, and the other end of the storage capacitor Cst can be connected to the first node N1. Optionally, the storage capacitor Cst may include two capacitor plates Cst1 and Cst2. In the embodiment of the present application, the capacitor plate Cst1 can be referred to as one end of the storage capacitor Cst, the first end, or the first storage capacitor electrode, and the capacitor plate Cst2 can be referred to as the other end of the storage capacitor Cst, the second end, or the second storage capacitor electrode.

[0077] In combination with the above embodiments, it can be seen that in the embodiment of the present application, the second transistor T2 is an N-type transistor, and the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all P-type transistors.

[0078] Optionally, each N-type transistor recorded in the embodiment of the present application may be an oxide transistor, and each P-type transistor may be a low-temperature polysilicon (LTPS) transistor. The oxide material may include indium gallium zinc oxide (IGZO), that is, the oxide transistor may be an IGZO transistor. The pixel circuit composed of the eight transistors may also be referred to as an LTPO pixel circuit. A display panel in which the pixel circuit of the display panel is the LTPO pixel circuit may be referred to as an LTPO display panel.

[0079] Taking the pixel circuit shown in FIG5 as an example, where the first potential is higher than the second potential, the driving principle of the pixel circuit described in the embodiment of the present application is described as follows.

[0080] During initialization phase t1, the potential of the second reset signal provided by the second reset signal line Reset_P, the potential of the first gate drive signal provided by the first gate signal line Gate_P, and the potential of the light control signal provided by the light control signal line EM are all at the first potential. The potential of the second gate drive signal provided by the second gate signal line Gate_N and the potential of the first reset signal provided by the first reset signal line Reset_H are all at the second potential. Accordingly, the seventh transistor T7 and the second transistor T2 are turned on. The fourth transistor T4, the fifth transistor T5, the first transistor T1, the sixth transistor T6, the second transistor T2, and the third transistor T3 are all turned off. Thus, the second reset signal of the second potential provided by the second reset power line Vinit2 can be transmitted to the anode of the light-emitting unit via the turned-on seventh transistor T7. The third reset signal of the second potential provided by the third reset power line Vint3 can be transmitted to the second node N2 via the turned-on eighth transistor T8, thereby resetting the anode of the light-emitting unit and the second node N2.

[0081] During compensation phase t2, the potential of the second reset signal provided by the second reset signal line Reset_P jumps to the second potential, the potential of the second gate drive signal provided by the second gate signal line Gate_N jumps to the first potential, and the potential of the light-emitting control signal provided by the light-emitting control signal line EM remains at the first potential. Accordingly, the first transistor T1, the second transistor T2, and the third transistor T3 are all turned on, while the seventh transistor T7, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned off. Thus, the first reset power supply signal is transmitted to N3 via the turned-on first transistor T1, and the second transistor T2 adjusts the potential of the first node N1 based on the potential of the third node N3. Furthermore, the reset power supply signal of the second potential provided by the first reset power supply line Vinit1 can be transmitted to the first node N1 via the turned-on first transistor T1 and the turned-on second transistor T2, thereby resetting the first node N1.

[0082] During the write phase t3, the potential of the second reset signal provided by the second reset signal line Reset_P jumps to the first potential, the first reset signal provided by the first reset signal line Reset_H remains at the first potential, the potential of the first gate drive signal provided by the first gate signal line Gate_P jumps to the second potential, the second gate signal line Gate_N remains at the first potential, and the potential of the light-emitting control signal provided by the light-emitting control signal line EM remains at the first potential. Under the bootstrap effect of the storage capacitor Cst, the potential of the first node N1 remains at the second potential. Accordingly, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all turned off. In this way, the data signal provided by the data signal line Data can be transmitted to the first node N1 in sequence through the turned-on fourth transistor T4, the third transistor T3, and the second transistor T2.

[0083] During light-emitting phase t4, the potential of the second reset signal provided by the second reset signal line Reset_P remains at the first potential, the first reset signal provided by the first reset signal line Reset_H remains at the first potential, the potential of the first gate drive signal provided by the first gate signal line Gate_P jumps to the second potential, the second gate signal line Gate_N jumps to the second potential, and the potential of the light-emitting control signal provided by the light-emitting control signal line EM jumps to the second potential. Under the bootstrap effect of the storage capacitor Cst, the potential of the first node N1 remains at the second potential of the data signal line Data. Accordingly, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are all turned off. Thus, the drive power signal provided by the drive power line VDD is transmitted to the second node N2 via the turned-on fifth transistor T5. The third transistor T3 can transmit a drive current to the third node N3 based on the potential of the first node N1 and the potential transmitted to the second node N2. Then, the driving current can be transmitted to the anode of the light emitting unit through the turned-on sixth transistor T6, generating a voltage difference between the anode and cathode layers of the light emitting unit, and the light emitting unit emits light.

[0084] In a feasible embodiment, the light emitting element may be an organic light emitting diode (OLED), including an anode layer, an organic light emitting layer and a cathode layer. As mentioned above, the flatness of the anode layer of the light emitting element affects the color separation of the light emitting element.

[0085] Figure 7 is a partial cross-sectional view of the structure at area AA of Figure 2. As shown in Figure 7, the display panel includes a first metal layer and an anode layer (not shown in the figure). The first metal layer has first signal lines 411, second signal lines 412, and third signal lines 413 arranged at equal intervals. The orthographic projection of the second signal line 412 on the substrate at least partially overlaps with the anode layer.

[0086] Therefore, the anode layer of the light emitting element can present a better flatness effect under the support of the first signal line, the second signal line and the third signal line.

[0087] It should be noted here that, in the present application, the "overlap" or "partial overlap" of the first to third signal lines, metal lines and other structures and other film layers, such as the anode layer, specifically refers to an overlapping or partially overlapping positional relationship between the orthographic projections of the two on the substrate, rather than a stacking relationship in which the two have direct contact.

[0088] In a feasible embodiment, the display panel may include an active layer Poly that constitutes a pixel circuit and is stacked in sequence along a direction away from the base substrate 101, a first gate insulating layer (gate insulator, GI1), a first gate layer Gate1, a second gate insulating layer GI2, a second gate layer Gate2, an oxide layer Oxid, a third gate insulating layer GI3, a third gate layer Gate3, a first interlevel dielectric layer (inter level dielectric, ILD0), a second interlevel dielectric layer ILD, a first source and drain layer SD1, a first planarization layer (planarization layer, PLN1), a second source and drain layer SD2, a second planarization layer PLN2, a third planarization layer PLN3, an anode layer (anode) and a pixel definition layer (PDL).

[0089] For example, the first metal layer may be the second source-drain layer SD2, and the second metal layer may be the first source-drain layer SD1. Figures 3 and 4 show schematic structural diagrams of the first source-drain layer and the second source-drain layer in Figure 2.

[0090] For example, as shown in FIG8 , the first metal layer may be a second source / drain layer SD2 , the first signal line 411 and the second signal line 412 may be configured as a driving power line VDD, and the third signal line 413 may be configured as a data signal line Data.

[0091] It should be noted that Figure 2 also shows that the first pixel circuit 1021 and the second pixel circuit 1022 are alternately arranged along the first direction, the first pixel circuit 1021 and the second pixel circuit 1022 are symmetrical along the second direction, the anode layer includes a first anode 1031 corresponding to the first sub-pixel and a second anode 1032 corresponding to the second sub-pixel, the first anode 1031 is symmetrical about the first boundary of the first pixel circuit 1021, the second anode 1032 is symmetrical about the second boundary of the second pixel circuit 1022, and the first boundary of the first pixel circuit 1021 and the second boundary of the second pixel circuit 1022 are parallel.

[0092] Furthermore, the second signal line 412 includes a first part corresponding to the first pixel circuit 1021, and a second part corresponding to the second pixel circuit 1022. The first part and the second part are symmetrical about the first boundary of the first pixel circuit 1021 in the positive projection on the substrate within the first sub-pixel area, and are symmetrical about the second boundary of the second pixel circuit 1022 in the second sub-pixel area.

[0093] In a feasible embodiment, as shown in Figure 8, the distance between two adjacent third signal lines, the distance between the first signal line and the second signal line, or the distance between the second signal line and the third signal line is equal (as shown in Figure 8a) and greater than or equal to 2.5μm, and the widths of the first signal line, the second signal line, and the third signal line are equal (as shown in Figure 8b) and greater than or equal to 2μm.

[0094] Thus, by adding a second signal line to the second source / drain layer SD2 beneath the first and second sub-pixels, the present embodiment effectively increases the overlap area between the second source / drain layer SD2 and the anode layer, improving the flatness of the corresponding anodes for the first and second sub-pixels. Furthermore, the aforementioned symmetrically structured first metal layer can further improve the flatness of the anodes at corresponding locations and provide a symmetrical metal routing environment. This can further enhance the performance of the display panel, including flatness. For example, providing a symmetrical pattern can create a more consistent underlying environment during patterning processes such as etching, as well as deposition processes for forming structures such as the light-emitting layer, thereby improving etching or deposition performance.

[0095] In one feasible embodiment, the anode layer further includes a third anode 1033 corresponding to the third sub-pixel. The third anode 1033 partially overlaps with the first pixel circuit 1021 and the second pixel circuit 1022, respectively, and is symmetrical along the first direction. To further improve the performance of the display panel, after the first sub-pixel 1031 and the second sub-pixel 1032 are planarized using the second source / drain layer SD2, the third anode 1033 can be optimized for planarization.

[0096] Optionally, the projection of the first signal line on the third anode is an integrated structure. For example, FIG9 is a cross-sectional view of the CC region in FIG2 provided in an embodiment of the present application. As shown in FIG9 , the first signal line is configured as an integrated driving power line VDD.

[0097] Therefore, in this embodiment of the present application, a second signal line is added to the second source-drain layer SD2 in the projection area of ​​the first and second sub-pixels to enhance the flatness of the anodes of the first and second sub-pixels. Furthermore, the drive power line VDD of the second source-drain layer SD2 in the projection area of ​​the third sub-pixel is integrated into an integrated structure to enhance the flatness of the anode of the third sub-pixel. Thus, by improving the second source-drain layer SD2, the flatness of the anodes of the first, second, and third sub-pixels can be improved, effectively avoiding color separation caused by uneven anodes.

[0098] In one feasible embodiment, FIG10 is a schematic diagram of a circuit structure provided by an embodiment of the present application. The connection structure shown in FIG10 corresponds to the connection structure of the first pixel circuit 1021 and the second pixel circuit 1022 in FIG2 . As shown in FIG10 , below the first pixel circuit 1021 and the second pixel circuit 1022, the first reset power line Vinit1, the second reset power line Vinit2, and the third reset power line Vinit3 are configured as signal lines extending along a first direction X, forming a mesh connection with the signal lines extending along a second direction Y.

[0099] It should be noted that the data signal line Data and the driving power line VDD are vertical signal lines, wherein the horizontal signal line mainly provides signals for multiple pixel circuits arranged in the horizontal direction, and the vertical signal line mainly provides signals for multiple pixel circuits arranged in the vertical direction.

[0100] FIG11 is a schematic diagram of the partial superposition of the active layer, first gate layer, second gate layer, and oxide layer of a display panel provided in an embodiment of the present application, wherein Vinit1, Vinit2, and Vinit3 are all formed of the first gate layer Gate1 metal; FIG12 is a schematic diagram of the partial superposition of the active layer, first gate layer, second gate layer, oxide layer, and third gate layer of a display panel provided in an embodiment of the present application, that is, the superposition position of the third gate layer is further shown on the basis of FIG11; FIG13 is a schematic diagram of the partial superposition of the active layer, first gate layer, second gate layer, oxide layer, third gate layer, first source and drain electrode, and second source and drain electrode of a display panel provided in an embodiment of the present application; FIG14 is a schematic diagram of the partial superposition of the active layer, first gate layer, second gate layer, oxide layer, third gate layer, first source and drain electrode layer, second source and drain electrode layer, anode layer, and pixel defining layer of a display panel provided in an embodiment of the present application. The stacking order of the above-mentioned metal layers is as described above and will not be repeated here.

[0101] In a feasible embodiment of the present application, since the flatness of the anode is strongly affected by the metal layer closest to the anode (the second source and drain layer SD2), and the influence is second only to that from the edge, the present application further proposes a method for optimizing the routing of the first source and drain layer SD1 to further enhance the flatness of the sub-pixel anode.

[0102] Optionally, a first auxiliary metal line is further provided on the first source-drain layer SD1, the first auxiliary metal line at least partially overlaps with the anode, and the overlapping area between the first auxiliary metal line and the projection of the third signal line on the first source-drain layer SD1 is less than 20% of the projection area of ​​the third signal line on the first source-drain layer SD1.

[0103] For example, as shown in Figure 15 , first auxiliary metal lines 51 are arranged symmetrically between two data signal lines, forming a complementary structure with the two data signal lines, further enhancing the flatness of the anode. Furthermore, the first auxiliary metal lines 51 form a uniformly spaced routing structure with the routing structure of the original circuit, increasing the overlap area between the first source and drain layer SD1 and the anode layer, providing a stable foundation for further improving anode flatness.

[0104] Preferably, the first auxiliary metal wire 51 is complementary to the structure of the two data signal lines Data, and the width of the first auxiliary metal wire 51 (as shown in d in FIG15 ) is greater than or equal to 2 μm. Furthermore, the first auxiliary metal wire 51 and the wiring structure in the original circuit form an equidistant and uniform wiring structure, and the distance between the first auxiliary metal wire 51 and the structure in the original circuit (as shown in c in FIG15 ) is greater than or equal to 1.5 μm.

[0105] It should be understood that since the first sub-pixel and the second sub-pixel are connected across the first pixel circuit and the second pixel circuit, the first auxiliary metal line is arranged at the projected position of the first boundary of the first pixel circuit and is symmetrical about the first boundary of the first pixel circuit, or the first auxiliary metal line is arranged on the second boundary of the second pixel circuit and is symmetrical about the second boundary of the second pixel circuit.

[0106] Figure 16 is a schematic diagram of the partial structure of a first source and drain layer provided in an embodiment of the present application, and Figure 17 is a schematic diagram of the partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer and a first source and drain of another display panel provided in an embodiment of the present application.

[0107] Therefore, the embodiment of the present application increases the overlapping area between the first source and drain electrode SD1 and the anode by adding a first auxiliary metal line to the first source and drain electrode layer SD1 in the projection area of ​​the first sub-pixel and the second sub-pixel, so as to enhance the flatness of the anodes of the first sub-pixel and the second sub-pixel, and effectively avoid the color separation caused by the uneven anode.

[0108] In a feasible embodiment, consistent with the second source / drain electrode layer SD2 , the first source / drain electrode layer SD1 can also optimize the planarity of the third anode.

[0109] 17-20 , the first source-drain layer SD1 includes a second auxiliary metal line 53 and a third auxiliary metal line 54 , which at least partially overlap with the third anode and are symmetrical along the second direction.

[0110] For example, as shown in FIG18 , the first source / drain layer SD1 adds a second auxiliary metal wire 53 and a third auxiliary metal wire 54 in the projection area of ​​the third anode, forming a symmetrical structure with the metal structure 55 in the original circuit, thereby achieving uniform support for the third anode, thereby effectively improving the flatness of the third anode.

[0111] Furthermore, since the influence becomes smaller as the metal layer is farther away from the anode, when the symmetry of the first source and drain SD1 in the first direction is not good, the third gate layer can be used to compensate for it.

[0112] Optionally, a projection of the third gate layer in the projection region of the third anode and a projection of the second metal layer in the projection region of the third anode are symmetrical along the first direction.

[0113] Exemplarily, as shown in FIG21 , a projection 61 of the third gate layer in the projection region of the third anode is symmetrical with a projection 55 of the second metal layer in the projection region of the third anode in the first direction.

[0114] In a feasible embodiment, in addition to optimizing the anode flatness through routing, the via design of the interlayer dielectric layer ILD and the flat layers (including the first flat layer PLN1, the second flat layer PLN2 and the third flat layer PLN3) will also affect the flatness of the anode.

[0115] In the related art, as shown in Figures 22 and 23, when the width of the opening of the pixel definition layer in a cross section parallel to the display panel is 22μm, the aperture ratio is 20.56%. The pixel definition layer (PDL as shown in the figure) may have a first opening corresponding to the first anode (first sub-pixel area), a second opening corresponding to the second anode (second sub-pixel area), and a third opening corresponding to the third anode (third sub-pixel area). There are 3 holes in the projected area of ​​the first opening, 2.5 holes in the projected area of ​​the second opening, and 4.5 holes in the projected area of ​​the third opening. The second sub-pixel has a -0.3μm overlap with the first planar layer PLN1. The distance d1 from the boundary of the third planar layer PLN3 to the boundary of the first opening is 13.6μm, the distance d2 to the boundary of the second opening is 25.115μm, and the distance d3 to the boundary of the third opening is 11.055μm.

[0116] Those skilled in the art will appreciate that the aforementioned 2.5 holes and 4.5 holes should be interpreted broadly. That is, if a portion of a via does not fall within a specific projected area, the cross-sectional area of ​​the via that does not fall within the projected area may be 30%-70%, for example, 40%-60%, of the overall cross-sectional area of ​​the via.

[0117] In the embodiment of the present application, the aperture ratio of the pixel defining layer is limited to 15.93%, which means that the projection areas of the first opening and the second opening include 3 via holes, and the projection area of ​​the third opening includes 1.5 via holes.

[0118] For example, as shown in Figures 24 and 25, after the restricted pixel definition layer, the projected area of ​​the first opening includes three vias, the projected area of ​​the second opening includes three vias, and the projected area of ​​the third opening includes 1.5 vias. The boundary of the second opening is +1.6μm away from the boundary of the vias in the first planar layer. The distance d1 from the boundary of the third planar layer PLN3 to the boundary of the first opening is 14.25μm, the distance d2 to the boundary of the second opening is 26.2μm, and the distance d3 to the boundary of the third opening is 12.625μm.

[0119] It should be noted here that the above-mentioned vias (10a-10c as shown in the figure) can be through-vias formed in, but not limited to, interlayer dielectric layers (such as the aforementioned first interlayer dielectric layer ILD0, second interlayer dielectric layer ILD) and the first flat layer PLN1, the second flat layer PLN2, and the third flat layer PLN3 in order to achieve electrical connection between metal traces and / or between electrodes and structures such as active layers.

[0120] Thus, by limiting the aperture ratio of the pixel-defining layer, the number of vias corresponding to the projected area of ​​the pixel opening is further reduced, thereby achieving the goal of improving anode flatness. At the same time, the edge of the second sub-pixel opening is effectively prevented from overlapping with the vias on the first planarization layer, further improving the flatness of the pixel anode edge.

[0121] In the description of this specification, it should be understood that the terms "upper," "lower," "front," "back," "length," "width," "left," "right," "vertical," "horizontal," "top," "bottom," and the like, indicating positions or locations, are based on the positions or locations shown in the accompanying drawings and are intended only to facilitate the description of this application and simplify the description. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting this application. For example, "upper" and "lower" are used to describe the relative relationship of one component in the drawings to another component, but these terms are used in this specification for convenience only, such as based on the orientation of the examples shown in the drawings. It should be understood that if the device in the drawings is flipped so that it is upside down, the component described as "upper" would become the component "lower." When a structure is "on" another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0122] In this application, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be interpreted broadly. For example, they can refer to fixed, removable, or integrated connections; mechanical, electrical, or communication connections; direct or indirect connections through an intermediate medium; internal communication between two components; or interaction between two components. A person skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances. In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or the first and second features being in contact through another feature between them. Furthermore, "above," "above," and "above" a first feature may include the first feature being directly above or diagonally above the second feature, or simply indicate that the first feature is at a higher level than the second feature. "Below," "below," and "below" a first feature may include the first feature being directly above or diagonally above the second feature, or simply indicate that the first feature is at a lower level than the second feature.

[0123] The above application provides many different embodiments or examples for implementing the different structures of the present application. In order to simplify the present application, the components and settings of specific examples are described above. Of course, these are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0124] The above are only specific embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various modifications or substitutions within the technical scope disclosed in this application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A display panel comprising a first metal layer and an anode layer stacked on a base substrate, The first metal layer includes a first signal line, a second signal line and a third signal line arranged at equal intervals; An orthographic projection of the second signal line on the base substrate at least partially overlaps with the anode layer.

2. The display panel according to claim 1, wherein The display panel comprises first pixel circuits and second pixel circuits alternately arranged along a first direction, wherein the first pixel circuits and the second pixel circuits are symmetrically arranged along a second direction; The anode layer includes a first anode corresponding to the first sub-pixel and a second anode corresponding to the second sub-pixel; the first anode is symmetrical about a first boundary of the first pixel circuit, the second anode is symmetrical about a second boundary of the second pixel circuit, and the first boundary of the first pixel circuit is parallel to the second boundary of the second pixel circuit; The second signal line includes a first part corresponding to the first pixel circuit and a second part corresponding to the second pixel circuit. In the orthographic projection of the first part and the second part on the substrate, the part located in the first sub-pixel area is symmetrical about the first boundary of the first pixel circuit, and the part located in the second sub-pixel area is symmetrical about the second boundary of the second pixel circuit.

3. The display panel according to claim 2, wherein: The distance between the first signal line and the second signal line is greater than or equal to 2.5 μm, Alternatively, the distance between the second signal line and the third signal line is greater than or equal to 2.5 μm, and the widths of the first signal line, the second signal line, and the third signal line are independently greater than or equal to 2 μm.

4. The display panel according to claim 2, wherein: It also includes a second metal layer, which has a first auxiliary metal line, and the positive projection of the first auxiliary metal line on the base substrate at least partially overlaps with the positive projection of the anode on the base substrate, and the overlapping area between the first auxiliary metal line and the projection of the third signal line on the base substrate is less than 20% of the projection of the third signal line on the base substrate.

5. The display panel according to claim 4, wherein: The first auxiliary metal line is disposed at a projected position of a first boundary of the first pixel circuit, and the first auxiliary metal line is symmetrical with respect to the first boundary of the first pixel circuit, or, The first auxiliary metal line is disposed on a second boundary of the second pixel circuit, and the first auxiliary metal line is symmetrical with respect to the second boundary of the second pixel circuit. The display panel according to claim 5 , wherein: The width of the first auxiliary metal line is greater than or equal to 2 μm.

7. The display panel according to claim 2, wherein: The anode layer further includes a third anode corresponding to the third sub-pixel, wherein an orthographic projection of the third anode on the substrate partially overlaps with the first pixel circuit and the second pixel circuit, respectively, and the third anode has a symmetry axis extending along the first direction; The projection of the first signal line in the third anode region is an integrated structure.

8. The display panel according to claim 2, wherein: The base substrate further includes a first reset power line, a second reset power line, and a third reset power line, wherein the first reset power line, the second reset power line, and the third reset power line are mesh-connected.

9. The display panel according to claim 8, wherein: The second metal layer also includes a second auxiliary metal line and a third auxiliary metal line, and the orthographic projections of the second auxiliary metal line and the third auxiliary metal line on the base substrate have at least partial overlaps with the orthographic projection of the third anode on the substrate; the second auxiliary metal line and the third auxiliary metal line are symmetrically distributed along the second direction.

10. The display panel according to claim 8, wherein: It further includes first to third gate layers stacked in sequence on the base substrate, wherein the first to third gate layers are all located between the base substrate and the first metal layer, and the projection of the third gate layer in the projection area of ​​the third anode is symmetrical with the projection of the second metal layer in the projection area of ​​the third anode along the first direction.

11. The display panel according to claim 8, wherein: The display panel further includes a pixel defining layer having first to third openings, wherein the first opening corresponds to the first anode, the second opening corresponds to the second anode, and the third opening corresponds to the third anode. The first opening and the second opening include three via holes within the projection area of ​​the base substrate, and the third opening includes 1.5 via holes within the projection area of ​​the base substrate.

12. The display panel according to any one of claims 2 to 11, wherein: The first signal line is a driving power line of the display panel, the second signal line is an auxiliary driving power line, and the third signal line is a data signal line of the display panel.

13. The display panel according to any one of claims 1 to 11, wherein: The first metal layer is a second source-drain electrode layer, and the second metal layer is a first source-drain electrode layer.

14. The display panel according to any one of claims 1 to 11, wherein: The pixel circuit includes: a first transistor, wherein a gate of the first transistor is connected to a first reset signal line, a first electrode of the first transistor is connected to a first reset power line, and a second electrode of the first transistor is connected to a third node; a second transistor, wherein a gate of the second transistor is connected to a first gate signal line included in the display panel, a first electrode of the second transistor is connected to the first node, and a second electrode of the second transistor is connected to the third node; a third transistor, wherein a gate of the third transistor is connected to the first node, a first electrode of the third transistor is connected to the second node, and a second electrode of the third transistor is connected to the third node; a fourth transistor, wherein a gate of the fourth transistor is connected to a second gate signal line included in the display panel, a first electrode of the fourth transistor is connected to a data signal line included in the display panel, and a second electrode of the fourth transistor is connected to the second node; a fifth transistor, wherein a gate of the fifth transistor is connected to the light emitting control signal line, a first electrode of the fifth transistor is connected to a driving power line included in the display panel, and a second electrode of the fifth transistor is connected to the second node; a sixth transistor, wherein a gate of the sixth transistor is connected to the light-emitting control signal line, a first electrode of the sixth transistor is connected to the third node, and a second electrode of the sixth transistor is connected to the light-emitting unit; a seventh transistor, wherein a gate of the seventh transistor is connected to a second gate signal line included in the display panel, a first electrode of the seventh transistor is connected to a second reset power line, and a second electrode of the seventh transistor is connected to the light-emitting unit; an eighth transistor, wherein the gate of the eighth transistor is connected to the second reset signal line, the first electrode of the eighth transistor is connected to the third reset power line included in the display panel, and the a second electrode of the eighth transistor connected to the second node; A storage capacitor, one end of which is connected to the driving power line, and the other end of which is connected to the first node.

15. A display device, comprising the display panel according to any one of claims 1 to 14.

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