Semiconductor device and manufacturing method therefor

Abstract

The present invention relates to the technical field of semiconductors, and in particular to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises a substrate, nanosheet channels, a metal gate, a source-drain region, and an insulating dielectric layer, wherein the nanosheet channels are located above the substrate, the metal gate surrounds the nanosheet channels, the source-drain region is connected to the nanosheet channels, and the insulating dielectric layer is located between the substrate and the source-drain region and between the substrate and the nanosheet channels. According to the present invention, etching of silicon in the source-drain region is added to form a trench where a source and a drain are communicated, and then an insulating dielectric material fills the trench to form complete isolation between the bottoms of the channels and the bottoms of the source and the drain, so that a substrate parasitic channel and channel leakage between the source and the drain are fundamentally eliminated.

Description

Semiconductor device and method for manufacturing the same Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] With the continuous scaling of transistor feature sizes, traditional MOSFET devices have undergone a transition from planar to three-dimensional structures, improving device performance while mitigating the impact of short-channel effects. Currently, research progress in GAA stacked nanosheet FETs has garnered widespread attention from both academia and industry. Continuously updated fabrication processes and key techniques, along with optimized device structures, are a hot research area for new CMOS devices, considered the mainstream device beyond the 3nm node.

[0003] The GAA stacked nanosheet FET, a novel device developed from FinFET and Nanowire-FET, features a gate-all-around structure and a horizontal nanosheet (NS) as the conductive channel. In terms of gate control, the gate-all-around structure offers superior gate control capabilities compared to FinFET devices, effectively suppressing the short-channel effect. In terms of current drive, the Nanosheet-GAAFET, with its adjustable gate and vertical and horizontal stacking design, significantly enhances the device's current drive performance.

[0004] In conventional CMOS integration processes for stacked nanosheet GAA-FETs, heavy doping with a type opposite to the source and drain doping of the device is typically required on the silicon substrate (or well region) to weaken or prevent leakage from the parasitic substrate channel between the source and drain. However, this parasitic substrate channel (parasitic FinFET) degrades GAA device characteristics, leading to gate failure under the short channel. The heavily doped substrate forms a bilateral heavily doped PN junction between the source and drain regions, increasing reverse junction leakage in the source and drain regions and the overall leakage current of the device.

[0005] Based on this, the present invention proposes a new method for preparing a semiconductor device. The method has a simple process and is compatible with the existing GAA process. It mainly forms an insulating dielectric isolation at the bottom of the source and drain regions and the bottom of the channel through an integrated process to eliminate the substrate parasitic channel and channel leakage between the source and drain.

[0006] Summary of the Invention

[0007] The object of the present invention is to provide a semiconductor device and a method for preparing the same, which forms an insulating dielectric isolation at the bottom of the source and drain regions and the bottom of the channel through an integrated process, thereby fundamentally eliminating the substrate parasitic channel and channel leakage between the source and drain.

[0008] In a first aspect, the present invention provides a semiconductor device comprising a substrate, a nanosheet channel, a metal gate, a source / drain region, and an insulating dielectric layer, wherein the nanosheet channel is located above the substrate, the metal gate surrounds the nanosheet channel, the source / drain region is connected to the nanosheet channel, and the insulating dielectric layer is located between the substrate and the source / drain region and the nanosheet channel.

[0009] As a preferred embodiment of this technical solution, it also includes an interlayer dielectric layer, a first conductive channel and a second conductive channel, the interlayer dielectric layer is located above the source and drain regions, the first conductive channel and the second conductive channel are both arranged inside the interlayer dielectric layer, and the first conductive channel is connected to the source and drain regions, and the second conductive channel is connected to the metal gate.

[0010] In a second aspect, the present invention further discloses a method for preparing the above-mentioned semiconductor device, which should also fall within the scope of protection of the present invention. The preparation method comprises the following steps:

[0011] By increasing the etching of silicon in the source and drain regions, trenches through which the source and drain penetrate are formed, and then insulating dielectric materials are filled in the trenches to form complete isolation between the bottom of the channel and the bottom of the source and drain.

[0012] As a preferred embodiment of this technical solution, the following steps are specifically included:

[0013] S1. A sacrificial layer and a channel layer are sequentially grown on a substrate, and the channel layer, the sacrificial layer and a portion of the substrate are etched into a plurality of periodically distributed fins, and a shallow trench isolation region is formed between two adjacent fins;

[0014] S2, forming a dummy gate layer on the exposed fin surface;

[0015] S3, depositing a first spacer dielectric on both sides of the dummy gate layer, and then etching the first spacer dielectric in the horizontal direction to form a first spacer; performing source and drain etching on the fin to form source and drain regions on both sides of the first spacer for preparing source and drain electrodes; etching away the edge portion of the sacrificial layer in the center direction of the source and drain region to form an embedded groove; depositing a second spacer dielectric so that the second spacer dielectric covers the entire surface and fills the embedded groove to form a second spacer; using anisotropic etching to remove the horizontal portion of the second spacer dielectric;

[0016] S4, etching the source and drain of the fin by an etching process, and penetrating the bottom of the trench by isotropic etching, and depositing an insulating dielectric material into the trench so that the insulating dielectric material covers the entire surface to form an insulating dielectric layer;

[0017] S5, isotropically etching the filled insulating dielectric layer to retain a portion of the underlying insulating dielectric layer; isotropically etching the second sidewall to remove a portion of the second sidewall dielectric in a vertical direction to form an inner sidewall;

[0018] S6. Epitaxially growing source and drain regions on the surface of the insulating dielectric layer, and doping the source and drain regions at the same time.

[0019] As a preferred embodiment of the present technical solution, in step S1 , the height of the fin is 10 nm-400 nm, the width is 1-100 nm, and the etching stops at or below the substrate.

[0020] As a preferred embodiment of the present technical solution, in step S3, the material of the first spacer dielectric and the second spacer dielectric includes any one or more of silicon nitride, doped silicon oxide and doped silicon carbide.

[0021] As a preferred embodiment of the present technical solution, in step S4, when the source and drain are etched, the aspect ratio of the formed trenches is h / a>1.

[0022] As a preferred embodiment of the present technical solution, in step S4, when filling the insulating dielectric material, the thickness b of the deposited film is greater than 0.5a.

[0023] As a preferred embodiment of the present technical solution, in step S6, when the source and drain regions are doped, for P-type FETs, the source and drain region materials are boron-doped SiGe, and for N-type FETs, the source and drain region materials are phosphorus-doped silicon.

[0024] As a preferred embodiment of this technical solution, the following steps are also included:

[0025] S7, depositing an interlayer dielectric in the source and drain regions, and performing chemical mechanical polishing on the interlayer dielectric until the dummy gate layer is exposed;

[0026] S8, etching and removing the dummy gate layer;

[0027] S9, etching away the sacrificial layer to release the channel layer to form a nanosheet channel;

[0028] S10, depositing a high-K metal gate to form a metal gate surrounding the nanosheet channel;

[0029] S11 , continue depositing an interlayer dielectric to form contact holes respectively contacting the source / drain region and the metal gate, etch the contact holes, and deposit silicon compounds to form a first conductive channel and a second conductive channel, respectively.

[0030] The semiconductor device and the method for manufacturing the same of the present invention have at least the following technical effects:

[0031] 1. The semiconductor device of the present invention includes a substrate, a nanosheet channel, a metal gate, a source / drain region, and an insulating dielectric layer. The insulating dielectric layer is located between the substrate, the source / drain region, and the nanosheet channel. Compared with the prior art, the provision of the insulating dielectric layer fundamentally eliminates the substrate parasitic channel and channel leakage between the source / drain region.

[0032] 2. In the process of preparing semiconductor devices, the present invention forms a trench through which the source and drain penetrate by increasing the etching of silicon in the source and drain regions, and then fills the trench with insulating dielectric material, thereby forming a complete isolation between the bottom of the channel and the bottom of the source and drain. Compared with processes such as heavy doping of the active region, the process cost is greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] FIG1 is a cross-sectional view along the XX' direction after a SiGe / Si stacked superlattice layer is grown on a silicon substrate according to the present invention;

[0035] FIG2 is a cross-sectional view along the XX' direction after the superlattice stack is formed into a plurality of periodically distributed fins according to the present invention;

[0036] FIG3 is a cross-sectional view along the XX′ direction after a shallow trench isolation region is formed between two adjacent fins according to the present invention;

[0037] FIG4 is a cross-sectional view along the XX′ direction after a dummy gate stack is formed on the exposed fin surface according to the present invention;

[0038] FIG5 is a cross-sectional view along the YY' direction after forming a dummy gate stack on the exposed fin surface of the present invention;

[0039] FIG6 is a cross-sectional view along the YY' direction after the dummy gate structure is patterned and formed according to the present invention;

[0040] FIG7 is a cross-sectional view along the YY' direction after depositing the first sidewall dielectric of the present invention;

[0041] 8 is a cross-sectional view along the YY' direction after etching the first sidewall dielectric to form the first sidewall according to the present invention;

[0042] FIG9 is a cross-sectional view along the YY' direction after etching the edge of the sacrificial layer according to the present invention;

[0043] FIG10 is a cross-sectional view along the YY' direction after the inner sidewall dielectric is deposited according to the present invention;

[0044] FIG11 is a cross-sectional view along the YY' direction after removing the horizontal portion of the inner wall dielectric of the present invention;

[0045] FIG12 is a schematic diagram of the three-dimensional structure of the present invention after forming a channel;

[0046] FIG13 is a partial cross-sectional view along the XX' direction before forming a channel of the present invention;

[0047] FIG14 is a cross-sectional view along the YY' direction after the trench is formed according to the present invention;

[0048] FIG15 is a partial cross-sectional view along the XX' direction after the trench is formed according to the present invention;

[0049] FIG16 is a cross-sectional view along the XX' direction after the trench is formed according to the present invention;

[0050] FIG17 is a cross-sectional view along the YY' direction after the insulating dielectric material is deposited according to the present invention;

[0051] FIG18 is a cross-sectional view along the YY' direction after the insulating dielectric layer is isotropically etched and filled according to the present invention;

[0052] FIG19 is a cross-sectional view along the YY' direction after the inner side wall is formed according to the present invention;

[0053] FIG20 is a cross-sectional view along the YY' direction after forming the epitaxially grown source and drain regions of the present invention;

[0054] 21 is a cross-sectional view along the YY' direction after depositing an interlayer dielectric layer in the source and drain regions of the present invention;

[0055] FIG22 is a cross-sectional view along the YY' direction after the dummy gate layer is etched away according to the present invention;

[0056] FIG23 is a cross-sectional view along the XX' direction after selectively etching the sacrificial layer in the superlattice stack according to the present invention;

[0057] FIG24 is a cross-sectional view along the XX' direction after depositing a high-K metal gate according to the present invention;

[0058] FIG25 is a cross-sectional view along the XX′ direction after top deposition of an interlayer dielectric according to the present invention.

[0059] Explanation of the accompanying drawings: 1: substrate; 2: sacrificial layer; 3: channel layer; 4: hard mask layer; 5: shallow trench isolation region; 6: dummy gate layer; 7: first sidewall; 8: second sidewall; 9: trench; 10: insulating dielectric layer; 11: inner sidewall; 12: source and drain regions; 13: interlayer dielectric layer; 14: metal gate; 15: first conductive channel; 16: second conductive channel. DETAILED DESCRIPTION

[0060] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0061] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0062] In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. In addition, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a communication between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0063] This embodiment provides a method for manufacturing a semiconductor device, comprising the following steps:

[0064] S1, sequentially growing a sacrificial layer 2 and a channel layer 3 on a substrate 1, etching the channel layer 3, the sacrificial layer 2 and a portion of the substrate 1 into a plurality of periodically distributed fins, and forming a shallow trench isolation region 5 between two adjacent fins;

[0065] S2, forming a dummy gate layer 6 on the exposed fin surface;

[0066] S3, depositing a first spacer dielectric on both sides of the dummy gate layer 6, and then etching the first spacer dielectric in the horizontal direction to form a first spacer 7; performing source and drain etching on the fin to form source and drain regions 12 on both sides of the first spacer 7 for preparing source and drain electrodes; etching away the edge portion of the sacrificial layer 2 in the center direction of the source and drain region 12 to form an embedded groove; depositing a second spacer dielectric so that the second spacer 8 dielectric covers the entire surface and fills the embedded groove to form a second spacer 8; using anisotropic etching, removing the horizontal portion of the second spacer dielectric;

[0067] S4, etching the fins for source and drain, and isotropically etching through the bottom of the trench, depositing an insulating dielectric material into the trench 9 so that the insulating dielectric material covers the entire surface, forming an insulating dielectric layer 10;

[0068] S5, isotropically etching the filled insulating dielectric layer 10, leaving a portion of the bottom insulating dielectric layer 10; isotropically etching the second sidewall 8, removing the portion of the dielectric in the second sidewall 8 in the vertical direction, to form an inner sidewall 11;

[0069] S6, epitaxially growing source and drain regions 12 on the surface of the insulating dielectric layer 10, and doping the source and drain regions 12 at the same time;

[0070] S7, depositing an interlayer dielectric in the source / drain region 12, and performing chemical mechanical polishing on the interlayer dielectric until the dummy gate layer 6 is exposed;

[0071] S8, etching and removing the dummy gate layer 6;

[0072] S9, etching and removing the sacrificial layer 2 to release the channel layer 3 to form a nanosheet channel;

[0073] S10, depositing a high-K metal gate 14 to form a metal gate 14 surrounding the nanosheet channel;

[0074] S11 , continue depositing interlayer dielectric to form contact holes contacting the source / drain region 12 and the metal gate 14 , etch the contact holes, and deposit silicon compounds to form a first conductive channel 15 and a second conductive channel 16 .

[0075] The preparation method is described in more detail below:

[0076] In step S1, as shown in FIG1 , a sacrificial layer 2 and a channel layer 3 are first grown in sequence on a substrate 1 by epitaxy, wherein the substrate 1 is generally a silicon substrate 1, the sacrificial layer 2 is generally SiGe, and the channel layer 3 is generally Si. The sacrificial layer 2 and the channel layer 3 are a superlattice structure. The Si layer determines the number of subsequent nanowires. The Si layer is ≥1, and each layer is less than 30 nm. The final thickness directly determines the height of the nanosheet channel and the electrical properties.

[0077] Based on the above, as shown in Figure 2, the sacrificial layer 2 and the channel layer 3 are further formed into a plurality of periodically distributed fins. Specifically, a hard mask layer 4 is deposited above the topmost channel layer 3. After patterning, the epitaxially grown superlattice stack is etched to form a plurality of periodically distributed fins. The fins have a height of 10nm-400nm and a width of 1-100nm. The etching stops at or below the substrate 1.

[0078] Based on the above, as shown in Figure 3, a shallow trench isolation (STI) region 5 is formed between two adjacent fins. Specifically, an insulating dielectric material is first deposited and planarized to expose the hard mask layer 4. The hard mask layer 4 is then removed by wet or dry etching. The insulating dielectric material is then selectively etched back to expose the three-dimensional fin structure, forming a shallow trench isolation region 5 between adjacent fins. The upper surface of the shallow trench isolation region 5 is generally flush with the interface between the superlattice stack structure in the fin and the single crystal silicon substrate 1, but can also be above or below the interface level.

[0079] In step S2, as shown in Figures 4-5, a dummy gate layer 6 is formed on the exposed fin surface. Specifically, an oxide layer and polysilicon (or amorphous silicon) are sequentially deposited above the shallow trench isolation region 5, and CMP is performed. Then, a dummy gate hard mask layer is deposited. Then, as shown in Figure 6, a dummy gate across the fin is formed through photolithography and etching patterning processes. After etching, the hard mask layer above the dummy gate is retained.

[0080] The material of the dummy gate hard mask layer may be oxide, carbide, organic matter, etc.

[0081] In step S3, as shown in Figures 7-8, a first spacer dielectric is deposited on both sides of the dummy gate layer 6, and then the spacer dielectric in the horizontal direction is etched, leaving only the dielectric on the side walls of the dummy gate and the dummy gate hard mask layer to form a first spacer 7; then, based on Figure 8, with reference to Figure 9, the dummy gate hard mask layer 4 and the first spacer 7 are used as masks, and the fin is etched for source and drain through an etching process to form source and drain regions 12 for preparing source and drain electrodes on both sides of the first spacer 7, and the edge portion of the sacrificial layer 2 is etched away in the center direction of the source and drain region 12 to form an embedded groove; further, based on Figure 9, with reference to Figure 10, a second spacer dielectric is deposited so that the second spacer dielectric covers the entire surface and fills the embedded groove to form a second spacer 8; finally, based on Figure 10, with reference to Figure 11, anisotropic etching is used to remove the horizontal portion of the second spacer dielectric.

[0082] The materials of the first and second spacer dielectrics can be silicon nitride, doped silicon oxide, doped silicon carbide, etc. During etching, the sacrificial layer 2 and the channel layer 3 have a large etching selectivity, so the integrity of the channel layer 3 can be guaranteed.

[0083] In step S4, as shown in Figures 12-16, first, the dummy gate layer 6 hard mask and the first sidewall 7 are used as masks, and the source and drain etching of the fin is performed through the etching process, and the bottom of the channel is penetrated by isotropic etching. The etching depth can be slightly higher and lower than the bottom of the STI etching to ensure that the aspect ratio h / a of the groove 9 formed after the source and drain etching is greater than 1; then, referring to Figure 17, an insulating dielectric material is filled into the channel by a deposition method with good conformality such as atomic layer deposition or CVD, and the insulating dielectric material covers the entire surface to form an insulating dielectric layer 10. Specifically, the thickness b of the deposited film is greater than 0.5a to ensure that the source and drain channels are completely filled.

[0084] The deposited insulating dielectric material can be SiO2 or a low-dielectric dielectric material, and the material can be the same as or different from the material of the shallow trench isolation region 5.

[0085] In step S5, as shown in FIG18 , the filled insulating dielectric layer 10 is isotropically etched to retain a portion of the underlying insulating dielectric layer 10 ; then, referring to FIG19 , the second sidewall 8 is isotropically etched to remove the portion of the second sidewall dielectric located in the vertical direction to form an inner sidewall 11 .

[0086] In step S6, referring to FIG20, the source and drain regions 12 are epitaxially grown by metal organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth or similar methods or a combination of the foregoing, and the source and drain regions 12 are doped at the same time. For P-type FETs, the material of the source and drain regions 12 is boron-doped SiGe (SiGe:B), and for N-type FETs, the material of the source and drain regions 12 is phosphorus-doped silicon (Si:P).

[0087] As can be seen from the above-described preparation method, the inner sidewall 11 of the present invention is formed through two etches: the first is anisotropic etching to remove the sidewall film in the horizontal source and drain regions 12, and the second is isotropic etching to form the inner sidewall 11. Between the two etches of the inner sidewall 11, the present invention increases the etching of the silicon in the source and drain regions 12 to form a trench 9 through which the source and drain penetrate. This trench 9 is then filled with a highly conformal insulating dielectric film to completely isolate the bottom of the trench from the bottom of the source and drain. Therefore, the present invention forms insulating dielectric isolation at the bottom of the source and drain regions 12 and the bottom of the channel through an integrated process, fundamentally eliminating parasitic channels in the substrate 1 between the source and drain and channel leakage.

[0088] In step S7 , after the source / drain regions 12 are formed, as shown in FIG. 21 , an interlayer dielectric is deposited on the source / drain regions 12 , and chemical mechanical polishing is performed on the interlayer dielectric to planarize it, and the hard mask layer 4 is removed to expose the dummy gate layer 6 .

[0089] In step S8 , based on the above, further, as shown in FIG22 , the dummy gate layer 6 formed of the polysilicon or amorphous silicon is etched away by a selective etching or corrosion process.

[0090] In step S9 , based on the above, further, as shown in FIG23 , the sacrificial layer 2 in the superlattice stack is selectively etched to release the nanosheet channel.

[0091] In step S10 , based on the above, further, as shown in FIG24 , high-K metal gates are sequentially deposited and CMP is performed to form NMOS and PMOS metal gates.

[0092] In step S11, based on the above, further, as shown in Figure 25, an interlayer dielectric is deposited on the top, and dielectric CMP is performed, and then contact hole lithography and etching are performed, and silicide is deposited to form contact holes that are respectively in contact with the source and drain regions 12 and the metal gate 14, and a conductive channel is formed in the contact holes.

[0093] On the other hand, another embodiment of the present invention also provides a semiconductor device, specifically including a substrate 1, a nanosheet channel, a metal gate 14, a source and drain region 12, an insulating dielectric layer 10, an interlayer dielectric layer 13, a first conductive channel 15 and a second conductive channel 16, wherein the nanosheet channel is located above the substrate 1, the metal gate 14 surrounds the nanosheet channel, the source and drain region 12 is connected to the nanosheet channel, the insulating dielectric layer 10 is located between the substrate 1 and the source and drain region 12 and the nanosheet channel, and the interlayer dielectric layer 13 is located above the source and drain region 12; and the first conductive channel 15 and the second conductive channel 16 are both arranged inside the interlayer dielectric layer 13, and the first conductive channel 15 is connected to the source and drain region 12, and the second conductive channel 16 is connected to the metal gate 14.

[0094] The semiconductor device of the above embodiment is formed by the aforementioned method embodiment. The materials and characteristics of each part can be referred to the above method embodiment and will not be described again here.

[0095] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to achieve the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: It comprises a substrate (1), a nanosheet channel, a metal gate (14), a source and drain region (12) and an insulating dielectric layer (10), The nanosheet channel is located above the substrate (1), the metal gate (14) surrounds the nanosheet channel, the source and drain regions (12) are connected to the nanosheet channel, and the insulating dielectric layer (10) is located between the substrate (1) and the source and drain regions (12) and the nanosheet channel.

2. The semiconductor device according to claim 1, wherein: It also includes an interlayer dielectric layer (13), a first conductive channel (15) and a second conductive channel (16), The interlayer dielectric layer (13) is located above the source and drain regions (12); the first conductive channel (15) and the second conductive channel (16) are both located inside the interlayer dielectric layer (13); the first conductive channel (15) is connected to the source and drain regions (12); and the second conductive channel (16) is connected to the metal gate (14).

3. The method for preparing a semiconductor device according to any one of claims 1 to 2, characterized in that: The following steps are involved: By increasing the etching of silicon in the source and drain regions (12), a trench (9) through which the source and drain penetrate is formed, and then an insulating dielectric material is filled in the trench (9) to form complete isolation of the bottom of the trench and the bottom of the source and drain.

4. The preparation method according to claim 3, characterized in that: The specific steps include: S1, sequentially growing a sacrificial layer (2) and a channel layer (3) on a substrate (1), etching the channel layer (3), the sacrificial layer (2) and a portion of the substrate into a plurality of periodically distributed fins, and forming a shallow trench isolation region (5) between two adjacent fins; S2, forming a dummy gate layer (6) on the exposed surface of the fin; S3, depositing a first sidewall dielectric on both sides of the dummy gate layer (6), then etching the first sidewall dielectric in a horizontal direction to form a first sidewall (7); performing source and drain etching on the fin, and forming a first sidewall dielectric on the first sidewall (7). Forming source and drain regions (12) for preparing source and drain electrodes on both sides; etching away the edge portion of the sacrificial layer (2) in the center direction of the source and drain region (12) to form an embedded groove; depositing a second sidewall dielectric so that the second sidewall dielectric covers the entire surface and fills the embedded groove to form a second sidewall (8); and removing the portion of the second sidewall dielectric in the horizontal direction by anisotropic etching; S4, etching the fins for source and drain by an etching process, and penetrating the bottom of the trench by isotropic etching, depositing insulating dielectric material into the trench (9), so that the insulating dielectric material covers the entire surface, forming an insulating dielectric layer (10); S5, isotropically etching the filled insulating dielectric layer (10) to retain a portion of the bottom insulating dielectric layer (10); isotropically etching the second sidewall (8) to remove a portion of the second sidewall dielectric in a vertical direction to form an inner sidewall (11); S6. Epitaxially growing source and drain regions (12) on the surface of the insulating dielectric layer (10), and doping the source and drain regions (12) at the same time.

5. The preparation method according to claim 4, characterized in that: In step S1, the height of the fin is 10 nm-400 nm, and the width is 1-100 nm, and the etching stops at the substrate (1) or below the substrate (1).

6. The preparation method according to claim 4, characterized in that: In step S3, the materials of the first spacer dielectric and the second spacer dielectric include any one or more of silicon nitride, doped silicon oxide and doped silicon carbide.

7. The preparation method according to claim 4, characterized in that: In step S4, when the source and drain are etched, the depth-to-width ratio of the formed trench (9) is h / a>1.

8. The preparation method according to claim 4, characterized in that: In step S4, when filling the insulating dielectric material, the thickness of the deposited film is b>0.5a.

9. The preparation method according to claim 4, characterized in that: In step S6, when the source and drain regions (12) are doped, for a P-type FET, the material of the source and drain regions (12) is boron-doped SiGe, and for an N-type FET, the material of the source and drain regions (12) is phosphorus-doped silicon.

10. The preparation method according to claim 4, characterized in that: The following steps are also included: S7, depositing an interlayer dielectric on the source and drain region (12), and performing chemical mechanical polishing on the interlayer dielectric until the dummy gate layer (6) is exposed; S8, etching and removing the dummy gate layer (6); S9, etching away the sacrificial layer (2) to release the channel layer (3) to form a nanosheet channel; S10, depositing a high-K metal gate to form a metal gate (14) surrounding the nanosheet channel; S11, continue to deposit interlayer dielectric to form contact holes respectively contacting the source and drain regions (12) and the metal gate (14), etch the contact holes, deposit silicon compounds, and respectively form a first conductive channel (15) and a second conductive channel (16).

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