Chip, preparation method for chip, and electronic device

Abstract

Provided in the embodiments of the present application are a chip, a preparation method for a chip, and an electronic device. The present application relates to the technical field of semiconductors. The chip includes a back-side power distribution network architecture, which mainly aims to reduce the source-drain electrode contact resistance in the back-side power distribution network architecture. The chip comprises a gate electrode and a dummy gate electrode, a first semiconductor area and a second semiconductor area, and a source-drain electrode and a dummy source-drain electrode, wherein the gate electrode and the dummy gate electrode are arranged side by side, the source-drain electrode is arranged on the side face of the first semiconductor area that faces towards the second semiconductor area, and the dummy source-drain electrode is arranged on the side face of the second semiconductor area that faces towards the first semiconductor area; and a first source-drain electrode contact member is disposed between the source-drain electrode and the dummy source-drain electrode, and a second source-drain electrode contact member which is in contact with the first source-drain electrode contact member is provided at the bottom face of the first source-drain electrode contact member. By means of changing the structure of a source-drain electrode and of a source-drain electrode contact member, a low resistance is achieved.

Description

Chip, chip manufacturing method and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on June 16, 2023, with application number 202310725754.2 and invention name “Chip, Chip Preparation Method and Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a chip, a chip preparation method, and an electronic device. Background Art

[0003] In the backside power delivery network (BSPDN) architecture, the ability to provide large area scaling has become a key means of further miniaturizing chips. For example, when used in memory chips or logic control chips, it can reduce chip area and lower voltage drop (IRdrop), improving chip performance and reducing power consumption.

[0004] See Figure 1, which shows an example of a backside power distribution network architecture. A transistor 10 is integrated in a chip 100. A backside contact 20 can be set on the back side of the transistor 10 (the side away from the metal interconnection layer). The backside contact 20 is electrically connected to the source and drain of the transistor 10 to supply power to the transistor 10.

[0005] However, it is difficult to form a low contact resistance between the backside through hole 20 and the source and drain electrodes, and there is a technical problem of excessively large contact resistance.

[0006] Summary of the Invention

[0007] The present application provides a chip, a chip manufacturing method, and an electronic device. The main purpose is to provide a backside power distribution network architecture that can reduce backside via and source-drain resistance.

[0008] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0009] In one aspect, the present application provides a chip, which may be a memory chip or a logic control chip.

[0010] The chip includes a gate and a virtual gate, a first semiconductor region and a second semiconductor region, a source and a drain, and a virtual source and a drain; the gate is located on one side of the first semiconductor region, for example, a ring channel structure or a ring gate structure, the virtual gate is located on one side of the second semiconductor region, the source and the drain are arranged on the side of the first semiconductor region facing the second semiconductor region, and the virtual source and the drain are arranged on the side of the second semiconductor region facing the first semiconductor region; there is a first source and drain contact between the source and the drain and the virtual source and drain, and the bottom surface of the first source and drain contact has a second source and drain contact in contact with the first source and drain contact, for example, the second source and drain contact can be a back through-hole structure.

[0011] In the chip involved in this application, the source and drain may need to be powered, so a source-drain contact electrically coupled to the source and drain can be provided. In the implementation of this application, after the source and drain are provided on the side of the first semiconductor region that can generate electron flow, and the virtual source and drain are provided on the side of the second semiconductor region that does not generate electron flow, a first source-drain contact is formed between the source and drain and the virtual source and drain, and a second source-drain contact is provided on the back of the first source-drain contact, and the first source-drain contact is in contact with the second source-drain contact. In this way, a voltage can be applied to the source and drain through the second source-drain contact and the first source-drain contact to power the transistor.

[0012] In this application, the first source-drain contact is formed between the source and drain electrodes and the dummy source and drain electrodes, and contacts the second source-drain contact. In this structure, after passing through the first semiconductor region, current only needs to pass horizontally through the source and drain electrodes to reach the first metal source-drain contact. This shortens the path of the current signal in the semiconductor material, thereby reducing contact resistance.

[0013] In the aforementioned related art, silicon is used as the source and drain material, and metal is used as the source and drain contact. Metal and silicon can form a large contact resistance in a low temperature environment, for example, below 400°C. However, in the present application, the first source and drain contact is in contact with the second source and drain contact, for example, metal is in contact with metal, and the contact resistance between the two source and drain contacts is small. In addition, a metal silicide with low resistance can be formed at the interface between the first source and drain contact and the source and drain. In this way, the resistance between the source and drain and the first source and drain contact can be reduced. Thus, the contact resistance between the second source and drain contact as the back contact hole and the source and drain is reduced.

[0014] In one possible implementation, a first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer includes metal silicide.

[0015] For example, in a feasible process, metal silicide can be deposited on the side of the source and drain; or, in another feasible process, after filling a first source and drain contact of metal material between the source and drain and the virtual source and drain, annealing is performed to form an interface layer of metal silicide.

[0016] In one possible implementation, the second source-drain contact contacts contact the first interface layer.

[0017] In this implementation structure, not only does the second source-drain contact contact contact the first source-drain contact, reducing the contact resistance between the two source-drain contacts, but the second source-drain contact also contacts the metal silicide, which has a lower resistance and reduces the contact resistance between the second source-drain contact and the source and drain, thereby further reducing the contact resistance of the device.

[0018] In one possible implementation, the bottom surfaces of the source and drain electrodes have a second interface layer, and the first interface layer includes metal silicide; the second source and drain contacts are in contact with the second interface layer on the bottom surfaces of the source and drain electrodes.

[0019] The second source-drain contact not only contacts the metal silicide on the side surfaces of the source and drain, but also contacts the metal silicide on the bottom surfaces of the source and drain, thereby further reducing the source-drain contact resistance of the device.

[0020] In one possible implementation, the first source-drain contact is manufactured using a front-side process, and the second source-drain contact is manufactured using a back-side process.

[0021] The first source-drain contact is manufactured by a front-side process, and the second source-drain contact is manufactured by a back-side process. This does not complicate the process and is compatible with existing process.

[0022] In one possible implementation, the source and drain have a middle position along the depth direction of the source and drain, and the middle position is located at half of the source and drain depth dimension; the contact surface between the first source and drain contact and the second source and drain contact is located on the side of the middle position away from the top surface of the source and drain.

[0023] For example, in some processes, if a deposition method is used to form an interface layer between the source and drain and the first source and drain contact, the interface layer can be located below the middle position of the source and drain. In some examples, the contact surface between the first source and drain contact and the second source and drain contact is located below the middle position, thereby increasing the area of ​​the interface layer and reducing the contact resistance.

[0024] In one possible implementation, the substrate has a first surface and a second surface; the gate, the virtual gate, the first semiconductor region, the second semiconductor region, the source and drain, the virtual source and drain, and the first source and drain contact are arranged on one side of the first surface of the substrate; the second source and drain contact passes through the first surface and the second surface of the substrate and contacts the first source and drain contact; the contact surface between the first source and drain contact and the second source and drain contact is located between the bottom surface of the source and drain and the first surface of the substrate.

[0025] In some processes, whether deposition or annealing is used to produce an interface layer containing metal silicide, the contact surface between the first source-drain contact and the second source-drain contact is set between the bottom surface of the source and drain and the first surface of the substrate, so that the area of ​​the interface layer can be larger and the contact resistance of the source and drain can be reduced.

[0026] In a possible implementation, a third source-drain contact is formed on a top surface of the first source-drain contact; the first source-drain contact and the third source-drain contact are an integrated structure.

[0027] In some related technologies, the first source-drain contact and the third source-drain contact are manufactured using two process steps, while the present application uses one process to manufacture an integrated first source-drain contact and a third source-drain contact, thereby reducing the contact resistance between the first source-drain contact and the third source-drain contact.

[0028] In a possible implementation, a third interface layer is provided on the top surface of the source and drain electrodes, and the third interface layer includes metal silicide; and the third source and drain contacts are in contact with the third interface layer on the top surface of the source and drain electrodes.

[0029] Since metal silicide has a relatively low resistance, the third source-drain contact contacts contact the interface layer containing the metal silicide, thereby further reducing the contact resistance.

[0030] In a possible implementation, the first source-drain contact, the second source-drain contact, and the third source-drain contact are made of the same material.

[0031] For example, at least one of Ti, Co, Ni, Mo, and Nb may be used.

[0032] In another aspect, the present application provides a method for preparing a chip, the method comprising:

[0033] A gate and a dummy gate, a first semiconductor region and a second semiconductor region, a source and a drain, and a dummy source and drain are formed, the gate and the dummy gate are arranged side by side, the first semiconductor region is located on one side of the gate or is surrounded by the gate, the second semiconductor region is located on one side of the dummy gate or is surrounded by the dummy gate, the source and the drain are arranged on a side of the first semiconductor region facing the second semiconductor region, the dummy source and the drain are arranged on a side of the second semiconductor region facing the first semiconductor region, and a gap is formed between the source and the drain and the dummy source and drain;

[0034] forming a first source-drain contact in the gap;

[0035] A second source-drain contact is formed on a bottom surface of the first source-drain contact, and the first source-drain contact is in contact with the second source-drain contact.

[0036] In the chip structure manufactured using the fabrication method disclosed herein, the first source-drain contact contacts the second source-drain contact, for example, by metal-to-metal contact, resulting in a low contact resistance between the two source-drain contacts. Furthermore, a low-resistance metal silicide (salicide) can be formed at the interface between the first source-drain contact and the source-drain electrode, thereby reducing the resistance between the source-drain electrode and the first source-drain contact. Consequently, the contact resistance between the second source-drain contact, which serves as a back contact hole, and the source-drain electrode is reduced.

[0037] In one possible implementation, a first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer contains metal silicide; a second source-drain contact is formed on the bottom surface of the first source-drain contact, including: the second source-drain contact is in contact with the first interface layer.

[0038] The second source-drain contact not only contacts the first source-drain contact, but also contacts the interface layer with smaller resistance, thereby further reducing the resistance between the second source-drain contact and the source and drain.

[0039] In one possible implementation, a first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer contains metal silicide, including: depositing metal silicide on the surface of the source-drain so that a first interface layer containing metal silicide is formed at the interface between the first source-drain contact and the source-drain.

[0040] In this process, an interface layer including metal silicide is formed by a deposition method.

[0041] In one possible implementation, a first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer contains metal silicide, including: annealing the first source-drain contact to form a first interface layer containing metal silicide at the interface between the first source-drain contact and the source-drain.

[0042] In this process, an interface layer containing metal silicide is prepared by annealing the second source-drain contact of the metal material.

[0043] In one possible implementation, before forming the first source-drain contact in the gap, the preparation method also includes: the top surface of the gap has a through hole opened in the dielectric layer, and the through hole is connected to the gap; forming the first source-drain contact in the gap includes: forming the first source-drain contact in both the through hole and the gap.

[0044] The first source-drain contact includes: a portion disposed between the source-drain and the virtual source-drain, and a portion located on one side of the top surface of the source-drain and the virtual source-drain. In the implementation process, the two portions are formed simultaneously.

[0045] In one possible implementation, the first source-drain contact is manufactured using a front-side process, and the second source-drain contact is manufactured using a back-side process.

[0046] On the other hand, the present application provides a chip packaging structure, which includes a first chip and a second chip. The first chip includes the chip in any of the above implementations, and the first chip is electrically connected to the second chip.

[0047] In this chip packaging structure, the first chip includes a backside power distribution network (BSPDN) architecture. The second source-drain contact, which serves as a backside via, contacts the first source-drain contact located between the source and drain electrodes and the dummy source and drain electrodes. The contact resistance between the two source-drain contacts is low. In addition, a low-resistance metal silicide (salicide) can be formed at the interface between the first source-drain contact and the source and drain electrodes, thereby reducing the resistance between the source and drain electrodes and the first source-drain contact. Consequently, the contact resistance between the second source-drain contact, which serves as a backside contact hole, and the source and drain electrodes is reduced.

[0048] In one possible implementation, the first chip and the second chip are stacked in three dimensions.

[0049] In a possible implementation, the first chip and the second chip are respectively integrated on a substrate.

[0050] On the other hand, the present application also provides an electronic device, including a circuit board and a chip in any of the above implementations, wherein the chip is arranged on the circuit board.

[0051] The electronic device provided in the embodiment of the present application includes the above-mentioned chip. Therefore, the electronic device provided in the embodiment of the present application and the chip of the above-mentioned technical solution can solve the same technical problems and achieve the same expected effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] FIG1 is a structural diagram of an example of a backside distribution network architecture;

[0053] FIG2 is a structural diagram of a chip package structure including a backside power distribution network architecture;

[0054] FIG3 is a partial process structure diagram of a chip including a backside power distribution network architecture provided by an embodiment of the present application;

[0055] FIG4 is a partial process structure diagram of a chip including a backside power distribution network architecture provided by an embodiment of the present application;

[0056] FIG5 is a partial process structure diagram of a chip including a backside power distribution network architecture provided by an embodiment of the present application;

[0057] FIG6 is a partial process structure diagram of a chip including a backside power distribution network architecture provided by an embodiment of the present application;

[0058] FIG7 is a partial process structure diagram of a chip including a backside power distribution network architecture provided by an embodiment of the present application;

[0059] FIG8 is a partial process structure diagram of a chip including a backside power distribution network architecture provided by an embodiment of the present application;

[0060] 9A to 9D are process structure diagrams corresponding to some steps in a process for preparing a chip including a backside power distribution network architecture provided by an embodiment of the present application;

[0061] 10A to 10D are process structure diagrams corresponding to some steps in a process for preparing a chip including a backside power distribution network architecture provided by an embodiment of the present application;

[0062] 11A to 32 are process structure diagrams corresponding to some steps in a preparation process of a chip including a backside power distribution network architecture provided in an embodiment of the present application. DETAILED DESCRIPTION

[0063] An embodiment of the present application provides an electronic device, which may be a mobile phone, a tablet personal computer, a laptop computer, a personal digital assistant (PDA), a camera, a personal computer, a notebook computer, an in-vehicle device, a wearable device, augmented reality (AR) glasses, an AR helmet, virtual reality (VR) glasses or a VR helmet, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder, etc.

[0064] In electronic devices such as the above examples, a backside power delivery network (BSPDN) architecture may be included.

[0065] For example, in FIG2 , a plurality of transistors are integrated in the first chip 101 . For example, the first chip 101 may be a memory chip. A backside contact 20 may be provided on the back side of the transistor. The backside contact 20 electrically connects the source and drain of the transistor of the first chip 101 .

[0066] In some examples, the first chip 101 and the second chip 102 in FIG. 2 may be three-dimensionally stacked and packaged to form a package structure including the first chip 101 .

[0067] In some other examples, the first chip 101 and the second chip 102 may be integrated on a substrate respectively. For example, the first chip 101 and the second chip 102 may be electrically connected via metal traces arranged on the substrate.

[0068] In a backside power distribution network (BSPDN) architecture such as the first chip 101 , in order to reduce the contact resistance between the backside vias and the source and drain, embodiments of the present application provide some novel chip structures, as detailed below.

[0069] As shown in Figure 3, Figure 3 is a process structure diagram of a chip provided in an embodiment of the present application. The chip includes a transistor, and the transistor has front and back source and drain contacts. On the front side of the transistor, a metal interconnect layer 4 is provided, which can be electrically connected to the transistor to form a circuit structure; on the back side of the transistor, a source and drain contact (or can be called a backside via) is provided, and the source and drain contacts are electrically connected to the source and drain of the transistor, and power is supplied to the source and drain of the transistor through the source and drain contacts.

[0070] The source and drain of the transistor involved in the embodiments of the present application can be understood as one of the source and drain of the transistor.

[0071] As shown in FIG3 , in the chip, a plurality of transistors are integrated along a direction parallel to the substrate 3 . These transistors include transistors that can realize switching functions and transistors that cannot realize switching functions.

[0072] For the sake of clarity in the embodiments of the present application, a transistor that cannot realize a switching function may be referred to as a dummy transistor, and a transistor that can realize a switching function may be referred to as a transistor.

[0073] In some examples, two adjacent transistors are separated by a dummy transistor, or one of the two adjacent transistors is a dummy transistor and the other is a transistor capable of implementing a switch function.

[0074] The source and drain in a dummy transistor are called dummy source and drain, and the gate is called a dummy gate.

[0075] FIG3 shows a transistor 1 and a dummy transistor 2 arranged adjacent to each other along a first direction, which may be parallel to a substrate 3. Transistor 1 includes a gate 11, a first semiconductor region 12 (also called a channel), and a source and drain 13. Dummy transistor 2 includes a dummy gate 21, a second semiconductor region 22, and a dummy source and drain 23.

[0076] In some examples, transistor 1 and dummy transistor 2 may be gate-all-around (GAA) transistors or channel-all-around (CAA) transistors as shown in FIG3 . In other examples, the gate and channel may be arranged in other ways, for example, the first semiconductor region is arranged on one side of the bottom surface of the gate, and the second semiconductor region is arranged on one side of the bottom surface of the dummy gate.

[0077] As shown in FIG3 , in the transistor 1 , the source and drain 13 are arranged on the side of the first semiconductor region 12 facing the second semiconductor region 22 , and the source and drain 13 are electrically connected to the first semiconductor region 12 . The dummy source and drain 23 are arranged on the side of the second semiconductor region 22 facing the first semiconductor region 12 .

[0078] In the process structure shown in Figure 3, another source and drain electrode is provided on the other end surface of the first semiconductor region 12 opposite the source and drain electrode 13. For example, if the source and drain electrode 13 in Figure 3 is a source electrode, the source and drain electrode at the other end is a drain electrode. When a voltage is applied to the source, drain, and gate electrodes, electrons flow in the first semiconductor region 12, forming a channel.

[0079] As shown in FIG3 , a first source-drain contact 14 is provided between the source-drain 13 and the dummy source-drain 23 . A second source-drain contact 15 is provided on the bottom surface of the first source-drain contact 14 , and the second source-drain contact 15 contacts the bottom surface of the first source-drain contact 14 .

[0080] The bottom surface and top surface of a structure involved in the embodiments of the present application are opposite to each other. In some examples, the top surface is the surface facing the chip metal interconnect layer 4, that is, the surface facing the front of the chip as shown in Figure 3, and the bottom surface is the surface away from the chip metal interconnect layer 4, or the bottom surface can be understood as the surface facing the substrate 3, or the bottom surface can be understood as the surface facing the back of the chip as shown in Figure 3.

[0081] Since the second source-drain contact 15 contacts the first source-drain contact 14 , and the first source-drain contact 14 is electrically connected to the source-drain 13 , in some scenarios, a voltage can be applied to the source-drain 13 through the second source-drain contact 15 and the first source-drain contact 14 , thereby supplying power to the transistor 1 .

[0082] In some structures, as shown in FIG3 , an interface layer 161 is formed at the interface between the first source-drain contact 14 and the source-drain electrode 13 . For example, when the first source-drain contact 14 comprises a metal material and the source-drain electrode 13 comprises silicon or silicon germanium, the interface layer 161 comprises a low-resistance metal silicide.

[0083] In an optional process, the source and drain 13, the virtual source and drain 23 and the first source and drain contact 14 can be manufactured using a front process. In this way, a metal silicide with a smaller resistance will be formed at the interface between the first source and drain contact 14 and the source and drain 13, so that the contact resistance between the source and drain 13 and the first source and drain contact 14 is smaller.

[0084] Among some optional materials, the first source-drain contact 14 and the second source-drain contact 15 can be made of a metal material, for example, at least one of Ti, Co, Ni, Mo, and Nb can be selected. As shown in the example provided in FIG3 , in an optional process, the second source-drain contact 15 can be made using a backside process. Even in a low-temperature backside process, due to the contact between the first source-drain contact 14 and the second source-drain contact 15 (e.g., metal-to-metal contact), the resistance at the interface between the first source-drain contact 14 and the second source-drain contact 15 is low. In this way, the resistance between the source-drain electrode 13 and the second source-drain contact 15 serving as a backside via can be reduced, thereby reducing power consumption and improving the performance of the transistor 1.

[0085] In the related art, after the source and drain are made by the front process, the source and drain contacts serving as the back-side through holes are made by the low-temperature back process. Under the low-temperature back process conditions, an interface layer with a large resistance is easily formed at the interface between the source and drain contacts made of metal material and the source and drain.

[0086] Therefore, as shown in the example of FIG3 , since the structure of the source and drain electrodes is changed, the resistance between the source and drain electrodes and the contact elements can be reduced by using chips manufactured using the front-side process and the back-side process.

[0087] In some related technologies, the source and drain electrodes are disposed between the first and second semiconductor regions, contacting not only the first semiconductor region but also the second semiconductor region. In the present application, the source and drain electrodes 13 electrically connected to the first semiconductor region 12 and the dummy source and drain electrodes 23 in contact with the second semiconductor region 22 are separated by a first source and drain contact 14. Compared to the aforementioned related technologies, in the present application, after passing through the first semiconductor region 12, the current only needs to pass horizontally through the source and drain electrodes 13 to reach the first source and drain contact 14 made of metal. This shortens the path of the current signal in the semiconductor material, thereby reducing contact resistance.

[0088] In some examples, as shown in FIG3 , a plurality of gates 11 are stacked on one side of the transistor 1 , and a plurality of dummy gates 21 are stacked on one side of the dummy transistor 2 .

[0089] Each gate 11 is correspondingly provided with a first semiconductor region 12, and each dummy gate 21 is correspondingly provided with a second semiconductor region 22. The source and drain electrodes 13 are provided on the side of the stacked plurality of first semiconductor regions 12 facing the second semiconductor regions 22, that is, the source and drain electrodes 13 are in contact with and electrically connected to each first semiconductor region 12. The dummy source and drain electrodes 23 are provided on the side of the stacked plurality of second semiconductor regions 22 facing the first semiconductor region 12, and the dummy source and drain electrodes 23 are in contact with each second semiconductor region 22.

[0090] 3 , an interface layer 161 is formed at the interface between the first source-drain contact 14 and the source-drain electrode 13 . The interface layer 161 can be implemented in various ways.

[0091] In a first implementation method, a space is formed between the first semiconductor region 12 and the second semiconductor region 22. Within the space, a source and drain 13 are formed on the side of the first semiconductor region 12, and a virtual source and drain 23 is formed on the side of the second semiconductor region 22. There is a gap between the source and drain 13 and the virtual source and drain 23. Metal material is filled in the gap, and then annealing is performed to form a first source and drain contact 14, and an interface layer 161 containing metal silicide is formed at the interface between the first source and drain contact 14 and the source and drain 13.

[0092] In this way, the chip structure shown in Figures 3, 4 and 5 can be obtained, that is, in the chips shown in Figures 3 to 5, an interface layer 161 is formed at the interface between the first source-drain contact 14 and the source-drain 13, and an interface layer 161 is formed at the interface between the first source-drain contact 14 and the virtual source-drain 23.

[0093] The second implementation method is to deposit metal silicides, such as at least one of TiSi, CoSi, Ni, MoSi, and NbSi, on the walls of the source and drain 13 and the virtual source and drain 23, respectively, and then form the first source and drain contacts 14 in the gap between the relative metal silicides.

[0094] In a third implementation method, there is a gap between the source and drain 13 and the virtual source and drain 23, and metals, such as at least one of Ti, Co, Ni, Mo, and Nb, are formed on the walls of the source and drain 13 and the virtual source and drain 23 respectively. These metals are then annealed to form metal silicides, and a first source and drain contact 14 is formed in the gap between the relative metal silicides.

[0095] Advantageously, the second and third implementations can produce the chip structures shown in Figures 6, 7, and 8, that is, not only is an interface layer 161 formed at the interface between the first source-drain contact 14 and the source-drain electrode 13, but an interface layer 162 is also formed on the top surface of the source-drain electrode 13, and an interface layer 163 is also formed on the bottom surface. In Figure 6, not only is an interface layer 161 formed at the interface between the first source-drain contact 14 and the source-drain electrode 13, but an interface layer 162 is also formed on the top surface of the source-drain electrode 13. In Figures 7 and 8, not only is an interface layer 161 formed at the interface between the first source-drain contact 14 and the source-drain electrode 13, but an interface layer 162 is also formed on the top surface of the source-drain electrode 13, and an interface layer 163 is also formed on the bottom surface.

[0096] The chip structures shown in Figures 3 to 8 of the embodiments of the present application also have the following differences: during the preparation process, the depths of the holes opened between the first semiconductor region 12 and the second semiconductor region 22 are different, and the positions of the contact surfaces A of the first source-drain contact 14 and the second source-drain contact 15 are different.

[0097] 9A to 9D illustrate the process of manufacturing the chips shown in FIG. 3 and FIG. 6 .

[0098] In FIG9A , after forming source and drain electrodes 13 on the side of the first semiconductor region 12 and dummy source and drain electrodes 23 on the side of the second semiconductor region 22, a gate dielectric layer 17 is filled in the remaining space. As shown in FIG9B , the gate dielectric layer 17 between the source and drain electrodes 13 and the dummy source and drain electrodes 23 is removed to form a hole. The bottom of the hole can be located below the middle position of the source and drain electrodes 13 and does not exceed the bottom surface of the source and drain electrodes 13. As shown in FIG9C , a first source and drain contact 14 is formed in the hole. As shown in FIG9D , a second source and drain contact 15 is formed. Thus, in the structure shown in FIG3 and FIG6 , the contact surface A between the first source and drain contact 14 and the second source and drain contact 15 is located between the middle position and the bottom surface of the source and drain electrodes 13.

[0099] As described above, along the depth direction of the source / drain electrode 13 , the source / drain electrode 13 has a middle position. As shown in FIG9B , the middle position Q is located at half the depth dimension of the source / drain electrode 13 .

[0100] 10A to 10D illustrate the process of manufacturing the chips shown in FIG. 4 and FIG. 7 .

[0101] In FIG10A , after forming source and drain electrodes 13 on the side of the first semiconductor region 12 and dummy source and drain electrodes 23 on the side of the second semiconductor region 22, a gate dielectric layer 17 is filled in the remaining space. As shown in FIG10B , the gate dielectric layer 17 between the source and drain electrodes 13 and the dummy source and drain electrodes 23 is removed to form a hole. The bottom surface of the hole can be flush with the bottom surface of the source and drain electrodes 13. Here, flush is shown as substantially flush. As shown in FIG10C , a first source and drain contact 14 is formed in the hole. As shown in FIG10D , a second source and drain contact 15 is formed. Thus, in the structure shown in FIG4 and FIG7 , the contact surface A between the first source and drain contact 14 and the second source and drain contact 15 is substantially flush with the bottom surface of the source and drain electrodes 13, or protrudes from the bottom surface of the source and drain electrodes 13.

[0102] 11A to 11D illustrate the process of manufacturing the chips shown in FIG. 5 and FIG. 8 .

[0103] In FIG11A , after forming source and drain electrodes 13 on the side of the first semiconductor region 12 and dummy source and drain electrodes 23 on the side of the second semiconductor region 22, a gate dielectric layer 17 is filled in the remaining space. As shown in FIG11B , the gate dielectric layer 17 between the source and drain electrodes 13 and the dummy source and drain electrodes 23 is removed to form a hole, the bottom of which penetrates to the first surface of the substrate 3. As shown in FIG11C , a first source and drain contact 14 is formed in the hole. As shown in FIG11D , a second source and drain contact 15 is formed, thereby obtaining the contact surface between the first source and drain contact 14 and the second source and drain contact 15 in the structures shown in FIG5 and FIG8 . The contact surface is substantially flush with the first surface of the substrate 3 or protrudes from the first surface of the substrate 3.

[0104] In the above example, the substrate 3 has a first surface and a second surface relative to each other, and the gate 11, the first semiconductor region 12, the source and drain 13 of the transistor 1, the virtual gate 21, the second semiconductor region 22 and the virtual source and drain 23 of the virtual transistor 2, and the first source and drain contact 14 are all arranged on the first surface side of the substrate 2; the second source and drain contact 15 passes through the first surface and the second surface of the substrate 2 and contacts the first source and drain contact 14.

[0105] Returning to Figures 7 and 8 above, there is not only an interface layer 161 at the interface between the source and drain electrodes 13 and the first source and drain contacts 14, but also an interface layer 162 on the bottom surface of the source and drain electrodes 13. The interface layer 162 on the bottom surface of the source and drain electrodes 13 can be formed by depositing metal silicide to form the interface layer 162 on the bottom surface, or metal can be deposited and then annealed to obtain the interface layer 162 on the bottom surface.

[0106] The second source-drain contact 15 contacts not only the interface layer 161 but also the interface layer 162. Since both the interface layer 161 and the interface layer 162 contain metal silicide with relatively low resistance, the resistance between the source-drain 13 and the second source-drain contact 15 can be further reduced, thereby further reducing the power consumption of the transistor 1.

[0107] Returning to Figures 3 to 8 above, a gate connection layer 41 is provided on the side of the multiple stacked gates 11 close to the metal interconnection layer 4, and the gate connection layer 41 is electrically connected to the multiple gates 11. A virtual gate connection layer 42 is provided on the side of the multiple stacked virtual gates 21 close to the metal interconnection layer 4, and a third source-drain contact 18 is provided between the gate connection layer 41 and the virtual gate connection layer 42. The third source-drain contact 18 is in contact with the first source-drain contact 14 located between the source-drain 13 and the virtual source-drain 23.

[0108] In some possible structures, the third source-drain contact 18 and the first source-drain contact 14 are integrally formed.

[0109] The third source-drain contact 18 and the first source-drain contact 14 are integrally structured. This can be understood as follows: in some optional processes, the first semiconductor region 12 and the second semiconductor region 22 are both filled with a gate dielectric layer between the gate connection layer 41 and the dummy gate connection layer 42. When a hole is formed between the first semiconductor region 12 and the second semiconductor region 22, the hole passes from between the gate connection layer 41 and the dummy gate connection layer 42 to between the first semiconductor region 12 and the second semiconductor region 22. The hole is then filled with metal to form the integral structure of the third source-drain contact 18 and the first source-drain contact 14. In other words, the first source-drain contact 14 and the third source-drain contact 18 can be simultaneously formed using a single process.

[0110] Returning to FIG. 3 to FIG. 5 , the interface layer 161 located at the interface between the source / drain electrode 13 and the first source / drain contact 14 contacts the third source / drain contact 18 , thereby reducing the resistance between the third source / drain contact 18 and the source / drain electrode 13 .

[0111] In some examples, to further reduce the resistance between the third source-drain contact 18 and the source-drain electrode 13, returning to Figures 6 to 8 above, the interface layer 162 located on the top surface of the source-drain electrode 13 contacts the third source-drain contact 18. Utilizing an interface layer containing metal silicide with low resistance can further reduce contact resistance and thus reduce power consumption of the transistor.

[0112] An embodiment of the present application also provides a method for preparing a chip. The chip prepared by this method belongs to a backside power delivery network (BSPDN) architecture and can reduce the contact resistance between the backside through-hole and the source and drain.

[0113] FIG12 is a flow chart of a chip manufacturing method according to an embodiment of the present application, which comprises:

[0114] S1: A gate and a virtual gate, a first semiconductor region and a second semiconductor region, a source and a drain and a virtual source and drain are formed, the gate and the virtual gate are arranged side by side, the first semiconductor region is located on one side of the gate or is surrounded by the gate, the second semiconductor region is located on one side of the virtual gate or is surrounded by the virtual gate, the source and the drain are arranged on the side of the first semiconductor region facing the second semiconductor region, the virtual source and the drain are arranged on the side of the second semiconductor region facing the first semiconductor region, and there is a gap between the source and the drain and the virtual source and the drain.

[0115] The source and drain in the transistor provided in the embodiment of the present application and the virtual source and drain in the virtual transistor are two independent structures.

[0116] S2: forming a first source-drain contact in the gap.

[0117] S3: forming a second source-drain contact on a bottom surface of the first source-drain contact, wherein the first source-drain contact contacts the second source-drain contact.

[0118] The specific process flow involved in the chip preparation method is introduced below with reference to the accompanying drawings.

[0119] Figures 13 to 32 show the process structure after each step of the process of manufacturing a chip according to an embodiment of the present application. Figures 13 to 32 are merely examples of what can be achieved, and other preparation processes can also be used.

[0120] 13 and 14A to 14C , FIG. 13 shows a top view, FIG. 14A is an A1 - A1 sectional view of FIG. 13 , FIG. 14B is a B1 - B1 sectional view of FIG. 13 , and FIG. 14C is a C1 - C1 sectional view of FIG. 13 .

[0121] 13 to 14C , semiconductor layers 201 and sacrificial layers 202 that are alternately stacked are disposed on a substrate 101 .

[0122] Among some selectable materials, the semiconductor layer 201 may be Si, and the sacrificial layer 202 may be SiGe.

[0123] In this embodiment, the substrate 101 includes a first semiconductor layer 101 a and a second semiconductor layer 101 c , and an etch stop layer 101 b is stacked between the first semiconductor layer 101 a and the second semiconductor layer 101 c .

[0124] The alternately stacked semiconductor layers 201 and sacrificial layers 202, and the substrate 101 are patterned to form a plurality of fins 400. The plurality of fins 400 are arranged in a direction parallel to the substrate 101. For example, FIG13 shows three fins 400 arranged in one direction.

[0125] As shown in FIG. 14B , each fin 400 includes a device region 401 (including alternately stacked semiconductor layers 201 and sacrificial layers 202 ) and a sub-fin region 402 located in the substrate 101 . Adjacent sub-fin regions in the substrate 101 are isolated by a shallow trench isolation layer 300 .

[0126] 14A , a dummy gate 500 may be disposed above the fin. Referring to FIG. 13 and FIG. 14A , the dummy gate 500 is substantially perpendicular to the fin 400 .

[0127] In some examples, a spacer 600 may be formed on a wall surface of the dummy gate 500 .

[0128] As shown in Figures 15 and 16A to 16C, Figure 15 shows a top view, Figure 16A is an A2-A2 cross-sectional view of Figure 15, Figure 16B is a B2-B2 cross-sectional view of Figure 15, and Figure 16C is a C2-C2 cross-sectional view of Figure 15.

[0129] As shown in FIG16A , the alternatingly stacked semiconductor layers 201 and the sacrificial layer 202 for forming the source and drain in the device region 401 in the fin 400 are etched until the surface of the substrate 101 is reached. FIG14A and FIG16A can be compared, as well as FIG14B and FIG16B can be compared.

[0130] As shown in Figures 17 and 18A to 18C, Figure 17 shows a top view, Figure 18A is an A3-A3 sectional view of Figure 17, Figure 18B is a B3-B3 sectional view of Figure 17, and Figure 18C is a C3-C3 sectional view of Figure 17.

[0131] In some optional process flows, comparing FIG. 16A and FIG. 18A , the sacrificial layer on the surface of the substrate 101 may be removed, and a bottom dielectric isolation (BDI) layer 203 may be deposited by methods such as atomic layer deposition (ALD). The bottom dielectric isolation layer may be made of at least one of SiO2, SiCN, SiON, and SiN.

[0132] In another process flow, the bottom dielectric isolation (BDI) layer 203 may not need to be formed.

[0133] As shown in Figures 19 and 20A to 20C, Figure 19 shows a top view, Figure 20A is an A4-A4 cross-sectional view of Figure 19, Figure 20B is a B4-B4 cross-sectional view of Figure 19, and Figure 20C is a C4-C4 cross-sectional view of Figure 19.

[0134] Comparing Figures 18A and 20A, further etching is performed in the area where a backside contact (BSC) is required to be formed, as shown in Figure 20A, etching is performed into the second semiconductor layer 101c of the substrate 101, so that a self-aligned cavity is formed in the second semiconductor layer 101c, that is, the cavity is aligned with and connected to the hole in Figure 18A above.

[0135] In this example, the etch stop layer 101b in the substrate 101 can limit the etching depth of the cavity.

[0136] As shown in Figures 21 and 22A to 22C, Figure 21 shows a top view, Figure 22A is an A5-A5 sectional view of Figure 21, Figure 22B is a B5-B5 sectional view of Figure 21, and Figure 22C is a C5-C5 sectional view of Figure 21.

[0137] The cavity formed in the above steps is filled with sacrificial material, for example, at least one of SiC, SiGe, SiNorC, etc., to form a sacrificial layer 700, and needs to be etched back to expose the sidewalls of the alternately stacked semiconductor layers 201 and sacrificial layers 202.

[0138] As shown in Figures 23 and 24A to 24C, Figure 23 shows a top view, Figure 24A is an A6-A6 cross-sectional view of Figure 23, Figure 24B is a B6-B6 cross-sectional view of Figure 23, and Figure 24C is a C6-C6 cross-sectional view of Figure 23.

[0139] The source and drain electrodes 13 and the dummy source and drain electrodes 23 are formed on the sidewalls of the holes formed above. For example, the source and drain electrodes 13 and the dummy source and drain electrodes 23 can be manufactured by epitaxial growth technology.

[0140] The source and drain electrodes 13 and the dummy source and drain electrodes 23 may be made of at least one of Si, SiGe, SiC, and B.

[0141] Furthermore, there is a gap between the opposite source and drain electrodes 13 and the dummy source and drain electrodes 23 , and the gap can accommodate subsequent source and drain contacts.

[0142] The source / drain electrode 13 is in contact with the semiconductor layer 201 on one side thereof, and the dummy source / drain electrode 23 is in contact with the semiconductor layer 201 on one side thereof.

[0143] In some optional process steps, before forming the source / drain electrodes 13 and the dummy source / drain electrodes 23 , the sacrificial layer 202 may be selectively etched away, and an insulating layer may be deposited to form sidewalls of the insulating layer on the sides of the sacrificial layer 202 .

[0144] As shown in Figures 25 and 26A to 26C, Figure 25 shows a top view, Figure 26A is an A7-A7 cross-sectional view of Figure 25, Figure 26B is a B7-B7 cross-sectional view of Figure 25, and Figure 26C is a C7-C7 cross-sectional view of Figure 25.

[0145] The dummy gate structure is etched to form a gate connection layer 41 and a dummy gate connection layer 42, and the sacrificial layer is etched to form a gate 11 and a dummy gate 21. A gate dielectric layer 17 is deposited. Unnecessary metal materials can be removed by chemical mechanical polishing.

[0146] In the structure shown above, it is shown that the sacrificial layer 202 can be selectively etched away to form the sidewall spacer 800. Furthermore, the sidewall spacer 800 is formed on the sidewall of the gate 11.

[0147] As shown in Figures 27 and 28A to 28C, Figure 27 shows a top view, Figure 28A is an A8-A8 cross-sectional view of Figure 27, Figure 28B is a B8-B8 cross-sectional view of Figure 27, and Figure 28C is a C8-C8 cross-sectional view of Figure 27.

[0148] 26A and 28A , the gate dielectric layer 17 is etched until the etching depth exceeds half of the source and drain electrodes 13 , and then the first source and drain contacts 14 are formed in the etched holes.

[0149] After the first source-drain contact 14 of metal material is filled, annealing treatment can be performed to form an interface layer 161 at the interface between the first source-drain contact 14 and the source-drain 13, and at the interface between the first source-drain contact 14 and the virtual source-drain 23, wherein the interface layer 161 includes metal silicide.

[0150] As shown in FIG29 , a metal interconnection layer 3 is formed on a side of the plurality of transistors away from the substrate 101 and bonded to a support plate 5 , for example, to a carrier wafer.

[0151] As shown in FIG30 , the structure shown in FIG29 is turned over, and the substrate 101 is thinned. The first semiconductor layer 101a and the etch stop layer 101b in FIG29 can be etched away until the sacrificial layer 700 in the second semiconductor layer 101c is exposed.

[0152] As shown in FIG31 , in one example, the material of the second semiconductor layer 101 c is silicon. Thus, part or all of the silicon may be removed and filled with dielectric material to form a dielectric layer 900 , and the sacrificial layer 700 may be exposed again.

[0153] As shown in Figure 32, the sacrificial layer 700 is removed. If necessary, further etching can be performed to expose the bottom surface of the first source-drain contact 14, and metal is filled to form the second source-drain contact 15, so that the bottom surface of the first source-drain contact 14 is in contact with the second source-drain contact 15.

[0154] In this way, a chip with a backside power delivery network (BSPDN) architecture can be manufactured. The chip can be a memory or a controller.

[0155] In the manufactured chip, the source and drain in the transistor that can realize the switching function and the virtual source and drain in the virtual transistor that cannot realize the switching function are two separate and independent film layer structures. A first source-drain contact is arranged between the two film layer structures, and a second source-drain contact is arranged on one side of the bottom surface of the first source-drain contact, and the two source-drain contacts are made to contact with each other to realize electrical conduction.

[0156] That is, the embodiments of the present application reduce the contact resistance between the two source-drain contacts and the contact resistance between the source-drain contact and the source-drain by changing the source-drain and virtual source-drain structures, as well as changing the structures of the first source-drain contact and the second source-drain contact. Ultimately, the source-drain contact resistance in the backside power delivery network (BSPDN) architecture can be reduced, thereby achieving low power consumption of the chip.

[0157] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0158] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A chip, characterized in that: include: A gate and a dummy gate, wherein the gate and the dummy gate are arranged side by side; A first semiconductor region and a second semiconductor region, the gate is located on one side of the first semiconductor region, and the dummy gate is located on one side of the second semiconductor region; A source and a drain and a virtual source and a drain, wherein the source and the drain are arranged on a side of the first semiconductor region facing the second semiconductor region, and the virtual source and the drain are arranged on a side of the second semiconductor region facing the first semiconductor region; A first source-drain contact is provided between the source-drain and the virtual source-drain. A second source-drain contact in contact with the first source-drain contact is provided on a bottom surface of the first source-drain contact.

2. The chip according to claim 1, characterized in that: A first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer includes metal silicide.

3. The chip according to claim 2, characterized in that: The second source-drain contact contacts the first interface layer.

4. The chip according to claim 2 or 3, characterized in that: The bottom surface of the source and drain has a second interface layer, and the second interface layer includes metal silicide; The second source-drain contact contacts the second interface layer.

5. The chip according to any one of claims 1 to 4, characterized in that: The first source-drain contact is made by a front-side process, and the second source-drain contact is made by a back-side process.

6. The chip according to any one of claims 1 to 5, characterized in that: Along the depth direction of the source and drain electrodes, the source and drain electrodes have a middle position, and the middle position is located at one-half of the depth dimension of the source and drain electrodes; The contact surface between the first source-drain contact and the second source-drain contact is located at a side of the middle position away from the top surface of the source and drain.

7. The chip according to claim 6, characterized in that: The chip further includes a substrate having a first surface and a second surface; The gate, the virtual gate, the first semiconductor region, the second semiconductor region, the source and drain, the virtual source and drain, and the first source and drain contact are arranged on one side of the first surface of the substrate; The second source-drain contact penetrates the first surface and the second surface of the substrate and contacts the first source-drain contact; The contact surface between the first source-drain contact and the second source-drain contact is located between the bottom surface of the source-drain and the first surface of the substrate.

8. The chip according to any one of claims 1 to 7, characterized in that: A third source-drain contact is provided on a top surface of the first source-drain contact; The first source-drain contact and the third source-drain contact are an integrated structure.

9. The chip according to claim 8, characterized in that: The top surface of the source and drain has a third interface layer, and the third interface layer includes metal silicide; The third source-drain contact contacts the third interface layer.

10. The chip according to claim 8 or 9, characterized in that: The first source-drain contact, the second source-drain contact and the third source-drain contact are made of the same material.

11. A method for preparing a chip, characterized in that: include: A gate and a virtual gate, a first semiconductor region and a second semiconductor region, a source and a drain and a virtual source and drain are formed, wherein the gate and the virtual gate are arranged side by side, the gate is located at one side of the first semiconductor region, the virtual gate is located at one side of the second semiconductor region, the source and drain are arranged on the side of the first semiconductor region facing the second semiconductor region, the virtual source and drain are arranged on the side of the second semiconductor region facing the first semiconductor region, and there is a gap between the source and drain and the virtual source and drain; forming a first source-drain contact in the gap; A second source-drain contact is formed on one side of the bottom surface of the first source-drain contact, and the first source-drain contact is in contact with the second source-drain contact.

12. The method for preparing a chip according to claim 11, characterized in that: A first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer comprises metal silicide; The second source-drain contact is formed on the bottom surface of the first source-drain contact, comprising: The second source-drain contact contacts the first interface layer.

13. The method for preparing a chip according to claim 12, characterized in that: The first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer contains metal silicide, including: A metal silicide is deposited on the surface of the source and drain electrodes to form a first interface layer containing the metal silicide on the surface of the source and drain electrodes.

14. The method for preparing a chip according to claim 12, characterized in that: The first interface layer is provided at the interface between the first source-drain contact and the source-drain, and the first interface layer contains metal silicide, including: Annealing the first source-drain contact so that a first interface layer containing the metal silicide is formed at the interface between the first source-drain contact and the source-drain, or; A metal is deposited on the surface of the source and drain electrodes, and the metal is annealed to form a first interface layer containing the metal silicide on the surface of the source and drain electrodes.

15. The method for preparing a chip according to any one of claims 11 to 14, characterized in that: Before forming the first source-drain contact in the gap, the preparation method further includes: The top surface of the gap has a through hole opened in the dielectric layer, and the through hole is connected to the gap; Forming the first source-drain contact in the gap includes: The first source-drain contacts are formed in both the through hole and the gap.

16. The method for preparing a chip according to any one of claims 11 to 15, characterized in that: The first source-drain contact is made by a front-side process, and the second source-drain contact is made by a back-side process.

17. An electronic device, characterized in that: include: The chip according to any one of claims 1 to 10, or a chip made by the method for making a chip according to any one of claims 11 to 16; A circuit board, on which the chip is arranged.

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