Semiconductor device

Abstract

Disclosed is a semiconductor device in which inflow of electrons or holes to a channel is controlled. This semiconductor device is provided with: an N-type diffusion layer that is connected to the channel; and a P-type diffusion layer that is connected to the channel. This semiconductor device is also provided with: one or both of a first gate that is capable of inducing carriers from the N-type diffusion layer into the channel or eliminating the carriers, and a second gate that is capable of inducing carriers from the P-type diffusion layer into the channel or eliminating the carriers; and a third gate that is capable of inducing carriers from at least one of the first gate and the second gate into the channel or eliminating the carriers.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] The performance improvement of conventional (von Neumann) computers, which has been achieved through the miniaturization and integration of semiconductor elements, has recently reached its physical and economic limits, making it difficult to achieve dramatic improvements in performance. On the other hand, the need for high-load calculations such as big data processing, media processing, deep learning, combinatorial optimization, quantum chemistry simulation, and Monte Carlo calculations is increasing year by year, and there are high expectations for further improvements in computer performance.

[0003] However, when performing such high-load calculations on conventional computers, it takes an extremely long or even unrealistic amount of time to obtain satisfactory results. Therefore, to meet these computational needs, computers with a processing concept different from conventional ones are required.

[0004] For this reason, quantum computers have been attracting a great deal of attention in recent years. In quantum computers, the state of one bit, 0 or 1, is expressed using different quantum states. And because quantum mechanics allows for the superposition of different quantum states, it is also possible to express a state in which one bit has the states of 0 and 1 superimposed.

[0005] Therefore, when displaying all n-digit numbers from 000...00 to 111...11 in binary on a conventional computer, 2 ｎ Previously, n bits were required, but with quantum computers, which can simultaneously represent both 0 and 1 with one bit, all of these can be represented with n bits.

[0006] This allows the apparent amount of information to be calculated to be compressed, making it possible to perform calculations dramatically faster than conventional computers, and making the large-scale quantum chemistry simulations and Monte Carlo calculations mentioned above possible. The bits of quantum computers are called qubits to distinguish them from the bits of conventional computers.

[0007] Several methods have been proposed for realizing quantum computers. One of them is to use electron spin as a quantum bit. In this method, the up and down spins of electrons correspond to the states 0 and 1.

[0008] Representative examples of this method are described in, for example, Non-Patent Documents 1 to 3. For example, in the example in Non-Patent Document 2, the potential of a Si channel on a buried oxide film (BOX) is controlled by a gate electrode to form quantum wells (quantum dots), and electrons are stored in each quantum well.

[0009] For example, by applying a magnetic field perpendicular to the chip surface, electrons undergo Zeeman separation, and electrons with spin parallel to the magnetic field (here referred to as up spin) have lower energy than electrons with spin antiparallel to the magnetic field (here referred to as down spin). In other words, an energy difference occurs between the up spin and down spin states of electrons.

[0010] In this state, by irradiating the electrons for a certain period of time with electromagnetic waves whose frequency corresponds to the energy difference created by Zeeman splitting, it is possible to change the up-spin state to down-spin and vice versa (this phenomenon is known as Rabi oscillations).

[0011] In other words, it is possible to change the state of 0 to 1 and the state of 1 to 0, thereby operating the rotation gate of a quantum circuit. In addition, by adjusting the gate voltage, the height of the potential barrier between each electron can be lowered, causing the spins of adjacent electrons to interfere (entangle). This makes it possible, for example, to exchange (swap) the spin states of adjacent electrons.

[0012] This enables swap gate operation in quantum circuits. Furthermore, when the spins of adjacent electrons are interfered with, the energy difference caused by Zeeman separation is affected by the orientation of the adjacent electrons. In other words, the value of the energy difference of electron A caused by Zeeman separation will differ depending on whether electron B next to electron A has up or down spin.

[0013] In this way, the frequency of the electromagnetic waves that can cause electron A to undergo Rabi oscillation changes depending on whether electron B has up spin or down spin. In other words, if the frequency of the irradiated electromagnetic waves is set to a constant value, a situation can be created in which electron A can be made to undergo Rabi oscillation if electron B has up spin, but electron A cannot be made to undergo Rabi oscillation if electron B has down spin. In other words, a so-called controlled NOT gate operation becomes possible, in which the quantum state of electron B determines whether the quantum state of electron A can be changed.

[0014] To read information (read the spin direction of an electron), an electron with a known spin (let's call it electron C) is placed in a quantum dot next to the quantum dot containing the electron to be read. If the electron to be read has the same spin direction as electron C, the electron to be read cannot tunnel to the dot containing electron C due to the Pauli blockade.

[0015] Therefore, only one electron C remains in the dot where electron C exists. On the other hand, if the spin of the electron to be read is antiparallel to that of electron C, the electron to be read can be tunneled to the dot where electron C exists.

[0016] Therefore, a dot where electron C exists can contain two electrons: the electron to be read and electron C. The difference in the number of charges in the dot where electron C exists can be read by placing a single-electron transistor next to the dot where electron C exists and monitoring the current value flowing through that transistor.

[0017] In this way, the spin direction of the electron being read can be indirectly determined by monitoring the current value of the single-electron transistor.

[0018] Furthermore, it has been found that the use of holes as well as electrons in quantum bits and sensors for reading information enables more scalable device operation. For example, Non-Patent Document 3 discloses a method for reading out the number of charges (in the above example, the number of charges in the dot where charge C exists) in a dot (a dot below SG3) next to a readout transistor (a transistor with SGS as its gate) using the readout transistor as a PMOS sensor.

[0019] First, the charge in the dot next to the readout transistor (the dot under SG3) is sent to the channel of the readout transistor (under SGS) by manipulating the gate voltages. Next, the readout transistor is operated as a PMOS, and a hole current flows from the source to the drain in the channel.

[0020] Then, the value of the hole current flowing through the channel changes depending on how many electrons are sent from the dots under SG3 to the channel portion under SGS (and as a result, how many electrons are accumulated in the channel portion under SGS). The more electrons accumulated in the channel, the more hole current flows, and the number of electrons accumulated in the channel can be determined from the difference.

[0021] This readout method will be referred to as PMOS readout in this specification. PMOS readout can detect the difference in the number of electrons accumulated in the channel under the SGS with high sensitivity using a large current. As noted in Non-Patent Document 3, the difference between the absence of electrons, the presence of one electron, and the presence of two electrons can be distinguished by a large current difference of about 3 nA.

[0022] D. M. Zajac, A. J. Sigilito, M. Russ, F. Borjans, J. M. Taylor, G. Burkard, J. R. Petta1, “Resonantly driven CNOT gate forelectron spins” Science 359, 439-442 (2018) N. Lee, R. Tsuchiya, G. Shinkai, Y. Kanno, T. Mine, T. Takahama, R. Mizokuchi, T. Kodera, D. Hisamoto, and H. Mizuno, “Enhancing electrostatic coupling in silicon quantum dot array by dual gate oxide thickness for Large-scale integration “Appl. Phys. Lett. 116, 162106 (2020); doi: 10.1063 / 1.5141522Digh Hisamoto, Noriyuki Lee, Ryuta Tsuchiya, Toshiyuki Mine, Takeru Utsugi, Shinichi Saito, Hiroyuki Mizuno, "Electron Charge Sensor with Hole Current Operating at Cryogenic Temperature", arXiv:2302.06135 [cond-mat. mes-hall], https: / / doi. org / 10.48550 / arXiv. 2302.06135.

[0023] After the PMOS readout described above is completed, the electrons accumulated under SGS must be removed from under SGS. If this is not done, for example, after the next calculation, if an attempt is made to send the electrons under SG3 under SGS again to read the result of the next calculation and perform PMOS readout, the electrons will be mixed with the electrons sent under SGS in the previous calculation, making it impossible to accurately read the result of the quantum calculation.

[0024] Therefore, after completing the PMOS readout, it is necessary to remove the electrons accumulated under the SGS from under the SGS before proceeding to readout of the next calculation result. In the device described in Non-Patent Document 3, the source and drain of the readout transistor with the SGS as the gate are only P-type diffusion layers.

[0025] The area under the SGS is almost entirely undoped Si. In this case, it is difficult to remove the electrons accumulated under the SGS by extracting them to the P-type diffusion layer, considering the potential profile. Furthermore, in Non-Patent Document 3, the reservoir is an N-type diffusion layer, but if electrons are extracted to the N-type diffusion layer of the reservoir, all of the electrons under SG1 and SG2 must also be extracted, which is extremely inefficient and unrealistic in terms of operation.

[0026] Therefore, if an N-type diffusion layer is provided in addition to a P-type diffusion layer as the source and drain connected to the read transistor whose gate is SGS, the electrons accumulated under SGS can be extracted to the N-type diffusion layer. For example, if the gate (SGS and TG) of the read transistor is set to a negative voltage and the voltage applied to the N-type diffusion layer is set to 0 V (i.e., the NMOS is turned off), the electrons accumulated under SGS can be extracted to the N-type diffusion layer.

[0027] Furthermore, if the carriers used as quantum bits can be holes instead of electrons, both electron spin and hole spin can be handled, enabling more advanced calculations. This can be achieved by providing a P-type diffusion layer in addition to an N-type diffusion layer as a reservoir that supplies carriers to the dot.

[0028] However, the above configuration poses a problem. For example, if the diffusion layers (source and drain) of the read transistor have both N-type and P-type polarities, a problem occurs in that electron leakage current also flows through the channel when hole current flows through the channel.

[0029] When reading PMOS, it is important to detect the difference in units of one electron accumulated in the channel, so if an electron leakage current flows into the channel, it is impossible to accurately detect the difference. Further details regarding this problem will be provided in the section on embodiments of the invention.

[0030] The above-mentioned problem is solved by a semiconductor device that controls the inflow of electrons or holes into a channel, the semiconductor device comprising an N-type diffusion layer connected to the channel and a P-type diffusion layer connected to the channel, a first gate that can induce or remove carriers from the N-type diffusion layer into the channel, or a second gate that can induce or remove carriers from the P-type diffusion layer into the channel, or both, and a third gate that can induce or remove carriers from at least one of the first gate and the second gate into the channel.

[0031] In semiconductor devices, electron current and hole current can be controlled with precision.

[0032]

[0033] In all the drawings for explaining the present embodiment, the same reference numerals are used to denote components having the same functions, and repeated explanations thereof are omitted as much as possible. Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings.

[0034] The structures and materials described in the examples are examples for embodying the idea of ​​the present invention, and are not intended to strictly specify the materials, dimensions, detailed structures, etc. Please note that the dimensions and scales of the drawings are not accurate, as priority has been given to ease of viewing.

[0035] Figure 1(a) shows a diagram of the device disclosed in Non-Patent Document 3, in which both N-type and P-type diffusion layers are arranged in each diffusion layer portion. In this specification, as in Figures 1(a)-(d), a top view and a cross-sectional view may be shown together on a single figure. References 101, 103, and 105 are N-type diffusion layers, 102, 104, and 106 are P-type diffusion layers, 107 is a channel, 108-117 are gate electrodes, 120 is a Si oxide film, and 122 is Si (substrate portion). Portion 107 is Si that is almost not doped with impurities.

[0036] The N-type diffusion layers 101, 103, and 105 are doped with, for example, phosphorus, and the P-type diffusion layers 102, 104, and 106 are doped with, for example, boron. The device shown in Figure 1 can be formed using, for example, an SOI (Silicon on Insulator) wafer and a conventional semiconductor process. For details of the manufacturing method, please refer to, for example, Non-Patent Documents 2 and 3.

[0037] An insulating film (e.g., a silicon oxide film, approximately 3-20 nm thick) is present between the channel and each gate electrode, and between each gate electrode. In the following description, 101 and 102 may be referred to as reservoirs, 103 and 104 as sources, and 105 and 106 as drains.

[0038] Figure 2(a) shows an example of a device with almost the same functions fabricated using a normal Si wafer instead of an SOI wafer. The difference from Figure 1 is that there is no Si oxide film 120 between the channel 107 and the Si substrate 122. In this case, the channel 107 and the Si substrate 122 are usually formed from the same material. Note that hereafter, an example using an SOI wafer will be basically explained. Furthermore, the device fabrication method using an SOI wafer shown below can also be applied to fabricate a device with almost the same functions when using a normal Si wafer.

[0039] 3 is a diagram illustrating the operation of the device shown in Figures 1(a) and 2(a). For example, by applying 0 V to 101, a positive voltage (for example, 2 V) to 108-114, a positive voltage (for example, 2 V) to 115-117, and a positive voltage (for example, 2 V) to 103, electrons can be transported from 101 to 103.

[0040] Furthermore, by applying a positive voltage (for example, 2 V) to 105 instead of 103, electrons can be transported from 101 to 105. (Electrons are shown as 301 in the figure.) Furthermore, by applying a negative voltage (for example, -2 V) to gate electrodes 108, 110, 112, and 114 and a positive voltage (for example, 2 V) to gate electrodes 109, 111, and 113, a quantum well can be formed in which electrons are trapped under gate electrodes 109, 111, and 113.

[0041] By further finely adjusting the voltages of these gate electrodes, it is possible to create a state in which one electron is trapped in each quantum well (under 109, 111, and 113) (a state as shown in Figure 4 can be created).

[0042] To transport electrons one by one, for example, a pulsed positive voltage is applied to the gate electrode 108, and the application time of the pulsed positive voltage is set to a time sufficient for only one electron to move from 101 to 109, thereby enabling the transport of only one electron from 101 to 109. Such single-electron transport and trapping methods have already been reported in many documents. For example, see Non-Patent Documents 1-3.

[0043] In the state shown in Figure 4, consider the case where a magnetic field B (>0) is applied perpendicular to the paper surface, from the Si substrate side of the device toward the gate electrode side. Also, define spin parallel to the magnetic field as up spin, and spin antiparallel to the magnetic field as down spin. The spin of the electrons below 113 is set to an up spin state.

[0044] Under these circumstances, by using a method (a method using Rabi oscillations) as described in the Background Art section, it is possible to change the spin direction of each electron under 109 and 111 (corresponding to a rotation gate operation). In addition, by weakening the voltage applied to 110 to cause the electrons under 109 and 111 to interfere with each other, it is possible to swap the spins of the electrons (corresponding to a swap gate operation), or to perform a gate operation in which the rotation of one spin state depends on the spin state of the other (corresponding to a controlled NOT gate operation) (these methods are also as described in the Background Art section).

[0045] After performing such a calculation using gate operation, the strength of the negative voltage applied to 112 is slightly weakened, and the value of the positive voltage applied to 113 is slightly strengthened. By doing so, if the electrons under 111 are of up spin, the electrons under 111 cannot move to 113 due to the Pauli blockade, but if the electrons under 111 are of down spin, a state can be created in which the electrons under 111 can move to 113.

[0046] In other words, if the electron under 111 has down spin, that electron will move under 113 after a certain time has passed, and two electrons will remain under 113. On the other hand, if the electron under 111 has up spin, it cannot move under 113, and so only one electron will remain under 113 even after a certain time has passed. In other words, if we know the number of electrons that exist under 113 after a certain time has passed, we can know the spin state of the electron that existed under 111.

[0047] Then, in order to know the number of electrons present under 113, the PMOS readout described in the Background Art section is performed. First, the electrons accumulated under 113 are moved to under 116. To do this, for example, a negative voltage (for example, -1 V) is applied to 113, a positive voltage (for example, 2 V) is applied to 114, and a positive voltage (for example, 2.5 V) greater than that of 114 is applied to 116, and then a negative voltage (for example, -2 V) is applied to 114 again, thereby moving the electrons accumulated under 113 to under 116.

[0048] The state after such movement is shown in Figure 5 (501 in Figure 5 is the electron after movement). Figure 5 shows the case where only one electron exists under 116, but as explained above, if there were two electrons in 113, two electrons would move under 116.

[0049] Then, when a negative voltage (for example, -1.5 V) is applied to 115, 116, and 117, and, for example, 0 V is applied to 104 and -0.1 V is applied to 106, holes (502) flow along the path indicated by the arrow (503) in the figure. Here, when electrons 501 are present under 116, the value of the hole current is larger than when electrons 501 are not present under 116.

[0050] Furthermore, the value of the hole current is larger when there are two electrons than when there is only one. The difference in the value of the hole current depending on the presence or absence of electrons and the number of electrons is very large, so by measuring the value of the hole current, it is possible to very clearly determine how many electrons are present under 116.

[0051] By knowing the number of electrons, it is possible to know the spin direction of the electrons that existed under 111, as described above. Knowing the spin direction of the electrons that existed under 111 means that the results of calculations performed using the electron spins under 109 and 111 can be known.

[0052] In this way, it becomes possible to perform quantum computer calculations and read out the results. Then, for electrons whose number has been read out, by making the voltages at 116 and 117 negative and applying a positive voltage of, for example, 0 V or higher to 105, the electrons under 116 can be extracted to 105. (In Non-Patent Document 3, the reservoir has only an N-type diffusion layer, and the source and drain have only P-type diffusion layers. Therefore, as described in the "Problems to be Solved by the Invention" section, it is not possible to extract the electrons under 116 to the source / drain.)

[0053] Furthermore, although it is possible to extract the electrons under 116 to the N-type diffusion layer on the reservoir side, in that case, all of the electrons accumulated under 109, 111, and 113 must also be extracted to the N-type diffusion layer, which is extremely inefficient in terms of operation.

[0054] Furthermore, if a calculation using those electrons (electrons accumulated under 109, 111, and 113) is in progress or has been completed, the calculation information will be lost if those electrons are extracted.

[0055] Therefore, extracting the electrons under 116 to the N-type diffusion layer on the reservoir side is extremely inefficient in terms of operation. Therefore, extracting the electrons under 116 to the N-type diffusion layer on the reservoir side is not practical. After the electrons under 116 are extracted to 105, the electrons placed under 109, 111, and 113 can be used again to perform the calculation using the electron spin as described above, and then a PMOS readout can be performed. In this way, by making it possible to use the transistor portion formed by gates 115, 116, and 117 as both a PMOS and an NMOS, the number of electrons present under 116 can be determined with high accuracy, and after the number has been determined, the electrons can be sent to 105.

[0056] In addition to PMOS readout, a readout method using a single-electron transistor that utilizes a quantum well formed under the gate 116 can also be considered for reading electrons. This method is as follows. For example, 0 V is applied to 103, 0.1 V is applied to 105, and a negative voltage is applied to 115 and 117, and a positive voltage is applied to 116. After that, by gradually decreasing the magnitude of the negative voltages of 115 and 117 to 0, electrons can tunnel from 103 to 105.

[0057] The value of the tunnel current at this time changes depending on the number of electrons present in 113. By reading this change, the number of electrons present in 113 can be determined. By performing this readout method using a single-electron transistor before performing PMOS readout, it becomes possible to more accurately grasp the number of electrons present under 113.

[0058] Naturally, while the above example describes calculations and readouts based on the spin of electrons, calculations and readouts based on the spin of holes may also be performed. If the spin of holes can be handled in addition to electrons, the degree of freedom in calculations will increase, enabling more advanced calculations. For this reason, for example, in Figure 5, an N-type diffusion layer 101 and a P-type diffusion layer 102 are provided, from which both electrons and holes can be sent into the channel.

[0059] This makes it possible to, for example, trap holes below 109, 111, and 113 for calculation, then send the holes below 113 below 116, and then use a transistor consisting of gates 115, 116, and 117 as an NMOS to monitor the current value of electrons flowing from 103 to 105, thereby counting the number of holes below 116. (In other words, it is possible to perform the reverse of the PMOS readout of electrons described above.) Furthermore, it also becomes possible to trap holes in 109 and electrons in 111, and perform calculations by interfering with the spin of the electrons and the spin of the holes, dramatically expanding the degree of freedom in device operation.

[0060] There is a problem here, which will be explained using Figure 6. In the PMOS readout described above, holes flow along the path 503, but at the same time, there is a problem in that a leakage current of electrons also flows along the path 601.

[0061] For example, when 0 V is applied to 103 and 104, 0.1 V is applied to 105, and −0.1 V is applied to 106, the current value flowing through the channel below 115, 116, and 117 changes according to the voltages of 115, 116, and 117 (assuming that the voltage of 115 = the voltage of 116 = the voltage of 117) as shown in the transistor characteristics of FIG. Ｇ is applied to 115, 116, and 117 to pass a hole current through the channel below 115, 116, and 117, an electron leakage current (shown as 601 in FIG. 6) also flows, although it is smaller than the hole current, as shown in FIG. 52.

[0062] For simplicity, in the above description, the voltage of 115 = the voltage of 116 = the voltage of 117, but in reality, it is desirable to set the voltage of 116 > the voltages of 115 and 117 so that the electrons 501 do not move from under 116 as much as possible (do not escape to the N-type diffusion layer or gates 114 and 113), and perform PMOS readout.

[0063] As described above, the PMOS readout is performed to accurately count the number of electrons under 116 in units of one. However, if electrons leaking from 103 come under 116 during the PMOS readout, it becomes impossible to know how many electrons were under 116, which is a problem.

[0064] This is one of the issues. Ｇ It may be possible to reduce the electron leakage current by applying a stronger negative voltage to 116, or by applying a stronger negative voltage only to 115. However, this would then raise the problem that the effect of the stronger negative voltage would increase the likelihood that the electrons sent under 116 would escape to another location (for example, by moving toward gate 114 or 113).

[0065] Furthermore, when a large negative voltage is applied to 115, a band-to-band tunneling phenomenon occurs at the junction between the diffusion layer and the channel 107, which causes another leakage current called GIDL (Gate Induced Drain Leakage). Ｇ In the negative voltage region where the value of is large, the dependency of the current value on the applied voltage is small.

[0066] In this so-called saturated current region, the amount of change in the hole current value due to the change in the threshold value of the transistor characteristics caused by the presence of electrons in the channel becomes small. Ｇ If a strong negative voltage is applied to the value of V, the amount of change in the hole current due to the presence of electrons will be small, and the accuracy of the PMOS readout will decrease. Ｇ Therefore, applying a voltage of 0.1 V is not advisable and is not practical.

[0067] Similar problems arise when electrons and holes are sent into the channel from 101 and 102. In Fig. 7(a), consider the case where a positive voltage (for example, 1.5 V) is applied to the gates of 108-114 and 116 and 117, and 0 V is applied to 101 and 102, 0.1 V to 105, and -0.1 V to 106, to transport electrons from 101 to 105.

[0068] At this time, for the same reason as described above, holes 701 may also leak into the channel 107 (the leakage path is shown by 702 in FIG. 7A). Conversely, consider applying a negative voltage (for example, −1.5 V) to the gates of 108-114 and 116 and 117, and applying, for example, 0 V to 101 and 102, 0.1 V to 105, and −0.1 V to 106, thereby transporting holes from 102 to 106.

[0069] At this time, for the same reason as described above, there is a possibility that electrons 301 may also leak into the channel 105 as shown in Fig. 7B (the leakage path is shown by 705 in Fig. 7B). If such a leak occurs, holes may mistakenly enter when electrons are to be stored below 109, 111, and 113, and conversely, electrons may mistakenly enter when holes are to be stored below 109, 111, and 113.

[0070] 8(a)-(c) are diagrams illustrating a method for solving the above-mentioned problem. In Fig. 8(a), a gate electrode 801 is disposed on the channel 107 in front of the N-type diffusion layer 103. For example, consider the case where 0 V is applied to 103 and 104, 0.1 V to 105, and -0.1 V to 106, and negative voltages are applied to 115, 116, and 117 (for example, -1.5 V to 116 and -1.7 V to 115 and 117), causing a hole current to flow from 104 to 106.

[0071] At this time, a stronger negative voltage (for example, -3 V) than the negative voltage applied to 115-117 is applied to 801 to prevent electrons from leaking from the N-type diffusion layer into the channel 107. To clearly explain this situation, we will use Figure 53. Figure 53 is almost the same as Figure 52, and shows the gate voltage dependency of the current flowing through the channel.

[0072] By applying voltages to gate electrodes 115, 116, and 117, a hole current is induced to flow from 104 to the channel, while by applying to gate 801 a negative voltage that is sufficiently stronger than the voltages applied to gate electrodes 115, 116, and 117, the electron leakage current can be reduced significantly (to almost zero) compared to the case of Fig. 52. Fig. 54(b) shows a potential diagram when a voltage is applied to 801 to block the inflow of electrons from N-type diffusion layer 103.

[0073] As shown in the figure, a negative voltage that is sufficiently stronger than that applied to gate 115 is applied to gate 801, so that the height of the potential barrier against electrons under gate 801 is sufficiently higher than that under gate 115, thereby blocking the inflow of electrons into the channel.

[0074] In this way, only hole current can flow into the channel below 115, 116, and 117, without electron leakage current from 103. The gate electrode 801 is far away from the portion where electrons are captured during PMOS readout (the channel portion below the gate electrode 116), with the gate electrode 115 sandwiched between them.

[0075] In this example, it is explained as a location where electrons are captured, but it may also be called a site, etc., and refers to a location that captures carriers such as holes as well as electrons.

[0076] Therefore, even if a strong negative voltage is applied to 801, the effect on the electrons captured in the channel portion below the gate electrode 116 is small, and there is almost no possibility that the electrons will move from below the gate electrode 116 to another location due to the effect of the voltage applied to 801.

[0077] Therefore, by placing the gate 801 and applying a strong negative voltage to it, electron leakage from 103 during PMOS readout is suppressed, and the charge to be readout, which is captured in the channel portion below the gate electrode 116, is prevented from escaping to another location, thereby solving the above-mentioned problem.

[0078] After the PMOS readout is complete, the electrons remaining under 116 can be extracted to the N-type diffusion layer 103 or 105. For example, by applying -3 V to 116 and 3 V to 115, 801, and 103, the electrons present under 116 can be extracted to the N-type diffusion layer 103. (That is, by regarding the transistor with 116 as the gate as an NMOS and applying a voltage that turns it off, the electrons under 116 can be removed and flowed into the N-type diffusion layer 103.) In this way, the electrons for which the PMOS readout has been completed can be removed, and a new readout operation can be carried out. When the electrons under 116 are extracted to the N-type diffusion layer 103, there is a possibility that a hole current will flow in from 104.

[0079] If holes flow in and remain under 116, this will have a negative effect on the next PMOS read. Therefore, when electrons are drawn out to the N-type diffusion layer 103, it is advisable to apply a large voltage to 115 so that holes from 104 do not flow in.

[0080] At this time, it is also preferable to apply a large voltage to 117 so that hole current from 106 does not flow in. By drawing electrons into the N-type diffusion layer 103 in this way, both electrons and holes can be completely removed from the channels under 115, 116, and 117.

[0081] 8(b), gate electrodes 801 and 802 are arranged on the channel 107 in front of the N-type diffusion layer 103 and the P-type diffusion layer 104. The difference from FIG. 8(a) is the presence of 802. By doing so, when electrons are caused to flow in the channel under 115, 116, and 117, if a strong positive voltage is applied to 802, it is possible to cause an electron current to flow while suppressing the leakage current of holes from 103 to the channel.

[0082] Specifically, for example, consider the case where 0 V is applied to 103 and 104, 0.1 V to 105, and −0.1 V to 106, and positive voltages are applied to 115, 116, and 117 (for example, 1.5 V to 116 and 1.7 V to 115 and 117), and an electron current flows from 103 to 105.

[0083] At this time, the same voltage as that applied to 115 is applied to 801, and a positive voltage (e.g., 3 V) stronger than the voltage applied to 801 is applied to 802 so as to suppress the inflow of holes from 104 to the channel 107.

[0084] That is, as shown in the potential profile for holes in FIG. 55(b), by applying to 802 a positive voltage that is sufficiently stronger than the voltage applied to 115, the potential barrier for holes below 802 becomes sufficiently high, blocking the inflow of holes into the channel.

[0085] This allows electrons to flow in the channels under 115, 116, and 117 without mixing with the hole current from 104. Of course, the reverse is also possible (that is, it is also possible to operate in such a way that a hole current flows without electrons flowing into the channel, as explained in FIG. 8A).

[0086] For example, consider the case where 0 V is applied to 103 and 104, 0.1 V to 105, and −0.1 V to 106, and negative voltages (for example, −1.5 V to 116 and −1.7 V to 115 and 117) are applied to 115, 116, and 117 to allow a hole current to flow from 104 to 106. In this case, the same negative voltage as that applied to 115 is applied to 802, and a negative voltage (for example, −3 V) stronger than that applied to 802 is applied to 801 so that the inflow of electrons from 103 to the channel 105 is suppressed.

[0087] This allows holes to flow in the channels under 115, 116, and 117 without mixing with the electron current from 103. By providing 801 and 802 in this way, electron current can flow without hole leakage, and vice versa.

[0088] This not only enables the PMOS reading of electrons as described above, but also enables operations such as capturing holes below 109, 111, and 113, performing calculations using the spin of the holes, and then transporting the holes below 113 to below 116, and reading the number of transported holes from the change in the electron current flowing from 103 to 105. In other words, contrary to the PMOS reading of electrons described above, NMOS reading of holes is also possible, which greatly widens the range of device operation.

[0089] After the NMOS readout is complete, any holes remaining under 116 can be extracted to the P-type diffusion layer 104 or 106. For example, by applying 3 V to 116 and -3 V to 115, 802, and 104, the holes present under 116 can be extracted to the P-type diffusion layer 104. (That is, by regarding a transistor with 116 as the gate as a PMOS and applying a voltage that turns it off, the holes under 116 can be removed and flowed into the P-type diffusion layer 104.) In this way, the holes whose NMOS readout has been completed can be removed, and a new readout operation can be carried out. When the holes under 116 are extracted to the P-type diffusion layer 104, there is a possibility that an electron current will flow in from 103.

[0090] If electrons flow in and remain under 116, this will have an adverse effect on the next NMOS read operation. Therefore, when holes are drawn into the P-type diffusion layer 104, it is preferable to apply a small voltage to 115 so that the electron current from 103 does not flow in. At the same time, it is also preferable to apply a small voltage to 117 so that the electron current from 105 does not flow in.

[0091] By drawing the holes into the P-type diffusion layer 104 in this way, both electrons and holes can be completely removed from the channel below the layers 115, 116, and 117.

[0092] 8(c) shows a structure in which gates (801-806) are placed in front of all the diffusion layers of the source, drain, and reservoir. This allows for the flow of electrons or holes from 103 and 104 to 101 and 102.

[0093] Furthermore, by providing gates 805 and 806 in front of the reservoir diffusion layer, when electrons are to flow into channel 107, a strong positive voltage can be applied to 806 to suppress the inflow of holes from 102, and when holes are to flow into channel 107, a strong negative voltage can be applied to 805 to suppress the inflow of electrons from 101.

[0094] Therefore, holes do not erroneously enter when attempting to capture electrons below 109, 111, and 113, and conversely, electrons do not erroneously enter when attempting to capture holes below 109, 111, and 113. Note that hereinafter, gates equivalent to 801-806 may be referred to as control gates.

[0095] 9 shows a cross-sectional view of a structure in which control gates (801-806) are placed in front of the diffusion layers. As shown in the figure, the channel extends to below the control gates.

[0096] Figure 10 shows an arrangement in which the portions 103, 104, 801, 802, 105, 106, 803, and 804 in Figure 9 are slightly shifted to the right. Of course, even with this arrangement, the same operation as the device shown in Figure 9 is possible, and the same effects can be obtained.

[0097] 11-14 show the fabrication of the channel portion with the control gate.

[0098] (FIG. 11) First, the SOI substrate is dry-etched so that a portion that will become the channel 107 remains, and then an oxide film is deposited and polished to form the structure shown in FIG. 11. The channel width is, for example, 50 nm. The channel thickness is also, for example, 50 nm.

[0099] (FIG. 12) A silicon oxide film (e.g., 5 nm thick) is formed, and then a film of phosphorus-doped polysilicon (e.g., 50 nm thick) is formed on top of that. Thereafter, the gate is processed into a shape like 108 by dry etching. The gap between 108 in the A-A' cross section is set to, e.g., 80 nm.

[0100] (FIG. 13) Resist is applied, the portion corresponding to 1301 is exposed to light and removed, and ions of, for example, phosphorus are implanted into the portion 1301 to form an N-type diffusion layer 101. After the resist is removed, resist is applied again, and the portion corresponding to 1302 is exposed to light and removed, and ions of, for example, boron are implanted into the portion 1302 to form a P-type diffusion layer 102.

[0101] When forming the P-type diffusion layer 102, boron is also implanted into a part of the gate 108. However, if the phosphorus concentration in the polysilicon of the gate 108 is set sufficiently higher than the concentration of the implanted boron, the part will remain N-type Si even after the boron is implanted into the gate 108, and no problem will occur.

[0102] To further prevent boron implantation into 108, it is advisable to deposit polysilicon doped with phosphorus, then deposit a silicon oxide film (for example, 50 nm thick) thereon, and then process it into the shape of 108 before implanting boron into portion 1302. In this way, most of the implanted boron will stop in the silicon oxide film on the polysilicon doped with phosphorus, preventing it from diffusing into the polysilicon.

[0103] (FIG. 14) After depositing a silicon oxide film (for example, 10 nm thick), a film of, for example, phosphorus-doped polysilicon (for example, 120 nm thick) is formed.

[0104] Thereafter, dry etching is performed so that the phosphorus-doped polysilicon is etched by a thickness of 120 nm, whereby the phosphorus-doped polysilicon is removed from above 108 as shown in FIG. 14, and phosphorus-doped polysilicon remains in the gaps and sidewalls of 108 (portions 1401, 1402, and 1403). Here, the portions corresponding to 1401 and 1402 are portions that will become control gates. How portions 1401, 1402, and 1403 are terminated in an actual process will be described in detail in the following examples.

[0105] In the above manufacturing method, the gate 108 is formed in a shape in which the control gates (1401, 1402) are short-circuited with each other, as shown in Figure 14. This shape has several advantages.

[0106] First, since the gate 108 is connected across the control gates (1401, 1402), when the phosphorus-doped polysilicon is deposited in the process of Fig. 14 and then etched back by the thickness of the deposited polysilicon, the gates 1401 and 1402 are automatically cut off above the gate 108. Therefore, an additional etching process for avoiding short-circuiting between the gates 1401 and 1402 is not required.

[0107] Furthermore, if the gate 108 is not connected across the control gates (1401, 1402), two separate gates will be created with the control gates (1401, 1402) in between, and therefore the device will not operate unless power is supplied to both of them and also to the control gate (i.e., carriers from each diffusion layer cannot be induced in the channel).

[0108] However, if the gates 108 are connected with the control gates (1401, 1402) sandwiched between them, the device can operate by supplying power only to the gate 108 and the control gate (i.e., carriers from each diffusion layer can be induced in the channel). This allows for savings in the number of power supplies, contact holes to the gate, pad terminals / wiring, etc., which is advantageous for reducing the chip area and increasing integration.

[0109] 11-14, a structure like that shown in Fig. 15 (a structure having control gates 1401, 1402, 1501, 1502, 1503, and 1504) can be formed. As shown in Fig. 15, gates 108, 115, and 117 are short-circuited with the control gates (1401, 1402, 1501, 1502, 1503, and 1504) in between.

[0110] FIG. 16 shows an example of voltage application when electrons or holes are caused to flow from 103 and 104 to 105 and 106 while sufficiently suppressing leakage of opposite charges.

[0111] The flat band voltage of the control gates 1501 and 1502 with respect to the channel 107 is Vfb. In any of the cases shown in Figures 16(a) to 16(c), when holes are to flow through the channel, it is necessary to apply a voltage such that V(115) < Vfb and holes are induced in the channel. Conversely, when electrons are to flow through the channel, it is necessary to apply a voltage such that V(115) > Vfb and electrons are induced in the channel.

[0112] In both cases, the voltage condition for holes to flow is V(1501) < V(115), and the voltage condition for electrons to flow is V(1502) > V(115). As mentioned above, this is because a strong voltage is applied to the control gate to prevent carriers of the opposite polarity to the charge to be flowed from the diffusion layer into the channel.

[0113] In any case, the absolute value of the voltage applied to V (115) is smaller than the absolute value of the voltage applied to the control gate for the purpose of blocking leakage current. This is also an important point. As shown in Figure 15, since the gate 115 is short-circuited with the control gates (1501, 1502) sandwiched between them, the voltage applied near the junction between the diffusion layer and the channel 107 is not the large voltage applied to the control gate for the purpose of blocking leakage current, but a voltage smaller than that applied to the gate 115.

[0114] As mentioned above, when a high voltage is applied to the junction between the diffusion layer and the channel 107, it may cause another leakage current called GIDL (Gate Induced Drain Leakage). However, in the above case, the voltage applied near the junction between the diffusion layer and the channel 107 is small, so that the GIDL current can be suppressed.

[0115] 16 is also effectively applicable when the gate 115 is not short-circuited across the control gates (1501, 1502). That is, even when the gate 115 is not short-circuited across the control gates (801, 802) as in Fig. 8, by replacing 801 with 1501 and 802 with 1502 and applying the voltage conditions in Fig. 16, electrons or holes can be made to flow from 103 and 104 to 105 and 106 while sufficiently suppressing leakage of opposite charges.

[0116] 16(c) shows a case where the same voltage is applied to the control gate associated with the N-type diffusion layer and the control gate associated with the P-type diffusion layer. In this case, the two control gates can be connected. In fact, connecting them allows power to be supplied to the control gate from only one point, which reduces the number of contact holes, pad terminals / wiring, etc., and is advantageous for reducing the chip area and increasing integration. This can be achieved by changing the position of the short-circuit part 108 at the stage in FIG. 12 in the manufacturing method diagrams of FIGS. 11-14.

[0117] Specifically, instead of arranging the short-circuited portion of 108 between the P-type diffusion layer and the N-type diffusion layer, it is sufficient to arrange it in the same direction as seen from the P-type diffusion layer and the N-type diffusion layer, as shown in Figure 17. If fabricated in this way, the control gates for the P-type diffusion layer and the N-type diffusion layer are connected, forming a single gate 1701.

[0118] As described above, when electrons or holes are caused to flow from 103 and 104 to 105 and 106 while sufficiently suppressing leakage of opposite charges, it goes without saying that, within the scope of knowledge of normal MOS transistor operation, a voltage greater than Vfb is applied to gates 116, 117, 1503, and 1504 to induce electrons in the channel when electrons are desired to flow, and a voltage smaller than Vfb is applied to gates 116, 117, 1503, and 1504 to induce holes in the channel when holes are desired to flow. It also goes without saying that, within the scope of knowledge of normal MOS transistor operation, it is necessary to satisfy V(103)<V(105) when electrons are caused to flow from 103 to 105, and V(104)>V(106) when holes are caused to flow from 104 to 106.

[0119] In this specification, descriptions of such common sense matters that are understood within the scope of knowledge of the operation of ordinary MOS transistors may be omitted.

[0120] Figure 18(a) shows the application of the structure of Figure 17 to the quantum device described above. In the device of Figure 18(a), the voltage application conditions for flowing electrons or holes from 103 and 104 to 105 and 106 while sufficiently suppressing leakage of opposite charges can be achieved by applying the voltage conditions shown in Figure 16(c) where V(1501) = V(1502) = V(1802).

[0121] 18(b) shows a simpler configuration in which a single control gate is formed for the P-type diffusion layer and the N-type diffusion layer. The control gates are designated by 1701, 1802, 1803, 1805, 1806, and 1807. 18(c) shows a case in which the gate 115 is not short-circuited across the control gate, and is separated into the gate 115 and the gate 1801.

[0122] In this case, it is necessary to supply power to the gate 115 and the gate 1801 separately, but this has the advantage that more precise voltage control for each gate becomes possible, improving the degree of freedom in device operation.

[0123] In the above embodiment, for example, polysilicon doped with phosphorus is used for the gate, but polysilicon doped with boron may also be used for the gate.

[0124] Figures 19-24 show more detailed layout and process, including how the gate wiring is routed.

[0125] (FIG. 19) First, the SOI substrate is dry-etched so that a portion that will become the channel 107 remains, and then an oxide film is deposited and polished to form the structure shown in FIG. 19. The channel width is, for example, 50 nm. The channel thickness is also, for example, 50 nm.

[0126] (FIG. 20) A silicon oxide film (e.g., 5 nm thick) is formed, and then a phosphorus-doped polysilicon film (e.g., 50 nm thick) is formed thereon. It is then processed by dry etching into a shape like 108. The gap between 108 in the A-A', B-B', and C-C' cross sections is, for example, 80 nm. Above and below 107 in FIG. 20(a), rectangular island patterns of member 108 are periodically and relatively densely arranged. A portion where island patterns are periodically and relatively densely arranged is referred to herein as a block pattern. While the island patterns are rectangular in this specification, they may also be polygonal or circular.

[0127] (FIG. 21) Resist is applied, the portion corresponding to 1301 is exposed to light and removed, and ions of, for example, phosphorus are implanted into the portion 1301 to form an N-type diffusion layer 101. After the resist is removed, resist is applied again, and the portion corresponding to 1302 is exposed to light and removed, and ions of, for example, boron are implanted into the portion 1302 to form a P-type diffusion layer 102.

[0128] When forming the P-type diffusion layer 102, boron is also implanted into a part of the gate 108. However, if the phosphorus concentration in the polysilicon of the gate 108 is set sufficiently higher than the concentration of the implanted boron, the part will remain N-type Si even after the boron is implanted into the gate 108, and no problem will occur.

[0129] To further prevent boron implantation into 108, it is advisable to deposit polysilicon doped with phosphorus, then deposit a silicon oxide film (for example, 50 nm thick) thereon, and then process it into the shape of 108 before implanting boron into portion 1302. In this way, most of the implanted boron will stop in the silicon oxide film on the polysilicon doped with phosphorus, preventing it from diffusing into the polysilicon.

[0130] (FIG. 22) After depositing a silicon oxide film (for example, 5 nm thick), a film of, for example, phosphorus-doped polysilicon (for example, 120 nm thick) is formed.

[0131] Thereafter, dry etching is performed so that the phosphorus-doped polysilicon is etched by a thickness of 120 nm, whereby the phosphorus-doped polysilicon is removed from above 108 as shown in Fig. 22, and phosphorus-doped polysilicon 2201 remains in the gaps and on the side walls of 108. Note that in the top view, the silicon oxide film deposited on the side walls of 108 is not shown in order to prioritize visibility.

[0132] (FIG. 23) Thereafter, in order to prevent short circuits between the control gates, the portions 2301 and 2302 are removed by etching. After that, a silicon oxide film 2303 is deposited as an interlayer film. The surface of 2303 is then flattened by polishing.

[0133] (FIG. 24) After that, contact holes are opened on the gate 108, control gate 2201, N-type diffusion layer 101, and P-type diffusion layer 102. After that, the process proceeds to the wiring step that is common in ordinary semiconductor processes. That is, by depositing metal material and patterning it into a wiring shape, wiring and pad portions that can supply power to each gate and diffusion layer are formed.

[0134] In the process of this embodiment, the control gate wiring is automatically formed along the block-shaped pattern 108. Therefore, an advantage is that a mask is not required to pattern the shape of the control gate material after it is deposited.

[0135] In the above embodiment, for example, polysilicon doped with phosphorus is used for the gate, but polysilicon doped with boron may also be used for the gate.

[0136] 25-30 show another example of a more detailed layout and process, including how the gate wiring is routed.

[0137] (FIG. 25) First, the SOI substrate is dry-etched so that a portion that will become the channel 107 remains, and then an oxide film is deposited and polished to form the structure shown in FIG. 25. The channel width is, for example, 50 nm. The channel thickness is also, for example, 50 nm.

[0138] (FIG. 26) A silicon oxide film (e.g., 5 nm thick) is formed, and then a polysilicon film (e.g., 50 nm thick) doped with phosphorus is formed on top of the silicon oxide film. After that, dry etching is performed to form a shape like 108. The gap between 108 in the A-A' cross section, the B-B' cross section, and the C-C' cross section is set to, e.g., 80 nm.

[0139] (FIG. 27) Resist is applied, the portion corresponding to 1301 is exposed to light and removed, and ions of, for example, phosphorus are implanted into the portion 1301 to form an N-type diffusion layer 101. After the resist is removed, resist is applied again, and the portion corresponding to 1302 is exposed to light and removed, and ions of, for example, boron are implanted into the portion 1302 to form a P-type diffusion layer 102.

[0140] When forming the P-type diffusion layer 102, boron is also implanted into a part of the gate 108. However, if the phosphorus concentration in the polysilicon of the gate 108 is set sufficiently higher than the concentration of the implanted boron, the part will remain N-type Si even after the boron is implanted into the gate 108, and no problem will occur.

[0141] To further prevent boron implantation into 108, it is advisable to deposit polysilicon doped with phosphorus, then deposit a silicon oxide film (for example, 50 nm thick) thereon, and then process it into the shape of 108 before implanting boron into portion 1302. In this way, most of the implanted boron will stop in the silicon oxide film on the polysilicon doped with phosphorus, preventing it from diffusing into the polysilicon.

[0142] (FIG. 28) After depositing a silicon oxide film (for example, 5 nm thick), for example, phosphorus-doped polysilicon (for example, 120 nm thick) is formed. Thereafter, dry etching is performed so that the phosphorus-doped polysilicon is etched by a thickness of 120 nm, whereby the phosphorus-doped polysilicon is removed from above 108 as shown in FIG. 28, and phosphorus-doped polysilicon 2201 remains in the gaps and sidewalls of 108.

[0143] In the top view, the silicon oxide film deposited on the sidewall of 108 is not shown for ease of viewing.

[0144] (FIG. 29) After that, a silicon oxide film 2303 is deposited as an interlayer film, and the surface of 2303 is then flattened by polishing.

[0145] (Fig. 30) After that, contact holes are opened on the gate 108, control gate 2201, N-type diffusion layer 101, and P-type diffusion layer 102. After that, the process proceeds to the wiring step that is common in ordinary semiconductor processes. That is, by depositing metal material and patterning it into a wiring shape, wiring and pad portions that can supply power to each gate and diffusion layer are formed.

[0146] The process of this embodiment does not require the etching (etching of portions 2301 and 2302) required in the process of FIG. 24 of the third embodiment to prevent short circuits between the control gates, and therefore the number of steps in device formation can be reduced compared to the process of the third embodiment.

[0147] In the above embodiment, for example, polysilicon doped with phosphorus is used for the gate, but polysilicon doped with boron may also be used for the gate.

[0148] In this embodiment, the fabrication process for the case where there is only one control gate (corresponding to the configuration of FIG. 18(a)) is shown in FIGS.

[0149] (FIG. 31) First, the SOI substrate is dry-etched so that a portion that will become the channel 107 remains, and then an oxide film is deposited and polished to form the structure shown in FIG. 31. The channel width is, for example, 50 nm. The channel thickness is also, for example, 50 nm.

[0150] (FIG. 32) A silicon oxide film (e.g., 5 nm thick) is formed, and then a polysilicon film (e.g., 50 nm thick) doped with phosphorus is formed on top of the silicon oxide film. After that, dry etching is performed to form a shape like 108. The gap between 108 in the A-A' cross section, the B-B' cross section, and the C-C' cross section is set to, e.g., 80 nm.

[0151] (FIG. 33) Resist is applied, the portion corresponding to 1301 is exposed to light and removed, and ions of, for example, phosphorus are implanted into the portion 1301 to form an N-type diffusion layer 101. After the resist is removed, resist is applied again, and the portion corresponding to 1302 is exposed to light and removed, and ions of, for example, boron are implanted into the portion 1302 to form a P-type diffusion layer 102.

[0152] When forming the P-type diffusion layer 102, boron is also implanted into a part of the gate 108. However, if the phosphorus concentration in the polysilicon of the gate 108 is set sufficiently higher than the concentration of the implanted boron, the part will remain N-type Si even after the boron is implanted into the gate 108, and no problem will occur.

[0153] To further prevent boron implantation into 108, it is advisable to deposit polysilicon doped with phosphorus, then deposit a silicon oxide film (for example, 50 nm thick) thereon, and then process it into the shape of 108 before implanting boron into portion 1302. In this way, most of the implanted boron will stop in the silicon oxide film on the polysilicon doped with phosphorus, preventing it from diffusing into the polysilicon.

[0154] (FIG. 34) After depositing a silicon oxide film (for example, 5 nm thick), for example, phosphorus-doped polysilicon (for example, 120 nm thick) is formed. Thereafter, dry etching is performed so that the phosphorus-doped polysilicon is etched by a thickness of 120 nm, whereby the phosphorus-doped polysilicon is removed from above 108 as shown in FIG. 28, and phosphorus-doped polysilicon 2201 remains in the gaps and sidewalls of 108.

[0155] In the top view, the silicon oxide film deposited on the sidewall of 108 is not shown for ease of viewing.

[0156] (FIG. 35) Then, a silicon oxide film 2303 is deposited as an interlayer film, and the surface of the silicon oxide film 2303 is then polished to make it flat.

[0157] (FIG. 36) After that, contact holes are opened on the gate 108, control gate 2201, N-type diffusion layer 101, and P-type diffusion layer 102. After that, the process proceeds to the wiring step that is common in ordinary semiconductor processes. That is, by depositing metal material and patterning it into a wiring shape, wiring and pad portions that can supply power to each gate and diffusion layer are formed.

[0158] The structure formed in this embodiment has only one control gate, and therefore only one contact to the control gate is required, which means that power needs to be supplied to the control gate at only one point, thereby reducing the number of contact holes, pad terminals / wirings, etc., which is advantageous for reducing the chip area and increasing integration.

[0159] 32, if the control gate is patterned so that it does not extend over the channel connected to the N-type diffusion layer, a structure such as that shown in Fig. 56 can be formed. This is the structure shown in Fig. 8(a) in which the control gate is placed only in front of the diffusion layer on one side.

[0160] In the above embodiment, for example, polysilicon doped with phosphorus is used for the gate, but polysilicon doped with boron may also be used for the gate.

[0161] In this embodiment, the fabrication process for the case where there is only one control gate and the gates 115 sandwiching the control gate are not short-circuited (corresponding to the configuration in FIG. 18(c)) is shown in FIGS.

[0162] (FIG. 37) First, the SOI substrate is dry-etched so that a portion that will become the channel 107 remains, and then an oxide film is deposited and polished to form the structure shown in FIG. 37. The channel width is, for example, 50 nm. The channel thickness is also, for example, 50 nm.

[0163] (FIG. 38) A silicon oxide film (e.g., 5 nm thick) is formed, and then a polysilicon film (e.g., 50 nm thick) doped with phosphorus is formed on top of that. After that, dry etching is performed to process it into the shapes shown in 108 and 3201. The gaps between 108 in the A-A' cross section, B-B' cross section, and C-C' cross section are set to, e.g., 80 nm.

[0164] (FIG. 39) Resist is applied, the portion corresponding to 1301 is exposed to light and removed, and ions of, for example, phosphorus are implanted into the portion 1301 to form an N-type diffusion layer 101. After the resist is removed, resist is applied again, and the portion corresponding to 1302 is exposed to light and removed, and ions of, for example, boron are implanted into the portion 1302 to form a P-type diffusion layer 102.

[0165] When forming the P-type diffusion layer 102, boron is also implanted into a part of the gate 108. However, if the phosphorus concentration in the polysilicon of the gate 108 is set sufficiently higher than the concentration of the implanted boron, the part will remain N-type Si even after the boron is implanted into the gate 108, and no problem will occur.

[0166] To further prevent boron implantation into 108, it is advisable to deposit polysilicon doped with phosphorus, then deposit a silicon oxide film (for example, 50 nm thick) thereon, and then process it into the shape of 108 before implanting boron into portion 1302. In this way, most of the implanted boron will stop in the silicon oxide film on the polysilicon doped with phosphorus, preventing it from diffusing into the polysilicon.

[0167] (FIG. 40) After depositing a silicon oxide film (for example, 5 nm thick), a film of, for example, phosphorus-doped polysilicon (for example, 120 nm thick) is formed.

[0168] Thereafter, dry etching is performed so that the phosphorus-doped polysilicon is etched by a thickness of 120 nm, whereby the phosphorus-doped polysilicon is removed from above 108 and 3201 as shown in Fig. 40, and phosphorus-doped polysilicon 2201 remains in the gaps and on the side walls of 108 and 3201. Note that in the top view, the silicon oxide film deposited on the side walls of 108 and 3201 is not shown in order to prioritize clarity.

[0169] (FIG. 41) After that, a silicon oxide film 2303 is deposited as an interlayer film, and the surface of 2303 is then flattened by polishing.

[0170] (FIG. 42) After that, contact holes are opened on the gate 108, gate 3201, control gate 2201, N-type diffusion layer 101, and P-type diffusion layer 102. After that, the process proceeds to the wiring step that is common in ordinary semiconductor processes. That is, by depositing metal material and patterning it into a wiring shape, wiring and pad portions that can supply power to each gate and diffusion layer are formed.

[0171] The structure formed in this embodiment has the advantage that it is possible to supply power separately to the gate 108 and the gate 3201, thereby enabling more precise voltage control for each gate and improving the degree of freedom in device operation. In order to suppress GIDL leakage current that occurs at the connection between the diffusion layers 101 and 102 and the channel 107, it is preferable to apply a voltage to the gate 3201 that is smaller in absolute value than the voltage applied to 2201.

[0172] In the above embodiment, for example, polysilicon doped with phosphorus is used for the gate, but polysilicon doped with boron may also be used for the gate.

[0173] This example shows an example in which a diffusion layer with a control gate is applied to a quantum bit array device. Figure 43 shows the above-described diffusion layer structure with a control gate at each of the four corners of the array. 3701 denotes a gate for capturing electrons and holes, and a gate for forming a barrier potential between adjacent captured electrons and holes.

[0174] The gates 3702 and 3702b are used to send electrons or holes to the channel 107, and are also used to read the number of electrons or holes. (They are used for PMOS readout of electrons and NMOS readout of holes.) An example of operation will be described below.

[0175] Similar to the previous embodiments, a positive voltage is applied to 3702b, 115c, and 1501c, 0 V is applied to 101c and 102c, and a voltage higher than 1501 is applied to 1502c, thereby suppressing the inflow of holes into the channel and allowing electrons to flow into the channel. Thereafter, the gate voltage 3701 is varied, and finally, a barrier potential and a trapping potential for electrons are alternately formed, and by adjusting the shape of the potential, electrons can be trapped periodically as shown in FIG.

[0176] In this state, quantum operations are performed using the spin of each electron, and finally, PMOS readout is performed to read out the information. Here, it is considered that electrons in the row in which gate 3702a exists are read out.

[0177] First, a positive voltage is applied to 107a, a positive voltage greater than that of 107a is applied to 3702a, and a negative voltage is applied to gates 3702 other than 3702a, causing only electrons in the row where gate 3702a exists to move to the channel portion below 3702a.

[0178] Next, with V(102)=0V and V(102a)<V(102), negative voltages are applied to 1502, 115, 3702, 115a, and 1502a, and a stronger negative voltage than 1502 is applied to 1501, thereby suppressing the inflow of electrons from 1501 into the channel while causing a hole current to flow through the channel, and the number of electrons below 3702a is read from the value of this hole current. At this time, by applying a voltage to gate 3702a that is larger than the voltages applied to the gates of the other 3702, it is possible to prevent the electrons to be read from escaping from below 3702a.

[0179] Once the readout is complete, in order to extract the electrons to the diffusion layer, a negative voltage is applied to 3702a, a positive voltage is applied to 3702 other than 3702a, and a positive voltage is applied to 115, 115a, 1501, 1501a, 101, and 101a, which is what is called an NMOS OFF operating voltage, and the electrons under 3702a are extracted to 101 or 101a. In this way, electron transport, PMOS readout, and removal of electrons after readout become possible.

[0180] In this example, another example in which a diffusion layer with a control gate is applied to a quantum bit array device is shown using Figures 45 and 46. The difference from Example 7 is that a P-type diffusion layer is arranged for each row.

[0181] Furthermore, a control gate 1502 is disposed in the portion of the channel in front of the P-type diffusion layer in each row. An example of operation is shown below. First, electrons are periodically disposed under 3701 as shown in FIG. 46. This can be done in the same manner as in Example 7. That is, while suppressing the inflow of holes using the control gate, electrons are caused to flow into the channel from the N-type diffusion layer on the left side, and then the gate voltage 3701 is varied, ultimately forming a barrier potential and a trap potential for the electrons alternately, and adjusting the shape of this potential makes it possible to trap electrons periodically, as shown in FIG. 46.

[0182] In this state, quantum operations are performed using the spin of each electron, and finally, PMOS readout is performed to read out the information. Here, we consider reading out electrons in the row where gate 115a is located. First, a positive voltage is applied to 107a, a positive voltage greater than that of 107a is applied to 115a, and a negative voltage is applied to all of 115a except 115a, causing only the electrons in the row where gate 115a is located to move below 115a.

[0183] Thereafter, by applying a negative voltage to 115a, 115b, 115d, and 1502, 0 V to 102a, a voltage smaller than that of 101a to 102b, and a stronger negative voltage than that of 1502 to 1501 and 1501a, holes can be made to flow from 102a to 102b while suppressing the inflow of electrons into the channel, and the number of electrons below 115a can be determined from the current value of these holes.

[0184] At this time, by making the voltage applied to the gate 115a larger than the voltage applied to the gates 115b and 115d, it is possible to prevent the electrons to be read from escaping from under 3702a.

[0185] When reading out the PMOS, it is advisable to set 115c and 115e to a positive voltage so that the holes flowing from 102a to 102b do not flow to any other locations. After reading out is completed, a negative voltage is applied to 115a, a positive voltage is applied to 115 other than 115a and to the control gates (1501, 1501a), and a positive voltage is also applied to 101 and 101a, thereby drawing out electrons to the N-type diffusion layer 101 or 101a.

[0186] In this way, electron transport, PMOS readout, and removal of the electrons after readout are possible. A feature of this configuration is that PMOS readout of electrons in one row and electrons in another row can be performed simultaneously. In other words, while electrons under 115a are being read out by PMOS readout of the hole current path from 102a to 102b, electrons under gates other than 115a in gate 115 can be simultaneously read out by PMOS readout using a hole current flowing from another P-type diffusion layer.

[0187] In this example, another example in which a diffusion layer with a control gate is applied to a quantum bit array device is shown using Figures 47 and 48. The difference from Example 7 is that a P-type diffusion layer is arranged for each row.

[0188] A control gate 1502 is disposed in the channel portion in front of the P-type diffusion layer in each row. Another difference from Example 8 is that a control gate 1502 is disposed individually in the channel portion in front of the P-type diffusion layer in each row. An example of operation is shown below.

[0189] First, electrons are periodically placed under 3701 as shown in Fig. 48. This can be done in the same way as in Example 7. That is, while suppressing the inflow of holes using the control gate, electrons are caused to flow into the channel from the N-type diffusion layer on the left side, and then the gate voltage 3701 is varied, and finally a barrier potential and a trap potential for the electrons are alternately formed, and the shape of the potential is adjusted, thereby making it possible to trap electrons periodically as shown in Fig. 48.

[0190] In this state, quantum operations are performed using the spin of each electron, and finally, PMOS readout is performed to read out the information. Here, we consider reading out electrons in the row where gate 115a is located. First, a positive voltage is applied to 107a, a positive voltage greater than 107a is applied to 115a, and a negative voltage is applied to all but 115a of 115, thereby moving only the electrons in the row where gate 115a is located below 115a.

[0191] Thereafter, by applying a negative voltage to 115a, 115b, 115d, 1502a, and 1502b, 0V to 102a, a voltage smaller than that of 101a to 102b, and a negative voltage stronger than that of 1502a, 1502b, and the other 1502 (control gates in front of the P-type diffusion layer) to 1501 and 1501a, it is possible to flow holes from 102a to 102b while suppressing the inflow of electrons into the channel, and the number of electrons below 115a can be determined from the current value of these holes.

[0192] In this case, by applying a voltage to gate 115a that is greater than the voltage applied to gates 115b and 115d, it is possible to prevent the electrons to be read from escaping from under 3702a. Note that, during this PMOS readout, it is preferable to set 115c and 115e to a positive voltage so that the holes flowing from 102a to 102b do not flow to any other location.

[0193] Once the readout is complete, a negative voltage is applied to 115a, a positive voltage is applied to 115 other than 115a and the control gates (1501, 1501a), and a positive voltage is also applied to 101 and 101a, thereby extracting the electrons to the N-type diffusion layer 101 or 101a. In this way, electron transport, PMOS readout, and removal of the electrons after readout are possible. A feature of this configuration is that PMOS readout of electrons from one row and electrons from another row can be performed simultaneously.

[0194] In other words, while the electrons under 115a are read by PMOS reading of the hole current path from 102a to 102b, the electrons under gates other than 115a in gate 115 can be simultaneously read by PMOS reading using a hole current flowing from another P-type diffusion layer.

[0195] The diffusion layer structure with a control gate can be applied to devices other than the quantum bit devices shown so far. An example is shown in Figure 49. The device in Figure 49 performs calculations using the spins of electrons stored in quantum dots formed under gate 4001 in the channel, and then reads out that information in the channel using quantum dots located under gate 4002 as charge sensors.

[0196] A detailed explanation of this method is given in the literature (Zwerver, A. M. J., Kraehenmann, T., Watson, T. F. et al. Qubits made by advanced semiconductor manufacturing. Nat Electron 5, 184-190 (2022)).

[0197] In this device, if the spins of electrons and holes could be used as quantum bits and also as carriers on the charge sensor side, the degree of freedom of the device would increase, enabling more advanced quantum computing. To achieve this, as shown in Figure 49(a), P-type diffusion layers and N-type diffusion layers, along with control gates for each, are placed at the four corners of the device.

[0198] In this way, by performing the operation described in the previous embodiments (i.e., the operation of suppressing the inflow of carriers on one side when allowing carriers on one side to flow into the channel), electrons or holes can be reliably flowed under the gates 4001 and 4002 without any mistake in polarity.

[0199] 49(b) shows the case where the control gate is common to the P-type diffusion layer and the N-type diffusion layer, and Fig. 49(c) shows the case where the control gate is common to the P-type diffusion layer and the N-type diffusion layer and the gates 108 and 1702 are independent. The manufacturing method and voltage application examples are as shown in the previous embodiments.

[0200] Of course, the diffusion layer structure with control gate can also be provided in the diffusion layer portion of a single transistor. An example is shown in Figure 50. Figure 50 shows a configuration in which a P-type diffusion layer and an N-type diffusion layer, and a control gate for each, are arranged on both sides of a transistor with a channel 107 and a gate 108.

[0201] By using this configuration and operating as described in the previous embodiments (i.e., operating to suppress the inflow of carriers on one side when allowing carriers on one side to flow into the channel), when electrons or holes are flowed into the channel, each carrier can be flowed into the channel while suppressing leakage of the opposite charge, thereby forming a highly reliable transistor.

[0202] Also, as can be seen from FIG. 52, even if only the voltage of the gate 108 is manipulated, it is not possible to prevent carriers from flowing into the channel from the diffusion layer (that is, the transistor cannot be turned off).

[0203] However, by providing a control gate, if a voltage is applied to the control gate that prevents electrons and holes from being induced in the channel (i.e., if a voltage sufficiently smaller than Vfb is applied to 1401 so that electrons do not flow from 101 into the channel, and a voltage sufficiently higher than Vfb is applied to 1402 so that holes do not flow from 102 into the channel), the flow of carriers into the channel can be blocked, and the transistor can be turned off.

[0204] Therefore, it is possible to suppress the power consumption of the transistor during standby. Fig. 50(a) shows an example in which control gates are formed individually for the N-type diffusion layer and the P-type diffusion layer, Fig. 50(b) shows a case in which the control gate is common to the P-type diffusion layer and the N-type diffusion layer, and Fig. 50(c) shows a case in which the control gate is common to the P-type diffusion layer and the N-type diffusion layer and the gates 108 and 1401 are independent. The manufacturing method and voltage application examples are as shown in the previous embodiments.

[0205] This example (FIG. 51) shows an example in which a diffusion layer structure with a control gate is applied to an FET biosensor. The diffusion layer structure with a control gate is provided on both sides of the channel 107. Looking at the A-A' cross section, an insulating film 4201 is present on the channel. 4201 is, for example, a silicon oxide film or a silicon nitride film, and its thickness is, for example, 10 nm.

[0206] Figure 51(b) illustrates how to use it. A chamber 4202 is placed on the FET, and an electrolyte solution containing test objects 4205 and 4206 is sealed in the chamber. Test object 4205 is a positively charged object, and 4206 is a negatively charged object. An electrode 4203 is placed so that it comes into contact with the aqueous solution. The electrode is, for example, an Ag / AgCl electrode. An example of test object detection is shown below.

[0207] For example, by applying a positive voltage to 4203, 1401, 1401b, 108, and 108b, a negative voltage to 101, and 0 V to 101b, an electron current flows through the channel 107. At the same time, by applying a strong positive voltage to 1402 and 1402b that is greater than that to 1401 and 1401b, the inflow of holes from 102 and 102b into the channel is blocked.

[0208] At this time, the positively charged test object 4205 is attracted to the channel 107. (Since the voltage of 4203 > the voltage of 101b = 0 V > the voltage of 101, the positively charged object is attracted to the channel side where the voltage is smaller.) When 4205 approaches or comes into contact with the channel, the value of the electronic current flowing through the channel changes.

[0209] The amount of change can be used to determine the type, charge state, and shape of the test object 4205. At this time, if a hole leakage current flows through the channel, the holes have a positive charge and are therefore repelled by the test object 4205, which has a positive charge, causing the test object 4205 to move away from the channel, thereby reducing the efficiency of the test.

[0210] However, if a diffusion layer structure with a control gate as in the present invention is provided, the inflow of holes into the channel is suppressed when an electron current is flowing through the channel, so there is no repulsion between the inspection object 4205 and the holes, which would reduce the efficiency of the inspection.

[0211] The same can be said when detecting the inspection target 4206. For example, by applying a negative voltage to 4203, 1402, 1402b, 108, and 108b, a positive voltage to 102, and 0 V to 102b, a hole current flows through the channel 107. At the same time, by applying a strong negative voltage to 1401 and 1401b, the absolute value of which is greater than that of the voltages of 1402 and 1402b, the inflow of electrons from 101 and 101b into the channel is blocked.

[0212] At this time, the negatively charged test object 4206 is attracted to the channel 107. (Since the voltage of 4203 < the voltage of 101b = 0V < the voltage of 101, the negatively charged object is attracted to the channel side where the voltage is greater.) When 4206 approaches or comes into contact with the channel, the value of the electronic current flowing through the channel changes.

[0213] The amount of change makes it possible to determine the type, charge state, and shape of the test object 4206. At this time, if an electron leakage current flows through the channel, the electrons have a negative charge, so they repel the negatively charged test object 4206, causing the test object 4206 to move away from the channel, thereby reducing the efficiency of the test.

[0214] However, if a diffusion layer structure with a control gate as in the present invention is provided, the inflow of electrons into the channel is suppressed when a hole current is flowing through the channel, so there is no repulsion between the object to be inspected 4206 and the electrons, which would reduce the efficiency of the inspection.

[0215] In planar technology, a common semiconductor manufacturing process, since FinFETs became commonplace, the layout of active region (fin) patterning has been restricted to align the line width and the width between the lines in order to achieve fine line widths. This is because when using a technology that uses phase interference to resolve patterns smaller than the wavelength of the lithography light source, or a spacer technology called SADP (self-aligned double patterning) to pattern down to half the size of the resolution limit, if all patterns are laid out in parallel with equal spacing, these technologies can be used effectively and fine line widths can be achieved. Figure 57 shows this.

[0216] Reference numeral 5701 denotes a Si substrate or an SOI substrate, 5700 denotes a resist pattern remaining after exposure and development, and 5702 denotes a portion from which the resist has been removed after exposure and development. When forming a dense pattern of fine lines, fine lines can be formed by making the line width of 5700 and the width of the space between the lines 5702 uniform and forming a parallel pattern, as shown in Figure 57.

[0217] Thereafter, the substrate 5701 is etched using the resist 5700 as a mask, and after the resist is removed, an oxide film is deposited and then polished, thereby forming a structure in which a fine channel 107 is sandwiched between oxide films, as shown in FIG. 58.

[0218] If it is desired to process the shape of the channel formed in this manner, for example, as shown in Figure 59, a resist is applied, exposed, and developed to form a resist pattern 5900 with a hole pattern formed in the area to be processed, and then dry etching is performed, and the resist pattern is then removed, thereby forming a shape as shown in Figure 60.

[0219] As can be seen from the above, the basic structure is defined by the parallel patterns shown in FIGS. 57 and 58, and subsequent processing (FIGS. 59 and 60) can only involve cutting a portion of the structure.

[0220] That is, when drawing a dense pattern of fine lines to form an array of elements, it is necessary to align the line width and the width between the lines and lay out the lines in parallel at equal intervals in order to achieve a fine line width, but in this case it is difficult to form a branched pattern such as that shown in the top view of Figure 11 in the embodiment of the present invention. Therefore, this embodiment shows a method and structure that solves this problem.

[0221] A solution to this problem is shown in Figures 61 and 62. The top view in Figure 61(a) shows two exposure patterns, 6100 (solid line) and 6101 (dashed line). The enclosed areas in each pattern are the portions of the resist that will be removed after exposure. The manufacturing method will be explained using the cross-sectional views of A-A' and B-B'.

[0222] 61(b), first, a mask layer 6102 having a sufficient selectivity to Si during etching is deposited on an SOI substrate, and then a mask layer 6103 having a sufficient selectivity to Si and the mask layer 6102 is deposited on top of that. The mask layer may be a combination of SiO2, SiN, amorphous silicon, spin-on glass (SOG), or a silicon-containing resin material. For example, SiO2 may be used for the mask layer 6102, and amorphous carbon may be used for the mask layer 6103.

[0223] Next, a resist is applied, and the resist is exposed using an exposure pattern 6101, and then developed. After that, dry etching with a good selectivity is performed so that 6103 is well etched and 6102 and Si are not etched very much, and then the resist is removed, thereby forming a shape as shown in Figure 61(c).

[0224] Then, a resist is applied, and the resist is exposed using an exposure pattern 6100, and then developed. After that, dry etching with a good selectivity is performed so that 6102 is well etched and 6103 and Si are not etched very much, and then the resist is removed, thereby forming a shape as shown in Figure 61(d).

[0225] Thereafter, the Si substrate is etched using the hard masks 6102 and 6103 as masks, and then the hard masks 6102 and 6103 are removed. After that, a silicon oxide film is formed and polished, thereby forming a lattice pattern channel as shown in FIG. 62.

[0226] By using this method, it is possible to form channels that bridge between parallel channel patterns of fine lines, i.e., it is possible to form a branched pattern as shown in the top view of Figure 11. Figure 62(b) clearly shows this.

[0227] In FIG. 61, by using only one mask pattern 6101 and making it so that it overlaps only the first and second patterns 6100 from the bottom, a structure like that shown in FIG. 62(b) can be formed.

[0228] This example shows a manufacturing method for preventing a thin channel pattern from collapsing after formation when forming the pattern as shown in Example 13. The top view of Figure 63(a) shows two exposure patterns, 6300 (solid line) and 6301 (dashed line).

[0229] The enclosed areas in each diagram are the patterns where the resist is removed after exposure. The manufacturing method will be explained using the cross-sectional views of AA' and BB'.

[0230] First, a resist is applied to an SOI substrate, and the resist is exposed using an exposure pattern 6301, then developed. After that, the Si in the 6301 portion is etched by dry etching, and the resist is then removed. Then, an oxide film is deposited, and polished to form a structure in which SiO2 is sandwiched between Si 107, as shown in Figure 63(b).

[0231] 63(c), a hard mask layer 6302 (e.g., a SiN film) having high selectivity to Si during etching is formed. Thereafter, a resist is applied, and the resist is exposed using an exposure pattern 6300, and then developed. After that, the hard mask 6302 and the Si 107 are dry-etched by dry etching.

[0232] During the dry etching of 107, conditions with a high selectivity are selected so that only Si is etched, with almost no SiO2 being etched. The resist is then removed. This allows the structure shown in Figure 63(d) to be formed.

[0233] Generally, when forming a Fin structure, if the height of Si 107 is high, when attempting to form a thin line pattern, the aspect ratio (thin line height / line width) becomes large, resulting in the problem that the pattern is more likely to collapse.

[0234] However, as in this embodiment, SiO2 lines are present in the pattern portion of 6301, and the SiO2 lines are structured to periodically sandwich Si 107, so that the channel 107 is supported by the SiO2 in the pattern portion of 6301, and it is possible to prevent the channel 107 from collapsing.

[0235] After the steps up to FIG. 63(c) are completed, the hard mask 6302 is removed, and then a silicon oxide film is formed and polished to form the structure shown in FIG.

[0236] To operate the devices with control gates shown in the previous embodiments, it is necessary to share appropriate voltages with the gates, including the control gate, depending on the operation at each time (for example, when transporting electrons, when reading out PMOS, when discharging electrons to the N-type diffusion layer, etc.).

[0237] To this end, as shown in FIG. 65, it is preferable to provide a control circuit unit section for controlling the voltage applied to the gates including the control gate, and to control the voltage applied to each gate during each operation.

[0238] In this embodiment, another method of arranging the control gates is shown in Figure 66. Compared with Figure 8(c), in Figure 66(a), the control gates 801, 803, and 805 cover the intersection of the channels extending from the N-type diffusion layer and the P-type diffusion layer.

[0239] The present invention can be effectively implemented even with such an arrangement of control gates. Specifically, consider the case where 0 V is applied to 103 and 104, 0.1 V to 105, and −0.1 V to 106, and positive voltages are applied to 115, 116, 117, and 803 (for example, 1.5 V to 116 and 1.7 V to 115, 117, and 803), and an electron current flows from 103 to 105.

[0240] At this time, the same voltage as that applied to 115 is applied to 801, and a positive voltage (e.g., 3 V) stronger than the voltage applied to 802 is applied to 802 so as to suppress the inflow of holes from 104 to the channel 107.

[0241] 55, by applying to 802 a positive voltage that is sufficiently stronger than the voltage applied to 115, the potential barrier against holes below 802 is made sufficiently high, blocking the inflow of holes into the channel. In this way, electrons can flow in the channels below 15, 116, and 117 without mixing with the hole current from 104.

[0242] For example, consider the case where 0 V is applied to 103 and 104, 0.1 V to 105, and −0.1 V to 106, and negative voltages are applied to 115, 116, 117, 803, and 804 (for example, −1.5 V to 116, and −1.7 V to 115, 117, 803, and 804), causing a hole current to flow from 104 to 106.

[0243] At this time, the same negative voltage as that applied to 115 is applied to 802, and a stronger negative voltage (for example, −3 V) than that applied to 802 is applied to 801 so as to suppress the inflow of electrons from 103 into the channel 105. By doing so, holes can flow in the channels below 115, 116, and 117 without being mixed with the electron current from 103.

[0244] FIG. 66(b) shows an example of an arrangement in which the positions of the N-type diffusion layer and the P-type diffusion layer are interchanged in FIG. 66(a).

[0245] 101 N-type diffusion layer, 102 P-type diffusion layer, 103 N-type diffusion layer, 104 P-type diffusion layer, 105 N-type diffusion layer, 106 P-type diffusion layer, 107 channel (silicon), 108 gate, 109 gate, 110 gate, 111 gate, 112 gate, 113 gate, 114 gate, 115 gate, 116 gate, 117 gate, 120 silicon oxide film, 122 silicon substrate, 301 electron, 302 electron current path, 501 electron, 502 hole, 503 hole current path, 504 electron, 505 electron, 601 electron leakage path, 602 electron, 701 hole, 702 hole leakage path, 703 electron current path, 704 hole current path, 705 Electron leakage path, 801 control gate, 802 control gate, 803 control gate, 804 control gate, 805 control gate, 806 control gate, 1301 mask pattern (opening portion) during ion implantation, 1302 mask pattern (opening portion) during ion implantation, 1401 control gate, 1402 control gate, 1403 sidewall of same material as control gate, 1501 control gate, 1502 control gate, 1503 control gate, 1504 control gate, 1701 control gate, 1801 gate, 1802 control gate, 1803 control gate, 1804 gate, 1805 control gate, 1806 control gate, 2201 control gate material, 2301 etched portion of control gate material, 2302 etched portion of control gate material, 2303 silicon oxide film, 2401 Contact hole, 3201 gate, 3701 gate array, 3702 gate array, 4201 insulating film, 4202 chamber, 4203 electrode, 4204 electrolyte, 4205 inspection object, 4206 inspection object, 5700 resist, 5701 Si or SOI substrate, 5702 area without resist, 5900 resist, 6100 exposure area, 6101 exposure area, 6102 hard mask, 6103 hard mask, 6300 exposure area, 6301 exposure area, 6302 hard mask

Claims

1. A semiconductor device that controls the flow of electrons or holes into a channel, comprising an N-type diffusion layer connected to the channel and a P-type diffusion layer connected to the channel, a first gate capable of inducing or removing carriers from the N-type diffusion layer into the channel, or both of a second gate capable of inducing or removing carriers from the P-type diffusion layer into the channel, and a third gate capable of inducing or removing carriers from at least one of the first gate and the second gate into the channel.

2. A semiconductor device as claimed in claim 1, wherein the third gate has a shape in which either or both of the first gate or the second gate are sandwiched between the third gate and short-circuited, and the third gate induces or removes carriers in channels on both sides of the first gate or the second gate or both of the first gate or the second gate.

3. A semiconductor device according to claim 2, wherein the first gate and the second gate are connected to each other.

4. A semiconductor device according to claim 1, further comprising a block pattern formed of the same material as the third gate, and wherein wiring for the first gate and the second gate is formed along the block pattern.

5. A semiconductor device as claimed in claim 4, wherein a block pattern formed of the same material as the third gate is surrounded by an enclosure structure formed of the same material as the third gate, and the first gate and the second gate are spaced apart on the inside and outside of the enclosure structure.

6. A semiconductor device as claimed in claim 1, wherein when electrons or holes are caused to flow into said channel from said N-type diffusion layer or said P-type diffusion layer, the voltage of the third gate is lower than the voltage of the second gate when electrons are caused to flow, and the voltage of the first gate is lower than the third gate voltage when holes are caused to flow.

7. A semiconductor device according to claim 6, wherein when electrons are caused to flow into the channel, the voltage of the third gate is higher than the flat band voltage, and when holes are caused to flow into the channel, the voltage of the third gate is lower than the flat band voltage.

8. A semiconductor device having the control mechanism described in claim 1, wherein the channel has at least one location where electric charge is trapped, and the value of the current flowing through the channel changes according to the amount of electric charge present at that location.

9. A semiconductor device as claimed in claim 8, wherein the charge trapped at said location is detected based on the value of the current flowing through said channel, the carriers of said current have an opposite sign to said charge, and when said current is flowing, a voltage is applied to a first or second gate to suppress the inflow of carriers of the opposite sign to the carriers of said current from said diffusion layer into said channel.

10. A semiconductor device as claimed in claim 1, wherein the channel has at least one location where charge is trapped, the channel spans multiple rows, and the current flowing through the channel varies depending on the amount of charge at the location.

11. A semiconductor device according to claim 10, wherein the charge trapped at said location is detected from the value of the current flowing through said channel, the carriers of said current have an opposite sign to said charge, and when said current is flowing, a voltage is applied to the first or second gate which suppresses carriers of the opposite sign to the current carriers from flowing from said diffusion layer into said channel.

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