Semiconductor device

Abstract

A semiconductor device (1) is provided with a plurality of semiconductor modules (2). Each of the plurality of semiconductor modules (2) is provided with: a base plate (13) having a first surface exposed to the outside of the semiconductor module (2) and a second surface on an opposite side of the first surface; an insulating substrate provided with a circuit pattern; a semiconductor chip bonded to the circuit pattern; a sealing part for sealing the insulating substrate and the semiconductor chip; and a first main electrode and a second main electrode led out from the inside of the sealing part in a direction opposite to a direction from the sealing part toward the base plate (13). A plan shape of the semiconductor module (2) has four corner parts and is rotationally symmetrical. The first main electrode is led out from the inside of the sealing part in each of the first corner part and the second corner part from among the four corner parts. The second main electrode is lead out from the inside of the sealing part in each of the third corner part and the fourth corner part from among the four corner parts.

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device including a semiconductor element for power control.

[0002] Conventionally, designers of electrical equipment such as industrial equipment or consumer equipment often select a power module from among several power modules offered by manufacturers of semiconductor devices for power control when designing the electrical equipment. A power module is a semiconductor device in which multiple semiconductor chips are mounted in a single package. When selecting a power module from among the power modules offered by manufacturers, the selected power module determines the circuit layout, the shape of the cooler, and the like, so the external shape of the electrical equipment is somewhat limited. On the other hand, there is also a demand for greater freedom in the shape of electrical equipment. However, from the perspective of the manufacturing cost of the power module or the reliability of the power module, it is difficult to redesign the power module for each electrical equipment.

[0003] Patent Document 1 discloses a semiconductor device in which multiple semiconductor chips are arranged in independent semiconductor modules, and the semiconductor modules are connected to each other to achieve functionality equivalent to that of a power module. The semiconductor modules disclosed in Patent Document 1 have similar configurations. The collector main electrode and emitter main electrode of each semiconductor module are arranged to reach the top surface of the semiconductor module and are connectable to an external circuit and to adjacent semiconductor modules. For example, adjacent semiconductor modules are arranged so that the collector main electrode of one semiconductor module faces the emitter main electrode of the other semiconductor module, and the collector main electrode and the emitter main electrode are fixed to a conductive plate with bolts. This connects the collector main electrode and the emitter main electrode to each other and fixes the two semiconductor modules to each other.

[0004] International Publication No. 2014 / 030254

[0005] In the semiconductor module of the semiconductor device disclosed in Patent Document 1, two collector main electrodes are adjacent to each other and two emitter main electrodes are adjacent to each other. For example, when adjacent semiconductor modules are arranged such that the collector main electrode of one semiconductor module faces the emitter main electrode of the other semiconductor module, the main electrode of the one semiconductor module that can be connected to an external circuit may be limited to the emitter electrode, and the main electrode of the other semiconductor module that can be connected to an external circuit may be limited to the collector electrode. In other words, in the semiconductor device disclosed in Patent Document 1, the layout of each semiconductor module is necessarily determined once the connection mode of the semiconductor modules is determined, resulting in limited flexibility in the layout of each semiconductor module. In the semiconductor device disclosed in Patent Document 1, it is difficult to change the layout of each semiconductor module to suit the connection to the external circuit, and measures such as wiring to connect the main electrodes of each semiconductor module to the external circuit may be required.

[0006] The present disclosure has been made in view of the above, and has an object to provide a semiconductor device that allows each of a plurality of semiconductor modules to be arranged with a high degree of freedom.

[0007] To solve the above-mentioned problems and achieve the object, the semiconductor device according to the present disclosure includes a plurality of semiconductor modules. Each of the plurality of semiconductor modules includes a base plate having a first surface exposed to the outside of the semiconductor module and a second surface opposite the first surface, an insulating substrate disposed on the second surface side and having a circuit pattern thereon, a semiconductor chip bonded to the circuit pattern, a sealing portion disposed on the second surface side and sealing the insulating substrate and the semiconductor chip, and first and second main electrodes extending from within the sealing portion in a direction opposite to the direction from the sealing portion toward the base plate. When viewed from a direction normal to the second surface, the semiconductor module has a planar shape with four corners and rotational symmetry. The first main electrodes extend from within the sealing portion at each of the first and second corners, which are two of the four corners that face each other across the center of the planar shape. The second main electrode is drawn out from inside the sealing portion at each of the third and fourth corners, which are the other two of the four corners other than the first and second corners.

[0008] The semiconductor device according to the present disclosure has the advantage that each of the plurality of semiconductor modules can be arranged with a high degree of freedom.

[0009] 1 is a perspective view showing a configuration example of a semiconductor device according to a first embodiment; a perspective view of a semiconductor module included in the semiconductor device according to the first embodiment; a top view of the semiconductor module included in the semiconductor device according to the first embodiment; a side view of the semiconductor module included in the semiconductor device according to the first embodiment; a bottom view of the semiconductor module included in the semiconductor device according to the first embodiment; a longitudinal sectional view of the semiconductor module included in the semiconductor device according to the first embodiment; a cross sectional view of the semiconductor module included in the semiconductor device according to the first embodiment; an internal wiring diagram of the semiconductor module included in the semiconductor device according to the first embodiment; a perspective view showing a state in which the semiconductor device according to the first embodiment is mounted on a substrate; a plan view of a substrate on which the semiconductor device according to the first embodiment is mounted; a diagram showing a first example of a combination pattern of semiconductor modules in the first embodiment; a diagram showing a second example of a combination pattern of semiconductor modules in the first embodiment; a perspective view of a semiconductor device according to a first modified example of the first embodiment; a top view of a semiconductor device according to a first modified example of the first embodiment; a perspective view of a semiconductor device according to a second modified example of the first embodiment; a top view of a semiconductor device according to a second modified example of the first embodiment; a perspective view of a semiconductor device according to a third modified example of the first embodiment; a perspective view of a semiconductor device according to a fourth modified example of the first embodiment; a perspective view of a semiconductor device according to a fifth modified example of the first embodiment;

[0010] Semiconductor devices according to embodiments will be described in detail below with reference to the drawings.

[0011] First Embodiment Fig. 1 is an exploded perspective view showing a configuration example of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 according to the first embodiment includes a plurality of semiconductor modules 2. The semiconductor device 1 is an integrated module in which a plurality of semiconductor modules 2 are integrated. Each of the plurality of semiconductor modules 2 has a similar configuration. The semiconductor device 1 illustrated in Fig. 1 includes two semiconductor modules 2.

[0012] FIG. 1 shows a semiconductor device 1, a substrate 3 on which the semiconductor device 1 is mounted, and a cooler 4 that cools the semiconductor device 1. The substrate 3 is a circuit board on which a circuit is mounted. For example, a control circuit that controls the semiconductor device 1 is mounted on the substrate 3. In the example shown in FIG. 1, the cooler 4 is fixed to the semiconductor device 1 with two screws 5. The cooler 4 may have any configuration. A heat sink may be used as the cooler 4 that cools the semiconductor device 1. In the following description, the side on which the substrate 3 is disposed relative to the semiconductor device 1 is referred to as "top," and the side on which the cooler 4 is disposed relative to the semiconductor device 1 is referred to as "bottom." The terms "top" and "bottom" are used for convenience and do not refer to the top and bottom of the semiconductor device 1 when it is actually disposed.

[0013] FIG. 2 is a perspective view of the semiconductor module 2 included in the semiconductor device 1 according to the first embodiment. FIG. 3 is a top view of the semiconductor module 2 included in the semiconductor device 1 according to the first embodiment. FIG. 4 is a side view of the semiconductor module 2 included in the semiconductor device 1 according to the first embodiment. FIG. 5 is a bottom view of the semiconductor module 2 included in the semiconductor device 1 according to the first embodiment. FIG. 6 is a vertical cross-sectional view of the semiconductor module 2 included in the semiconductor device 1 according to the first embodiment. FIG. 7 is a horizontal cross-sectional view of the semiconductor module 2 included in the semiconductor device 1 according to the first embodiment. FIG. 8 is an internal wiring diagram of the semiconductor module 2 included in the semiconductor device 1 according to the first embodiment.

[0014] As shown in FIGS. 6 and 7 , the semiconductor module 2 includes a plurality of main electrodes 10, an IGBT (Insulated Gate Bipolar Transistor) 11, an FWD (Free Wheeling Diode) 12, a base plate 13, an insulating substrate 14, a plurality of wires 16, a case 17, a lid 18, and a sealing material 19.

[0015] The base plate 13 is a metal plate. The base plate 13 transfers heat generated in each of the IGBT 11 and the FWD 12 to the cooler 4. The material of the base plate 13 is a metal material with high thermal conductivity, such as copper or aluminum. The base plate 13 has a lower surface which is a first surface, and an upper surface which is a second surface opposite to the first surface. The lower surface of the base plate 13 is the surface exposed to the outside of the semiconductor module 2 and faces the side where the cooler 4 is disposed. By directly or indirectly contacting the lower surface with the cooler 4, the base plate 13 can transfer the generated heat to the cooler 4.

[0016] The insulating substrate 14 is disposed on the upper surface side of the base plate 13. The insulating material constituting the insulating substrate 14 is, for example, ceramic or resin. A circuit pattern 15 made of copper foil is provided on the upper surface of the insulating substrate 14.

[0017] Each of the IGBT 11 and the FWD 12 is a semiconductor chip joined to the circuit pattern 15. Each of the IGBT 11 and the FWD 12 is joined to the circuit pattern 15 by, for example, soldering. The IGBT 11 and the FWD 12 are connected in parallel to each other.

[0018] The multiple wires 16 provided in the semiconductor module 2 include wires 16 connecting the electrodes of the IGBT 11 and the electrodes of the FWD 12, wires 16 connecting the electrodes of the IGBT 11 and the circuit pattern 15, and wires 16 connecting the electrodes of the FWD 12 and the circuit pattern 15.

[0019] The case 17 is provided on the upper surface of the base plate 13. The case 17 forms the outer shell of the semiconductor module 2. The case 17 has four side surfaces that follow the outer edge of the base plate 13. Each of the four side surfaces includes a normal direction to the upper surface of the base plate 13. In the following description, the normal direction to the upper surface of the base plate 13 will be simply referred to as the normal direction. Figure 4 shows one of the four side surfaces of the case 17.

[0020] Case 17 surrounds insulating substrate 14, and IGBT 11, FWD 12, circuit pattern 15, and multiple wires 16 on insulating substrate 14. The lower end of case 17 is closed by base plate 13. The upper end of case 17 is closed by lid 18. A space formed by base plate 13, case 17, and lid 18 is filled with sealing material 19. Case 17, lid 18, and sealing material 19 are provided on the upper surface side of base plate 13 and form a sealing portion that seals insulating substrate 14 and the semiconductor chip.

[0021] A groove 21 is formed on each of the four side surfaces of the case 17. The groove 21 is recessed from the outside of the sealing portion toward the inside of the sealing portion and extends along a direction perpendicular to the normal direction. The depth direction of the groove 21 is the direction from the outside of the sealing portion toward the inside of the sealing portion. The extending direction of the groove 21 is a direction perpendicular to the normal direction and perpendicular to the depth direction of the groove 21. In the following description, the extending direction of the groove 21 is also referred to as the longitudinal direction of the groove 21.

[0022] The cross section shown in Fig. 6 is a cross section including the normal direction, and is a cross section perpendicular to the longitudinal direction of groove 21 formed on each of two opposing side surfaces among the four side surfaces. The shape of groove 21 in the cross section shown in Fig. 6 is a trapezoidal shape in which the width of groove 21, which is the length in the normal direction perpendicular to the longitudinal direction, increases from the outside of the sealing portion toward the inside of the sealing portion.

[0023] One of two adjacent semiconductor modules 2 shown in FIG. 1 is designated the first semiconductor module, and the other is designated the second semiconductor module. The first semiconductor module and the second semiconductor module are arranged with one side surface of the first semiconductor module facing one side surface of the second semiconductor module. As shown in FIG. 1 , a pin 6 is inserted into a gap formed by combining a groove 21 on the side surface of the first semiconductor module with a groove 21 on the side surface of the second semiconductor module. The pin 6 is inserted along the longitudinal direction of these grooves 21. The first semiconductor module and the second semiconductor module are connected to each other by the pin 6 inserted into the gap formed by combining the groove 21 of the first semiconductor module with the groove 21 of the second semiconductor module.

[0024] When the pin 6 is inserted, a portion of the pin 6 is inserted into the groove 21 of the first semiconductor module, and another portion of the pin 6 is inserted into the groove 21 of the second semiconductor module. The cross section of the portion of the pin 6 inserted into the groove 21 of the first semiconductor module and the cross section of the portion of the pin 6 inserted into the groove 21 of the second semiconductor module each have a trapezoidal shape that can fit into the groove 21. When the pin 6 is inserted into the groove 21, the pin 6 does not come out of the groove 21 even if it is pulled in a direction perpendicular to the longitudinal direction of the groove 21. Even if a force in a direction that separates the first semiconductor module and the second semiconductor module is applied to at least one of the first semiconductor module and the second semiconductor module, the pin 6 does not come out of the groove 21, and therefore the first semiconductor module and the second semiconductor module are not separated. In this way, the first semiconductor module and the second semiconductor module are connected to each other by the pin 6. The first semiconductor module and the second semiconductor module are integrated together using pins 6 .

[0025] In the above description, the pins 6 are inserted into the grooves 21 on the side surfaces of the first semiconductor module and the grooves 21 on the side surfaces of the second semiconductor module that face the first semiconductor module. Alternatively, the pins 6 may be inserted into the grooves 21 on the side surfaces of the first semiconductor module and the grooves 21 on the side surfaces of the second semiconductor module that are adjacent to the first semiconductor module. In this case, the pins 6 are arranged so as to straddle the first semiconductor module and the second semiconductor module in the direction in which the pins 6 are inserted. In this case, the first semiconductor module and the second semiconductor module are also integrated by using the pins 6. The number of pins 6 used to connect the first semiconductor module and the second semiconductor module is not limited to one, and may be multiple. The pins 6 may be inserted into the grooves 21 on the first semiconductor module and the grooves 21 on the second semiconductor module, and may be inserted at any position. Furthermore, the shape of the grooves 21 is not limited to a trapezoidal shape. Groove 21 may be formed in any way so that when a force is applied to at least one of the first and second semiconductor modules in a direction that separates the first and second semiconductor modules, inserted pin 6 will not come out of groove 21. For example, groove 21 may be L-shaped or S-shaped, and pin 6 may have a shape that corresponds to groove 21 so that it can be inserted into groove 21.

[0026] 5, four semicircular notches 22 are formed on the outer edge of the base plate 13. The planar shape of the base plate 13 is a square with the four notches 22 formed therein. Each notch 22 is formed at the center of each side of the square.

[0027] 1 is passed through the notch 22 and screwed into the hole in the cooler 4. By screwing the screw 5, the base plate 13 is fastened to the cooler 4. By fastening the base plate 13 to the cooler 4, the semiconductor module 2 is fixed to the cooler 4.

[0028] A recess 23 is formed on each of the four side surfaces of the case 17. The recess 23 is formed on the cutout 22. The recess 23 is recessed from the outside of the sealing portion toward the inside of the sealing portion and is formed along the normal direction. The cross section shown in FIG. 7 is a cross section perpendicular to the normal direction and passing through the groove 21 formed on each of the four side surfaces of the case 17. The shape of the recess 23 in the cross section shown in FIG. 7 is a semicircle that is slightly larger than the cutout 22. The depth of the recess 23, which is the length recessed from the outside of the sealing portion toward the inside of the sealing portion, is set to a depth that allows the head of the screw 5 to pass through when the screw 5 is installed.

[0029] 1 , screws 5 are attached to two locations, namely, the notch 22 at one end and the notch 22 at the other end in the direction in which the first semiconductor module and the second semiconductor module are arranged. The first semiconductor module and the second semiconductor module, which are integrated with each other by the pins 6, are fixed to the cooler 4 by the two screws 5, thereby fixing the cooler 4 to the semiconductor device 1.

[0030] The positions at which the screws 5 are attached are not limited to the example shown in Fig. 1 . The number of attached screws 5 is not limited to two and may be any number. It is sufficient that the screws 5 are attached to at least one of the positions at which the screws 5 can be attached. Holes into which the screws 5 are screwed are formed at the positions in the cooler 4 where the screws 5 are attached.

[0031] 1 , when the semiconductor device 1 is viewed from above, there are six notches 22 on the outer edge of the planar shape of the semiconductor device 1. A screw 5 can be attached at each of the six notches 22. Furthermore, when the semiconductor device 1 is viewed from above, there is a hole in the center of the semiconductor device 1 formed by combining the notch 22 of the first semiconductor module and the notch 22 of the second semiconductor module. A screw 5 can also be attached at the position of this hole. The screw 5 is attached at least at one of these positions.

[0032] 1 , when the pin 6 is inserted so as to pass through the center of the semiconductor device 1, and the screw 5 is attached to the hole located at the center of the semiconductor device 1, the pin 6 is inserted after the screw 5 is attached. Alternatively, the pin 6 is inserted into the groove 21 of the first semiconductor module and the groove 21 of the second semiconductor module, excluding the recess 23 through which the screw 5 is inserted. This prevents the pin 6 from interfering with the attachment of the screw 5.

[0033] According to the above description, the multiple semiconductor modules 2 of the semiconductor device 1 are integrated by the pins 6 and fixed to the cooler 4 by the screws 5. In this way, the cooler 4 is fixed to the semiconductor device 1. By using the screws 5 and the pins 6 as components for fixing the cooler 4, the cooler 4 can be fixed to the semiconductor device 1 with a small number of components. This makes it possible to miniaturize the configuration including the semiconductor device 1 and the cooler 4. Furthermore, it is possible to simplify the assembly work for the configuration including the semiconductor device 1 and the cooler 4. By forming the four notches 22 in the base plate 13, the positions of the screws 5 can be appropriately selected to fix the cooler 4.

[0034] Fig. 3 shows the shape of the top surface of the semiconductor module 2. Fig. 5 shows the shape of the bottom surface of the semiconductor module 2. The outer edge shape of the top surface of the semiconductor module 2 and the outer edge shape of the bottom surface of the semiconductor module 2 are the same. The planar shapes of the outer edge shape of the top surface of the semiconductor module 2 and the outer edge shape of the bottom surface of the semiconductor module 2 are the planar shapes of the semiconductor module 2 when viewed from the normal direction.

[0035] When the planar shape of the semiconductor module 2 is rotated 90 degrees around the center of the planar shape of the semiconductor module 2, the planar shape of the semiconductor module 2 after the rotation overlaps with the planar shape of the semiconductor module 2 before the rotation. That is, the planar shape of the semiconductor module 2 has four-fold symmetry. In this way, the planar shape of the semiconductor module 2 has rotational symmetry. The posture of the outer hull of the semiconductor module 2 does not appear to change before and after the semiconductor module 2 is rotated 90 degrees around an axis in the normal direction passing through the center of the planar shape of the semiconductor module 2 as the rotation axis.

[0036] The planar shape of the semiconductor module 2 is the same as that of the base plate 13, that is, a square with four notches 22 formed therein. Since each notch 22 is formed at the center of each side of the square, the planar shape of the semiconductor module 2 has four-fold symmetry. Also, the planar shape of the semiconductor module 2 has four corners, just like a square.

[0037] Here, of the four corners, the lower left corner of the semiconductor module 2 is defined as the first corner. The corner on the same diagonal as the first corner in the planar shape of the semiconductor module 2 is defined as the second corner. The second corner is defined as the upper right corner of the semiconductor module 2. That is, the first corner and the second corner are the two of the four corners that face each other across the center of the planar shape of the semiconductor module 2. Furthermore, the two of the four corners other than the first and second corners are defined as the third and fourth corners. The third corner is defined as the upper left corner of the semiconductor module 2. The fourth corner is defined as the lower right corner of the semiconductor module 2. Note that in the description of FIG. 3 , the upper left, lower left, upper right, and lower right refer to positions relative to the center of the planar shape of the semiconductor module 2, and refer to the positions in FIG. 3 .

[0038] 8, the semiconductor module 2 has a plurality of main electrodes 10, which include two gate electrodes 10a, six collector electrodes 10b, and six emitter electrodes 10c. The term "main electrodes 10" refers to the two gate electrodes 10a, the six collector electrodes 10b, and the six emitter electrodes 10c without distinction. Each of the six collector electrodes 10b is also referred to as a "first main electrode." Each of the six emitter electrodes 10c is also referred to as a "second main electrode."

[0039] One end of each of the multiple main electrodes 10 is soldered to the circuit pattern 15. Each of the multiple main electrodes 10 is electrically insulated from the base plate 13 by the insulating substrate 14. The other end of each of the multiple main electrodes 10 is exposed to the outside of the sealing portion. Each of the multiple main electrodes 10 penetrates the lid 18 and is drawn from the inside of the sealing portion to the outside of the sealing portion. Each of the multiple main electrodes 10 is drawn from the inside of the sealing portion in a direction opposite to the direction from the sealing portion toward the base plate 13, i.e., upward. Each of the multiple main electrodes 10 extends from the surface of the sealing portion opposite the base plate 13, i.e., in the normal direction from the upper surface of the lid 18.

[0040] As shown in Figure 3, three collector electrodes 10b, which are first main electrodes, extend from the first corner. Three collector electrodes 10b, which are first main electrodes, extend from the second corner. Three emitter electrodes 10c, which are second main electrodes, extend from the third corner. Three emitter electrodes 10c, which are second main electrodes, extend from the fourth corner. Furthermore, two gate electrodes 10a extend from positions adjacent to the three emitter electrodes 10c at the fourth corner.

[0041] Fig. 9 is a perspective view showing a state in which the semiconductor device 1 according to the first embodiment is mounted on a substrate 3. Fig. 10 is a plan view of the substrate 3 on which the semiconductor device 1 according to the first embodiment is mounted.

[0042] As shown in FIG. 10 , a plurality of holes 25 are formed in the substrate 3. A main electrode 10 passes through each of the plurality of holes 25. A plurality of electrodes 24 are also provided on the substrate 3. Each of the plurality of electrodes 24 is formed at a position where the main electrode 10 passes through. The plurality of electrodes 24 provided on the substrate 3 include an electrode 24a to which only the main electrode 10 of one of the two semiconductor modules 2 is connected, and an electrode 24b to which the main electrodes 10 of both of the two semiconductor modules 2 are connected. The electrode 24b is an electrode that electrically connects the main electrode 10 of one of the two semiconductor modules 2 to the main electrode 10 of the other semiconductor module 2. The term "electrode 24" will be used to refer to the electrodes 24a and 24b without distinction.

[0043] The substrate 3 is placed over the semiconductor device 1. The main electrodes 10 passed through the holes 25 are connected to the electrodes 24 by soldering. In this way, the semiconductor device 1 is mounted on the substrate 3, as shown in Fig. 9. The two semiconductor modules 2 are electrically connected to each other via a circuit mounted on the substrate 3.

[0044] Because each of the multiple main electrodes 10 extends in the normal direction from the upper surface of the lid 18, the main electrodes 10 can be passed through each hole 25 when the substrate 3 is placed over the semiconductor device 1. Because each main electrode 10 is directly joined to the substrate 3 by soldering, no additional elements, such as wiring or a terminal block, are required to mount the semiconductor device 1 on the substrate 3. As long as the electrodes 24 and holes 25 are formed on the substrate 3, no elements different from those required when a conventional power module is mounted need to be added to the substrate 3. Therefore, the semiconductor device 1 can be easily mounted on the substrate 3.

[0045] By providing the insulating substrate 14 on the semiconductor module 2, each of the main electrodes 10 and the circuit pattern 15 are electrically insulated from the base plate 13. Because each of the main electrodes 10 extends upward from the upper surface of the lid 18, electrical insulation between each of the main electrodes 10 and the cooler 4 can be easily ensured. This simplifies the insulation design of the semiconductor device 1.

[0046] By arranging the semiconductor modules 2 so that the main electrodes 10 of one semiconductor module 2 are adjacent to the main electrodes 10 of the other semiconductor module 2, the two semiconductor modules 2 can be electrically connected in a variety of arrangements using short wiring patterns. That is, the two semiconductor modules 2 can be electrically connected using a wiring pattern with low inductance. Because the two semiconductor modules 2 can be electrically connected using a short wiring pattern, it is also easy to implement a snubber circuit or a protection circuit for noise reduction. Being able to electrically connect the two semiconductor modules 2 using a short wiring pattern is also advantageous in terms of ease of design and reduced malfunction. Compared to conventional discrete semiconductors, the semiconductor device 1 is advantageous in terms of allowing greater freedom in the arrangement of the semiconductor modules 2, simplified insulation design, simple wiring patterns, smaller circuit size, and low inductance.

[0047] Next, combination patterns of the semiconductor modules 2 will be described. Two examples of combination patterns will be described here. Fig. 11 is a diagram showing a first example of a combination pattern of the semiconductor modules 2 in the first embodiment. Fig. 12 is a diagram showing a second example of a combination pattern of the semiconductor modules 2 in the first embodiment. Figs. 11 and 12 show the top surface of a semiconductor device 1 made up of two semiconductor modules 2.

[0048] 11 and 12, the left semiconductor module 2 is the first semiconductor module, and the right semiconductor module 2 is the second semiconductor module. In addition, in Figures 11 and 12, electrode 24b is shown for reference to show the main electrodes 10 of the first semiconductor module and the main electrodes 10 of the second semiconductor module, which are electrically connected to each other by electrode 24b on substrate 3.

[0049] In the first example shown in Figure 11, the positions of the collector electrode 10b and the emitter electrode 10c in the first semiconductor module are the same as those in the second semiconductor module. In Figure 11, the collector electrode 10b is located at the lower left and upper right of the first semiconductor module, and the emitter electrode 10c is located at the upper left and lower right of the first semiconductor module. The arrangement of the collector electrode 10b and the emitter electrode 10c in the second semiconductor module is the same as that in the first semiconductor module. In the first example, the first semiconductor module and the second semiconductor module are arranged so that the collector electrode 10b and the emitter electrode 10c, which are different types of main electrodes 10, are adjacent to each other.

[0050] 11 , the collector electrode 10b in the upper right portion of the first semiconductor module and the emitter electrode 10c in the upper left portion of the second semiconductor module are connected to each other by an electrode 24b. In the first example, the first semiconductor module and the second semiconductor module are connected in series. In the description of FIG. 11 , the terms upper left, lower left, upper right, and lower right refer to positions relative to the center of the planar shape of the semiconductor module 2, and refer to positions in FIG. 11 .

[0051] In the second example shown in Figure 12, the second semiconductor module is rotated 90 degrees clockwise from the state shown in Figure 11. The positions of the collector electrode 10b and the emitter electrode 10c in the first semiconductor module in Figure 12 are the same as those in the first semiconductor module shown in Figure 11. In Figure 12, the collector electrode 10b is located at the upper left and lower right of the second semiconductor module, and the emitter electrode 10c is located at the lower left and upper right of the second semiconductor module. In the second example, the first semiconductor module and the second semiconductor module are arranged so that the main electrodes 10 of the same type are adjacent to each other. That is, the collector electrodes 10b of the same type of main electrodes 10 are adjacent to each other, and the emitter electrodes 10c of the same type of main electrodes 10 are adjacent to each other.

[0052] In a second example shown in Figure 12, the emitter electrode 10c at the lower right of the first semiconductor module and the emitter electrode 10c at the lower left of the second semiconductor module are connected to each other by an electrode 24b. In the second example, the first semiconductor module and the second semiconductor module are connected in parallel. In the description of Figure 12, the terms upper left, lower left, upper right, and lower right represent positions relative to the center of the planar shape of the semiconductor module 2, and represent positions in Figure 12. The combination patterns of the semiconductor modules 2 are not limited to those exemplified in Figures 11 and 12.

[0053] Since the planar shape of semiconductor module 2 has rotational symmetry, the appearance of the outer shape of the second semiconductor module does not change before and after rotating the second semiconductor module. Also, since collector electrode 10b is disposed at two corners on one diagonal line and emitter electrode 10c is disposed at two corners on the other diagonal line, the positions of collector electrode 10b and emitter electrode 10c in the second semiconductor module are different between Figure 11 and Figure 12.

[0054] 11 and 12 , the semiconductor device 1 allows the arrangement of the first main electrodes and the second main electrodes in each semiconductor module 2 to be changed without changing the posture of the outer casing of each semiconductor module 2. This allows for a high degree of freedom in the arrangement of the semiconductor modules 2 that are connected to each other. In addition, the main electrodes 10 that are electrically connected to each other in the semiconductor modules 2 can be selected with a high degree of freedom.

[0055] In the semiconductor device 1, by appropriately arranging the electrodes 24b, it is possible to select with a high degree of freedom the manner of electrical connection between the semiconductor modules 2 that are coupled to each other. For example, it is possible to arbitrarily select either a serial connection or a parallel connection for the electrical connection between the semiconductor modules 2. The semiconductor device 1 may include a mixture of semiconductor modules 2 that are connected to each other in series and semiconductor modules 2 that are connected to each other in parallel.

[0056] In the above description, each main electrode 10 is electrically connected to the substrate 3 by soldering, but a method other than soldering may be used to connect each main electrode 10 to the substrate 3. For example, each main electrode 10 may be electrically connected to the substrate 3 by press-fitting each main electrode 10 into the substrate 3.

[0057] In the above description, the sealing portion of the semiconductor module 2 includes the case 17, the lid 18, and the sealing material 19. The configuration of the sealing portion is not limited to the configuration described above. The sealing portion may be made of, for example, a molded resin. The components provided on the upper surface of the base plate 13 are sealed by being covered with the molded resin. The molded resin may be a transfer mold formed by transfer molding.

[0058] The semiconductor chips included in the semiconductor module 2 may be semiconductor chips other than the IGBT 11 or the FWD 12. The semiconductor chips included in the semiconductor module 2 may be, for example, metal oxide semiconductor field effect transistors (MOSFETs), diodes, silicon carbide (SiC) devices, or gallium nitride (GaN) devices. For example, if the semiconductor chips included in the semiconductor module 2 are MOSFETs, the first and second main electrodes described above may be source and drain electrodes. If the semiconductor chips included in the semiconductor module 2 are diodes, the first and second main electrodes described above may be anode and cathode electrodes. The semiconductor module 2 may also be an intelligent power module (IPM) in which a gate drive circuit is added to a configuration sealed in a sealing portion.

[0059] In the above description, the semiconductor device 1 is assumed to include two semiconductor modules 2. The number of semiconductor modules 2 constituting the semiconductor device 1 is arbitrary. The arrangement of each of the multiple semiconductor modules 2 is also arbitrary. The arrangement of the multiple semiconductor modules 2 may be determined in accordance with the configuration of an electrical device in which the semiconductor device 1 is provided. For example, the arrangement of the multiple semiconductor modules 2 may be determined in accordance with the circuit system of a power conversion device in which the semiconductor device 1 is provided.

[0060] Next, modifications of the semiconductor device 1 will be described. Fig. 13 is a perspective view showing a semiconductor device 1A according to a first modification of the first embodiment. Fig. 14 is a top view showing the semiconductor device 1A according to the first modification of the first embodiment. Figs. 13 and 14 show the semiconductor device 1A and a heat sink 4A, which is a cooler. The heat sink 4A is fixed to the semiconductor device 1A.

[0061] The semiconductor device 1A includes six semiconductor modules 2 arranged in a line to match the shape of the heat sink 4A. In FIG. 14 , an example of connection using wiring on the front side of the substrate 3 is indicated by a dot-dash line, and an example of connection using wiring on the back side of the substrate 3 is indicated by a dashed line. The six semiconductor modules 2 include semiconductor modules 2 that are adjacent to each other and connected to each other via the substrate 3. Also, as shown in FIG. 14 , among the six semiconductor modules 2, semiconductor modules 2 that are not adjacent to each other may be connected to each other via the substrate 3. For example, a configuration in which multiple semiconductor modules 2 are arranged in a line, like the semiconductor device 1A, can be applied to electrical equipment with a slim shape. In this way, a semiconductor device 1A in which multiple semiconductor modules 2 are arranged to match the desired shape of the electrical equipment can be realized.

[0062] Fig. 15 is a perspective view showing a semiconductor device 1B according to a second modified example of the first embodiment. Fig. 16 is a top view showing the semiconductor device 1B according to the second modified example of the first embodiment. Figs. 15 and 16 show the semiconductor device 1B and a heat sink 4B, which is a cooler. The heat sink 4B is fixed to the semiconductor device 1B.

[0063] The semiconductor device 1B includes three sets of two semiconductor modules 2 similar to those shown in Fig. 1. That is, the semiconductor device 1B includes six semiconductor modules 2. The six semiconductor modules 2 are arranged in a staggered pattern. In Fig. 16, an example of connection by wiring on the substrate 3 is represented by dashed lines.

[0064] Fig. 17 is a perspective view showing a semiconductor device 1C according to a third modification of the first embodiment. Fig. 17 shows the semiconductor device 1C and a heat sink 4C, which is a cooler. The heat sink 4C is fixed to the semiconductor device 1C. The semiconductor device 1C includes three sets of two semiconductor modules 2 similar to those shown in Fig. 1. That is, the semiconductor device 1C includes six semiconductor modules 2. The six semiconductor modules 2 are arranged in a matrix.

[0065] The semiconductor modules 2 of the semiconductor device 1 may be arranged in a staggered arrangement as shown in Figures 15 and 16, or may be arranged in a matrix as shown in Figure 17. The semiconductor modules 2 of the semiconductor device 1 may include a mixture of semiconductor modules 2 arranged in a staggered arrangement and semiconductor modules 2 arranged in a matrix.

[0066] FIG. 18 is a perspective view showing a semiconductor device 1D according to a fourth modification of the first embodiment. FIG. 18 shows the semiconductor device 1D and a heat sink 4D, which is a cooler. The heat sink 4D is fixed to the semiconductor device 1D. The semiconductor device 1D includes six semiconductor modules 2. The heat sink 4D has an L-shaped planar shape. The six semiconductor modules 2 are arranged in an L-shape to match the planar shape of the heat sink 4D. For example, the arrangement of multiple semiconductor modules 2, as in the semiconductor device 1D, may be determined according to the shape of an electrical device intended by a designer. In this way, a semiconductor device 1D can be realized in which multiple semiconductor modules 2 are arranged to match the shape desired for the electrical device.

[0067] Fig. 19 is a perspective view showing a semiconductor device 1E according to a fifth modification of the first embodiment. Fig. 19 shows the semiconductor device 1E and a heat sink 4E, which is a cooler. The heat sink 4E is fixed to the semiconductor device 1E. The semiconductor device 1E includes six semiconductor modules 2. The six semiconductor modules 2 are arranged to fit the planar shape of the heat sink 4E. The arrangement of the six semiconductor modules 2 in Fig. 19 is a further modification of the arrangement shown in Fig. 17 or the arrangement shown in Fig. 18.

[0068] For example, the arrangement of the plurality of semiconductor modules 2 may be determined as in the semiconductor device 1E according to the shape of the electrical equipment intended by the designer. In this way, the semiconductor device 1E in which the plurality of semiconductor modules 2 are arranged to match the desired shape of the electrical equipment can be realized.

[0069] As in each of the variations of the first embodiment, the semiconductor device 1A-1E can be configured according to the designer's intentions by arranging multiple semiconductor modules 2. This makes it possible to apply the semiconductor device 1A-1E to power conversion devices with various circuit types, such as three-phase inverters, single-phase inverters, choppers, and three-level inverters. By combining multiple semiconductor modules 2, the semiconductor device 1A-1E can also achieve functionality equivalent to that of a power module in which multiple semiconductor chips are mounted in a single package.

[0070] In the semiconductor device 1, 1A-1E described in the first embodiment, when a failure occurs in one of the plurality of semiconductor modules 2, only the failed semiconductor module 2 can be replaced. Therefore, according to the first embodiment, it is possible to reduce the repair costs of the semiconductor device 1, 1A-1E.

[0071] According to the first embodiment, each of the plurality of semiconductor modules 2 included in the semiconductor device 1, 1A-1E has a planar shape that has four corners and rotational symmetry. The first main electrode is extended from each of the first and second corners, which are opposed to each other, among the four corners. The second main electrode is extended from each of the third and fourth corners, which are the two corners other than the first and second corners. The semiconductor module 2 having such a configuration can change the arrangement of the first and second main electrodes in the semiconductor module 2 by rotating the semiconductor module 2 without changing the posture of the outer casing of the semiconductor module 2. Furthermore, the main electrodes 10 electrically connected between the semiconductor modules 2 can be selected with a high degree of freedom. As a result, the effect of allowing each of the plurality of semiconductor modules 2 to be arranged with a high degree of freedom is achieved.

[0072] The configurations described in the above embodiments are examples of the contents of the present disclosure. The configurations of the embodiments can be combined with other known technologies. Part of the configurations of the embodiments can be omitted or modified without departing from the gist of the present disclosure.

[0073] 1, 1A, 1B, 1C, 1D, 1E semiconductor device, 2 semiconductor module, 3 substrate, 4 cooler, 4A, 4B, 4C, 4D, 4E heat sink, 5 screw, 6 pin, 10 main electrode, 10a gate electrode, 10b collector electrode, 10c emitter electrode, 11 IGBT, 12 FWD, 13 base plate, 14 insulating substrate, 15 circuit pattern, 16 wire, 17 case, 18 lid, 19 sealing material, 21 groove, 22 notch, 23 recess, 24, 24a, 24b electrodes, 25 hole.

Claims

1. A semiconductor module comprising: a base plate having a first surface exposed to the outside of the semiconductor module and a second surface opposite to the first surface; an insulating substrate disposed on the second surface side and having a circuit pattern provided thereon; a semiconductor chip bonded to the circuit pattern; a sealing portion disposed on the second surface side and sealing the insulating substrate and the semiconductor chip; and a first main electrode and a second main electrode extending from inside the sealing portion in a direction opposite to a direction from the sealing portion toward the base plate; wherein the planar shape of the semiconductor module when viewed from a normal direction of the second surface has four corners and is a shape having rotational symmetry; and the first main electrode is extended from inside the sealing portion at each of a first corner and a second corner which are two of the four corners that face each other across the center of the planar shape; the second main electrode is drawn out from inside the sealing portion at each of a third corner and a fourth corner, which are the other two of the four corners other than the first corner and the second corner.

2. The semiconductor device according to claim 1, characterized in that the sealing portion has four side surfaces including a normal direction to the second surface, each of the four side surfaces has a groove formed thereon that is recessed toward the inside of the sealing portion and extends along a direction perpendicular to the normal direction to the second surface, and two adjacent semiconductor modules, a first semiconductor module and a second semiconductor module, are connected to each other by pins inserted into the grooves of the first semiconductor module and the grooves of the second semiconductor module.

3. The semiconductor device according to claim 1 or 2, characterized in that the outer edge of said base plate is formed with notches through which screws for fixing said base plate to a cooler can be passed.

4. A semiconductor device according to any one of claims 1 to 3, characterized in that each of the first main electrode and the second main electrode is electrically insulated from the base plate by the insulating substrate.

5. A semiconductor device according to any one of claims 1 to 4, characterized in that each of the first main electrode and the second main electrode extends in the normal direction of the second surface from a surface of the sealing portion opposite the base plate.

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