Upper-arm drive circuit

Abstract

The present invention prevents malfunction of an upper-arm switching element due to the output of a power conversion circuit having a negative potential and undershooting.　This upper-arm drive circuit comprises: a first switching element SW1 connected between a gate of an upper-arm switching element Q1 and a reference potential terminal; a second switching element SW2 having a drain connected to the gate of the first switching element SW1; and a potential control circuit 4. In at least a first period T1 in which the reference potential terminal of the upper-arm switching element Q1 has a negative potential and undershoots UND, the potential control circuit 4 controls the potential of a source of the second switching element SW2 to a first potential V1 at which the first switching element SW1 can be maintained to be ON even if the second switching element SW2 is turned ON due to a malfunction. In a subsequent second period T2, the potential control circuit 4 controls the potential of the source of the second switching element SW2 to a second potential V2 which is lower than the first potential V1 and at which the first switching element SW1 can be turned OFF when the second switching element SW2 is turned ON.

Description

Upper arm drive circuit

[0001] The present invention relates to an upper arm driver circuit.

[0002] With the rise in global awareness of environmental conservation, the demand for energy conservation has increased further, and power conversion devices (inverters) are widely adopted in various fields. For power conversion devices installed in the drive systems of railway vehicles, air conditioners, etc., high reliability, as well as high performance and efficiency, are becoming important issues.

[0003] A typical power conversion device includes a power conversion circuit configured as a bridge circuit having upper and lower arms each made up of a switching element and a freewheeling diode connected in antiparallel to the switching element, an upper arm drive circuit that drives and controls the switching element of the upper arm, and a lower arm drive circuit that drives and controls the switching element of the lower arm.

[0004] An example of technology related to upper arm driver circuits is Patent Document 1. Figure 2A and the abstract of Patent Document 1 state that "an upper arm driver circuit is provided that, in a power conversion device having a bridge circuit composed of upper and lower arms, can stably control the upper arm without malfunctioning even when the output of the power conversion device becomes negative potential," and that "an upper arm driver circuit that drives and controls an upper arm switching element of a power conversion device includes an upper arm gate voltage output wiring connected to the gate of the upper arm switching element, a first upper arm driver circuit reference potential wiring, an upper arm gate voltage reference potential wiring connected to an inverter output of the power conversion device, and an upper arm driver circuit reference potential wiring potential control circuit that controls the first upper arm driver circuit reference potential wiring to a potential lower than the reference potential when the inverter output is equal to or lower than a predetermined potential lower than the reference potential, and the first upper arm driver circuit reference potential wiring is connected to the reference potential via the upper arm driver circuit reference potential wiring potential control circuit."

[0005] Japanese Patent Application Laid-Open No. 2022-146525

[0006] In Patent Document 1, when the inverter output of the power conversion device becomes negative potential, the upper arm drive circuit reference potential wiring (12) is immediately controlled to become negative potential.

[0007] For example, in FIG. 2A of Patent Document 1, when the inverter output (8) is negative, the upper arm drive circuit reference potential wiring (12) is the same as the inverter output (8). In this state, to prevent the upper arm IGBT (2) from malfunctioning and turning on, the upper arm drive MOSFET (10) must be on and the upper arm drive MOSFET (9) must be off. However, the upper arm drive MOSFET (10) has a weak ability to maintain its on state, and if noise is introduced, the upper arm drive MOSFET (9) may malfunction and turn on, causing the gate charge of the upper arm drive MOSFET (10) to drain and turn off. As a result, the gate charge of the upper arm IGBT (2) cannot be drained, and if noise or other factors are introduced into the gate of the upper arm IGBT (2) in this state, the upper arm IGBT (2) may malfunction and turn on.

[0008] In particular, immediately after the upper arm IGBT (2) is turned off, the inverter output (8) becomes negative potential and an undershoot occurs. During the period in which the undershoot occurs, that is, the period from when the undershoot starts to when it ends and the negative potential of the steady state is reached, noise that turns off the upper arm drive MOSFET (10) is likely to occur, and there is a problem in that the upper arm IGBT (2) is likely to malfunction.

[0009] An object of the present invention is to provide an upper arm driver circuit that can prevent malfunction of an upper arm switching element caused by the output of a power conversion circuit being at a negative potential and undershooting.

[0010] In order to solve the above-mentioned problems, an upper arm drive circuit of the present invention is an upper arm drive circuit for driving an upper arm switching element of a power conversion circuit, and includes: a first switching element having a drain connected to a gate of the upper arm switching element and a source connected to a reference potential terminal of the upper arm switching element; a second switching element having a drain connected to the gate of the first switching element; and a potential control circuit connected to a reference potential, the reference potential terminal of the upper arm switching element, and a source of the second switching element, and controlling the potential of the source of the second switching element; In a first period from immediately after the upper arm switching element is turned off and including at least the time when the reference potential terminal of the upper arm switching element is at a negative potential and the undershoot ends, the potential of the source of the second switching element is controlled to a first potential at which the first switching element can remain on even if the second switching element is turned on due to a malfunction, and in a second period from the end of the first period to before the upper arm switching element is turned on, the potential of the source of the second switching element is controlled to a second potential that is lower than the first potential and can turn off the first switching element when the second switching element is turned on.

[0011] The upper arm driver circuit of the present invention can prevent malfunction of the upper arm switching element caused by the output of the power conversion circuit being at a negative potential and undershooting.

[0012] 1 is a circuit diagram showing a schematic configuration of an upper arm drive circuit of Example 1. 2 is a timing chart illustrating the operation of the upper arm drive circuit of Example 1. 3 is a circuit diagram illustrating the operation of the upper arm drive circuit of Example 1 in a first period. 4 is a circuit diagram illustrating the operation of the upper arm drive circuit of Example 1 in a second period. 5 is a circuit diagram illustrating the operation of the upper arm drive circuit of Example 1 in a third period. 6 is a circuit diagram illustrating the operation of the upper arm drive circuit of Example 1 in a fourth period. 7 is a circuit diagram showing a schematic configuration of an upper arm drive circuit of Example 2. 8 is a circuit diagram showing a schematic configuration of an upper arm drive circuit of Example 3. 9 is a circuit diagram showing a schematic configuration of an upper arm drive circuit of Example 4.

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0014] FIG. 1 is a circuit diagram showing a schematic configuration of an upper arm driver circuit according to a first embodiment.

[0015] The power conversion device 3 has an upper arm drive circuit 1, a power conversion circuit 2, and a lower arm drive circuit (not shown).

[0016] The power conversion circuit 2 includes an upper-arm switching element Q1 and a lower-arm switching element Q2 connected in series between a DC power supply potential VDC and a reference potential GND, an upper-arm freewheeling diode DQ1 connected in anti-parallel to the upper-arm switching element Q1, and a lower-arm freewheeling diode DQ2 connected in anti-parallel to the lower-arm switching element Q2. An AC output of the power conversion circuit 2 is output to an output terminal OUT from a connection node between the upper-arm switching element Q1 and the lower-arm switching element Q2.

[0017] The upper-arm switching element Q1 and the lower-arm switching element Q2 may be, for example, an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET). When a MOSFET is used, the body diode built into the MOSFET may be used as the upper-arm freewheel diode DQ1 and the lower-arm freewheel diode DQ2. In this embodiment, an example will be described in which the upper-arm switching element Q1 and the lower-arm switching element Q2 are N-type switching elements. The reference potential GND is, for example, a ground potential, but is not limited to this.

[0018] The upper arm driver circuit 1 is a driver circuit that drives the upper arm switching element Q1, and the lower arm driver circuit (not shown) is a driver circuit that drives the lower arm switching element Q2.

[0019] The upper arm driver circuit 1 of this embodiment includes a first switching element SW1, a second switching element SW2, and a potential control circuit 4.

[0020] The drain of the first switching element SW1 is connected to the gate of the upper-arm switching element Q1, and the source is connected to the reference potential terminal of the upper-arm switching element Q1. By turning on the first switching element SW1, the gate of the upper-arm switching element Q1 and the reference potential terminal are shorted, and charge can be extracted from the gate of the upper-arm switching element Q1. For example, an N-type MOSFET can be used as the first switching element SW1.

[0021] The drain of the second switching element SW2 is connected to the gate of the first switching element SW1. As the second switching element SW2, for example, an N-type MOSFET can be used.

[0022] The potential control circuit 4 is connected to a reference potential GND, the reference potential terminal of the upper-arm switching element Q1, and the source of the second switching element SW2, and controls the potential of the source of the second switching element SW2. The reference potential GND is, for example, ground potential, but is not limited to this. The reference potential GND of the upper-arm driver circuit 1 may be the same as or different from the reference potential GND of the power conversion circuit 2.

[0023] The potential control circuit 4 of this embodiment is an example having a first circuit 5 provided between the reference potential GND and the source of the second switching element SW2, and a second circuit 6 provided between the reference potential terminal of the upper arm switching element Q1 and the source of the second switching element SW2.

[0024] The first circuit 5 of this embodiment shows an example having a third switching element SW3 that turns on and off between the reference potential GND and the source of the second switching element SW2, and a first diode D1 that is connected in parallel to the third switching element SW3, has a cathode connected to the reference potential GND, and an anode connected to the source of the second switching element SW2.

[0025] The second circuit 6 of this embodiment shows an example having a second diode D2 whose cathode is connected to the reference potential terminal of the upper arm switching element Q1 and whose anode is connected to the source of the second switching element SW2, and a first resistor R1 connected in series with the second diode D2.

[0026] The connection node N is a connection node between the reference potential GND, the reference potential terminal of the upper arm switching element Q1, and the source of the second switching element SW2.

[0027] The upper-arm driver circuit 1 of this embodiment preferably also includes a second resistor R2 connected to the gate of the upper-arm switching element Q1 and a Zener diode ZD having a cathode connected to the gate of the upper-arm switching element Q1 and an anode connected to the reference potential terminal of the upper-arm switching element Q1. The second resistor R2 serves as a gate resistor for the upper-arm switching element Q1. The second resistor R2 is connected between the gate of the upper-arm switching element Q1 and a gate drive circuit (not shown) that applies an ON signal to the gate of the upper-arm switching element Q1. While FIG. 1 illustrates an example in which the second resistor R2 is connected to the right of the drain of the first switching element SW1 (the side closer to the gate of the upper-arm switching element Q1), this is not limiting and the second resistor R2 may also be connected to the left of the drain of the first switching element SW1. The Zener diode ZD limits the voltage between the gate of the upper-arm switching element Q1 and the reference potential terminal to protect the upper-arm switching element Q1.

[0028] The upper arm driver circuit 1 of this embodiment preferably further includes a third diode D3 having a cathode connected to the gate of the first switching element SW1 and an anode connected to the source of the first switching element SW1.

[0029] The upper arm driver circuit 1 of this embodiment preferably further includes a third resistor R3 connected between the source of the second switching element SW2 and the potential control circuit 4. The location of the third resistor R3 is not limited thereto, and it may be located in another position.

[0030] The upper arm driver circuit 1 of this embodiment also includes a gate driver circuit (not shown) that applies an ON signal to the gate of the upper arm switching element Q1, a control circuit (not shown) that controls the operation of the first switching element SW1, a control circuit (not shown) that controls the operation of the second switching element SW2, a control circuit (not shown) that controls the operation of the third switching element SW3, and a discharge circuit (not shown) that extracts charge from the gate of the upper arm switching element Q1, but detailed description thereof will be omitted.

[0031] 2 is a timing chart illustrating the operation of the upper arm driver circuit of Example 1. In FIG. 2, the horizontal axis represents time t.

[0032] In Fig. 2, Q1 indicates the on / off state of the upper-arm switching element Q1. Note that there is a delay time between when an on signal or an off signal is applied to the gate of the upper-arm switching element Q1 and when the upper-arm switching element Q1 actually turns on or off. Fig. 2 shows the timing when the upper-arm switching element Q1 actually turns on or off, rather than the timing of the on signal or off signal.

[0033] In FIG. 2 , OUT indicates the potential of the output terminal OUT of the power conversion circuit 2, with the vertical axis representing potential V. GND indicates the potential of the reference potential GND, which is, for example, 0 V in this embodiment. The output terminal OUT of the power conversion circuit 2 is connected to the reference potential terminal of the upper-arm switching element Q1 and the source of the first switching element SW1, so these have the same potential. The output of the power conversion circuit 2 (and the potential of the reference potential terminal of the upper-arm switching element Q1) is assumed to be positive while the upper-arm switching element Q1 is on and negative while the upper-arm switching element Q1 is off. Furthermore, the following description assumes that an undershoot UND occurs immediately after the upper-arm switching element Q1 is turned off, and that the potential remains steady and negative after the undershoot UND ends. In particular, noise is likely to occur during the undershoot UND, which can easily cause malfunctions of the switching elements.

[0034] 2 , N indicates the potential of the connection node N, and the vertical axis represents potential V. In this embodiment, the potential of the connection node N is described as being approximately the same as the potential of the source of the second switching element SW2. The potential of the connection node N is a first potential V1 during the first period T1, the third period T3, and the fourth period T4, and is a second potential V2 lower than the first potential V1 during the second period T2. The first potential V1 is approximately the same as the potential of the reference potential GND, and the second potential V2 is approximately the same as the negative potential of the output of the power conversion circuit 2.

[0035] In FIG. 2, SW3 indicates the on / off state of the third switching element SW3, which is on during the first period T1 and the fourth period T4, and off during the second period T2 and the third period T3.

[0036] The potential control circuit 4 of this embodiment controls the potential of the source of the second switching element SW2 to a first potential V1 at which the first switching element SW1 can remain on even if the second switching element SW2 malfunctions and turns on during a first period T1 that begins immediately after the upper-arm switching element Q1 is turned off and includes at least the time when the reference potential terminal of the upper-arm switching element Q1 is at a negative potential and the undershoot UND ends, and controls the potential of the source of the second switching element SW2 to a second potential V2 that is lower than the first potential V1 and that can turn off the first switching element SW1 when the second switching element SW2 is turned on during a second period T2 that begins immediately after the upper-arm switching element Q1 is turned off and includes at least the time when the reference potential terminal of the upper-arm switching element Q1 is at a negative potential and the undershoot UND ends.

[0037] It is desirable that the first period T1 be longer than the second period T2, thereby making it possible to lengthen the first period T1, which can prevent malfunction due to noise.

[0038] Furthermore, the second period T2 is preferably a period equal to or longer than the delay time between when an ON signal is applied to the gate of the upper-arm switching element Q1 from a gate drive circuit (not shown) and when the upper-arm switching element Q1 is turned on. In order to lengthen the first period T1, it is preferable to switch to the second period T2 immediately before turning on the upper-arm switching element Q1. If the second period T2 is set to be the same as the delay time, the first period T1 can be lengthened. If the second period T2 is set to be longer than the delay time, the first period T1 will be shortened, but variations in the delay time can be accommodated.

[0039] Next, specific operations will be described with reference to FIGS.

[0040] FIG. 3 is a circuit diagram illustrating the operation of the upper arm driver circuit of the first embodiment in the first period.

[0041] During the first period T1, as shown in FIG. 3, the upper arm switching element Q1 is in an off state, the first switching element SW1 is on, the second switching element SW2 is off, and the third switching element SW3 is on.

[0042] Since the output of the power conversion circuit 2 is at a negative potential, a current i flows from the reference potential GND via the third switching element SW3, the first resistor R1, and the second diode D2. At this time, the potential of the connection node N is the first potential V1, which is approximately the same as the potential of the reference potential GND. In the second circuit 6 of this embodiment, the forward voltage of the second diode D2 alone cannot cover the potential difference between the potential of the reference potential GND and the potential of the output of the power conversion circuit 2, so the first resistor R1 is provided to share the potential difference.

[0043] Now, consider a case where noise occurs during the undershoot UND, causing the second switching element SW2 to malfunction and turn on. In this case, the second switching element SW2 turns on and becomes conductive, so the gate of the first switching element SW1 also becomes the first potential V1. At this time, the output of the power conversion circuit 2 is at a negative potential, so the gate of the first switching element SW1 has a higher potential than the source. Therefore, even if the second switching element SW2 malfunctions and turns on, the first switching element SW1 can remain on. The first potential V1 must be a potential that allows the first switching element SW1 to remain on even if the second switching element SW2 malfunctions and turns on. Therefore, it is sufficient for the first potential V1 to be at least a potential higher than the negative potential of the output of the power conversion circuit 2 by the threshold value of the first switching element SW1.

[0044] Furthermore, since the first switching element SW1 remains on, the short circuit between the gate of the upper arm switching element Q1 and the reference potential terminal is maintained, and even if noise occurs and enters the gate of the upper arm switching element Q1, the charge on the gate of the upper arm switching element Q1 can be extracted via the first switching element SW1, thereby preventing the upper arm switching element Q1 from malfunctioning and turning on.

[0045] FIG. 4 is a circuit diagram illustrating the operation of the upper arm driver circuit of the first embodiment in the second period.

[0046] In the second period T2, as shown in FIG. 4, the upper arm switching element Q1 is changed from OFF to ON (turned ON).

[0047] To achieve this, the third switching element SW3 is turned off. Because the output of the power conversion circuit 2 is at a negative potential, the potential of the connection node N becomes substantially equal to the negative potential of the output of the power conversion circuit 2 via the second diode D2. This allows the potential of the source of the second switching element SW2 to be set to a second potential V2 that is lower than the first potential V1 and that can turn off the first switching element SW1 when the second switching element SW2 is turned on. To turn off the first switching element SW1, the second potential V2 is set so that the potential of the gate of the first switching element SW1 is lower than the potential obtained by adding the negative potential of the output of the power conversion circuit 2 to the threshold of the first switching element SW1.

[0048] Then, a control circuit (not shown) switches the second switching element SW2 from off to on, causing it to conduct. Since the output of the power conversion circuit 2 is at a negative potential, charge is extracted from the gate of the first switching element SW1, causing a current i to flow through the path shown in Figure 4, turning off the first switching element SW1 (from on to off).

[0049] An on signal is applied to the gate of the upper arm switching element Q1 from a gate drive circuit (not shown). When the first switching element SW1 is turned off, the first switching element SW1 becomes non-conductive, and the potential between the reference potential terminal and gate of the upper arm switching element Q1 becomes equal to or greater than the threshold, turning on the upper arm switching element Q1.

[0050] The reason why the third switching element SW3 is turned off in the second period T2 is that if the third switching element SW3 remains on and the potential of the connection node N remains at the first potential V1, as explained in FIG. 3, the first switching element SW1 will remain on even if the second switching element SW2 is turned on, and the upper arm switching element Q1 cannot be turned on even if an on signal is applied to the gate of the upper arm switching element Q1.

[0051] FIG. 5 is a circuit diagram illustrating the operation of the upper arm driver circuit of the first embodiment in the third period.

[0052] 5, in the third period T3, the upper arm switching element Q1 is on, the potential of the output of the power conversion circuit 2 is positive, the first switching element SW1 is off, the second switching element SW2 is on, and the third switching element SW3 is off. At this time, the current i from the output of the power conversion circuit 2 flows to the reference potential GND via the third diode D3, the second switching element SW2, the third resistor R3, the connection node N, and the first diode D1 along the path shown in FIG.

[0053] If the third resistor R3 were not provided, a nearly short-circuit state would occur, which would cause a problem of burning out the first diode D1, the second switching element SW2, and the third diode D3, which are elements on the path of the current i, and especially the second switching element SW2. In contrast, in this embodiment, the third resistor R3 prevents these elements from burning out, and reduces the current i that steadily flows while the upper-arm switching element Q1 is on, thereby reducing power consumption.

[0054] Furthermore, in the state of FIG. 5, current i flows through the third diode D3, causing the source of the first switching element SW1 to have a higher potential than the gate, and a reverse bias can be created between the gate and source of the first switching element SW1 by the amount of the forward voltage of the third diode D3, so that the first switching element SW1 can be reliably kept in the off state.

[0055] FIG. 6 is a circuit diagram illustrating the operation of the upper arm driver circuit of the first embodiment in the fourth period.

[0056] 6, in order to turn off the upper-arm switching element Q1, a discharge circuit (not shown) draws charge from the gate of the upper-arm switching element Q1, thereby turning off the upper-arm switching element Q1. Also, a control circuit (not shown) turns off the second switching element SW2 and turns on the first switching element SW1, thereby maintaining the upper-arm switching element Q1 in an off state.

[0057] As described above, the upper arm driver circuit 1 of the embodiment can prevent the upper arm switching element from malfunctioning due to the output of the power conversion circuit 2 being at a negative potential and undershooting.

[0058] Note that a signal having the reverse logic to the ON or OFF signal applied to the gate of the upper-arm switching element Q1 may be used as the signal for turning on or off the third switching element SW3, thereby simplifying the configuration of a control circuit (not shown) for controlling the operation of the third switching element SW3.

[0059] FIG. 7 is a circuit diagram showing a schematic configuration of an upper arm driver circuit according to the second embodiment.

[0060] The second embodiment is a modification of the first embodiment, in which the third switching element SW3 in the first circuit 5 is a MOSFET, and the first diode D1 is configured as a body diode built into the MOSFET. For example, an N-type MOSFET can be used as the third switching element SW3.

[0061] According to this embodiment, the first circuit 5 can be configured simply.

[0062] FIG. 8 is a circuit diagram showing a schematic configuration of an upper arm driver circuit according to the third embodiment.

[0063] Example 3 is a modified example of Example 1, in which the second circuit 6 has a fourth switching element SW4 that turns on and off between the reference potential terminal of the upper arm switching element Q1 and the source of the second switching element SW2.

[0064] The fourth switching element SW4 may be operated in the opposite logic to that of the third switching element SW3.

[0065] FIG. 9 is a circuit diagram showing a schematic configuration of an upper arm driver circuit according to a fourth embodiment.

[0066] Example 4 is a modification of Example 1. The potential control circuit 4 of this example includes a fifth switching element SW5 that selectively switches on either the connection between the source of the second switching element SW2 and the reference potential GND or the connection between the source of the second switching element SW2 and the reference potential terminal of the upper-arm switching element Q1, and a first diode D1 that is connected in parallel to the fifth switching element SW5, has a cathode connected to the reference potential GND, and an anode connected to the source of the second switching element SW2.

[0067] This embodiment corresponds to an embodiment in which the third switching element SW3 and the fourth switching element SW4 of the third embodiment are combined into one fifth switching element SW5.

[0068] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied.

[0069] 1: upper arm drive circuit, 2: power conversion circuit, 3: power conversion device, 4: potential control circuit, 5: first circuit, 6: second circuit, SW1: first switching element, SW2: second switching element, SW3: third switching element, SW4: fourth switching element, D1: first diode, D2: second diode, D3: third diode, ZD: Zener diode, R1: first resistor, R2: second resistor, R3: third resistor, N: connection node, Q1: upper arm switching element, Q2: lower arm switching element, DQ1: upper arm freewheel diode, DQ2: lower arm freewheel diode, VDC: DC power supply potential, OUT: output terminal, GND: reference potential, UND: undershoot, t: time, T1: first period, T2: second period, T3: third period, T4: fourth period, V: potential, V1: first potential, V2: second potential, i: current

Claims

1. An upper arm drive circuit for driving an upper arm switching element of a power conversion circuit, comprising: a first switching element having a drain connected to a gate of the upper arm switching element and a source connected to a reference potential terminal of the upper arm switching element; a second switching element having a drain connected to the gate of the first switching element; and a potential control circuit connected to a reference potential, the reference potential terminal of the upper arm switching element, and a source of the second switching element, for controlling the potential of the source of the second switching element; the potential control circuit controls the potential of the source of the second switching element to a first potential at which the first switching element can remain on even if the second switching element is turned on due to a malfunction, during a first period from immediately after the upper arm switching element is turned off and including at least the time when the reference potential terminal of the upper arm switching element is at a negative potential and an undershoot ends, and controls the potential of the source of the second switching element to a second potential that is lower than the first potential and at which the first switching element can be turned off when the second switching element is turned on, during a second period from the end of the first period to before the upper arm switching element is turned on.

2. The upper arm drive circuit according to claim 1, wherein the first period is longer than the second period.

3. An upper arm drive circuit as claimed in claim 1, further comprising a gate drive circuit which applies an ON signal or OFF signal to the gate of said upper arm switching element, and said second period is equal to or longer than the delay time from when an ON signal is applied to the gate of said upper arm switching element until said upper arm switching element turns ON.

4. An upper arm drive circuit according to claim 1, characterized in that the potential control circuit has a first circuit provided between the reference potential and the source of the second switching element, and a second circuit provided between the reference potential terminal of the upper arm switching element and the source of the second switching element.

5. An upper arm drive circuit according to claim 4, characterized in that the first circuit comprises a third switching element which switches on and off between the reference potential and the source of the second switching element, and a first diode which is connected in parallel to the third switching element, the cathode of which is connected to the reference potential, and the anode of which is connected to the source of the second switching element.

6. An upper arm driver circuit according to claim 5, wherein the third switching element is a MOSFET, and the first diode is a body diode built into the MOSFET.

7. An upper arm drive circuit according to claim 4, characterized in that the second circuit comprises a second diode having a cathode connected to the reference potential terminal of the upper arm switching element and an anode connected to the source of the second switching element, and a first resistor connected in series with the second diode.

8. An upper arm drive circuit according to claim 4, characterized in that the second circuit has a fourth switching element which turns on and off between the reference potential terminal of the upper arm switching element and the source of the second switching element.

9. An upper arm drive circuit according to claim 1, characterized in that the potential control circuit comprises: a fifth switching element which selectively switches on between the source of the second switching element and the reference potential or between the source of the second switching element and the reference potential terminal of the upper arm switching element; and a first diode connected in parallel to the fifth switching element, with a cathode connected to the reference potential and an anode connected to the source of the second switching element.

10. An upper arm drive circuit according to claim 1, further comprising: a second resistor connected to the gate of the upper arm switching element; and a Zener diode having a cathode connected to the gate of the upper arm switching element and an anode connected to the reference potential terminal of the upper arm switching element.

11. The upper arm drive circuit according to claim 1, further comprising a third diode having a cathode connected to the gate of the first switching element and an anode connected to the source of the first switching element.

12. The upper arm driver circuit according to claim 1, further comprising a third resistor connected between the source of said second switching element and said potential control circuit.

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