Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device includes: a chip that is formed of a wide bandgap semiconductor and that has a main surface on which a semiconductor region of a first conductivity type is formed; a base impurity region of a second conductivity type formed in a surface layer part of the semiconductor region; a first impurity region formed in a surface layer part of the base impurity region; and a second impurity region that is adjacent to the first impurity region in a first direction and that has a conductivity type opposite to that of the first impurity region formed in the surface layer part of the base impurity region. The second impurity region has a protrusion part that is formed in a band shape extending in a second direction orthogonal to the first direction and that selectively protrudes to the first impurity region in the first direction.

Description

Semiconductor device and method for manufacturing the same Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2023-099595 filed with the Japan Patent Office on June 16, 2023, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0003] Patent Document 1 describes － A plurality of p-type body regions are formed on the surface of a SiC semiconductor layer, each constituting a unit cell, an n-type source region formed inside the p-type body region, a gate electrode facing the p-type body region via a gate insulating film, and n-type gate electrodes formed adjacent to each other on the back surface of the SiC semiconductor layer. ＋ type drain region and p ＋ a p-type collector region, a p-type body region, and a ＋ between the n-type drain region － and a p-type drift region. ＋ The present invention discloses a SiC semiconductor device in which the collector region is formed so as to cover a region including at least two unit cells in the X-axis along the surface of the SiC semiconductor layer.

[0004] JP 2015-207588 A

[0005] An embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof that can form impurity regions with high precision even in a fine pattern.

[0006] One embodiment of the present disclosure provides a semiconductor device including: a chip formed of a wide bandgap semiconductor and having a main surface on which a semiconductor region of a first conductivity type is formed; a base impurity region of a second conductivity type formed in a surface layer portion of the semiconductor region; a first impurity region formed in the surface layer portion of the base impurity region; and a second impurity region of an opposite conductivity type to the first impurity region formed in the surface layer portion of the base impurity region, the second impurity region being adjacent to the first impurity region in a first direction, wherein the second impurity region is formed in a strip shape extending in a second direction perpendicular to the first direction, and has a protrusion that protrudes selectively into the first impurity region in the first direction.

[0007] One embodiment of the present disclosure provides a method for forming a semiconductor device, comprising the steps of: preparing a wafer formed of a wide bandgap semiconductor and having a main surface on which a semiconductor region of a first conductivity type is formed; selectively injecting a second conductivity type impurity into the semiconductor region to selectively form a plurality of body regions spaced apart in a first direction in a surface layer portion of the semiconductor region; and forming a first mask to selectively cover each of the body regions, the first mask including a first portion extending in a second direction perpendicular to the first direction and having a first width in the first direction, and a pair of protrusions protruding from a center of the first portion in the second direction to both sides in the first direction; and injecting the first conductivity type impurity into the body region through the first mask. forming a first impurity region in a surface layer portion of the body region by implanting a second conductivity type impurity into the contact pattern region through the second mask, thereby forming a gate electrode that covers a channel formed in a region between the semiconductor region and the first impurity region in the surface layer portion of the body region.

[0008] According to the semiconductor device and the manufacturing method thereof according to an embodiment of the present disclosure, it is possible to form impurity regions with high precision even in fine patterns.

[0009] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example layout of a first main surface. FIG. 4 is an enlarged plan view showing a main portion of the first main surface. FIG. 5 is an enlarged plan view showing further main portions of the first main surface. FIG. 6 is an enlarged plan view showing a main portion of FIG. 5 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5 . FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 5 . FIG. 10 is a cross-sectional view taken along line XX in FIG. 5 . FIG. 11 is a schematic diagram showing a wafer. FIG. 12A is a cross-sectional view showing a method for manufacturing a semiconductor device. FIG. 12B is a cross-sectional view showing a process subsequent to FIG. 12A . FIG. 12C is a cross-sectional view showing a process subsequent to FIG. 12B . FIG. 12D is a cross-sectional view showing a process subsequent to FIG. 12C . FIG. 12E is a cross-sectional view showing a process subsequent to FIG. 12D . 12F is a cross-sectional view showing a step after FIG. 12E. FIG. 12G is a cross-sectional view showing a step after FIG. 12F. FIG. 12H is a cross-sectional view showing a step after FIG. 12G. FIG. 12I is a cross-sectional view showing a step after FIG. 12H. FIG. 12J is a cross-sectional view showing a step after FIG. 12I. FIG. 12K is a cross-sectional view showing a step after FIG. 12J. FIG. 12L is a cross-sectional view showing a step after FIG. 12K. FIG. 12M is a cross-sectional view showing a step after FIG. 12L. FIG. 12N is a cross-sectional view showing a step after FIG. 12M. FIG. 12O is a cross-sectional view showing a step after FIG. 12N. FIG. 12P is a cross-sectional view showing a step after FIG. 12O. FIG. 13 is a diagram showing a plane pattern of the first mask shown in FIG. 12G. FIG. 14 is a cross-sectional view showing modified examples of the source region and body contact region of FIG. 6. FIG. 15 is a diagram showing a first modified example of the body contact region. FIG. 16 is a diagram showing a second modified example of the body contact region. 17, 18, and 19 are diagrams illustrating a third, fourth, and fifth modified examples of the body contact region, respectively.

[0010] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0011] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0012] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0013] Fig. 1 is a plan view showing a semiconductor device 1 according to an embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a first main surface 3. Fig. 4 is an enlarged plan view showing a main portion of the first main surface 3. Fig. 5 is an enlarged plan view showing further main portions of the first main surface 3.

[0014] Fig. 6 is an enlarged plan view showing a main part of Fig. 5. Fig. 7 is a cross-sectional view taken along line VII-VII shown in Fig. 5. Fig. 8 is a cross-sectional view taken along line VIII-VIII shown in Fig. 5. Fig. 9 is a cross-sectional view taken along line IX-IX shown in Fig. 5. Fig. 10 is a cross-sectional view taken along line XX shown in Fig. 5.

[0015] 1 to 10, semiconductor device 1 is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a vertical structure. Semiconductor device 1 is a SiC semiconductor device having a chip 2 including a SiC single crystal. Chip 2 may be referred to as a "SiC chip" or a "semiconductor chip."

[0016] In this embodiment, the chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 is made of 4H-SiC single crystal, but the chip 2 may be made of another polytype.

[0017] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0018] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0019] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0020] In the following description, one side of the first direction X refers to the third side surface 5C side, and the other side of the first direction X refers to the fourth side surface 5D side. Furthermore, one side of the second direction Y refers to the first side surface 5A side, and the other side of the second direction Y refers to the second side surface 5B side. In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0021] The chip 2 (first main surface 3 and second main surface 4) has an off-axis angle inclined at a predetermined angle in a predetermined off-axis direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off-axis direction by the off-axis angle. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off-axis angle.

[0022] The off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0023] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0024] The semiconductor device 1 includes an n-type first semiconductor region 6 formed in a region (surface layer portion) on the first main surface 3 side of the chip 2. The first semiconductor region 6 may also be referred to as a "drift region," a "drain drift region," a "drain region," or the like. A drain potential as a high potential (first potential) is applied to the first semiconductor region 6. The first semiconductor region 6 is formed in a layer shape extending along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer).

[0025] The semiconductor device 1 includes an n-type second semiconductor region 7 formed in a region (surface layer) on the second main surface 4 side within the chip 2. A drain potential is applied to the second semiconductor region 7. The second semiconductor region 7 may also be referred to as a "drain region," etc. The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6, and is electrically connected to the first semiconductor region 6 within the chip 2.

[0026] The second semiconductor region 7 is formed in a layer shape extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 7 is made of a semiconductor substrate (specifically, a SiC substrate). That is, the chip 2 has a layered structure including a semiconductor substrate and an epitaxial layer. The second semiconductor region 7 has a thickness greater than that of the first semiconductor region 6.

[0027] The semiconductor device 1 includes an active region 8 set in a chip 2. The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 8 is set in an inner portion of the chip 2 and spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 8 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar area of ​​the active region 8 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0028] The semiconductor device 1 includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is provided in a region between the periphery of the chip 2 and the active region 8 in a plan view. The peripheral region 9 extends in a strip shape along the active region 8 in a plan view, and is set in a polygonal ring shape (a square ring in this embodiment) surrounding the active region 8.

[0029] The semiconductor device 1 includes a plurality of p-type body regions 20 formed in a surface layer portion of the first main surface 3 in the active region 8. A source potential is applied to the plurality of body regions 20 as a low potential (second potential) different from a high potential (first potential). The plurality of body regions 20 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of body regions 20 are arranged in a strip shape extending in the second direction Y.

[0030] The plurality of body regions 20 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The plurality of body regions 20 are preferably formed at intervals from the middle of the first semiconductor region 6 toward the first main surface 3. The plurality of body regions 20 are exposed from the first main surface 3.

[0031] The semiconductor device 1 includes a p-type outer body region 21 formed in the peripheral region 9 in a surface layer portion of the first main surface 3. The outer body region 21 preferably has a p-type impurity concentration substantially equal to the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the outer body region 21 may be lower than the p-type impurity concentration of the body region 20, or may be higher than the p-type impurity concentration of the body region 20.

[0032] The outer body region 21 is formed at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) toward the active region 8, and extends in a strip shape along the active region 8. The outer body region 21 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions.

[0033] In this embodiment, the outer body region 21 surrounds the active region 8 in a plan view and is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. In other words, the outer body region 21 forms the boundary between the active region 8 and the outer peripheral region 9. The outer body region 21 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4 ).

[0034] The outer body region 21 has an inner edge portion on the active region 8 side and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer body region 21 is connected to the plurality of body regions 20 in a portion extending in the first direction X. As a result, the outer body region 21 is fixed to the same potential as the plurality of body regions 20.

[0035] The outer body region 21 preferably has a width greater than that of the body region 20. The width of the body region 20 is the width in a direction perpendicular to the extending direction (i.e., the first direction X). The width of the outer body region 21 is the width in a direction perpendicular to the extending direction. Of course, the width of the outer body region 21 may be approximately equal to the width of the body region 20 or may be less than the thickness of the body region 20.

[0036] The ratio of the width of the outer body region 21 to the width of the body region 20 may be 10 or greater and 50 or less. The width ratio is preferably 20 or greater and 40 or less.

[0037] The outer body region 21 is formed at a distance from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 across a part of the first semiconductor region 6. The outer body region 21 is preferably formed at a distance from the middle of the first semiconductor region 6 toward the first main surface 3. The outer body region 21 is exposed from the first main surface 3.

[0038] The outer body region 21 preferably has a thickness (depth) approximately equal to the thickness (depth) of the body region 20. Of course, the thickness of the outer body region 21 may be less than the thickness of the body region 20 or may be greater than the thickness of the body region 20.

[0039] 6 to 9 , semiconductor device 1 includes a plurality of n-type surface drift regions 22 formed in a surface portion of first main surface 3. In this embodiment, each of the plurality of surface drift regions 22 is made of a part of first semiconductor region 6. Of course, the plurality of surface drift regions 22 may have an n-type impurity concentration higher than the n-type impurity concentration of first semiconductor region 6, or may have an n-type impurity concentration lower than the n-type impurity concentration of first semiconductor region 6.

[0040] The surface drift regions 22 are each defined in a region between adjacent body regions 20 in the first direction X. Specifically, the surface drift regions 22 are each defined by the body regions 20 and the outer body regions 21 in the surface portion of the first main surface 3. The surface drift regions 22 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y. In other words, the surface drift regions 22 are formed in a stripe shape extending in the second direction Y.

[0041] The semiconductor device 1 includes n-type source regions 23 formed in the surface layer portions of the plurality of body regions 20. The source regions 23 have an n-type impurity concentration higher than the n-type impurity concentration of the first semiconductor region 6. A source potential is applied to the source regions 23.

[0042] The semiconductor device 1 includes a plurality of p-type contact regions 25 formed in the surface layer portions of the plurality of body regions 20 in the active region 8. The contact regions 25 may also be referred to as "back gate regions." A source potential is applied to the plurality of contact regions 25. The contact regions 25 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.

[0043] 5 and 6 , each body region 20 has a plurality of first sections 10 and a plurality of second sections 11 alternately arranged in the second direction Y. A clear boundary between the first sections 10 and the second sections 11 need not be formed. For clarity, in FIGS. 5 and 6 , the boundary between the first sections 10 and the second sections 11 is indicated by a dashed line. As shown in FIGS. 5 and 6 , the first sections 10 and the second sections 11 may have the same length or different lengths in the second direction Y. For example, the first sections 10 may be longer than the second sections 11, or the first sections 10 may be shorter than the second sections 11, in the second direction Y.

[0044] The multiple contact regions 25 are arranged at intervals for each first section 10 so as to skip each second section 11 in the second direction Y. In the body region 20, the contact region 25 and the regions on both sides of the contact region 25 in the first direction X may be the first sections 10. The second sections 11 may be regions between the multiple contact regions 25 adjacent to each other in the second direction Y.

[0045] Each contact region 25 extends in a strip shape along the extension direction of the body region 20 (second direction Y). The contact region 25 is formed at a distance from the outer body region 21 in the second direction Y. That is, the contact region 25 is not formed in the outer body region 21. The contact region 25 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the first semiconductor region 6 with a part of the body region 20 interposed therebetween. Each contact region 25 is formed at a distance from both the peripheries on one side and the other side of the body region 20 in the first direction X. In this embodiment, the contact region 25 is formed in the center of the body region 20 in the first direction X.

[0046] By forming the contact regions 25, the source region 23 is separated into a plurality of source regions 24A, 24B in the first section 10. In other words, one contact region 25 is interposed in a region between the first source region 24A and the second source region 24B in the surface layer portion of the corresponding body region 20. Each contact region 25 is sandwiched between the first source region 24A and the second source region 24B in the first direction X.

[0047] The plurality of source regions 24A, 24B include, in a surface layer portion of each body region 20, a first source region 24A located on one side in the first direction X and a second source region 24B located on the other side in the first direction X. In this embodiment, one first source region 24A is formed on one end side of the body region 20 in the first direction X, and one second source region 24B is formed on the other end side of the body region 20.

[0048] The first source region 24A is formed at an interval from one end to the other end of the body region 20, and extends in a strip shape along the extension direction of the body region 20. The first source region 24A is formed at an interval from the bottom of the body region 20 toward the first main surface 3, and faces the first semiconductor region 6 with a part of the body region 20 sandwiched therebetween.

[0049] The second source region 24B is formed at a distance from the first source region 24A on the other end side of the body region 20. The second source region 24B is formed at a distance from the other end of the body region 20 to one end side, and extends in a strip shape along the extension direction of the body region 20. The second source region 24B is formed at a distance from the bottom of the body region 20 on the first main surface 3 side, and faces the first semiconductor region 6 with a part of the body region 20 in between.

[0050] 6, the contact region 25 includes a first portion 12 extending in a strip shape in the second direction Y, and a plurality of protrusions 13 protruding outward in the first direction X from the first portion 12.

[0051] The first portion 12 crosses the first section 10 of the body region 20 in the second direction Y and has an end at the boundary between the first section 10 and the second section 11. The first portion 12 may be referred to by another name depending on its planar shape. For example, as shown in FIG. 6 , if the shape assumed excluding the protrusion 13 (the shape obtained by connecting the upper and lower opposing portions sandwiching the protrusion 13 in the second direction Y with a dashed line 17) is a strip in plan view, the first portion 12 may be referred to as a strip portion. The width (first width W1) of the first portion 12 may be, for example, 0.2 μm or more and 0.6 μm or less. The first width W1 may be constant or approximately constant in the second direction Y.

[0052] In this embodiment, the multiple protrusions 13 may include a pair of protrusions 14A, 14B protruding from the center of the first portion 12 in the second direction Y to both sides in the first direction X. That is, one protrusion 13 is formed on one side and one on the other side in the first direction X of the first portion 12. In this embodiment, the protrusion 13 protruding toward the first source region 24A is the first protrusion 14A, and the protrusion 13 protruding toward the second source region 24B is the second protrusion 14B. The first protrusion 14A and the second protrusion 14B protrude toward opposite sides from the same position on the first portion 12.

[0053] Each of the protrusions 14A, 14B may protrude from the first portion 12 and have a polygonal shape in plan view having one or more apexes 49. In this embodiment, each of the protrusions 14A, 14B is formed in a triangular shape in plan view. In the contact region 25, the apexes 49 have a rounded shape.

[0054] The pair of protrusions 14A, 14B may have a diamond-shaped or circular overall shape in a plan view, protruding evenly on both sides of the first portion 12. The overall shape of the pair of protrusions 14A, 14B may be defined by an outline 15 of the pair of protrusions 14A, 14B and an inner extension line 16 (a virtual line) of the outline 15 extending toward the inside of the contact region 25 (first portion 12). FIG. 6 illustrates a diamond-shaped pattern of the pair of protrusions 14A, 14B. In this embodiment, the overall width (second width W2) of the pair of protrusions 14A, 14B from the end of the first protrusion 14A in the first direction X to the end of the second protrusion 14B in the first direction X may be 1.2 μm or more and 1.6 μm or less.

[0055] In this embodiment, the width WS of each of the first source region 24A and the second source region 24B on both sides of the first portion 12 in the first direction X may be larger than the overall width (second width W2) of the pair of protrusions 14A, 14B. The width WS may be, for example, not less than 2 μm and not more than 4 μm.

[0056] The semiconductor device 1 includes a plurality of p-type channel regions 26, 27 formed in a surface layer portion of the first main surface 3. The plurality of channel regions 26, 27 are defined in the surface layer portions of the plurality of body regions 20 in regions between the ends of the plurality of body regions 20 (the plurality of surface drift regions 22) and the peripheries of the source regions 23. In this embodiment, the plurality of channel regions 26, 27 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of channel regions 26, 27 are arranged in stripes extending in the second direction Y.

[0057] The plurality of channel regions 26, 27 includes a plurality of first channel regions 26 and a plurality of second channel regions 27. The plurality of first channel regions 26 are formed in regions on the side of the plurality of first source regions 24A and form current paths extending in the horizontal direction. The plurality of second channel regions 27 are formed in regions on the side of the plurality of second source regions 24B and form current paths extending in the horizontal direction.

[0058] The semiconductor device 1 includes a plurality of planar electrode type gate structures 30 arranged on the first main surface 3 in the active region 8. The plurality of gate structures 30 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of gate structures 30 are arranged in stripes extending in the second direction Y. The extending direction of the plurality of gate structures 30 coincides with the off-direction of the SiC single crystal.

[0059] Each gate structure 30 is disposed on at least one channel region 26, 27. In this embodiment, each gate structure 30 is disposed across one surface drift region 22 to straddle two adjacent body regions 20, and covers the multiple channel regions 26, 27. Specifically, each gate structure 30 is disposed across the source region 23 on one body region 20 side and the source region 23 on the other body region 20 side, and covers the surface drift region 22, the source region 23 (first source region 24A and second source region 24B), the first channel region 26, and the second channel region 27.

[0060] The configuration of one gate structure 30 will be described below. The gate structure 30 has a stacked structure including an insulating film 31 and a gate electrode 32. The gate structure 30 does not have insulating sidewall structures (spacers) on the sides of the gate electrode 32. The insulating film 31 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 31 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 31 include a silicon oxide film made of an oxide of the chip 2.

[0061] The insulating film 31 covers the first main surface 3 in a film-like manner and is disposed on at least one of the channel regions 26, 27. In this embodiment, the insulating film 31 is disposed across one surface drift region 22 and straddles two adjacent body regions 20, and covers the multiple channel regions 26, 27.

[0062] Specifically, the insulating film 31 is arranged to straddle the source region 23 on one body region 20 side and the source region 23 on the other body region 20 side, and covers the surface drift region 22, the source region 23 (first source region 24A and second source region 24B), the first channel region 26, and the second channel region 27.

[0063] In the first section 10, the insulating film 31 partially covers the first source region 24A at a distance from the contact region 25, and exposes a part of the first source region 24A and the contact region 25 from the first main surface 3. In the first section 10, the insulating film 31 partially covers the second source region 24B at a distance from the contact region 25, and exposes a part of the second source region 24B and the contact region 25 from the first main surface 3. In the second section 11, the insulating film 31 partially covers the source region 23, and exposes a part of the source region 23 from the first main surface 3.

[0064] The thickness of the insulating film 31 may be 10 nm or more and 150 nm or less. The thickness of the insulating film 31 may be a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less. The thickness of the insulating film 31 is preferably 25 nm or more and 75 nm or less.

[0065] The gate electrode 32 is disposed on the insulating film 31 and faces at least one of the channel regions 26, 27 across the insulating film 31. A gate potential as a control potential is applied to the gate electrode 32. The gate electrode 32 controls inversion and non-inversion of at least one of the channel regions 26, 27 in response to the gate potential.

[0066] The gate electrode 32 includes a conductive semiconductor polycrystalline. The gate electrode 32 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The conductivity type of the gate electrode 32 is adjusted depending on the gate threshold voltage to be achieved. The gate electrode 32 may also be referred to as a "polysilicon gate," a "poly gate," or the like.

[0067] The gate electrode 32 is formed in a strip shape extending in the second direction Y. That is, the extending direction of the gate electrode 32 coincides with the off-direction of the SiC single crystal. In this embodiment, the gate electrode 32 is formed spaced apart inward from both ends of the insulating film 31 in the first direction X, exposing both ends of the insulating film 31. The gate electrode 32 is disposed on the insulating film 31 so as to cross one surface drift region 22 and straddle two adjacent body regions 20, and faces the multiple channel regions 26, 27 across the insulating film 31.

[0068] Specifically, the gate electrode 32 is arranged to straddle the source region 23 on one body region 20 side and the source region 23 on the other body region 20 side, and faces the surface drift region 22, the source region 23 (first source region 24A and second source region 24B), the first channel region 26, and the second channel region 27 across the insulating film 31.

[0069] The gate electrode 32 has an electrode surface 33, a first sidewall 34 on one side in the first direction X, and a second sidewall 35 on the other side in the first direction X. The electrode surface 33 extends along the insulating film 31 (first main surface 3). The electrode surface 33 may extend substantially parallel to the insulating film 31 (first main surface 3).

[0070] The first sidewall 34 is formed at a distance from one end of the insulating film 31 to the other end in the first direction X, and extends in the vertical direction Z. The second sidewall 35 is formed at a distance from the other end of the insulating film 31 to the one end in the first direction X, and extends in the vertical direction Z.

[0071] The first sidewall 34 and the second sidewall 35 may extend perpendicular to the insulating film 31. That is, the gate electrode 32 may be formed in a quadrangular shape (a flattened rectangular shape) in a cross-sectional view. The first sidewall 34 and the second sidewall 35 may be obliquely inclined toward the electrode surface 33. That is, the gate electrode 32 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in a cross-sectional view.

[0072] The width of the gate structure 30 may be 1 μm or more and 10 μm or less. The width of the gate structure 30 is the width in a direction perpendicular to the extending direction (i.e., the first direction X). The width of the gate structure 30 is preferably 1 μm or more and 5 μm or less.

[0073] The thickness of the gate structure 30 may be 0.1 μm or more and 2.0 μm or less, and preferably 0.2 μm or more and 1.0 μm or less.

[0074] 4 , 5 , and 10 , semiconductor device 1 includes a p-type termination region 45 formed on first main surface 3 in peripheral region 9. Termination region 45 may also be referred to as a “well region,” “termination well region,” or the like. Termination region 45 may have a p-type impurity concentration substantially equal to the p-type impurity concentration of outer body region 21. The p-type impurity concentration of termination region 45 may be higher than the p-type impurity concentration of outer body region 21, or may be lower than the p-type impurity concentration of outer body region 21.

[0075] Termination region 45 is spaced inward from the periphery of first main surface 3 and is formed in a region between the periphery of first main surface 3 and outer body region 21. Termination region 45 extends in a band shape along outer body region 21 in a plan view. Termination region 45 has a portion extending in a band shape in first direction X and a portion extending in a band shape in second direction Y in a plan view, and defines active region 8 from multiple directions.

[0076] In this embodiment, the termination region 45 surrounds the outer body region 21 in a plan view and is defined as a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The termination region 45 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4 ).

[0077] The termination region 45 is formed at a distance from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 across a part of the first semiconductor region 6. The termination region 45 is preferably formed at a distance from the middle of the first semiconductor region 6 toward the first main surface 3. The termination region 45 may have a thickness (depth) approximately equal to the thickness (depth) of the outer body region 21. The thickness of the termination region 45 may be greater than or less than the thickness of the outer body region 21.

[0078] The termination region 45 has an inner edge on the active region 8 side and an outer edge on the peripheral side of the first main surface 3. The inner edge of the termination region 45 is connected to the outer edge of the outer body region 21. As a result, the termination region 45 is fixed to the same potential as the outer body region 21 and is electrically connected to the plurality of body regions 20 via the outer body region 21. In this embodiment, the inner edge of the termination region 45 is connected to the outer edge of the outer body region 21 along the entire periphery.

[0079] The termination region 45 (inner edge portion) has an overlap region 46 that overlaps the outer edge portion of the outer body region 21. The overlap region 46 is a high-concentration region that includes the outer edge portion of the outer body region 21 and the inner edge portion of the termination region 45. In other words, the overlap region 46 includes both the p-type impurities of the outer body region 21 and the p-type impurities of the termination region 45, and has a p-type impurity concentration that is higher than both the p-type impurity concentrations of the outer body region 21 and the termination region 45.

[0080] The overlap region 46 extends in a band shape along the outer body region 21 in a plan view. The overlap region 46 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view, thereby partitioning the active region 8 from multiple directions. In this embodiment, the overlap region 46 is partitioned into a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3. The width of the overlap region 46 is preferably greater than the width of the body region 20. Of course, the width of the overlap region 46 may be equal to or less than the width of the body region 20.

[0081] The semiconductor device 1 may have a relatively high-concentration p-type well region (46) instead of the overlap region 46. In this case, the well region (46) has a p-type impurity concentration higher than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the termination region 45. The well region (46) may be formed in either or both of the surface layer portion of the outer body region 21 and the surface layer portion of the termination region 45.

[0082] The semiconductor device 1 includes at least one (preferably two to 20) p-type field region 47 formed in the surface layer portion of the first main surface 3 in the peripheral region 9. The number of the multiple field regions 47 is typically three to eight. In this embodiment, the semiconductor device 1 includes three field regions 47. The multiple field regions 47 are formed in an electrically floating state and relieve the electric field within the chip 2 at the periphery of the first main surface 3. The number, spacing, width, depth, p-type impurity concentration, etc. of the field regions 47 are arbitrary and can take various values ​​depending on the electric field to be relieved.

[0083] The field region 47 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 20 (termination region 45). The p-type impurity concentration of the field region 47 may be higher than the p-type impurity concentration of the body region 20 (termination region 45), or may be lower than the p-type impurity concentration of the body region 20 (termination region 45).

[0084] The plurality of field regions 47 are formed inwardly from the periphery of the first main surface 3 at intervals inward from the periphery of the first main surface 3 in a region between the periphery of the first main surface 3 and the active region 8. Specifically, the plurality of field regions 47 are formed in a region between the periphery of the first main surface 3 and the outer body region 21. More specifically, the plurality of field regions 47 are arranged in a region between the periphery of the first main surface 3 and the termination region 45 at intervals on the periphery side of the first main surface 3 from the termination region 45.

[0085] The field regions 47 are formed in strip shapes extending along the active region 8 (termination region 45) in plan view. Each of the field regions 47 has a strip-like portion extending in the first direction X and a strip-like portion extending in the second direction Y. In this embodiment, the field regions 47 are formed in polygonal ring shapes (quadrilateral ring shapes in this embodiment) surrounding the active region 8 (termination region 45) in plan view. The field regions 47 may have edge portions that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) (see FIG. 4 ).

[0086] The plurality of field regions 47 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The plurality of field regions 47 are preferably formed at intervals from the middle of the first semiconductor region 6 toward the first main surface 3.

[0087] 10 , the semiconductor device 1 includes a peripheral insulating film 51 that covers the first main surface 3 in the peripheral region 9. The peripheral insulating film 51 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the peripheral insulating film 51 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the peripheral insulating film 51 includes a silicon oxide film made of an oxide of the chip 2. The peripheral insulating film 51 is preferably made of the same insulating material as the insulating material of the insulating film 31. The peripheral insulating film 51 preferably has a thickness approximately equal to that of the insulating film 31.

[0088] The peripheral insulating film 51 covers the first main surface 3 in the peripheral region 9 in a film-like manner. The peripheral insulating film 51 collectively covers the outer body region 21, the termination region 45, and the plurality of field regions 47. The peripheral insulating film 51 is connected to the plurality of insulating films 31 on the active region 8 side. Specifically, the peripheral insulating film 51 is formed integrally with the plurality of insulating films 31, and together with the plurality of insulating films 31, forms a single insulating film.

[0089] 4, 5, and 10, the semiconductor device 1 includes a gate wiring 52 arranged on the first main surface 3 in the peripheral region 9. The semiconductor device 1 does not have insulating sidewall structures (spacers) on the sides of the gate wiring 52. The gate wiring 52 is selectively routed on the first main surface 3 and has a portion that extends in a different direction from the multiple gate electrodes 32. The gate wiring 52 is connected to the multiple gate electrodes 32 and applies gate signals to the multiple gate electrodes 32. The gate wiring 52 may also be referred to as a "polysilicon gate wiring," a "poly gate wiring," a "second gate electrode," or the like.

[0090] The gate wiring 52 includes a conductive semiconductor polycrystalline. The gate wiring 52 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate wiring 52 preferably has the same conductivity type as the gate electrode 32. The conductivity type of the gate wiring 52 is adjusted according to the conductivity type of the gate electrode 32.

[0091] The gate wiring 52 is disposed on the peripheral insulating film 51 in the peripheral region 9. Specifically, the gate wiring 52 is disposed on a portion of the peripheral insulating film 51 that covers the outer body region 21, and faces the outer body region 21 across the peripheral insulating film 51. The gate wiring 52 is formed at a distance from the periphery of the first main surface 3 toward the active region 8, and extends in a strip shape along the active region 8. The gate wiring 52 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions.

[0092] In this embodiment, the gate wiring 52 surrounds the active region 8 in a plan view and is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The gate wiring 52 may be terminated or endless. In this embodiment, the gate wiring 52 extends in a strip shape (a ring shape in this embodiment) along the outer body region 21 in a plan view and faces the outer body region 21 across the outer insulating film 51 over the entire area in the stacking direction. The gate wiring 52 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ).

[0093] The gate wiring 52 is formed to be narrower than the outer body region 21 in a plan view, and is disposed above the outer body region 21 at a distance from the inner and outer edges of the outer body region 21. That is, in this embodiment, the multiple gate electrodes 32 are extended up to above the outer body region 21, and the gate wiring 52 is connected to the multiple gate electrodes 32 above the outer body region 21.

[0094] The width of the gate wiring 52 is preferably larger than the width of the gate electrode 32. The width of the gate wiring 52 is the width in a direction perpendicular to the extending direction. Of course, the width of the gate wiring 52 may be equal to or smaller than the width of the gate electrode 32. The width of the gate wiring 52 may be larger than the width of the outer body region 21. The thickness of the gate wiring 52 is preferably approximately equal to the thickness of the gate electrode 32.

[0095] The gate wiring 52 has a wiring surface 53, a first wiring sidewall 54 on the inner edge side, and a second wiring sidewall 55 on the outer edge side. The wiring surface 53 extends along the peripheral insulating film 51 (first main surface 3). The wiring surface 53 may extend substantially parallel to the peripheral insulating film 51 (first main surface 3). The first wiring sidewall 54 extends in the vertical direction Z on the peripheral insulating film 51, and the second wiring sidewall 55 extends in the vertical direction Z on the peripheral insulating film 51.

[0096] The first wiring sidewall 54 is connected to the plurality of gate electrodes 32 (the first sidewall 34 and the second sidewall 35) at a portion extending in the first direction X. That is, the gate wiring 52 has a plurality of portions connected in a T-shape to the plurality of gate electrodes 32. As a result, the gate wiring 52 is fixed to the same potential as the plurality of gate electrodes 32.

[0097] The first wiring sidewall 54 and the second wiring sidewall 55 may extend perpendicular to the peripheral insulating film 51. That is, the gate wiring 52 may be formed in a quadrangular shape (a flattened rectangular shape) in a cross-sectional view. The first wiring sidewall 54 and the second wiring sidewall 55 may be obliquely inclined toward the wiring surface 53. That is, the gate wiring 52 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in a cross-sectional view.

[0098] The semiconductor device 1 includes an insulating interlayer film 70 that covers the first main surface 3. The interlayer film 70 may also be referred to as an "interlayer insulating film," "intermediate insulating film," or the like. The interlayer film 70 has an insulating surface 71 that extends along the first main surface 3. The interlayer film 70 collectively covers the active region 8 and the peripheral region 9 on the first main surface 3.

[0099] The interlayer film 70 covers the multiple gate structures 30 in the active region 8. The interlayer film 70 directly covers both the insulating film 31 and the gate electrode 32 for each gate structure 30. That is, the interlayer film 70 has portions that directly cover the electrode surface 33, the first sidewall 34, and the second sidewall 35 of the gate electrode 32.

[0100] The interlayer film 70 collectively covers the outer body region 21, the termination region 45, and the plurality of field regions 47 in the peripheral region 9, sandwiching the peripheral insulating film 51 therebetween. The interlayer film 70 directly covers both the peripheral insulating film 51 and the gate wiring 52. That is, the interlayer film 70 has portions that directly cover the wiring surface 53, the first wiring sidewall 54, and the second wiring sidewall 55 of the gate wiring 52. In this embodiment, the interlayer film 70 is continuous with the first to fourth side surfaces 5A to 5D. The interlayer film 70 may be formed spaced inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral portion of the first main surface 3 (the first semiconductor region 6).

[0101] 7 to 9, in this embodiment, the interlayer film 70 has a layered structure including a first oxide film 72 (first insulating film) and a second oxide film 73 (second insulating film) stacked in this order from the first main surface 3 side. That is, the interlayer film 70 has an insulating surface 71 formed by the second oxide film 73. The first oxide film 72 has a single-layer structure made of a silicon oxide film with no impurities added. The first oxide film 72 may also be referred to as an NSG film (nondoped silicate glass film).

[0102] The first oxide film 72 collectively covers the active region 8 and the peripheral region 9. The first oxide film 72 collectively covers the plurality of gate structures 30 in the active region 8. The first oxide film 72 covers both the insulating film 31 and the gate electrode 32 of each gate structure 30 in a film-like manner.

[0103] The first oxide film 72 has a first covering portion 74, a second covering portion 75, and a third covering portion 76. The first covering portion 74 extends horizontally in a film shape along the insulating film 31 (first main surface 3), and has a portion that contacts the first sidewall 34 (second sidewall 35) of the gate electrode 32. In this embodiment, the first covering portion 74 (first oxide film 72) has a thickness that is less than the thickness of the gate electrode 32, and covers the insulating film 31 at a distance from the height position of the electrode surface 33 of the gate electrode 32 toward the insulating film 31.

[0104] The second covering portion 75 is drawn out from the first covering portion 74 toward the electrode surface 33 in the stacking direction, and directly covers the first side wall 34 (second side wall 35) in a film-like manner.

[0105] The third covering portion 76 is drawn out from the second covering portion 75 toward the electrode surface 33 and extends horizontally in a film shape along the electrode surface 33. The third covering portion 76 directly covers the entire electrode surface 33 between the first side wall 34 and the second side wall 35. It is preferable that the third covering portion 76, together with the second covering portion 75, forms an arc-shaped corner portion that is curved in an arc shape in a portion that covers the corner of the gate electrode 32. The arc-shaped corner portion may have a center of curvature on the gate electrode 32 side.

[0106] In the peripheral region 9, the first oxide film 72 collectively covers the outer body region 21, the termination region 45, and the plurality of field regions 47 with the peripheral insulating film 51 sandwiched therebetween. The first oxide film 72 covers the gate wiring 52 in the peripheral region 9.

[0107] The second oxide film 73 may have a single-layer structure made of a silicon oxide film containing phosphorus, or a multilayer structure including a silicon oxide film containing phosphorus. The silicon oxide film containing phosphorus may contain boron. The silicon oxide film containing phosphorus may be called a PSG film (Phosphorus Silicon Glass Film). The silicon oxide film containing both phosphorus and boron may be called a BPSG film (Boron Phosphorus Silicon Glass Film).

[0108] The second oxide film 73 may have a single layer structure made of a PSG film or a BPSG film stacked on the first oxide film 72. The second oxide film 73 may have a layered structure including a PSG film stacked on the first oxide film 72 and a BPSG film stacked on the PSG film. The second oxide film 73 may have a layered structure including a BPSG film stacked on the first oxide film 72 and a PSG film stacked on the BPSG film. In this embodiment, the second oxide film 73 has a single layer structure made of a PSG film, for example.

[0109] The second oxide film 73 covers the first oxide film 72 in a film-like manner, and collectively covers the active region 8 and the peripheral region 9 with the first oxide film 72 sandwiched therebetween. The second oxide film 73 collectively covers the plurality of gate structures 30 in the active region 8 with the first oxide film 72 sandwiched therebetween. Specifically, the second oxide film 73 covers both the insulating film 31 and the gate electrode 32 in a film-like manner with the first oxide film 72 sandwiched therebetween.

[0110] The second oxide film 73 includes a first upper covering portion 80 and a second upper covering portion 81. The first upper covering portion 80 covers the first covering portion 74 of the first oxide film 72. The first upper covering portion 80 covers the insulating film 31 in a portion located above the first covering portion 74, with the first covering portion 74 sandwiched between them.

[0111] The first upper covering portion 80 extends in a film-like manner in the stacking direction from above the first covering portion 74 along the second covering portion 75, and covers the first sidewall 34 (second sidewall 35) of the gate structure 30 with the second covering portion 75 in between.

[0112] The second upper covering portion 81 covers the third covering portion 76 of the first oxide film 72. The second upper covering portion 81 extends horizontally in a film-like manner from the first upper covering portion 80 along the third covering portion 76, and covers the electrode surface 33 of the gate structure 30 with the third covering portion 76 in between. The second upper covering portion 81 covers the entire electrode surface 33 with the third covering portion 76 in between the first sidewall 34 and the second sidewall 35. It is preferable that the second upper covering portion 81, together with the first upper covering portion 80, form an arc-shaped curved corner portion in a portion covering the corner of the gate wiring 52. The arc-shaped corner portion may have a center of curvature on the gate wiring 52 side.

[0113] In the peripheral region 9, the second oxide film 73 collectively covers the outer body region 21, the termination region 45, and the plurality of field regions 47, sandwiching the peripheral insulating film 51 and the first oxide film 72 therebetween. In the peripheral region 9, the second oxide film 73 covers the gate wiring 52, sandwiching the first oxide film 72 therebetween.

[0114] The semiconductor device 1 includes a plurality of source openings 90 formed in the interlayer film 70 in the active region 8. The plurality of source openings 90 are formed in regions on the sides of the plurality of gate electrodes 32 at intervals from the plurality of gate electrodes 32, respectively, and expose the first main surface 3 (chip 2). Specifically, the plurality of source openings 90 are formed in regions between the plurality of gate electrodes 32, respectively, and penetrate the insulating film 31 and the interlayer film 70.

[0115] The plurality of source openings 90 penetrate both the first oxide film 72 and the second oxide film 73, and have wall surfaces defined by both the first oxide film 72 and the second oxide film 73. The plurality of source openings 90 have opening ends defined by arc corners of the interlayer film 70. The plurality of source openings 90 expose the corresponding plurality of source regions 23 (first source regions 24A and second source regions 24B) and contact regions 25, respectively.

[0116] In this embodiment, the source openings 90 are formed at intervals in the first direction X and in stripes extending in the second direction Y. That is, the source openings 90 are formed in stripes extending in the second direction Y. The source openings 90 are formed at intervals from the gate wiring 52 in the second direction Y. That is, the source openings 90 are formed in a region surrounded by the gate electrodes 32 and the gate wiring 52.

[0117] A plurality of source openings 90 may be formed in a region between two gate structures 30 adjacent to each other in the first direction X. In this case, the plurality of source openings 90 may be formed in a line at intervals in the second direction Y. Furthermore, in this case, each source opening 90 may be formed in a quadrilateral shape (square shape) in a plan view, a rectangular shape extending in the first direction X, a rectangular shape extending in the second direction Y, a hexagonal shape, a circular shape, or the like.

[0118] The source opening 90 may have a width W of 0.2 μm or more and 3 μm or less. The width W of the source opening 90 is preferably 0.3 μm or more and 1 μm or less. The source opening 90 may have a depth D of 0.2 μm or more and 2 μm or less. The depth D of the source opening 90 is preferably 0.5 μm or more and 1 μm or less.

[0119] The source opening 90 preferably has an aspect ratio D / W of 0.3 or more and 3 or less. The aspect ratio D / W is defined by the ratio of the depth D of the source opening 90 to the width W of the source opening 90. The aspect ratio D / W is preferably 0.5 or more and 2 or less. It is particularly preferable that the aspect ratio D / W exceeds 1. According to this configuration, the multiple gate structures 30 are arranged at a narrow pitch.

[0120] The semiconductor device 1 includes a plurality of source recesses 91 formed in the first main surface 3 in portions exposed from the plurality of source openings 90. The semiconductor device 1 does not necessarily have to have the source recesses 91. Therefore, a configuration not including the source recesses 91 may be employed.

[0121] The plurality of source recesses 91 each have a planar shape that matches the planar shape of the corresponding source opening 90, and are recessed from the first main surface 3 toward the second main surface 4. The plurality of source recesses 91 are formed at intervals from the bottoms of the corresponding body regions 20 toward the first main surface 3, and expose the corresponding plurality of source regions 23 and contact regions 25. Specifically, the plurality of source recesses 91 are formed at intervals from the bottoms of the corresponding plurality of source regions 23 (contact regions 25) toward the first main surface 3.

[0122] The semiconductor device 1 includes at least one outer opening 92 (a plurality of outer openings in this embodiment) formed in the interlayer film 70 in the peripheral region 9. The plurality of outer openings 92 are formed in a portion of the interlayer film 70 that covers the termination region 45. The plurality of outer openings 92 penetrate the interlayer film 70 to expose the termination region 45. In this embodiment, the plurality of outer openings 92 are formed in a portion of the interlayer film 70 that covers the overlap region 46 of the termination region 45 to expose the overlap region 46.

[0123] The outer openings 92 may expose the outer body region 21 instead of or in addition to the termination region 45 (overlap region 46). The outer openings 92 penetrate both the first oxide film 72 and the second oxide film 73 and have wall surfaces defined by both the first oxide film 72 and the second oxide film 73. The outer openings 92 have opening ends defined by arcuate corners of the interlayer film 70.

[0124] The outer openings 92 are spaced apart along the termination region 45 (overlap region 46) (see FIGS. 4 and 5). The outer openings 92 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view. The outer openings 92 may be formed in a strip shape extending along the termination region 45 (overlap region 46) in a plan view. The outer openings 92 may have an aspect ratio D / W (preferably greater than 1), similar to the source openings 90.

[0125] The semiconductor device 1 may have a single outer opening 92. The single outer opening 92 may be formed in a strip shape extending along the termination region 45 (overlap region 46). The single outer opening 92 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.

[0126] The single outer opening 92 may be formed in the shape of an ended or endless polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The single outer opening 92 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) following the termination region 45 (overlap region 46) in a plan view (see FIG. 4 ).

[0127] The semiconductor device 1 includes a plurality of outer recesses 93 formed in the first main surface 3 in the portions exposed from the plurality of outer openings 92. The semiconductor device 1 does not necessarily have to have the outer recesses 93. Therefore, a configuration not having the outer recesses 93 may be employed.

[0128] The multiple outer recesses 93 each have a planar shape that matches the planar shape of the corresponding outer opening 92, and are recessed from the first main surface 3 toward the second main surface 4. The multiple outer recesses 93 are formed at intervals from the bottom of the termination region 45 (overlap region 46) toward the first main surface 3, and each exposes the termination region 45 (overlap region 46). When a single outer opening 92 is formed, a single outer recess 93 that matches the planar shape of the single outer opening 92 is formed.

[0129] The semiconductor device 1 includes at least one gate opening 94 (in this embodiment, multiple gate openings 94) formed in the interlayer film 70 in the peripheral region 9. The multiple gate openings 94 are formed in portions of the interlayer film 70 that cover the gate wiring 52. The multiple gate openings 94 penetrate the interlayer film 70 and expose the wiring surface 53 of the gate wiring 52.

[0130] The plurality of gate openings 94 penetrate both the first oxide film 72 and the second oxide film 73, and have wall surfaces defined by both the first oxide film 72 and the second oxide film 73. The plurality of gate openings 94 have opening ends defined by arcuate corners of the interlayer film 70.

[0131] The multiple gate openings 94 are formed at intervals along the gate wiring 52 (see FIGS. 4 and 5). The multiple gate openings 94 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view. The multiple gate openings 94 may be formed in a strip shape extending along the gate wiring 52 in a plan view. Like the source openings 90, the gate openings 94 may have an aspect ratio D / W (preferably greater than 1).

[0132] The semiconductor device 1 may have a single gate opening 94. The single gate opening 94 may be formed in a strip shape extending along the gate wiring 52. The single gate opening 94 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.

[0133] The single gate opening 94 may be formed in the shape of an ended or endless polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The single gate opening 94 may have an edge portion that connects a portion extending in the first direction X and a portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in plan view, following the gate wiring 52 (see FIG. 4 ).

[0134] 1 and other figures, the semiconductor device 1 includes a source pad electrode 95 disposed on the interlayer film 70. The source pad electrode 95 is a terminal electrode to which a source potential is applied from the outside. The source pad electrode 95 may also be referred to as a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like.

[0135] The source pad electrode 95 is disposed on a portion of the interlayer film 70 that covers the active region 8. The source pad electrode 95 covers the plurality of gate electrodes 32 with the interlayer film 70 in between, and is electrically separated from the plurality of gate electrodes 32 by the interlayer film 70. The source pad electrode 95 is electrically connected to the plurality of body regions 20, the outer body region 21, the plurality of source regions 23 (first source region 24A and second source region 24B), contact region 25, etc. via the plurality of source openings 90.

[0136] In this embodiment, the source pad electrode 95 has a first pad portion 96, a second pad portion 97, and a third pad portion 98. The first pad portion 96 has a relatively large planar area and forms the main body of the source pad electrode 95. In this embodiment, the first pad portion 96 is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the active region 8. The first pad portion 96 covers the multiple gate electrodes 32 with the interlayer film 70 sandwiched therebetween, and is electrically connected to the multiple body regions 20 and the like via the multiple source openings 90.

[0137] The second pad portion 97 has a planar area smaller than that of the first pad portion 96, and is drawn out in a strip shape (rectangular shape) from one end of the first pad portion 96 in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The second pad portion 97 covers the plurality of gate electrodes 32 with the interlayer film 70 sandwiched therebetween, and is electrically connected to the plurality of body regions 20 etc. via the plurality of source openings 90.

[0138] The third pad portion 98 has a plane area smaller than that of the first pad portion 96, and is drawn out in a strip shape (rectangular shape) from the other end of the first pad portion 96 in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 97 in the second direction Y. The third pad portion 98 covers the plurality of gate electrodes 32 with the interlayer film 70 sandwiched therebetween, and is electrically connected to the plurality of body regions 20 etc. via the plurality of source openings 90.

[0139] The planar area of ​​the third pad portion 98 may be approximately equal to the planar area of ​​the second pad portion 97. Of course, the planar area of ​​the third pad portion 98 may be larger than the planar area of ​​the second pad portion 97, or may be smaller than the planar area of ​​the second pad portion 97. Either or both of the second pad portion 97 and the third pad portion 98 may be used as a terminal portion for monitoring a current.

[0140] The source pad electrode 95 does not necessarily have to have both the second pad portion 97 and the third pad portion 98. The source pad electrode 95 may have only one of the second pad portion 97 and the third pad portion 98. Of course, the source pad electrode 95 may be made up of only the first pad portion 96, and may not have the second pad portion 97 or the third pad portion 98.

[0141] 7 to 9, the source pad electrode 95 includes a first underlying electrode film 100 and a first main electrode film 102. The first underlying electrode film 100 may be referred to as a "source underlying electrode film," and the first main electrode film 102 may be referred to as a "source main electrode film."

[0142] The first underlying electrode film 100 forms a lower layer of the source pad electrode 95 (first pad portion 96, second pad portion 97, and third pad portion 98), and covers the interlayer film 70 in the active region 8. The first underlying electrode film 100 collectively covers the region of the interlayer film 70 where the multiple source openings 90 are formed. In other words, the first underlying electrode film 100 extends from above the insulating surface 71 into the multiple source openings 90.

[0143] The first base electrode film 100 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the plurality of source openings 90 in a film-like manner. The first base electrode film 100 defines recesses in each of the plurality of source openings 90. The first base electrode film 100 may have a portion that partially covers the gate wiring 52 with the interlayer film 70 sandwiched therebetween. The first base electrode film 100 may be formed spaced inward from the gate wiring 52 in a plan view.

[0144] In this embodiment, the first base electrode film 100 has a laminated structure including a first electrode film 103 laminated on the interlayer film 70 and a second electrode film 104 laminated on the first electrode film 103. In this embodiment, the first electrode film 103 includes a Ti film, and the second electrode film 104 includes a TiN film.

[0145] The first base electrode film 100 does not necessarily have a laminated structure, but may have a single-layer structure consisting of either the first electrode film 103 (Ti film) or the second electrode film 104 (TiN film). The thickness of the first electrode film 103 may be 10 nm or more and 100 nm or less. The thickness of the second electrode film 104 may be 50 nm or more and 200 nm or less.

[0146] The first electrode film 103 collectively covers the region of the interlayer film 70 where the multiple source openings 90 are formed, and extends into the multiple source openings 90 from above the insulating surface 71. The first electrode film 103 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 90 in a film-like manner. The first electrode film 103 directly covers the insulating surface 71.

[0147] That is, the first electrode film 103 directly covers the second oxide film 73 on the insulating surface 71. The first oxide film 72 faces the plurality of gate electrodes 32 in the portion covering the insulating surface 71, with the interlayer film 70 sandwiched therebetween.

[0148] The first electrode film 103 covers the arc corner portion of the interlayer film 70 (second oxide film 73) in a film-like manner, following the arc corner portion, and extends into the source opening 90. In other words, the first electrode film 103 has a portion that extends in an arc shape at the arc corner portion. This improves the film formability of the first electrode film 103 on the interlayer film 70 (wall surface of the source opening 90).

[0149] The first electrode film 103 extends along the wall surface of the source opening 90 and covers the insulating film 31, the first oxide film 72, and the second oxide film 73. The first electrode film 103 faces the first sidewall 34 (second sidewall 35) of the gate electrode 32 with the interlayer film 70 interposed therebetween.

[0150] The first electrode film 103 covers the first main surface 3 at the bottom of each source opening 90 in a film-like manner, and is electrically connected to the first main surface 3. Specifically, the first electrode film 103 has a portion that covers the bottom of each source opening 90 in a film-like manner, and is electrically connected to the plurality of source regions 23 (first source region 24A and second source region 24B) and the contact region 25.

[0151] The second electrode film 104 collectively covers, in a film form, the region of the interlayer film 70 on the first electrode film 103 where the plurality of source openings 90 are formed. The second electrode film 104 has a portion that covers, in a film form, the insulating surface 71 of the interlayer film 70 with the first electrode film 103 in between, and a portion that covers, in a film form, the wall surfaces of the plurality of source openings 90 with the first electrode film 103 in between.

[0152] The second electrode film 104 faces the plurality of gate electrodes 32 in the portion covering the insulating surface 71 with the first electrode film 103 and the interlayer film 70 interposed therebetween.

[0153] The second electrode film 104, following the first electrode film 103, covers the arc corners of the interlayer film 70 (second oxide film 73) in a film-like manner and extends into the source opening 90. In other words, the second electrode film 104 has a portion that extends in an arc shape at the arc corners of the interlayer film 70. This improves the film formability of the second electrode film 104 on the interlayer film 70 (wall surface of the source opening 90).

[0154] The second electrode film 104 extends along the wall surface of the source opening 90 and covers the insulating film 31, the first oxide film 72, and the second oxide film 73 with the first electrode film 103 interposed therebetween. The second electrode film 104 faces the first sidewall 34 (second sidewall 35) of the gate electrode 32 with the first electrode film 103 and the interlayer film 70 interposed therebetween.

[0155] The second electrode film 104 has a portion that covers the bottom of each source opening 90 in a film-like manner, sandwiching the first electrode film 103 therebetween, and is electrically connected to multiple source regions 23 (first source region 24A and second source region 24B) and contact region 25.

[0156] The first main electrode film 102 forms an upper layer of the source pad electrode 95 (the first pad portion 96, the second pad portion 97, and the third pad portion 98), and covers the first base electrode film 100 in a film form. The first main electrode film 102 contains a conductive material different from the conductive material of the first base electrode film 100.

[0157] The first main electrode film 102 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The first main electrode film 102 has a thickness greater than the thickness (total thickness) of the first underlying electrode film 100.

[0158] The thickness of the first main electrode film 102 may be 0.5 μm or more and 5 μm or less. The thickness of the first main electrode film 102 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0159] The first main electrode film 102 is mechanically and electrically connected to the first underlying electrode film 100 in a portion covering the insulating surface 71. As a result, the first main electrode film 102 faces the multiple gate electrodes 32 with the first underlying electrode film 100 and the interlayer film 70 sandwiched therebetween.

[0160] Semiconductor device 1 includes source finger electrodes 110 extending from source pad electrode 95 onto peripheral region 9. Source finger electrode 110 transmits a source potential applied to source pad electrode 95 to peripheral region 9. In this embodiment, source finger electrode 110 is routed from a portion of source pad electrode 95 (first pad portion 96) on the fourth side surface 5D side onto a portion of interlayer film 70 covering peripheral region 9.

[0161] Source finger electrodes 110 are extended onto termination region 45 and electrically connected to termination region 45 through a plurality of outer openings 92. Specifically, source finger electrodes 110 are electrically connected to overlap region 46 of termination region 45 through a plurality of outer openings 92.

[0162] The source finger electrodes 110 extend in a strip shape along the termination region 45 (overlap region 46). In plan view, the source finger electrodes 110 have a strip-like portion extending in the first direction X and a strip-like portion extending in the second direction Y. In this embodiment, the source finger electrodes 110 are formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surround the source pad electrode 95. The source finger electrodes 110 may have edge portions that connect the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in plan view (see FIG. 4 ).

[0163] Like the source pad electrode 95, the source finger electrode 110 includes a first underlying electrode film 100 and a first main electrode film 102. The first underlying electrode film 100 forms a lower layer portion of the source finger electrode 110 and covers the interlayer film 70 in the peripheral region 9.

[0164] The first underlying electrode film 100 collectively covers, in a film-like manner, the region of the interlayer film 70 where the multiple outer openings 92 are formed. That is, the first underlying electrode film 100 extends from above the insulating surface 71 into the multiple outer openings 92. The first underlying electrode film 100 has a portion that covers, in a film-like manner, the insulating surface 71 of the interlayer film 70, and a portion that covers, in a film-like manner, the wall surfaces of the multiple outer openings 92. The first underlying electrode film 100 defines recesses within the multiple outer openings 92. Like the source pad electrode 95, the first underlying electrode film 100 has a stacked structure including a first electrode film 103 and a second electrode film 104.

[0165] The first main electrode film 102 forms an upper layer of the source finger electrode 110 and covers the first underlying electrode film 100 in a film form. The first main electrode film 102 is mechanically and electrically connected to the first underlying electrode film 100 in the portion covering the insulating surface 71. In other words, the first main electrode film 102 is electrically connected to the termination region 45 (overlapping region 46) via the first underlying electrode film 100.

[0166] The semiconductor device 1 includes gate finger electrodes 115 selectively routed on the interlayer film 70. The gate finger electrodes 115 transmit a gate potential to the gate wiring 52. The gate finger electrodes 115 are routed on a portion of the interlayer film 70 that covers the gate wiring 52 (i.e., on the outer periphery region 9), and are electrically connected to the gate wiring 52 through a plurality of gate openings 94.

[0167] The gate finger electrode 115 is disposed in a region between the source pad electrode 95 and the source finger electrode 110 and is spaced apart from the source pad electrode 95 and the source finger electrode 110. The gate finger electrode 115 is disposed on the gate wiring 52 and extends in a strip shape along the gate wiring 52. The gate finger electrode 115 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in plan view.

[0168] In this embodiment, the gate finger electrode 115 is formed in a band shape with four sides parallel to the periphery of the first main surface 3 and surrounds the source pad electrode 95. The gate finger electrode 115 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ). The gate finger electrode 115 has a pair of open ends on the fourth side surface 5D side through which the source finger electrode 110 passes.

[0169] 10 , the gate finger electrode 115 includes a second underlying electrode film 120 and a second main electrode film 122. The second underlying electrode film 120 may be referred to as a “gate underlying electrode film,” and the second main electrode film 122 may be referred to as a “gate main electrode film.”

[0170] The second base electrode film 120 forms a lower layer of the gate finger electrode 115 and covers the interlayer film 70 in the peripheral region 9. The second base electrode film 120 collectively covers the region of the interlayer film 70 in which the multiple gate openings 94 are formed. In other words, the second base electrode film 120 extends from above the insulating surface 71 into the multiple gate openings 94. The second base electrode film 120 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner and a portion that covers the wall surfaces of the multiple gate openings 94 in a film-like manner. The second base electrode film 120 defines multiple recesses within the multiple gate openings 94.

[0171] The second underlying electrode film 120 has a layered structure similar to that of the first electrode film 103 and the second electrode film 104 of the first underlying electrode film 100. The layered structure of the second underlying electrode film 120 is similar to that of the first electrode film 103 and the second electrode film 104 of the first underlying electrode film 100, and therefore a description thereof will be omitted.

[0172] The second main electrode film 122 forms an upper layer of the gate finger electrode 115 and covers the second base electrode film 120 in a film form. The second main electrode film 122 contains a conductive material different from the conductive material of the second base electrode film 120.

[0173] The second main electrode film 122 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The second main electrode film 122 preferably includes the same type of conductive material as the conductive material of the first main electrode film 102. The second main electrode film 122 may have a thickness approximately equal to that of the first main electrode film 102.

[0174] The second main electrode film 122 is mechanically and electrically connected to the second base electrode film 120 in the portion covering the insulating surface 71 .

[0175] The semiconductor device 1 includes a gate pad electrode 130 disposed on the interlayer film 70. The gate pad electrode 130 is a terminal electrode to which a gate potential is applied from the outside. The gate pad electrode 130 may also be referred to as a "second pad electrode," a "second main surface electrode," a "second terminal electrode," or the like. The gate pad electrode 130 is disposed in a region between the source pad electrode 95 and the source finger electrodes 110 and spaced apart from the source pad electrode 95 and the source finger electrodes 110.

[0176] In this embodiment, the gate pad electrode 130 is disposed in a region on the third side surface 5C side with respect to the first pad portion 96, and is sandwiched between the second pad portion 97 and the third pad portion 98. In other words, the gate pad electrode 130 faces the first pad portion 96 in the first direction X, and faces the second pad portion 97 and the third pad portion 98 in the second direction Y.

[0177] The gate pad electrode 130 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate pad electrode 130 has a planar area less than that of the source pad electrode 95 (first pad portion 96). The gate pad electrode 130 may have a planar area less than that of the second pad portion 97 (third pad portion 98).

[0178] The gate pad electrode 130 is disposed on a portion covering the active region 8 and the peripheral region 9, and is connected to the gate finger electrode 115. The gate pad electrode 130 may cover the plurality of gate electrodes 32 with the interlayer film 70 interposed therebetween, or may cover the gate wiring 52 with the interlayer film 70 interposed therebetween.

[0179] Like the gate finger electrode 115, the gate pad electrode 130 includes a second base electrode film 120 and a second main electrode film 122. The second base electrode film 120 forms a lower layer portion of the gate pad electrode 130 and covers the interlayer film 70 in a film-like manner. The second main electrode film 122 forms an upper layer portion of the gate pad electrode 130 and covers the second base electrode film 120 in a film-like manner.

[0180] The gate potential applied to the gate pad electrode 130 is applied to the gate wiring 52 via the gate finger electrode 115. The gate potential is transmitted to the plurality of gate electrodes 32 via a wiring path (current path) along the gate wiring 52. This turns on the plurality of gate electrodes 32, controlling the on / off of the plurality of channel regions 26, 27.

[0181] The semiconductor device 1 includes a drain pad electrode 140 covering the second main surface 4. The drain pad electrode 140 is a terminal electrode to which a drain potential is applied from the outside. The drain pad electrode 140 may also be referred to as a "third pad electrode," a "third main surface electrode," a "third terminal electrode," or the like. The drain pad electrode 140 is electrically connected to the second semiconductor region 7. The drain pad electrode 140 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The drain pad electrode 140 may also partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.

[0182] The breakdown voltage that can be applied between the source pad electrode 95 and the drain pad electrode 140 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0183] 11 is a schematic diagram showing a wafer 150 used in manufacturing the semiconductor device 1. Referring to FIG. 11, the wafer 150 is a base material of the chip 2 and includes a SiC single crystal. The wafer 150 is formed in a flat disk shape. Of course, the wafer 150 may also be formed in a flat rectangular parallelepiped shape. The wafer 150 has a first wafer main surface 151 on one side, a second wafer main surface 152 on the other side, and a wafer side surface 153 connecting the first wafer main surface 151 and the second wafer main surface 152.

[0184] The first wafer main surface 151 corresponds to the first main surface 3 of the chip 2, and the second wafer main surface 152 corresponds to the second main surface 4 of the chip 2. The first wafer main surface 151 and the second wafer main surface 152 are formed by the c-plane of the SiC single crystal. The first wafer main surface 151 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 152 is formed by the carbon surface of the SiC single crystal. The wafer 150 (the first wafer main surface 151 and the second wafer main surface 152) has the off-direction and off-angle described above.

[0185] The wafer 150 has a mark 154 on the wafer side surface 153 that indicates the crystal orientation of the SiC single crystal. The mark 154 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 151 in a plan view.

[0186] The mark 154 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The mark 154 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.

[0187] The wafer 150 includes a first semiconductor region 6 in a region (surface layer portion) on the first wafer main surface 151 side. The first semiconductor region 6 is formed in a layer shape extending along the first wafer main surface 151. In this embodiment, the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer).

[0188] The wafer 150 includes a second semiconductor region 7 in a region (surface layer portion) on the second wafer main surface 152 side. The second semiconductor region 7 is formed in a layer extending along the second main surface 4 and is electrically connected to the first semiconductor region 6. In this embodiment, the second semiconductor region 7 is made of the wafer main body (specifically, a SiC wafer). That is, in this embodiment, the wafer 150 is made of an epitaxial wafer (a so-called epiwafer) having a layered structure including the wafer main body and an epitaxial layer.

[0189] For example, a plurality of device regions 155 and a plurality of cutting lines 156 are set on the wafer 150 by alignment marks or the like. Each device region 155 corresponds to a semiconductor device 1. Each of the plurality of device regions 155 is set to have a quadrangular shape in a plan view.

[0190] In this embodiment, the multiple device regions 155 are set in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 155 are set at intervals inward from the periphery of the first wafer main surface 151 in a plan view. The multiple cutting lines 156 are set in a grid pattern extending along the first direction X and the second direction Y to partition the multiple device regions 155.

[0191] 12A to 12P are cross-sectional views showing a manufacturing method of the semiconductor device 1. Each of FIGS. 12A to 12P shows a cross section of a portion of an active region 8 in one device region 155. The left drawings in FIGS. 12A to 12P correspond to a portion of the cross section in FIG. 7, and the right drawings correspond to a portion of the cross section in FIG. 8. FIG. 13 is a diagram showing a planar pattern of the first mask 37 shown in FIG. 12G.

[0192] Referring to FIG. 12A , first, the aforementioned wafer 150 is prepared. Next, referring to FIG. 12B , a base mask 18 is formed on the first wafer main surface 151. The base mask 18 is preferably an inorganic mask (i.e., a hard mask). The base mask 18 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the base mask 18 is made of a silicon oxide film (insulating film). The base mask 18 may be formed by a CVD method. Next, the base mask 18 is patterned to form a base opening 19. The base opening 19 selectively exposes regions of the first wafer main surface 151 where the body region 20 and the outer body region 21 (not shown) are to be formed.

[0193] 12C , p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation via the base mask 18, thereby forming a plurality of body regions 20. Furthermore, p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation via the base mask 18, thereby forming outer body regions 21.

[0194] 12D , a sidewall insulating film 28 is formed on the first wafer main surface 151 so as to cover the base mask 18 and the body region 20. The sidewall insulating film 28 is preferably an inorganic mask (i.e., a hard mask). The sidewall insulating film 28 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the sidewall insulating film 28 is made of a silicon oxide film (insulating film). The sidewall insulating film 28 may be formed by a CVD method.

[0195] 12E , the sidewall insulating film 28 is etched back. The etchback is continued until the surfaces of the base mask 18 and the body region 20 are exposed. As a result, portions of the sidewall insulating film 28 that contact the sides of the base mask 18 are selectively left, forming sidewalls 29. The sidewalls 29 cover the periphery of each body region 20. The portions of the body region 20 covered by the sidewalls 29 are the multiple channel regions 26 and 27. The width WB of the exposed region of the body region 20 sandwiched between adjacent sidewalls 29 may be, for example, 4 μm or more and 10 μm or less.

[0196] 12F , a mask material 36 is formed to cover the sidewalls 29 and the base mask 18 so as to backfill the base opening 19 of the base mask 18. The mask material 36 may be an organic material. The mask material 36 may include a positive or negative photosensitive resin film (i.e., a resist film) as the organic material. Of course, the mask material 36 may also be an inorganic material (e.g., a silicon oxide film, a silicon nitride film, a polysilicon film, etc.).

[0197] 12G, the mask material 36 is patterned to form a first mask 37. The first mask 37 has a first opening 38 that exposes a region where the source region 23 (first source region 24A and second source region 24B) is to be formed.

[0198] 13 , the first mask 37 matches the planar shape of the contact region 25. The first mask 37 includes a first portion 39 extending in a strip shape in the second direction Y, and a plurality of protrusions 40 protruding outward in the first direction X from the first portion 39.

[0199] The first portion 39 crosses the first section 10 of the body region 20 in the second direction Y and has an end at the boundary between the first section 10 and the second section 11. The first portion 39 may be referred to by another name depending on its planar shape. For example, as shown in FIG. 13 , if the shape assumed excluding the protrusion 40 (the shape obtained by connecting the portions facing each other above and below the protrusion 40 in the second direction Y with a dashed line 44) is a band in plan view, the first portion 39 may be referred to as a band-shaped portion. The width (third width W3) of the first portion 39 may be, for example, not less than 0.2 μm and not more than 0.6 μm.

[0200] In this embodiment, the multiple protrusions 40 may include a pair of protrusions 41A, 41B protruding from the center of the first portion 39 in the second direction Y to both sides in the first direction X. That is, one protrusion 40 is formed on one side and one on the other side in the first direction X of the first portion 39. In this embodiment, the protrusion 40 protruding toward the channel region 26 is the first protrusion 41A, and the protrusion 40 protruding toward the channel region 27 is the second protrusion 41B. The first protrusion 41A and the second protrusion 41B protrude toward opposite sides from the same position on the first portion 39.

[0201] Each of the protrusions 41A, 41B may protrude from the first portion 39 and have a polygonal shape in plan view having one or more apexes 48. In this embodiment, each of the protrusions 41A, 41B is formed in a triangular shape in plan view. In the first mask 37, the apexes 48 have a sharply pointed shape.

[0202] The pair of protrusions 41A, 41B may have a diamond-shaped or circular overall shape in a plan view, protruding evenly on both sides of the first portion 39. The overall shape of the pair of protrusions 41A, 41B may be defined by an outline 42 of the pair of protrusions 41A, 41B and an inner extension line 43 (a virtual line) of the outline 42 extending toward the inside of the contact region 25 (first portion 39). FIG. 13 illustrates a diamond-shaped pattern of the pair of protrusions 41A, 41B. In this embodiment, the overall width (fourth width W4) of the pair of protrusions 41A, 41B from the end of the first protrusion 41A in the first direction X to the end of the second protrusion 41B in the first direction X may be 1.2 μm or more and 1.6 μm or less.

[0203] Furthermore, the aspect ratio of the first portion 39 of the first mask 37 (height H of the first mask 37 / third width W3) may be equal to or greater than 5 and equal to or less than 25. The aspect ratio of the portion of the first mask 37 where the pair of protrusions 41A, 41B are formed (height H of the first mask 37 / fourth width W4) may be equal to or greater than 0.8 and equal to or less than 4.8.

[0204] 12H , n-type impurities are selectively introduced into the surface layer of body region 20 by ion implantation via first mask 37, thereby forming source region 23. Also, contact pattern region 50 is formed from a part of body region 20 that was covered with first mask 37. After source region 23 is formed, first mask 37 is removed.

[0205] Next, referring to FIG. 12I , a mask material is formed to cover the sidewalls 29 and the base mask 18. The mask material may be an organic material. The organic material may include a positive or negative photosensitive resin film (i.e., a resist film). Of course, the mask material may also be an inorganic material (e.g., a silicon oxide film, a silicon nitride film, a polysilicon film, etc.). Next, the mask material is patterned to form a second mask 56. The second mask 56 has a second opening 57 that exposes a region where the contact region 25 is to be formed.

[0206] 12J , p-type impurities are selectively introduced into the surface layer of the body region 20 by ion implantation using a second mask 56, thereby forming the contact region 25. The contact region 25 is formed in the same planar pattern as the first mask 37. However, slight pattern misalignment may occur due to an error in the ion incident angle when introducing the p-type impurities. Therefore, the tops 49 of the pair of protrusions 14A, 14B of the contact region 25 may have a rounded shape, unlike the tops 48 of the pair of protrusions 41A, 41B of the first mask 37 (see FIG. 6 ).

[0207] 12K, a base insulating film 58 is formed to cover the first wafer main surface 151. The base insulating film 58 is a base for the insulating film 31 and the peripheral insulating film 51. The base insulating film 58 may be formed by a chemical vapor deposition (CVD) method or an oxidation treatment method (for example, a thermal oxidation treatment method).

[0208] 12L, a base electrode is formed on the base insulating film 58. The base electrode is the base of the gate electrode 32 and the gate wiring 52. The base electrode includes conductive polysilicon. The base electrode may be formed by a CVD method. Next, the base electrode is patterned to form the gate electrode 32 and the gate wiring 52.

[0209] Next, referring to FIG. 12M , an interlayer film 70 is formed on the first wafer main surface 151. In this process, the interlayer film 70 is formed to have portions that directly cover the electrode surface 33, the first sidewall 34, and the second sidewall 35 of the gate electrode 32. In this embodiment, the interlayer film 70 has a stacked structure including a first oxide film 72 and a second oxide film 73. The first oxide film 72 includes a silicon oxide film with no impurities added. The second oxide film 73 includes a silicon oxide film containing phosphorus. The first oxide film 72 may be formed by a CVD method. The second oxide film 73 may be formed by a CVD method. After the process of forming the second oxide film 73, a reflow process (heat treatment process) is performed on the interlayer film 70. This smoothes the corners and rough surfaces of the interlayer film 70.

[0210] 12N, a mask having a predetermined layout is placed on the interlayer film 70. The mask exposes regions where a plurality of source openings 90, a plurality of outer openings 92, and a plurality of gate openings 94 are to be formed, and covers the remaining regions. Next, unnecessary portions of the interlayer film 70 and unnecessary portions of the base insulating film 58 are removed by etching using the mask.

[0211] In this step, unnecessary portions of the second oxide film 73, the first oxide film 72, and the base insulating film 58 are removed in this order. The etching method may be wet etching and / or dry etching. The etching method is preferably anisotropic dry etching (e.g., RIE (Reactive Ion Etching)). This forms a plurality of source openings 90, a plurality of outer openings 92, and a plurality of gate openings 94 in the interlayer film 70. The insulating film 31 and the peripheral insulating film 51 are also formed. This step may include the steps of forming a plurality of source recesses 91 and a plurality of outer recesses 93. In this case, a step of further recessing portions of the first wafer main surface 151 exposed through the plurality of source openings 90 and the plurality of outer openings 92 toward the second wafer main surface 152 is performed. The mask is then removed.

[0212] 12O, a reflow process forms a surface curved obliquely upward like gate electrode 32 at the upper corner of interlayer film 70. The reflow conditions are not particularly limited as long as they allow the sharp upper corner of interlayer film 70 to become arc-shaped after the etching shown in FIG. 12N. For example, the reflow conditions may be appropriately determined depending on the film thickness and film quality of interlayer film 70, the opening width of source opening 90, and the like.

[0213] 12P , a first underlying electrode film 100 and a second underlying electrode film 120 are formed on the interlayer film 70. The first underlying electrode film 100 and the second underlying electrode film 120 may be formed by sputtering or vapor deposition. Next, a first main electrode film 102 and a second main electrode film 122 are formed on the first underlying electrode film 100 and the second underlying electrode film 120, respectively. The first main electrode film 102 and the second main electrode film 122 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The first main electrode film 102 and the second main electrode film 122 may be formed by sputtering or vapor deposition.

[0214] Thereafter, a drain pad electrode 140 is formed on the second wafer main surface 152. The drain pad electrode 140 may be formed by sputtering or vapor deposition. Then, the wafer 150 is cut along the cutting lines 156 to cut out a plurality of semiconductor devices 1. Through the steps including those described above, the semiconductor device 1 is manufactured.

[0215] For example, in order to meet the demand for miniaturization of devices, multiple gate structures 30 may be arranged at a narrow pitch. As the distance between adjacent gate structures 30 becomes narrower, the formation areas of the source region 23 and the contact region 25 also become narrower. As a result, the installation areas of the first mask 37 and the second mask 56 when forming the source region 23 and the contact region 25 are reduced.

[0216] In particular, referring to FIG. 12G , the first mask 37 is formed away from the base mask 18 and the sidewalls 29, etc., and therefore has no lateral support. This reduces its resistance to external forces, making it more susceptible to tipping or tilting due to its own weight or external forces. In contrast, according to the above-described method, as shown in FIG. 13 , the first mask 37 has a pair of protrusions 41A, 41B, which are partially wider. This pair of protrusions 41A, 41B improves the first mask's resistance (strength) to external forces, thereby preventing tipping or tilting of the first mask 37. As a result, the source region 23 and the contact region 25 can be formed with high precision even in fine patterns.

[0217] Furthermore, the chip 2 is a wide bandgap semiconductor (SiC in this embodiment). Wide bandgap semiconductors have a low diffusion coefficient of implanted impurity ions. Therefore, when forming an impurity region toward the bottom of the wafer 150, a method using high-acceleration implantation is used, rather than thermal diffusion, as is used with Si and other materials. To prevent highly accelerated impurity ions from penetrating the mask (resist) and being implanted, the mask must be thick. For example, in this embodiment, the first mask 37 is thickened to prevent n-type impurities from penetrating the first mask 37 and being implanted into the contact pattern region 50 during the formation of the source region 23. Specifically, the aspect ratio (height H of the first mask 37 / third width W3) of the first portion 39 of the first mask 37 is set to be 5 or greater and 25 or less. With such a high aspect ratio, there is a significant concern about the first mask 37 tipping or tilting. However, the presence of the pair of protrusions 41A and 41B can eliminate such concerns.

[0218] Alternatively, it is possible to omit the steps of FIGS. 12G and 12H and form the source region 23 by implanting n-type impurities into the entire region sandwiched between the sidewalls 29. Subsequently, p-type impurities may be implanted into the source region 23 through a second mask 56 laterally supported by the sidewalls 29 to form the contact region 25. However, the contact region 25 must be formed by implanting p-type impurities at an excessive concentration sufficient to cancel out the n-type of the previously formed source region 23. Excessive implantation of impurity ions may deteriorate the surface condition of the first wafer main surface 151 (e.g., roughen the surface) and degrade the functionality of the semiconductor device 1. For example, the surface roughness may increase the contact resistance between the source pad electrode 95 and the contact region 25. In contrast, the above-described method requires only one ion implantation for each impurity region, thereby maintaining a good surface condition of the first wafer main surface 151.

[0219] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0220] For example, in the above-described embodiment, the contact region 25 is partially widened to form a pair of protrusions 14A and 14B. However, as shown in FIG. 14 , the first source region 24A and the second source region 24B may be partially widened. In this case, a pair of protrusions 59A and 59B may be formed from the first source region 24A and the second source region 24B, respectively, protruding toward the inside of the contact region 25. Additionally, a structure similar to the pair of protrusions 14A and 14B may be applied to minute impurity regions formed in the chip 2, regardless of their function. For example, the structure may be applied to a plurality of field regions 47 formed in the peripheral region 9.

[0221] 15 to 19 may be employed as modified patterns of the contact region 25. In Fig. 15, the first width W1 of the first portion 12 of the contact region 25 gradually narrows from the pair of protrusions 14A, 14B toward the ends in the second direction Y. As a result, the first portion 12 may be formed in a generally tapered shape in plan view.

[0222] 16, a plurality of protrusions 14A, 14B are formed on one side and the other side of the first portion 12 of the contact region 25 in the first direction X. In Fig. 17, a pair of protrusions 14A, 14B protrude in opposite directions from different positions on the first portion 12 in the second direction Y.

[0223] In Fig. 18, each of the protrusions 14A, 14B is formed in a semicircular shape in a plan view. In Fig. 19, each of the protrusions 14A, 14B is formed in a quadrangular shape in a plan view. In this case, the corners (tops 49) of the quadrangle may be rounded.

[0224] For example, in each of the above-described embodiments, a configuration in which the relationship between the a-axis direction and the m-axis direction is interchanged may be adopted. A specific configuration in this case can be obtained by interchangeing the "a-axis direction (off direction)" and the "m-axis direction (direction perpendicular to the off direction)" in the above description and the accompanying drawings.

[0225] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an “n-type” semiconductor region is inverted to “p-type” and the conductivity type of a “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0226] In the above-described embodiments, the chip 2 (first semiconductor region 6 and second semiconductor region 7) includes single crystal SiC. However, the chip 2 (first semiconductor region 6 and second semiconductor region 7) may include single crystal wide bandgap semiconductors other than single crystal SiC. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. Examples of single crystal wide bandgap semiconductors include gallium nitride, diamond, and gallium oxide. Of course, the chip 2 (first semiconductor region 6 and second semiconductor region 7) may include single crystal silicon.

[0227] In the above-described embodiments, the n-type second semiconductor region 7 has been described. However, a p-type second semiconductor region 7 may be adopted instead of the n-type second semiconductor region 7. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure. The p-type second semiconductor region 7 may be an impurity region containing p-type impurities introduced into a surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0228] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc., as necessary.

[0229] [Supplementary Note 1-1] A semiconductor device (1) comprising: a chip (2) formed of a wide bandgap semiconductor and having a main surface on which a semiconductor region (6) of a first conductivity type is formed; a base impurity region (20) of a second conductivity type formed in a surface layer portion of the semiconductor region (6); a first impurity region (13, 25) formed in a surface layer portion of the base impurity region (20); and a second impurity region (25, 13) of an opposite conductivity type to the first impurity region (13, 25) formed in the surface layer portion of the base impurity region (20), the second impurity region (25, 13) being adjacent to the first impurity region (13, 25) in a first direction (X), the second impurity region (25, 13) being formed in a strip shape extending in a second direction (Y) perpendicular to the first direction (X), and having a protrusion (13) that protrudes selectively toward the first impurity region (13, 25) in the first direction (X).

[0230] [Supplementary Note 1-2] The semiconductor device (1) according to Supplementary Note 1-1, wherein the second impurity region (25, 13) is sandwiched between the first impurity regions (13, 25) on both sides in the first direction (X), and a pair of the protrusions (14A, 14B) protrude toward opposite sides in the first direction (X).

[0231] [Appendix 1-3] The semiconductor device (1) according to Appendix 1-2, wherein the second impurity region (25, 13) includes a first portion (12) extending in the second direction (Y) and having a first width (W1) in the first direction (X), and the pair of protrusions (14A, 14B) protruding from a center of the first portion (12) in the second direction (Y) to both sides in the first direction (X).

[0232] [Appendix 1-4] The semiconductor device (1) according to Appendix 1-3, wherein the pair of protrusions (14A, 14B) have a diamond-shaped or circular overall shape that protrudes evenly on both sides of the first portion (12) in a plan view.

[0233] [Appendix 1-5] The semiconductor device (1) according to appendix 1-3 or appendix 1-4, wherein the first width (W1) of the first portion (12) is 0.2 μm or more and 0.6 μm or less, and the entire second width (W2) of the pair of protrusions (14A, 14B) from an end of one of the protrusions (13) to an end of the other of the protrusions (13) is 1.2 μm or more and 1.6 μm or less.

[0234] [Appendix 1-6] The semiconductor device (1) according to appendix 1-5, wherein a width (WS) of the first impurity region (13, 25) in the first direction (X) is larger than the second width (W2) of the pair of protrusions (14A, 14B).

[0235] [Appendix 1-7] The semiconductor device (1) according to appendix 1-1, comprising: a body region (20) as the base impurity region (20) formed in a surface layer portion of the semiconductor region (6); the first impurity region (13) formed in a surface layer portion of the body region (20); a body contact region (25) as the second impurity region (25) formed in the surface layer portion of the body region (20) and connected to the body region (20) through the first impurity region (13); a channel (26, 27) formed in a region between the semiconductor region (6) and the first impurity region (13) in the surface layer portion of the body region (20); and a gate electrode (32) formed on the channel (26, 27) via an insulating film (31).

[0236] [Supplementary Note 1-8] The semiconductor device (1) according to Supplementary Note 1-7, wherein a plurality of the body regions (20) are arranged in a stripe pattern extending in the second direction (Y), each of the body regions (20) has a plurality of first sections (10) and a plurality of second sections (11) alternating in the second direction (Y), and the plurality of the body contact regions (25) are arranged at intervals for each of the first sections (10) so as to skip each of the second sections (11) in the second direction (Y).

[0237] [Appendix 1-9] The semiconductor device (1) according to Appendix 1-8, wherein the body contact region (25) includes a first portion (12) that crosses the first section (10) in the second direction (Y) and has a first width (W1) in the first direction (X), and the pair of protrusions (14A, 14B) that protrude from a center of the first portion (12) in the second direction (Y) to both sides in the first direction (X).

[0238] [Appendix 1-10] The semiconductor device (1) according to appendix 1-9, wherein the pair of protrusions (14A, 14B) have a diamond or circular overall shape in a plan view, protruding evenly on both sides of the first portion (12).

[0239] [Appendix 1-11] The semiconductor device (1) according to appendix 1-10, wherein the first width (W1) of the first portion (12) is 0.2 μm or more and 0.6 μm or less, and a second width (W2) of the entire pair of protrusions (14A, 14B) from an end of one of the protrusions (14A) to an end of the other of the protrusions (14B) is 1.2 μm or more and 1.6 μm or less.

[0240] [Appendix 1-12] The semiconductor device (1) according to appendix 1-11, wherein a width (WS) of the first impurity region (13) in the first direction (X) is greater than the second width (W2) of the pair of protrusions (14A, 14B).

[0241] [Appendix 1-13] The semiconductor device (1) according to appendix 1-1, comprising: a body region (20) as the base impurity region (20) formed in a surface layer portion of the semiconductor region (6); the second impurity region (13) formed in a surface layer portion of the body region (20); a body contact region (25) as the first impurity region (25) formed in the surface layer portion of the body region (20) and connected to the body region (20) through the second impurity region (13); a channel (26, 27) formed in a region between the semiconductor region (6) and the second impurity region (13) in the surface layer portion of the body region (20); and a gate electrode (32) formed on the channel (26, 27) via an insulating film (31).

[0242] [Supplementary Note 1-14] The semiconductor device (1) according to Supplementary Note 1-13, wherein a plurality of the body regions (20) are arranged in a stripe pattern extending in the second direction (Y), each of the body regions (20) has a plurality of first sections (10) and a plurality of second sections (11) arranged alternately in the second direction (Y), and a plurality of body contact regions (25) are arranged at intervals for each of the first sections (10) so as to skip each of the second sections (11) in the second direction (Y).

[0243] [Appendix 1-15] The semiconductor device (1) according to any one of Appendices 1-1 to 1-14, wherein the chip (2) is a SiC chip.

[0244] [Supplementary Note 1-16] A process for selectively forming a plurality of body regions (20) spaced apart in a first direction (X) in a surface layer portion of the semiconductor region (6) by selectively implanting a second conductivity type impurity into the semiconductor region (6), and a process for forming a first mask (37) for selectively covering each of the body regions (20), the first mask (37) including: a first portion (39) extending in a second direction (Y) perpendicular to the first direction (X) and having a first width (W3) in the first direction (X); and the pair of protrusions (41A, 41B) protruding from a center of the first portion (39) in the second direction (Y) on both sides in the first direction (X), a second mask (56) having an opening (57) that selectively exposes the contact pattern region (50) and covers the first impurity region (13); ...

[0245] [Appendix 1-17] The method for manufacturing a semiconductor device (1) according to appendix 1-16 further includes the steps of: forming, on the main surface (151), a hard mask (18) having openings (19) selectively in regions where the body region (20) is to be formed; forming the body region (20) by implanting second conductivity type impurities through the hard mask (18), and then forming sidewalls (29) on the sides of the hard mask (18) to cover regions where the channels (26, 27) are to be formed; forming a mask material (36) to cover the sidewalls (29) and the hard mask (18) so as to backfill the openings in the hard mask (18); and patterning the mask material (36) to form the first mask (37).

[0246] [Appendix 1-18] The method for manufacturing a semiconductor device (1) according to appendix 1-16 or appendix 1-17, wherein the aspect ratio of the first portion (12) of the first mask (37) (height (H) of the first portion (39) / width (W3) of the first portion (39)) is 5 or more and 25 or less.

[0247] 1: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: First semiconductor region 7: Second semiconductor region 8: Active region 9: Peripheral region 10: First section 11: Second section 12: First portion 13: Convex portion 14A: First convex portion 14B: Second convex portion 15: Outline 16: Inner extension line 17: Broken line 18: Base mask 19: Base opening 20: Body region 21: Outer body region 22: Surface drift region 23: Source region 24A: First source region 24B: Second source region 25: Contact region 26: First channel region 27 : Second channel region 28 : Sidewall insulating film 29 : Sidewall 30 : Gate structure 31 : Insulating film 32 : Gate electrode 33 : Electrode surface 34 : First sidewall 35 : Second sidewall 36 : Mask material 37 : First mask 38 : First opening 39 : First portion 40 : Convex portion 41A : First convex portion 41B : Second convex portion 42 : Outline 43 : Inner extension line 44 : Dashed line 45 : Termination region 46 : Overlap region 47 : Field region 48 : Top portion 49 : Top portion 50 : Contact pattern region 51 : Peripheral insulating film 52 : Gate wiring 53 : Wiring surface 54 : First wiring sidewall 55 : Second wiring sidewall 56 : Second mask 57 : Second opening 58 : Base insulating film 59A : Convex portion 59B : Convex portion 70 : Interlayer film 71 : Insulating surface 72 : First oxide film 73 : Second oxide film 74 : First covering portion 75 : Second covering portion 76 : Third covering portion 80 : First upper covering portion 81 : Second upper covering portion 90 : Source opening 91 : Source recess 92 : Outer opening 93 : Outer recess 94 : Gate opening 95 : Source pad electrode 96 : First pad portion 97 : Second pad portion 98 : Third pad portion 100 : First base electrode film 102 : First main electrode film 103 : First electrode film 104 : Second electrode film 110 : Source finger electrode115: Gate finger electrode 120: Second base electrode film 122: Second main electrode film 130: Gate pad electrode 140: Drain pad electrode 150: Wafer 151: First wafer main surface 152: Second wafer main surface 153: Wafer side surface 154: Mark 155: Device region 156: Planned cutting line W1: First width W2: Second width W3: Third width W4: Fourth width X: First direction Y: Second direction Z: Vertical direction

Claims

1. A semiconductor device comprising: a chip formed of a wide bandgap semiconductor and having a main surface on which a semiconductor region of a first conductivity type is formed; a base impurity region of a second conductivity type formed in a surface layer portion of the semiconductor region; a first impurity region formed in the surface layer portion of the base impurity region; and a second impurity region of an opposite conductivity type to the first impurity region formed in the surface layer portion of the base impurity region, the second impurity region being adjacent to the first impurity region in a first direction, wherein the second impurity region is formed in a band shape extending in a second direction perpendicular to the first direction, and has a protrusion that selectively protrudes into the first impurity region in the first direction.

2. The semiconductor device according to claim 1, wherein the second impurity region is sandwiched between the first impurity regions on both sides in the first direction, and a pair of the protrusions protrude in opposite directions in the first direction.

3. The semiconductor device described in claim 2, wherein the second impurity region includes a first portion extending in the second direction and having a first width in the first direction, and a pair of protrusions protruding from a center in the second direction of the first portion on both sides in the first direction.

4. The semiconductor device according to claim 3, wherein the pair of protruding portions have an overall diamond or circular shape in a plan view, protruding evenly on both sides of the first portion.

5. A semiconductor device as described in claim 3 or 4, wherein the first width of the first portion is not less than 0.2 μm and not more than 0.6 μm, and a second width of the pair of protrusions as a whole from an end of one of the protrusions to an end of the other of the protrusions is not less than 1.2 μm and not more than 1.6 μm.

6. The semiconductor device according to claim 5, wherein the width of said first impurity region in said first direction is larger than said second width of said pair of protrusions.

7. The semiconductor device according to claim 1, comprising: a body region serving as the base impurity region formed in a surface layer portion of the semiconductor region; the first impurity region formed in the surface layer portion of the body region; a body contact region serving as the second impurity region formed in the surface layer portion of the body region and connected to the body region through the first impurity region; a channel formed in a region between the semiconductor region and the first impurity region in the surface layer portion of the body region; and a gate electrode formed on the channel via an insulating film.

8. The semiconductor device described in claim 7, wherein a plurality of the body regions are arranged in a stripe pattern extending in the second direction, each of the body regions has a plurality of first sections and a plurality of second sections alternating in the second direction, and the plurality of the body contact regions are arranged with intervals between each of the first sections so as to skip each of the second sections in the second direction.

9. The semiconductor device described in claim 8, wherein the body contact region includes a first portion that crosses the first section in the second direction and has a first width in the first direction, and a pair of protrusions that protrude from a center in the second direction of the first portion on both sides in the first direction.

10. The semiconductor device according to claim 9, wherein the pair of protrusions have an overall diamond or circular shape in a plan view, protruding evenly on both sides of the first portion.

11. The semiconductor device described in claim 10, wherein the first width of the first portion is not less than 0.2 μm and not more than 0.6 μm, and a second width of the pair of protrusions as a whole from an end of one of the protrusions to an end of the other of the protrusions is not less than 1.2 μm and not more than 1.6 μm.

12. The semiconductor device according to claim 11, wherein the width of said first impurity region in said first direction is larger than said second width of said pair of protrusions.

13. The semiconductor device according to claim 1, comprising: a body region serving as the base impurity region formed in a surface layer portion of the semiconductor region; the second impurity region formed in the surface layer portion of the body region; a body contact region serving as the first impurity region formed in the surface layer portion of the body region and connected to the body region through the second impurity region; a channel formed in a region between the semiconductor region and the second impurity region in the surface layer portion of the body region; and a gate electrode formed on the channel via an insulating film.

14. The semiconductor device described in claim 13, wherein a plurality of the body regions are arranged in stripes extending in the second direction, each of the body regions has a plurality of first sections and a plurality of second sections alternating in the second direction, and a plurality of body contact regions are arranged at intervals between each of the first sections so as to skip each of the second sections in the second direction.

15. The semiconductor device according to any one of claims 1 to 14, wherein the chip is a SiC chip.

16. A process for forming a wafer formed of a wide band gap semiconductor and having a first conductivity type semiconductor region formed on a main surface thereof, selectively forming a plurality of body regions spaced apart in a first direction in a surface layer portion of the semiconductor region by selectively injecting a second conductivity type impurity into the semiconductor region; a process for forming a first mask for selectively covering each of the body regions, the first mask including a first portion extending in a second direction perpendicular to the first direction and having a first width in the first direction and a pair of protrusions protruding from a center of the first portion in the second direction to both sides in the first direction; a process for forming a first impurity region in a surface layer portion of the body region by injecting the first conductivity type impurity into the body region through the first mask, and leaving a contact pattern region consisting of a part of the body region in the region that was covered by the first mask; a process for forming a second mask having an opening for selectively exposing the contact pattern region and covering the first impurity region; and a process for forming a body contact region in a surface layer portion of the body region by injecting the second conductivity type impurity into the contact pattern region through the second mask. forming a gate electrode covering a channel formed in a surface portion of the body region in a region between the semiconductor region and the first impurity region.

17. The method for manufacturing a semiconductor device according to claim 16, further comprising the steps of: forming a hard mask on the main surface, the hard mask having an opening selectively in a region where the body region is to be formed; forming sidewalls on sides of the hard mask to cover the region where the channel is to be formed after the body region is formed by implanting a second conductivity type impurity through the hard mask; forming a mask material to cover the sidewalls and the hard mask so as to backfill the opening in the hard mask; and forming the first mask by patterning the mask material.

18. The method for manufacturing a semiconductor device according to claim 16 or 17, wherein the aspect ratio of the first portion of the first mask (height of the first portion / width of the first portion) is 5 or more and 25 or less.

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